2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <linux/hdmi.h>
29 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 #include "evergreend.h"
36 * update the N and CTS parameters for a given pixel clock rate
38 static void evergreen_hdmi_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
40 struct drm_device
*dev
= encoder
->dev
;
41 struct radeon_device
*rdev
= dev
->dev_private
;
42 struct radeon_hdmi_acr acr
= r600_hdmi_acr(clock
);
43 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
44 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
45 uint32_t offset
= dig
->afmt
->offset
;
47 WREG32(HDMI_ACR_32_0
+ offset
, HDMI_ACR_CTS_32(acr
.cts_32khz
));
48 WREG32(HDMI_ACR_32_1
+ offset
, acr
.n_32khz
);
50 WREG32(HDMI_ACR_44_0
+ offset
, HDMI_ACR_CTS_44(acr
.cts_44_1khz
));
51 WREG32(HDMI_ACR_44_1
+ offset
, acr
.n_44_1khz
);
53 WREG32(HDMI_ACR_48_0
+ offset
, HDMI_ACR_CTS_48(acr
.cts_48khz
));
54 WREG32(HDMI_ACR_48_1
+ offset
, acr
.n_48khz
);
57 static void evergreen_hdmi_write_sad_regs(struct drm_encoder
*encoder
)
59 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
60 struct drm_connector
*connector
;
61 struct radeon_connector
*radeon_connector
= NULL
;
65 static const u16 eld_reg_to_type
[][2] = {
66 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
67 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
68 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
69 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
70 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
71 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
80 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
81 if (connector
->encoder
== encoder
)
82 radeon_connector
= to_radeon_connector(connector
);
85 if (!radeon_connector
) {
86 DRM_ERROR("Couldn't find encoder's connector\n");
90 sad_count
= drm_edid_to_sad(radeon_connector
->edid
, &sads
);
92 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
97 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
101 for (j
= 0; j
< sad_count
; j
++) {
102 struct cea_sad
*sad
= &sads
[j
];
104 if (sad
->format
== eld_reg_to_type
[i
][1]) {
105 value
= MAX_CHANNELS(sad
->channels
) |
106 DESCRIPTOR_BYTE_2(sad
->byte2
) |
107 SUPPORTED_FREQUENCIES(sad
->freq
);
108 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
109 value
|= SUPPORTED_FREQUENCIES_STEREO(sad
->freq
);
113 WREG32(eld_reg_to_type
[i
][0], value
);
120 * build a HDMI Video Info Frame
122 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder
*encoder
,
123 void *buffer
, size_t size
)
125 struct drm_device
*dev
= encoder
->dev
;
126 struct radeon_device
*rdev
= dev
->dev_private
;
127 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
128 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
129 uint32_t offset
= dig
->afmt
->offset
;
130 uint8_t *frame
= buffer
+ 3;
132 /* Our header values (type, version, length) should be alright, Intel
133 * is using the same. Checksum function also seems to be OK, it works
134 * fine for audio infoframe. However calculated value is always lower
135 * by 2 in comparison to fglrx. It breaks displaying anything in case
136 * of TVs that strictly check the checksum. Hack it manually here to
137 * workaround this issue. */
140 WREG32(AFMT_AVI_INFO0
+ offset
,
141 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
142 WREG32(AFMT_AVI_INFO1
+ offset
,
143 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
144 WREG32(AFMT_AVI_INFO2
+ offset
,
145 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
146 WREG32(AFMT_AVI_INFO3
+ offset
,
147 frame
[0xC] | (frame
[0xD] << 8));
150 static void evergreen_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
152 struct drm_device
*dev
= encoder
->dev
;
153 struct radeon_device
*rdev
= dev
->dev_private
;
154 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
155 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
156 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
157 u32 base_rate
= 24000;
159 if (!dig
|| !dig
->afmt
)
162 /* XXX two dtos; generally use dto0 for hdmi */
163 /* Express [24MHz / target pixel clock] as an exact rational
164 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
165 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
167 WREG32(DCCG_AUDIO_DTO0_PHASE
, base_rate
* 100);
168 WREG32(DCCG_AUDIO_DTO0_MODULE
, clock
* 100);
169 WREG32(DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc
->crtc_id
));
174 * update the info frames with the data from the current display mode
176 void evergreen_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
178 struct drm_device
*dev
= encoder
->dev
;
179 struct radeon_device
*rdev
= dev
->dev_private
;
180 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
181 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
182 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
183 struct hdmi_avi_infoframe frame
;
187 /* Silent, r600_hdmi_enable will raise WARN for us */
188 if (!dig
->afmt
->enabled
)
190 offset
= dig
->afmt
->offset
;
192 evergreen_audio_set_dto(encoder
, mode
->clock
);
194 WREG32(HDMI_VBI_PACKET_CONTROL
+ offset
,
195 HDMI_NULL_SEND
); /* send null packets when required */
197 WREG32(AFMT_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
199 WREG32(HDMI_VBI_PACKET_CONTROL
+ offset
,
200 HDMI_NULL_SEND
| /* send null packets when required */
201 HDMI_GC_SEND
| /* send general control packets */
202 HDMI_GC_CONT
); /* send general control packets every frame */
204 WREG32(HDMI_INFOFRAME_CONTROL0
+ offset
,
205 HDMI_AUDIO_INFO_SEND
| /* enable audio info frames (frames won't be set until audio is enabled) */
206 HDMI_AUDIO_INFO_CONT
); /* required for audio info values to be updated */
208 WREG32(AFMT_INFOFRAME_CONTROL0
+ offset
,
209 AFMT_AUDIO_INFO_UPDATE
); /* required for audio info values to be updated */
211 WREG32(HDMI_INFOFRAME_CONTROL1
+ offset
,
212 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
214 WREG32(HDMI_GC
+ offset
, 0); /* unset HDMI_GC_AVMUTE */
216 WREG32(HDMI_AUDIO_PACKET_CONTROL
+ offset
,
217 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
218 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
220 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ offset
,
221 AFMT_60958_CS_UPDATE
); /* allow 60958 channel status fields to be updated */
223 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
225 WREG32(HDMI_ACR_PACKET_CONTROL
+ offset
,
226 HDMI_ACR_AUTO_SEND
| /* allow hw to sent ACR packets when required */
227 HDMI_ACR_SOURCE
); /* select SW CTS value */
229 evergreen_hdmi_update_ACR(encoder
, mode
->clock
);
231 WREG32(AFMT_60958_0
+ offset
,
232 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
234 WREG32(AFMT_60958_1
+ offset
,
235 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
237 WREG32(AFMT_60958_2
+ offset
,
238 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
239 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
240 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
241 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
242 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
243 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
245 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
247 WREG32(AFMT_AUDIO_PACKET_CONTROL2
+ offset
,
248 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
250 /* fglrx sets 0x40 in 0x5f80 here */
251 evergreen_hdmi_write_sad_regs(encoder
);
253 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
255 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
259 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
261 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
265 evergreen_hdmi_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
267 WREG32_OR(HDMI_INFOFRAME_CONTROL0
+ offset
,
268 HDMI_AVI_INFO_SEND
| /* enable AVI info frames */
269 HDMI_AVI_INFO_CONT
); /* required for audio info values to be updated */
271 WREG32_P(HDMI_INFOFRAME_CONTROL1
+ offset
,
272 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
273 ~HDMI_AVI_INFO_LINE_MASK
);
275 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL
+ offset
,
276 AFMT_AUDIO_SAMPLE_SEND
); /* send audio packets */
278 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
279 WREG32(AFMT_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
280 WREG32(AFMT_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
281 WREG32(AFMT_RAMP_CONTROL2
+ offset
, 0x00000001);
282 WREG32(AFMT_RAMP_CONTROL3
+ offset
, 0x00000001);
285 void evergreen_hdmi_enable(struct drm_encoder
*encoder
, bool enable
)
287 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
288 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
290 /* Silent, r600_hdmi_enable will raise WARN for us */
291 if (enable
&& dig
->afmt
->enabled
)
293 if (!enable
&& !dig
->afmt
->enabled
)
296 dig
->afmt
->enabled
= enable
;
298 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
299 enable
? "En" : "Dis", dig
->afmt
->offset
, radeon_encoder
->encoder_id
);