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drm/radeon: implement pci config reset for evergreen/cayman (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / ni.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
31 #include "nid.h"
32 #include "atom.h"
33 #include "ni_reg.h"
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
37
38 static const u32 tn_rlc_save_restore_register_list[] =
39 {
40 0x98fc,
41 0x98f0,
42 0x9834,
43 0x9838,
44 0x9870,
45 0x9874,
46 0x8a14,
47 0x8b24,
48 0x8bcc,
49 0x8b10,
50 0x8c30,
51 0x8d00,
52 0x8d04,
53 0x8c00,
54 0x8c04,
55 0x8c10,
56 0x8c14,
57 0x8d8c,
58 0x8cf0,
59 0x8e38,
60 0x9508,
61 0x9688,
62 0x9608,
63 0x960c,
64 0x9610,
65 0x9614,
66 0x88c4,
67 0x8978,
68 0x88d4,
69 0x900c,
70 0x9100,
71 0x913c,
72 0x90e8,
73 0x9354,
74 0xa008,
75 0x98f8,
76 0x9148,
77 0x914c,
78 0x3f94,
79 0x98f4,
80 0x9b7c,
81 0x3f8c,
82 0x8950,
83 0x8954,
84 0x8a18,
85 0x8b28,
86 0x9144,
87 0x3f90,
88 0x915c,
89 0x9160,
90 0x9178,
91 0x917c,
92 0x9180,
93 0x918c,
94 0x9190,
95 0x9194,
96 0x9198,
97 0x919c,
98 0x91a8,
99 0x91ac,
100 0x91b0,
101 0x91b4,
102 0x91b8,
103 0x91c4,
104 0x91c8,
105 0x91cc,
106 0x91d0,
107 0x91d4,
108 0x91e0,
109 0x91e4,
110 0x91ec,
111 0x91f0,
112 0x91f4,
113 0x9200,
114 0x9204,
115 0x929c,
116 0x8030,
117 0x9150,
118 0x9a60,
119 0x920c,
120 0x9210,
121 0x9228,
122 0x922c,
123 0x9244,
124 0x9248,
125 0x91e8,
126 0x9294,
127 0x9208,
128 0x9224,
129 0x9240,
130 0x9220,
131 0x923c,
132 0x9258,
133 0x9744,
134 0xa200,
135 0xa204,
136 0xa208,
137 0xa20c,
138 0x8d58,
139 0x9030,
140 0x9034,
141 0x9038,
142 0x903c,
143 0x9040,
144 0x9654,
145 0x897c,
146 0xa210,
147 0xa214,
148 0x9868,
149 0xa02c,
150 0x9664,
151 0x9698,
152 0x949c,
153 0x8e10,
154 0x8e18,
155 0x8c50,
156 0x8c58,
157 0x8c60,
158 0x8c68,
159 0x89b4,
160 0x9830,
161 0x802c,
162 };
163
164 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169 extern void evergreen_mc_program(struct radeon_device *rdev);
170 extern void evergreen_irq_suspend(struct radeon_device *rdev);
171 extern int evergreen_mc_init(struct radeon_device *rdev);
172 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174 extern void evergreen_program_aspm(struct radeon_device *rdev);
175 extern void sumo_rlc_fini(struct radeon_device *rdev);
176 extern int sumo_rlc_init(struct radeon_device *rdev);
177 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
178
179 /* Firmware Names */
180 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
181 MODULE_FIRMWARE("radeon/BARTS_me.bin");
182 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
183 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
184 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
185 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
186 MODULE_FIRMWARE("radeon/TURKS_me.bin");
187 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
188 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
189 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
190 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
191 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
192 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
193 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
194 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
195 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
196 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
197 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
198 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
199 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
200 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
201
202
203 static const u32 cayman_golden_registers2[] =
204 {
205 0x3e5c, 0xffffffff, 0x00000000,
206 0x3e48, 0xffffffff, 0x00000000,
207 0x3e4c, 0xffffffff, 0x00000000,
208 0x3e64, 0xffffffff, 0x00000000,
209 0x3e50, 0xffffffff, 0x00000000,
210 0x3e60, 0xffffffff, 0x00000000
211 };
212
213 static const u32 cayman_golden_registers[] =
214 {
215 0x5eb4, 0xffffffff, 0x00000002,
216 0x5e78, 0x8f311ff1, 0x001000f0,
217 0x3f90, 0xffff0000, 0xff000000,
218 0x9148, 0xffff0000, 0xff000000,
219 0x3f94, 0xffff0000, 0xff000000,
220 0x914c, 0xffff0000, 0xff000000,
221 0xc78, 0x00000080, 0x00000080,
222 0xbd4, 0x70073777, 0x00011003,
223 0xd02c, 0xbfffff1f, 0x08421000,
224 0xd0b8, 0x73773777, 0x02011003,
225 0x5bc0, 0x00200000, 0x50100000,
226 0x98f8, 0x33773777, 0x02011003,
227 0x98fc, 0xffffffff, 0x76541032,
228 0x7030, 0x31000311, 0x00000011,
229 0x2f48, 0x33773777, 0x42010001,
230 0x6b28, 0x00000010, 0x00000012,
231 0x7728, 0x00000010, 0x00000012,
232 0x10328, 0x00000010, 0x00000012,
233 0x10f28, 0x00000010, 0x00000012,
234 0x11b28, 0x00000010, 0x00000012,
235 0x12728, 0x00000010, 0x00000012,
236 0x240c, 0x000007ff, 0x00000000,
237 0x8a14, 0xf000001f, 0x00000007,
238 0x8b24, 0x3fff3fff, 0x00ff0fff,
239 0x8b10, 0x0000ff0f, 0x00000000,
240 0x28a4c, 0x07ffffff, 0x06000000,
241 0x10c, 0x00000001, 0x00010003,
242 0xa02c, 0xffffffff, 0x0000009b,
243 0x913c, 0x0000010f, 0x01000100,
244 0x8c04, 0xf8ff00ff, 0x40600060,
245 0x28350, 0x00000f01, 0x00000000,
246 0x9508, 0x3700001f, 0x00000002,
247 0x960c, 0xffffffff, 0x54763210,
248 0x88c4, 0x001f3ae3, 0x00000082,
249 0x88d0, 0xffffffff, 0x0f40df40,
250 0x88d4, 0x0000001f, 0x00000010,
251 0x8974, 0xffffffff, 0x00000000
252 };
253
254 static const u32 dvst_golden_registers2[] =
255 {
256 0x8f8, 0xffffffff, 0,
257 0x8fc, 0x00380000, 0,
258 0x8f8, 0xffffffff, 1,
259 0x8fc, 0x0e000000, 0
260 };
261
262 static const u32 dvst_golden_registers[] =
263 {
264 0x690, 0x3fff3fff, 0x20c00033,
265 0x918c, 0x0fff0fff, 0x00010006,
266 0x91a8, 0x0fff0fff, 0x00010006,
267 0x9150, 0xffffdfff, 0x6e944040,
268 0x917c, 0x0fff0fff, 0x00030002,
269 0x9198, 0x0fff0fff, 0x00030002,
270 0x915c, 0x0fff0fff, 0x00010000,
271 0x3f90, 0xffff0001, 0xff000000,
272 0x9178, 0x0fff0fff, 0x00070000,
273 0x9194, 0x0fff0fff, 0x00070000,
274 0x9148, 0xffff0001, 0xff000000,
275 0x9190, 0x0fff0fff, 0x00090008,
276 0x91ac, 0x0fff0fff, 0x00090008,
277 0x3f94, 0xffff0000, 0xff000000,
278 0x914c, 0xffff0000, 0xff000000,
279 0x929c, 0x00000fff, 0x00000001,
280 0x55e4, 0xff607fff, 0xfc000100,
281 0x8a18, 0xff000fff, 0x00000100,
282 0x8b28, 0xff000fff, 0x00000100,
283 0x9144, 0xfffc0fff, 0x00000100,
284 0x6ed8, 0x00010101, 0x00010000,
285 0x9830, 0xffffffff, 0x00000000,
286 0x9834, 0xf00fffff, 0x00000400,
287 0x9838, 0xfffffffe, 0x00000000,
288 0xd0c0, 0xff000fff, 0x00000100,
289 0xd02c, 0xbfffff1f, 0x08421000,
290 0xd0b8, 0x73773777, 0x12010001,
291 0x5bb0, 0x000000f0, 0x00000070,
292 0x98f8, 0x73773777, 0x12010001,
293 0x98fc, 0xffffffff, 0x00000010,
294 0x9b7c, 0x00ff0000, 0x00fc0000,
295 0x8030, 0x00001f0f, 0x0000100a,
296 0x2f48, 0x73773777, 0x12010001,
297 0x2408, 0x00030000, 0x000c007f,
298 0x8a14, 0xf000003f, 0x00000007,
299 0x8b24, 0x3fff3fff, 0x00ff0fff,
300 0x8b10, 0x0000ff0f, 0x00000000,
301 0x28a4c, 0x07ffffff, 0x06000000,
302 0x4d8, 0x00000fff, 0x00000100,
303 0xa008, 0xffffffff, 0x00010000,
304 0x913c, 0xffff03ff, 0x01000100,
305 0x8c00, 0x000000ff, 0x00000003,
306 0x8c04, 0xf8ff00ff, 0x40600060,
307 0x8cf0, 0x1fff1fff, 0x08e00410,
308 0x28350, 0x00000f01, 0x00000000,
309 0x9508, 0xf700071f, 0x00000002,
310 0x960c, 0xffffffff, 0x54763210,
311 0x20ef8, 0x01ff01ff, 0x00000002,
312 0x20e98, 0xfffffbff, 0x00200000,
313 0x2015c, 0xffffffff, 0x00000f40,
314 0x88c4, 0x001f3ae3, 0x00000082,
315 0x8978, 0x3fffffff, 0x04050140,
316 0x88d4, 0x0000001f, 0x00000010,
317 0x8974, 0xffffffff, 0x00000000
318 };
319
320 static const u32 scrapper_golden_registers[] =
321 {
322 0x690, 0x3fff3fff, 0x20c00033,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x929c, 0x00000fff, 0x00000001,
352 0x929c, 0x00000fff, 0x00000001,
353 0x55e4, 0xff607fff, 0xfc000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x6ed8, 0x00010101, 0x00010000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0xfffffffe, 0x00000000,
366 0x9838, 0xfffffffe, 0x00000000,
367 0xd0c0, 0xff000fff, 0x00000100,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd0b8, 0x73773777, 0x12010001,
371 0xd0b8, 0x73773777, 0x12010001,
372 0x5bb0, 0x000000f0, 0x00000070,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2408, 0x00030000, 0x000c007f,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x4d8, 0x00000fff, 0x00000100,
393 0x4d8, 0x00000fff, 0x00000100,
394 0xa008, 0xffffffff, 0x00010000,
395 0xa008, 0xffffffff, 0x00010000,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x90e8, 0x001fffff, 0x010400c0,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c30, 0x0000000f, 0x00040005,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x900c, 0x00ffffff, 0x0017071f,
407 0x28350, 0x00000f01, 0x00000000,
408 0x28350, 0x00000f01, 0x00000000,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9688, 0x00300000, 0x0017000f,
412 0x960c, 0xffffffff, 0x54763210,
413 0x960c, 0xffffffff, 0x54763210,
414 0x20ef8, 0x01ff01ff, 0x00000002,
415 0x20e98, 0xfffffbff, 0x00200000,
416 0x2015c, 0xffffffff, 0x00000f40,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x8974, 0xffffffff, 0x00000000,
424 0x8974, 0xffffffff, 0x00000000
425 };
426
427 static void ni_init_golden_registers(struct radeon_device *rdev)
428 {
429 switch (rdev->family) {
430 case CHIP_CAYMAN:
431 radeon_program_register_sequence(rdev,
432 cayman_golden_registers,
433 (const u32)ARRAY_SIZE(cayman_golden_registers));
434 radeon_program_register_sequence(rdev,
435 cayman_golden_registers2,
436 (const u32)ARRAY_SIZE(cayman_golden_registers2));
437 break;
438 case CHIP_ARUBA:
439 if ((rdev->pdev->device == 0x9900) ||
440 (rdev->pdev->device == 0x9901) ||
441 (rdev->pdev->device == 0x9903) ||
442 (rdev->pdev->device == 0x9904) ||
443 (rdev->pdev->device == 0x9905) ||
444 (rdev->pdev->device == 0x9906) ||
445 (rdev->pdev->device == 0x9907) ||
446 (rdev->pdev->device == 0x9908) ||
447 (rdev->pdev->device == 0x9909) ||
448 (rdev->pdev->device == 0x990A) ||
449 (rdev->pdev->device == 0x990B) ||
450 (rdev->pdev->device == 0x990C) ||
451 (rdev->pdev->device == 0x990D) ||
452 (rdev->pdev->device == 0x990E) ||
453 (rdev->pdev->device == 0x990F) ||
454 (rdev->pdev->device == 0x9910) ||
455 (rdev->pdev->device == 0x9913) ||
456 (rdev->pdev->device == 0x9917) ||
457 (rdev->pdev->device == 0x9918)) {
458 radeon_program_register_sequence(rdev,
459 dvst_golden_registers,
460 (const u32)ARRAY_SIZE(dvst_golden_registers));
461 radeon_program_register_sequence(rdev,
462 dvst_golden_registers2,
463 (const u32)ARRAY_SIZE(dvst_golden_registers2));
464 } else {
465 radeon_program_register_sequence(rdev,
466 scrapper_golden_registers,
467 (const u32)ARRAY_SIZE(scrapper_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
471 }
472 break;
473 default:
474 break;
475 }
476 }
477
478 #define BTC_IO_MC_REGS_SIZE 29
479
480 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
481 {0x00000077, 0xff010100},
482 {0x00000078, 0x00000000},
483 {0x00000079, 0x00001434},
484 {0x0000007a, 0xcc08ec08},
485 {0x0000007b, 0x00040000},
486 {0x0000007c, 0x000080c0},
487 {0x0000007d, 0x09000000},
488 {0x0000007e, 0x00210404},
489 {0x00000081, 0x08a8e800},
490 {0x00000082, 0x00030444},
491 {0x00000083, 0x00000000},
492 {0x00000085, 0x00000001},
493 {0x00000086, 0x00000002},
494 {0x00000087, 0x48490000},
495 {0x00000088, 0x20244647},
496 {0x00000089, 0x00000005},
497 {0x0000008b, 0x66030000},
498 {0x0000008c, 0x00006603},
499 {0x0000008d, 0x00000100},
500 {0x0000008f, 0x00001c0a},
501 {0x00000090, 0xff000001},
502 {0x00000094, 0x00101101},
503 {0x00000095, 0x00000fff},
504 {0x00000096, 0x00116fff},
505 {0x00000097, 0x60010000},
506 {0x00000098, 0x10010000},
507 {0x00000099, 0x00006000},
508 {0x0000009a, 0x00001000},
509 {0x0000009f, 0x00946a00}
510 };
511
512 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
513 {0x00000077, 0xff010100},
514 {0x00000078, 0x00000000},
515 {0x00000079, 0x00001434},
516 {0x0000007a, 0xcc08ec08},
517 {0x0000007b, 0x00040000},
518 {0x0000007c, 0x000080c0},
519 {0x0000007d, 0x09000000},
520 {0x0000007e, 0x00210404},
521 {0x00000081, 0x08a8e800},
522 {0x00000082, 0x00030444},
523 {0x00000083, 0x00000000},
524 {0x00000085, 0x00000001},
525 {0x00000086, 0x00000002},
526 {0x00000087, 0x48490000},
527 {0x00000088, 0x20244647},
528 {0x00000089, 0x00000005},
529 {0x0000008b, 0x66030000},
530 {0x0000008c, 0x00006603},
531 {0x0000008d, 0x00000100},
532 {0x0000008f, 0x00001c0a},
533 {0x00000090, 0xff000001},
534 {0x00000094, 0x00101101},
535 {0x00000095, 0x00000fff},
536 {0x00000096, 0x00116fff},
537 {0x00000097, 0x60010000},
538 {0x00000098, 0x10010000},
539 {0x00000099, 0x00006000},
540 {0x0000009a, 0x00001000},
541 {0x0000009f, 0x00936a00}
542 };
543
544 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
545 {0x00000077, 0xff010100},
546 {0x00000078, 0x00000000},
547 {0x00000079, 0x00001434},
548 {0x0000007a, 0xcc08ec08},
549 {0x0000007b, 0x00040000},
550 {0x0000007c, 0x000080c0},
551 {0x0000007d, 0x09000000},
552 {0x0000007e, 0x00210404},
553 {0x00000081, 0x08a8e800},
554 {0x00000082, 0x00030444},
555 {0x00000083, 0x00000000},
556 {0x00000085, 0x00000001},
557 {0x00000086, 0x00000002},
558 {0x00000087, 0x48490000},
559 {0x00000088, 0x20244647},
560 {0x00000089, 0x00000005},
561 {0x0000008b, 0x66030000},
562 {0x0000008c, 0x00006603},
563 {0x0000008d, 0x00000100},
564 {0x0000008f, 0x00001c0a},
565 {0x00000090, 0xff000001},
566 {0x00000094, 0x00101101},
567 {0x00000095, 0x00000fff},
568 {0x00000096, 0x00116fff},
569 {0x00000097, 0x60010000},
570 {0x00000098, 0x10010000},
571 {0x00000099, 0x00006000},
572 {0x0000009a, 0x00001000},
573 {0x0000009f, 0x00916a00}
574 };
575
576 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
577 {0x00000077, 0xff010100},
578 {0x00000078, 0x00000000},
579 {0x00000079, 0x00001434},
580 {0x0000007a, 0xcc08ec08},
581 {0x0000007b, 0x00040000},
582 {0x0000007c, 0x000080c0},
583 {0x0000007d, 0x09000000},
584 {0x0000007e, 0x00210404},
585 {0x00000081, 0x08a8e800},
586 {0x00000082, 0x00030444},
587 {0x00000083, 0x00000000},
588 {0x00000085, 0x00000001},
589 {0x00000086, 0x00000002},
590 {0x00000087, 0x48490000},
591 {0x00000088, 0x20244647},
592 {0x00000089, 0x00000005},
593 {0x0000008b, 0x66030000},
594 {0x0000008c, 0x00006603},
595 {0x0000008d, 0x00000100},
596 {0x0000008f, 0x00001c0a},
597 {0x00000090, 0xff000001},
598 {0x00000094, 0x00101101},
599 {0x00000095, 0x00000fff},
600 {0x00000096, 0x00116fff},
601 {0x00000097, 0x60010000},
602 {0x00000098, 0x10010000},
603 {0x00000099, 0x00006000},
604 {0x0000009a, 0x00001000},
605 {0x0000009f, 0x00976b00}
606 };
607
608 int ni_mc_load_microcode(struct radeon_device *rdev)
609 {
610 const __be32 *fw_data;
611 u32 mem_type, running, blackout = 0;
612 u32 *io_mc_regs;
613 int i, ucode_size, regs_size;
614
615 if (!rdev->mc_fw)
616 return -EINVAL;
617
618 switch (rdev->family) {
619 case CHIP_BARTS:
620 io_mc_regs = (u32 *)&barts_io_mc_regs;
621 ucode_size = BTC_MC_UCODE_SIZE;
622 regs_size = BTC_IO_MC_REGS_SIZE;
623 break;
624 case CHIP_TURKS:
625 io_mc_regs = (u32 *)&turks_io_mc_regs;
626 ucode_size = BTC_MC_UCODE_SIZE;
627 regs_size = BTC_IO_MC_REGS_SIZE;
628 break;
629 case CHIP_CAICOS:
630 default:
631 io_mc_regs = (u32 *)&caicos_io_mc_regs;
632 ucode_size = BTC_MC_UCODE_SIZE;
633 regs_size = BTC_IO_MC_REGS_SIZE;
634 break;
635 case CHIP_CAYMAN:
636 io_mc_regs = (u32 *)&cayman_io_mc_regs;
637 ucode_size = CAYMAN_MC_UCODE_SIZE;
638 regs_size = BTC_IO_MC_REGS_SIZE;
639 break;
640 }
641
642 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
643 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
644
645 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
646 if (running) {
647 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
648 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
649 }
650
651 /* reset the engine and set to writable */
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
654
655 /* load mc io regs */
656 for (i = 0; i < regs_size; i++) {
657 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
658 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
659 }
660 /* load the MC ucode */
661 fw_data = (const __be32 *)rdev->mc_fw->data;
662 for (i = 0; i < ucode_size; i++)
663 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
664
665 /* put the engine back into the active state */
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
669
670 /* wait for training to complete */
671 for (i = 0; i < rdev->usec_timeout; i++) {
672 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
673 break;
674 udelay(1);
675 }
676
677 if (running)
678 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
679 }
680
681 return 0;
682 }
683
684 int ni_init_microcode(struct radeon_device *rdev)
685 {
686 const char *chip_name;
687 const char *rlc_chip_name;
688 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
689 size_t smc_req_size = 0;
690 char fw_name[30];
691 int err;
692
693 DRM_DEBUG("\n");
694
695 switch (rdev->family) {
696 case CHIP_BARTS:
697 chip_name = "BARTS";
698 rlc_chip_name = "BTC";
699 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
700 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
701 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
702 mc_req_size = BTC_MC_UCODE_SIZE * 4;
703 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
704 break;
705 case CHIP_TURKS:
706 chip_name = "TURKS";
707 rlc_chip_name = "BTC";
708 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
709 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
710 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
711 mc_req_size = BTC_MC_UCODE_SIZE * 4;
712 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
713 break;
714 case CHIP_CAICOS:
715 chip_name = "CAICOS";
716 rlc_chip_name = "BTC";
717 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
718 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
719 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
720 mc_req_size = BTC_MC_UCODE_SIZE * 4;
721 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
722 break;
723 case CHIP_CAYMAN:
724 chip_name = "CAYMAN";
725 rlc_chip_name = "CAYMAN";
726 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
727 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
728 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
729 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
730 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
731 break;
732 case CHIP_ARUBA:
733 chip_name = "ARUBA";
734 rlc_chip_name = "ARUBA";
735 /* pfp/me same size as CAYMAN */
736 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
737 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
738 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
739 mc_req_size = 0;
740 break;
741 default: BUG();
742 }
743
744 DRM_INFO("Loading %s Microcode\n", chip_name);
745
746 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
747 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
748 if (err)
749 goto out;
750 if (rdev->pfp_fw->size != pfp_req_size) {
751 printk(KERN_ERR
752 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
753 rdev->pfp_fw->size, fw_name);
754 err = -EINVAL;
755 goto out;
756 }
757
758 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
759 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
760 if (err)
761 goto out;
762 if (rdev->me_fw->size != me_req_size) {
763 printk(KERN_ERR
764 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
765 rdev->me_fw->size, fw_name);
766 err = -EINVAL;
767 }
768
769 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
770 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
771 if (err)
772 goto out;
773 if (rdev->rlc_fw->size != rlc_req_size) {
774 printk(KERN_ERR
775 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
776 rdev->rlc_fw->size, fw_name);
777 err = -EINVAL;
778 }
779
780 /* no MC ucode on TN */
781 if (!(rdev->flags & RADEON_IS_IGP)) {
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
784 if (err)
785 goto out;
786 if (rdev->mc_fw->size != mc_req_size) {
787 printk(KERN_ERR
788 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
789 rdev->mc_fw->size, fw_name);
790 err = -EINVAL;
791 }
792 }
793
794 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
796 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
797 if (err) {
798 printk(KERN_ERR
799 "smc: error loading firmware \"%s\"\n",
800 fw_name);
801 release_firmware(rdev->smc_fw);
802 rdev->smc_fw = NULL;
803 err = 0;
804 } else if (rdev->smc_fw->size != smc_req_size) {
805 printk(KERN_ERR
806 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
807 rdev->mc_fw->size, fw_name);
808 err = -EINVAL;
809 }
810 }
811
812 out:
813 if (err) {
814 if (err != -EINVAL)
815 printk(KERN_ERR
816 "ni_cp: Failed to load firmware \"%s\"\n",
817 fw_name);
818 release_firmware(rdev->pfp_fw);
819 rdev->pfp_fw = NULL;
820 release_firmware(rdev->me_fw);
821 rdev->me_fw = NULL;
822 release_firmware(rdev->rlc_fw);
823 rdev->rlc_fw = NULL;
824 release_firmware(rdev->mc_fw);
825 rdev->mc_fw = NULL;
826 }
827 return err;
828 }
829
830 int tn_get_temp(struct radeon_device *rdev)
831 {
832 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
833 int actual_temp = (temp / 8) - 49;
834
835 return actual_temp * 1000;
836 }
837
838 /*
839 * Core functions
840 */
841 static void cayman_gpu_init(struct radeon_device *rdev)
842 {
843 u32 gb_addr_config = 0;
844 u32 mc_shared_chmap, mc_arb_ramcfg;
845 u32 cgts_tcc_disable;
846 u32 sx_debug_1;
847 u32 smx_dc_ctl0;
848 u32 cgts_sm_ctrl_reg;
849 u32 hdp_host_path_cntl;
850 u32 tmp;
851 u32 disabled_rb_mask;
852 int i, j;
853
854 switch (rdev->family) {
855 case CHIP_CAYMAN:
856 rdev->config.cayman.max_shader_engines = 2;
857 rdev->config.cayman.max_pipes_per_simd = 4;
858 rdev->config.cayman.max_tile_pipes = 8;
859 rdev->config.cayman.max_simds_per_se = 12;
860 rdev->config.cayman.max_backends_per_se = 4;
861 rdev->config.cayman.max_texture_channel_caches = 8;
862 rdev->config.cayman.max_gprs = 256;
863 rdev->config.cayman.max_threads = 256;
864 rdev->config.cayman.max_gs_threads = 32;
865 rdev->config.cayman.max_stack_entries = 512;
866 rdev->config.cayman.sx_num_of_sets = 8;
867 rdev->config.cayman.sx_max_export_size = 256;
868 rdev->config.cayman.sx_max_export_pos_size = 64;
869 rdev->config.cayman.sx_max_export_smx_size = 192;
870 rdev->config.cayman.max_hw_contexts = 8;
871 rdev->config.cayman.sq_num_cf_insts = 2;
872
873 rdev->config.cayman.sc_prim_fifo_size = 0x100;
874 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
875 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
876 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
877 break;
878 case CHIP_ARUBA:
879 default:
880 rdev->config.cayman.max_shader_engines = 1;
881 rdev->config.cayman.max_pipes_per_simd = 4;
882 rdev->config.cayman.max_tile_pipes = 2;
883 if ((rdev->pdev->device == 0x9900) ||
884 (rdev->pdev->device == 0x9901) ||
885 (rdev->pdev->device == 0x9905) ||
886 (rdev->pdev->device == 0x9906) ||
887 (rdev->pdev->device == 0x9907) ||
888 (rdev->pdev->device == 0x9908) ||
889 (rdev->pdev->device == 0x9909) ||
890 (rdev->pdev->device == 0x990B) ||
891 (rdev->pdev->device == 0x990C) ||
892 (rdev->pdev->device == 0x990F) ||
893 (rdev->pdev->device == 0x9910) ||
894 (rdev->pdev->device == 0x9917) ||
895 (rdev->pdev->device == 0x9999) ||
896 (rdev->pdev->device == 0x999C)) {
897 rdev->config.cayman.max_simds_per_se = 6;
898 rdev->config.cayman.max_backends_per_se = 2;
899 } else if ((rdev->pdev->device == 0x9903) ||
900 (rdev->pdev->device == 0x9904) ||
901 (rdev->pdev->device == 0x990A) ||
902 (rdev->pdev->device == 0x990D) ||
903 (rdev->pdev->device == 0x990E) ||
904 (rdev->pdev->device == 0x9913) ||
905 (rdev->pdev->device == 0x9918) ||
906 (rdev->pdev->device == 0x999D)) {
907 rdev->config.cayman.max_simds_per_se = 4;
908 rdev->config.cayman.max_backends_per_se = 2;
909 } else if ((rdev->pdev->device == 0x9919) ||
910 (rdev->pdev->device == 0x9990) ||
911 (rdev->pdev->device == 0x9991) ||
912 (rdev->pdev->device == 0x9994) ||
913 (rdev->pdev->device == 0x9995) ||
914 (rdev->pdev->device == 0x9996) ||
915 (rdev->pdev->device == 0x999A) ||
916 (rdev->pdev->device == 0x99A0)) {
917 rdev->config.cayman.max_simds_per_se = 3;
918 rdev->config.cayman.max_backends_per_se = 1;
919 } else {
920 rdev->config.cayman.max_simds_per_se = 2;
921 rdev->config.cayman.max_backends_per_se = 1;
922 }
923 rdev->config.cayman.max_texture_channel_caches = 2;
924 rdev->config.cayman.max_gprs = 256;
925 rdev->config.cayman.max_threads = 256;
926 rdev->config.cayman.max_gs_threads = 32;
927 rdev->config.cayman.max_stack_entries = 512;
928 rdev->config.cayman.sx_num_of_sets = 8;
929 rdev->config.cayman.sx_max_export_size = 256;
930 rdev->config.cayman.sx_max_export_pos_size = 64;
931 rdev->config.cayman.sx_max_export_smx_size = 192;
932 rdev->config.cayman.max_hw_contexts = 8;
933 rdev->config.cayman.sq_num_cf_insts = 2;
934
935 rdev->config.cayman.sc_prim_fifo_size = 0x40;
936 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
937 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
938 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
939 break;
940 }
941
942 /* Initialize HDP */
943 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
944 WREG32((0x2c14 + j), 0x00000000);
945 WREG32((0x2c18 + j), 0x00000000);
946 WREG32((0x2c1c + j), 0x00000000);
947 WREG32((0x2c20 + j), 0x00000000);
948 WREG32((0x2c24 + j), 0x00000000);
949 }
950
951 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
952
953 evergreen_fix_pci_max_read_req_size(rdev);
954
955 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
956 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
957
958 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
959 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
960 if (rdev->config.cayman.mem_row_size_in_kb > 4)
961 rdev->config.cayman.mem_row_size_in_kb = 4;
962 /* XXX use MC settings? */
963 rdev->config.cayman.shader_engine_tile_size = 32;
964 rdev->config.cayman.num_gpus = 1;
965 rdev->config.cayman.multi_gpu_tile_size = 64;
966
967 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
968 rdev->config.cayman.num_tile_pipes = (1 << tmp);
969 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
970 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
971 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
972 rdev->config.cayman.num_shader_engines = tmp + 1;
973 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
974 rdev->config.cayman.num_gpus = tmp + 1;
975 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
976 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
977 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
978 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
979
980
981 /* setup tiling info dword. gb_addr_config is not adequate since it does
982 * not have bank info, so create a custom tiling dword.
983 * bits 3:0 num_pipes
984 * bits 7:4 num_banks
985 * bits 11:8 group_size
986 * bits 15:12 row_size
987 */
988 rdev->config.cayman.tile_config = 0;
989 switch (rdev->config.cayman.num_tile_pipes) {
990 case 1:
991 default:
992 rdev->config.cayman.tile_config |= (0 << 0);
993 break;
994 case 2:
995 rdev->config.cayman.tile_config |= (1 << 0);
996 break;
997 case 4:
998 rdev->config.cayman.tile_config |= (2 << 0);
999 break;
1000 case 8:
1001 rdev->config.cayman.tile_config |= (3 << 0);
1002 break;
1003 }
1004
1005 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1006 if (rdev->flags & RADEON_IS_IGP)
1007 rdev->config.cayman.tile_config |= 1 << 4;
1008 else {
1009 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1010 case 0: /* four banks */
1011 rdev->config.cayman.tile_config |= 0 << 4;
1012 break;
1013 case 1: /* eight banks */
1014 rdev->config.cayman.tile_config |= 1 << 4;
1015 break;
1016 case 2: /* sixteen banks */
1017 default:
1018 rdev->config.cayman.tile_config |= 2 << 4;
1019 break;
1020 }
1021 }
1022 rdev->config.cayman.tile_config |=
1023 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1024 rdev->config.cayman.tile_config |=
1025 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1026
1027 tmp = 0;
1028 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1029 u32 rb_disable_bitmap;
1030
1031 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1032 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1033 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1034 tmp <<= 4;
1035 tmp |= rb_disable_bitmap;
1036 }
1037 /* enabled rb are just the one not disabled :) */
1038 disabled_rb_mask = tmp;
1039 tmp = 0;
1040 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1041 tmp |= (1 << i);
1042 /* if all the backends are disabled, fix it up here */
1043 if ((disabled_rb_mask & tmp) == tmp) {
1044 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1045 disabled_rb_mask &= ~(1 << i);
1046 }
1047
1048 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1049 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1050
1051 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1052 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1053 if (ASIC_IS_DCE6(rdev))
1054 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1055 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1056 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1057 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1058 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1059 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1060 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1061
1062 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1063 (rdev->flags & RADEON_IS_IGP)) {
1064 if ((disabled_rb_mask & 3) == 1) {
1065 /* RB0 disabled, RB1 enabled */
1066 tmp = 0x11111111;
1067 } else {
1068 /* RB1 disabled, RB0 enabled */
1069 tmp = 0x00000000;
1070 }
1071 } else {
1072 tmp = gb_addr_config & NUM_PIPES_MASK;
1073 tmp = r6xx_remap_render_backend(rdev, tmp,
1074 rdev->config.cayman.max_backends_per_se *
1075 rdev->config.cayman.max_shader_engines,
1076 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1077 }
1078 WREG32(GB_BACKEND_MAP, tmp);
1079
1080 cgts_tcc_disable = 0xffff0000;
1081 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1082 cgts_tcc_disable &= ~(1 << (16 + i));
1083 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1084 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1085 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1086 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1087
1088 /* reprogram the shader complex */
1089 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1090 for (i = 0; i < 16; i++)
1091 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1092 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1093
1094 /* set HW defaults for 3D engine */
1095 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1096
1097 sx_debug_1 = RREG32(SX_DEBUG_1);
1098 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1099 WREG32(SX_DEBUG_1, sx_debug_1);
1100
1101 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1102 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1103 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1104 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1105
1106 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1107
1108 /* need to be explicitly zero-ed */
1109 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1110 WREG32(SQ_LSTMP_RING_BASE, 0);
1111 WREG32(SQ_HSTMP_RING_BASE, 0);
1112 WREG32(SQ_ESTMP_RING_BASE, 0);
1113 WREG32(SQ_GSTMP_RING_BASE, 0);
1114 WREG32(SQ_VSTMP_RING_BASE, 0);
1115 WREG32(SQ_PSTMP_RING_BASE, 0);
1116
1117 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1118
1119 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1120 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1121 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1122
1123 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1124 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1125 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1126
1127
1128 WREG32(VGT_NUM_INSTANCES, 1);
1129
1130 WREG32(CP_PERFMON_CNTL, 0);
1131
1132 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1133 FETCH_FIFO_HIWATER(0x4) |
1134 DONE_FIFO_HIWATER(0xe0) |
1135 ALU_UPDATE_FIFO_HIWATER(0x8)));
1136
1137 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1138 WREG32(SQ_CONFIG, (VC_ENABLE |
1139 EXPORT_SRC_C |
1140 GFX_PRIO(0) |
1141 CS1_PRIO(0) |
1142 CS2_PRIO(1)));
1143 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1144
1145 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1146 FORCE_EOV_MAX_REZ_CNT(255)));
1147
1148 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1149 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1150
1151 WREG32(VGT_GS_VERTEX_REUSE, 16);
1152 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1153
1154 WREG32(CB_PERF_CTR0_SEL_0, 0);
1155 WREG32(CB_PERF_CTR0_SEL_1, 0);
1156 WREG32(CB_PERF_CTR1_SEL_0, 0);
1157 WREG32(CB_PERF_CTR1_SEL_1, 0);
1158 WREG32(CB_PERF_CTR2_SEL_0, 0);
1159 WREG32(CB_PERF_CTR2_SEL_1, 0);
1160 WREG32(CB_PERF_CTR3_SEL_0, 0);
1161 WREG32(CB_PERF_CTR3_SEL_1, 0);
1162
1163 tmp = RREG32(HDP_MISC_CNTL);
1164 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1165 WREG32(HDP_MISC_CNTL, tmp);
1166
1167 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1168 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1169
1170 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1171
1172 udelay(50);
1173
1174 /* set clockgating golden values on TN */
1175 if (rdev->family == CHIP_ARUBA) {
1176 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1177 tmp &= ~0x00380000;
1178 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1179 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1180 tmp &= ~0x0e000000;
1181 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1182 }
1183 }
1184
1185 /*
1186 * GART
1187 */
1188 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1189 {
1190 /* flush hdp cache */
1191 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1192
1193 /* bits 0-7 are the VM contexts0-7 */
1194 WREG32(VM_INVALIDATE_REQUEST, 1);
1195 }
1196
1197 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1198 {
1199 int i, r;
1200
1201 if (rdev->gart.robj == NULL) {
1202 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1203 return -EINVAL;
1204 }
1205 r = radeon_gart_table_vram_pin(rdev);
1206 if (r)
1207 return r;
1208 radeon_gart_restore(rdev);
1209 /* Setup TLB control */
1210 WREG32(MC_VM_MX_L1_TLB_CNTL,
1211 (0xA << 7) |
1212 ENABLE_L1_TLB |
1213 ENABLE_L1_FRAGMENT_PROCESSING |
1214 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1215 ENABLE_ADVANCED_DRIVER_MODEL |
1216 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1217 /* Setup L2 cache */
1218 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1219 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1220 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1221 EFFECTIVE_L2_QUEUE_SIZE(7) |
1222 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1223 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1224 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1225 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1226 /* setup context0 */
1227 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1228 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1229 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1230 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1231 (u32)(rdev->dummy_page.addr >> 12));
1232 WREG32(VM_CONTEXT0_CNTL2, 0);
1233 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1234 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1235
1236 WREG32(0x15D4, 0);
1237 WREG32(0x15D8, 0);
1238 WREG32(0x15DC, 0);
1239
1240 /* empty context1-7 */
1241 /* Assign the pt base to something valid for now; the pts used for
1242 * the VMs are determined by the application and setup and assigned
1243 * on the fly in the vm part of radeon_gart.c
1244 */
1245 for (i = 1; i < 8; i++) {
1246 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1247 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1248 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1249 rdev->gart.table_addr >> 12);
1250 }
1251
1252 /* enable context1-7 */
1253 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1254 (u32)(rdev->dummy_page.addr >> 12));
1255 WREG32(VM_CONTEXT1_CNTL2, 4);
1256 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1257 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1258 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1259 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1260 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1261 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1262 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1263 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1264 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1265 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1266 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1267 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1268 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1269
1270 cayman_pcie_gart_tlb_flush(rdev);
1271 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1272 (unsigned)(rdev->mc.gtt_size >> 20),
1273 (unsigned long long)rdev->gart.table_addr);
1274 rdev->gart.ready = true;
1275 return 0;
1276 }
1277
1278 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1279 {
1280 /* Disable all tables */
1281 WREG32(VM_CONTEXT0_CNTL, 0);
1282 WREG32(VM_CONTEXT1_CNTL, 0);
1283 /* Setup TLB control */
1284 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1285 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1286 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1287 /* Setup L2 cache */
1288 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1289 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1290 EFFECTIVE_L2_QUEUE_SIZE(7) |
1291 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1292 WREG32(VM_L2_CNTL2, 0);
1293 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1294 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1295 radeon_gart_table_vram_unpin(rdev);
1296 }
1297
1298 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1299 {
1300 cayman_pcie_gart_disable(rdev);
1301 radeon_gart_table_vram_free(rdev);
1302 radeon_gart_fini(rdev);
1303 }
1304
1305 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1306 int ring, u32 cp_int_cntl)
1307 {
1308 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1309
1310 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1311 WREG32(CP_INT_CNTL, cp_int_cntl);
1312 }
1313
1314 /*
1315 * CP.
1316 */
1317 void cayman_fence_ring_emit(struct radeon_device *rdev,
1318 struct radeon_fence *fence)
1319 {
1320 struct radeon_ring *ring = &rdev->ring[fence->ring];
1321 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1322
1323 /* flush read cache over gart for this vmid */
1324 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1325 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1326 radeon_ring_write(ring, 0);
1327 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1328 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1329 radeon_ring_write(ring, 0xFFFFFFFF);
1330 radeon_ring_write(ring, 0);
1331 radeon_ring_write(ring, 10); /* poll interval */
1332 /* EVENT_WRITE_EOP - flush caches, send int */
1333 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1334 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1335 radeon_ring_write(ring, addr & 0xffffffff);
1336 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1337 radeon_ring_write(ring, fence->seq);
1338 radeon_ring_write(ring, 0);
1339 }
1340
1341 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1342 {
1343 struct radeon_ring *ring = &rdev->ring[ib->ring];
1344
1345 /* set to DX10/11 mode */
1346 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1347 radeon_ring_write(ring, 1);
1348
1349 if (ring->rptr_save_reg) {
1350 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1351 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1352 radeon_ring_write(ring, ((ring->rptr_save_reg -
1353 PACKET3_SET_CONFIG_REG_START) >> 2));
1354 radeon_ring_write(ring, next_rptr);
1355 }
1356
1357 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1358 radeon_ring_write(ring,
1359 #ifdef __BIG_ENDIAN
1360 (2 << 0) |
1361 #endif
1362 (ib->gpu_addr & 0xFFFFFFFC));
1363 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1364 radeon_ring_write(ring, ib->length_dw |
1365 (ib->vm ? (ib->vm->id << 24) : 0));
1366
1367 /* flush read cache over gart for this vmid */
1368 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1369 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1370 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1371 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1372 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1373 radeon_ring_write(ring, 0xFFFFFFFF);
1374 radeon_ring_write(ring, 0);
1375 radeon_ring_write(ring, 10); /* poll interval */
1376 }
1377
1378 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1379 {
1380 if (enable)
1381 WREG32(CP_ME_CNTL, 0);
1382 else {
1383 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1384 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1385 WREG32(SCRATCH_UMSK, 0);
1386 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1387 }
1388 }
1389
1390 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1391 struct radeon_ring *ring)
1392 {
1393 u32 rptr;
1394
1395 if (rdev->wb.enabled)
1396 rptr = rdev->wb.wb[ring->rptr_offs/4];
1397 else {
1398 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1399 rptr = RREG32(CP_RB0_RPTR);
1400 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1401 rptr = RREG32(CP_RB1_RPTR);
1402 else
1403 rptr = RREG32(CP_RB2_RPTR);
1404 }
1405
1406 return rptr;
1407 }
1408
1409 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1410 struct radeon_ring *ring)
1411 {
1412 u32 wptr;
1413
1414 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1415 wptr = RREG32(CP_RB0_WPTR);
1416 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1417 wptr = RREG32(CP_RB1_WPTR);
1418 else
1419 wptr = RREG32(CP_RB2_WPTR);
1420
1421 return wptr;
1422 }
1423
1424 void cayman_gfx_set_wptr(struct radeon_device *rdev,
1425 struct radeon_ring *ring)
1426 {
1427 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1428 WREG32(CP_RB0_WPTR, ring->wptr);
1429 (void)RREG32(CP_RB0_WPTR);
1430 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1431 WREG32(CP_RB1_WPTR, ring->wptr);
1432 (void)RREG32(CP_RB1_WPTR);
1433 } else {
1434 WREG32(CP_RB2_WPTR, ring->wptr);
1435 (void)RREG32(CP_RB2_WPTR);
1436 }
1437 }
1438
1439 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1440 {
1441 const __be32 *fw_data;
1442 int i;
1443
1444 if (!rdev->me_fw || !rdev->pfp_fw)
1445 return -EINVAL;
1446
1447 cayman_cp_enable(rdev, false);
1448
1449 fw_data = (const __be32 *)rdev->pfp_fw->data;
1450 WREG32(CP_PFP_UCODE_ADDR, 0);
1451 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1452 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1453 WREG32(CP_PFP_UCODE_ADDR, 0);
1454
1455 fw_data = (const __be32 *)rdev->me_fw->data;
1456 WREG32(CP_ME_RAM_WADDR, 0);
1457 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1458 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1459
1460 WREG32(CP_PFP_UCODE_ADDR, 0);
1461 WREG32(CP_ME_RAM_WADDR, 0);
1462 WREG32(CP_ME_RAM_RADDR, 0);
1463 return 0;
1464 }
1465
1466 static int cayman_cp_start(struct radeon_device *rdev)
1467 {
1468 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1469 int r, i;
1470
1471 r = radeon_ring_lock(rdev, ring, 7);
1472 if (r) {
1473 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1474 return r;
1475 }
1476 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1477 radeon_ring_write(ring, 0x1);
1478 radeon_ring_write(ring, 0x0);
1479 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1480 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1481 radeon_ring_write(ring, 0);
1482 radeon_ring_write(ring, 0);
1483 radeon_ring_unlock_commit(rdev, ring);
1484
1485 cayman_cp_enable(rdev, true);
1486
1487 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1488 if (r) {
1489 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1490 return r;
1491 }
1492
1493 /* setup clear context state */
1494 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1495 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1496
1497 for (i = 0; i < cayman_default_size; i++)
1498 radeon_ring_write(ring, cayman_default_state[i]);
1499
1500 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1501 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1502
1503 /* set clear context state */
1504 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1505 radeon_ring_write(ring, 0);
1506
1507 /* SQ_VTX_BASE_VTX_LOC */
1508 radeon_ring_write(ring, 0xc0026f00);
1509 radeon_ring_write(ring, 0x00000000);
1510 radeon_ring_write(ring, 0x00000000);
1511 radeon_ring_write(ring, 0x00000000);
1512
1513 /* Clear consts */
1514 radeon_ring_write(ring, 0xc0036f00);
1515 radeon_ring_write(ring, 0x00000bc4);
1516 radeon_ring_write(ring, 0xffffffff);
1517 radeon_ring_write(ring, 0xffffffff);
1518 radeon_ring_write(ring, 0xffffffff);
1519
1520 radeon_ring_write(ring, 0xc0026900);
1521 radeon_ring_write(ring, 0x00000316);
1522 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1523 radeon_ring_write(ring, 0x00000010); /* */
1524
1525 radeon_ring_unlock_commit(rdev, ring);
1526
1527 /* XXX init other rings */
1528
1529 return 0;
1530 }
1531
1532 static void cayman_cp_fini(struct radeon_device *rdev)
1533 {
1534 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1535 cayman_cp_enable(rdev, false);
1536 radeon_ring_fini(rdev, ring);
1537 radeon_scratch_free(rdev, ring->rptr_save_reg);
1538 }
1539
1540 static int cayman_cp_resume(struct radeon_device *rdev)
1541 {
1542 static const int ridx[] = {
1543 RADEON_RING_TYPE_GFX_INDEX,
1544 CAYMAN_RING_TYPE_CP1_INDEX,
1545 CAYMAN_RING_TYPE_CP2_INDEX
1546 };
1547 static const unsigned cp_rb_cntl[] = {
1548 CP_RB0_CNTL,
1549 CP_RB1_CNTL,
1550 CP_RB2_CNTL,
1551 };
1552 static const unsigned cp_rb_rptr_addr[] = {
1553 CP_RB0_RPTR_ADDR,
1554 CP_RB1_RPTR_ADDR,
1555 CP_RB2_RPTR_ADDR
1556 };
1557 static const unsigned cp_rb_rptr_addr_hi[] = {
1558 CP_RB0_RPTR_ADDR_HI,
1559 CP_RB1_RPTR_ADDR_HI,
1560 CP_RB2_RPTR_ADDR_HI
1561 };
1562 static const unsigned cp_rb_base[] = {
1563 CP_RB0_BASE,
1564 CP_RB1_BASE,
1565 CP_RB2_BASE
1566 };
1567 static const unsigned cp_rb_rptr[] = {
1568 CP_RB0_RPTR,
1569 CP_RB1_RPTR,
1570 CP_RB2_RPTR
1571 };
1572 static const unsigned cp_rb_wptr[] = {
1573 CP_RB0_WPTR,
1574 CP_RB1_WPTR,
1575 CP_RB2_WPTR
1576 };
1577 struct radeon_ring *ring;
1578 int i, r;
1579
1580 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1581 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1582 SOFT_RESET_PA |
1583 SOFT_RESET_SH |
1584 SOFT_RESET_VGT |
1585 SOFT_RESET_SPI |
1586 SOFT_RESET_SX));
1587 RREG32(GRBM_SOFT_RESET);
1588 mdelay(15);
1589 WREG32(GRBM_SOFT_RESET, 0);
1590 RREG32(GRBM_SOFT_RESET);
1591
1592 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1593 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1594
1595 /* Set the write pointer delay */
1596 WREG32(CP_RB_WPTR_DELAY, 0);
1597
1598 WREG32(CP_DEBUG, (1 << 27));
1599
1600 /* set the wb address whether it's enabled or not */
1601 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1602 WREG32(SCRATCH_UMSK, 0xff);
1603
1604 for (i = 0; i < 3; ++i) {
1605 uint32_t rb_cntl;
1606 uint64_t addr;
1607
1608 /* Set ring buffer size */
1609 ring = &rdev->ring[ridx[i]];
1610 rb_cntl = order_base_2(ring->ring_size / 8);
1611 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1612 #ifdef __BIG_ENDIAN
1613 rb_cntl |= BUF_SWAP_32BIT;
1614 #endif
1615 WREG32(cp_rb_cntl[i], rb_cntl);
1616
1617 /* set the wb address whether it's enabled or not */
1618 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1619 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1620 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1621 }
1622
1623 /* set the rb base addr, this causes an internal reset of ALL rings */
1624 for (i = 0; i < 3; ++i) {
1625 ring = &rdev->ring[ridx[i]];
1626 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1627 }
1628
1629 for (i = 0; i < 3; ++i) {
1630 /* Initialize the ring buffer's read and write pointers */
1631 ring = &rdev->ring[ridx[i]];
1632 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1633
1634 ring->rptr = ring->wptr = 0;
1635 WREG32(cp_rb_rptr[i], ring->rptr);
1636 WREG32(cp_rb_wptr[i], ring->wptr);
1637
1638 mdelay(1);
1639 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1640 }
1641
1642 /* start the rings */
1643 cayman_cp_start(rdev);
1644 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1645 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1646 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1647 /* this only test cp0 */
1648 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1649 if (r) {
1650 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1651 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1652 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1653 return r;
1654 }
1655
1656 return 0;
1657 }
1658
1659 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1660 {
1661 u32 reset_mask = 0;
1662 u32 tmp;
1663
1664 /* GRBM_STATUS */
1665 tmp = RREG32(GRBM_STATUS);
1666 if (tmp & (PA_BUSY | SC_BUSY |
1667 SH_BUSY | SX_BUSY |
1668 TA_BUSY | VGT_BUSY |
1669 DB_BUSY | CB_BUSY |
1670 GDS_BUSY | SPI_BUSY |
1671 IA_BUSY | IA_BUSY_NO_DMA))
1672 reset_mask |= RADEON_RESET_GFX;
1673
1674 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1675 CP_BUSY | CP_COHERENCY_BUSY))
1676 reset_mask |= RADEON_RESET_CP;
1677
1678 if (tmp & GRBM_EE_BUSY)
1679 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1680
1681 /* DMA_STATUS_REG 0 */
1682 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1683 if (!(tmp & DMA_IDLE))
1684 reset_mask |= RADEON_RESET_DMA;
1685
1686 /* DMA_STATUS_REG 1 */
1687 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1688 if (!(tmp & DMA_IDLE))
1689 reset_mask |= RADEON_RESET_DMA1;
1690
1691 /* SRBM_STATUS2 */
1692 tmp = RREG32(SRBM_STATUS2);
1693 if (tmp & DMA_BUSY)
1694 reset_mask |= RADEON_RESET_DMA;
1695
1696 if (tmp & DMA1_BUSY)
1697 reset_mask |= RADEON_RESET_DMA1;
1698
1699 /* SRBM_STATUS */
1700 tmp = RREG32(SRBM_STATUS);
1701 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1702 reset_mask |= RADEON_RESET_RLC;
1703
1704 if (tmp & IH_BUSY)
1705 reset_mask |= RADEON_RESET_IH;
1706
1707 if (tmp & SEM_BUSY)
1708 reset_mask |= RADEON_RESET_SEM;
1709
1710 if (tmp & GRBM_RQ_PENDING)
1711 reset_mask |= RADEON_RESET_GRBM;
1712
1713 if (tmp & VMC_BUSY)
1714 reset_mask |= RADEON_RESET_VMC;
1715
1716 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1717 MCC_BUSY | MCD_BUSY))
1718 reset_mask |= RADEON_RESET_MC;
1719
1720 if (evergreen_is_display_hung(rdev))
1721 reset_mask |= RADEON_RESET_DISPLAY;
1722
1723 /* VM_L2_STATUS */
1724 tmp = RREG32(VM_L2_STATUS);
1725 if (tmp & L2_BUSY)
1726 reset_mask |= RADEON_RESET_VMC;
1727
1728 /* Skip MC reset as it's mostly likely not hung, just busy */
1729 if (reset_mask & RADEON_RESET_MC) {
1730 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1731 reset_mask &= ~RADEON_RESET_MC;
1732 }
1733
1734 return reset_mask;
1735 }
1736
1737 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1738 {
1739 struct evergreen_mc_save save;
1740 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1741 u32 tmp;
1742
1743 if (reset_mask == 0)
1744 return;
1745
1746 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1747
1748 evergreen_print_gpu_status_regs(rdev);
1749 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1750 RREG32(0x14F8));
1751 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1752 RREG32(0x14D8));
1753 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1754 RREG32(0x14FC));
1755 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1756 RREG32(0x14DC));
1757
1758 /* Disable CP parsing/prefetching */
1759 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1760
1761 if (reset_mask & RADEON_RESET_DMA) {
1762 /* dma0 */
1763 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1764 tmp &= ~DMA_RB_ENABLE;
1765 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1766 }
1767
1768 if (reset_mask & RADEON_RESET_DMA1) {
1769 /* dma1 */
1770 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1771 tmp &= ~DMA_RB_ENABLE;
1772 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1773 }
1774
1775 udelay(50);
1776
1777 evergreen_mc_stop(rdev, &save);
1778 if (evergreen_mc_wait_for_idle(rdev)) {
1779 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1780 }
1781
1782 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1783 grbm_soft_reset = SOFT_RESET_CB |
1784 SOFT_RESET_DB |
1785 SOFT_RESET_GDS |
1786 SOFT_RESET_PA |
1787 SOFT_RESET_SC |
1788 SOFT_RESET_SPI |
1789 SOFT_RESET_SH |
1790 SOFT_RESET_SX |
1791 SOFT_RESET_TC |
1792 SOFT_RESET_TA |
1793 SOFT_RESET_VGT |
1794 SOFT_RESET_IA;
1795 }
1796
1797 if (reset_mask & RADEON_RESET_CP) {
1798 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1799
1800 srbm_soft_reset |= SOFT_RESET_GRBM;
1801 }
1802
1803 if (reset_mask & RADEON_RESET_DMA)
1804 srbm_soft_reset |= SOFT_RESET_DMA;
1805
1806 if (reset_mask & RADEON_RESET_DMA1)
1807 srbm_soft_reset |= SOFT_RESET_DMA1;
1808
1809 if (reset_mask & RADEON_RESET_DISPLAY)
1810 srbm_soft_reset |= SOFT_RESET_DC;
1811
1812 if (reset_mask & RADEON_RESET_RLC)
1813 srbm_soft_reset |= SOFT_RESET_RLC;
1814
1815 if (reset_mask & RADEON_RESET_SEM)
1816 srbm_soft_reset |= SOFT_RESET_SEM;
1817
1818 if (reset_mask & RADEON_RESET_IH)
1819 srbm_soft_reset |= SOFT_RESET_IH;
1820
1821 if (reset_mask & RADEON_RESET_GRBM)
1822 srbm_soft_reset |= SOFT_RESET_GRBM;
1823
1824 if (reset_mask & RADEON_RESET_VMC)
1825 srbm_soft_reset |= SOFT_RESET_VMC;
1826
1827 if (!(rdev->flags & RADEON_IS_IGP)) {
1828 if (reset_mask & RADEON_RESET_MC)
1829 srbm_soft_reset |= SOFT_RESET_MC;
1830 }
1831
1832 if (grbm_soft_reset) {
1833 tmp = RREG32(GRBM_SOFT_RESET);
1834 tmp |= grbm_soft_reset;
1835 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1836 WREG32(GRBM_SOFT_RESET, tmp);
1837 tmp = RREG32(GRBM_SOFT_RESET);
1838
1839 udelay(50);
1840
1841 tmp &= ~grbm_soft_reset;
1842 WREG32(GRBM_SOFT_RESET, tmp);
1843 tmp = RREG32(GRBM_SOFT_RESET);
1844 }
1845
1846 if (srbm_soft_reset) {
1847 tmp = RREG32(SRBM_SOFT_RESET);
1848 tmp |= srbm_soft_reset;
1849 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1850 WREG32(SRBM_SOFT_RESET, tmp);
1851 tmp = RREG32(SRBM_SOFT_RESET);
1852
1853 udelay(50);
1854
1855 tmp &= ~srbm_soft_reset;
1856 WREG32(SRBM_SOFT_RESET, tmp);
1857 tmp = RREG32(SRBM_SOFT_RESET);
1858 }
1859
1860 /* Wait a little for things to settle down */
1861 udelay(50);
1862
1863 evergreen_mc_resume(rdev, &save);
1864 udelay(50);
1865
1866 evergreen_print_gpu_status_regs(rdev);
1867 }
1868
1869 int cayman_asic_reset(struct radeon_device *rdev)
1870 {
1871 u32 reset_mask;
1872
1873 reset_mask = cayman_gpu_check_soft_reset(rdev);
1874
1875 if (reset_mask)
1876 r600_set_bios_scratch_engine_hung(rdev, true);
1877
1878 cayman_gpu_soft_reset(rdev, reset_mask);
1879
1880 reset_mask = cayman_gpu_check_soft_reset(rdev);
1881
1882 if (reset_mask)
1883 evergreen_gpu_pci_config_reset(rdev);
1884
1885 r600_set_bios_scratch_engine_hung(rdev, false);
1886
1887 return 0;
1888 }
1889
1890 /**
1891 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1892 *
1893 * @rdev: radeon_device pointer
1894 * @ring: radeon_ring structure holding ring information
1895 *
1896 * Check if the GFX engine is locked up.
1897 * Returns true if the engine appears to be locked up, false if not.
1898 */
1899 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1900 {
1901 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1902
1903 if (!(reset_mask & (RADEON_RESET_GFX |
1904 RADEON_RESET_COMPUTE |
1905 RADEON_RESET_CP))) {
1906 radeon_ring_lockup_update(ring);
1907 return false;
1908 }
1909 /* force CP activities */
1910 radeon_ring_force_activity(rdev, ring);
1911 return radeon_ring_test_lockup(rdev, ring);
1912 }
1913
1914 static int cayman_startup(struct radeon_device *rdev)
1915 {
1916 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1917 int r;
1918
1919 /* enable pcie gen2 link */
1920 evergreen_pcie_gen2_enable(rdev);
1921 /* enable aspm */
1922 evergreen_program_aspm(rdev);
1923
1924 /* scratch needs to be initialized before MC */
1925 r = r600_vram_scratch_init(rdev);
1926 if (r)
1927 return r;
1928
1929 evergreen_mc_program(rdev);
1930
1931 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
1932 r = ni_mc_load_microcode(rdev);
1933 if (r) {
1934 DRM_ERROR("Failed to load MC firmware!\n");
1935 return r;
1936 }
1937 }
1938
1939 r = cayman_pcie_gart_enable(rdev);
1940 if (r)
1941 return r;
1942 cayman_gpu_init(rdev);
1943
1944 /* allocate rlc buffers */
1945 if (rdev->flags & RADEON_IS_IGP) {
1946 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1947 rdev->rlc.reg_list_size =
1948 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1949 rdev->rlc.cs_data = cayman_cs_data;
1950 r = sumo_rlc_init(rdev);
1951 if (r) {
1952 DRM_ERROR("Failed to init rlc BOs!\n");
1953 return r;
1954 }
1955 }
1956
1957 /* allocate wb buffer */
1958 r = radeon_wb_init(rdev);
1959 if (r)
1960 return r;
1961
1962 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1963 if (r) {
1964 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1965 return r;
1966 }
1967
1968 r = uvd_v2_2_resume(rdev);
1969 if (!r) {
1970 r = radeon_fence_driver_start_ring(rdev,
1971 R600_RING_TYPE_UVD_INDEX);
1972 if (r)
1973 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1974 }
1975 if (r)
1976 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1977
1978 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1979 if (r) {
1980 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1981 return r;
1982 }
1983
1984 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1985 if (r) {
1986 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1987 return r;
1988 }
1989
1990 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1991 if (r) {
1992 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1993 return r;
1994 }
1995
1996 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1997 if (r) {
1998 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1999 return r;
2000 }
2001
2002 /* Enable IRQ */
2003 if (!rdev->irq.installed) {
2004 r = radeon_irq_kms_init(rdev);
2005 if (r)
2006 return r;
2007 }
2008
2009 r = r600_irq_init(rdev);
2010 if (r) {
2011 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2012 radeon_irq_kms_fini(rdev);
2013 return r;
2014 }
2015 evergreen_irq_set(rdev);
2016
2017 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2018 RADEON_CP_PACKET2);
2019 if (r)
2020 return r;
2021
2022 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2023 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2024 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2025 if (r)
2026 return r;
2027
2028 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2029 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2030 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2031 if (r)
2032 return r;
2033
2034 r = cayman_cp_load_microcode(rdev);
2035 if (r)
2036 return r;
2037 r = cayman_cp_resume(rdev);
2038 if (r)
2039 return r;
2040
2041 r = cayman_dma_resume(rdev);
2042 if (r)
2043 return r;
2044
2045 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2046 if (ring->ring_size) {
2047 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2048 RADEON_CP_PACKET2);
2049 if (!r)
2050 r = uvd_v1_0_init(rdev);
2051 if (r)
2052 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2053 }
2054
2055 r = radeon_ib_pool_init(rdev);
2056 if (r) {
2057 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2058 return r;
2059 }
2060
2061 r = radeon_vm_manager_init(rdev);
2062 if (r) {
2063 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2064 return r;
2065 }
2066
2067 if (ASIC_IS_DCE6(rdev)) {
2068 r = dce6_audio_init(rdev);
2069 if (r)
2070 return r;
2071 } else {
2072 r = r600_audio_init(rdev);
2073 if (r)
2074 return r;
2075 }
2076
2077 return 0;
2078 }
2079
2080 int cayman_resume(struct radeon_device *rdev)
2081 {
2082 int r;
2083
2084 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2085 * posting will perform necessary task to bring back GPU into good
2086 * shape.
2087 */
2088 /* post card */
2089 atom_asic_init(rdev->mode_info.atom_context);
2090
2091 /* init golden registers */
2092 ni_init_golden_registers(rdev);
2093
2094 radeon_pm_resume(rdev);
2095
2096 rdev->accel_working = true;
2097 r = cayman_startup(rdev);
2098 if (r) {
2099 DRM_ERROR("cayman startup failed on resume\n");
2100 rdev->accel_working = false;
2101 return r;
2102 }
2103 return r;
2104 }
2105
2106 int cayman_suspend(struct radeon_device *rdev)
2107 {
2108 radeon_pm_suspend(rdev);
2109 if (ASIC_IS_DCE6(rdev))
2110 dce6_audio_fini(rdev);
2111 else
2112 r600_audio_fini(rdev);
2113 radeon_vm_manager_fini(rdev);
2114 cayman_cp_enable(rdev, false);
2115 cayman_dma_stop(rdev);
2116 uvd_v1_0_fini(rdev);
2117 radeon_uvd_suspend(rdev);
2118 evergreen_irq_suspend(rdev);
2119 radeon_wb_disable(rdev);
2120 cayman_pcie_gart_disable(rdev);
2121 return 0;
2122 }
2123
2124 /* Plan is to move initialization in that function and use
2125 * helper function so that radeon_device_init pretty much
2126 * do nothing more than calling asic specific function. This
2127 * should also allow to remove a bunch of callback function
2128 * like vram_info.
2129 */
2130 int cayman_init(struct radeon_device *rdev)
2131 {
2132 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2133 int r;
2134
2135 /* Read BIOS */
2136 if (!radeon_get_bios(rdev)) {
2137 if (ASIC_IS_AVIVO(rdev))
2138 return -EINVAL;
2139 }
2140 /* Must be an ATOMBIOS */
2141 if (!rdev->is_atom_bios) {
2142 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2143 return -EINVAL;
2144 }
2145 r = radeon_atombios_init(rdev);
2146 if (r)
2147 return r;
2148
2149 /* Post card if necessary */
2150 if (!radeon_card_posted(rdev)) {
2151 if (!rdev->bios) {
2152 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2153 return -EINVAL;
2154 }
2155 DRM_INFO("GPU not posted. posting now...\n");
2156 atom_asic_init(rdev->mode_info.atom_context);
2157 }
2158 /* init golden registers */
2159 ni_init_golden_registers(rdev);
2160 /* Initialize scratch registers */
2161 r600_scratch_init(rdev);
2162 /* Initialize surface registers */
2163 radeon_surface_init(rdev);
2164 /* Initialize clocks */
2165 radeon_get_clock_info(rdev->ddev);
2166 /* Fence driver */
2167 r = radeon_fence_driver_init(rdev);
2168 if (r)
2169 return r;
2170 /* initialize memory controller */
2171 r = evergreen_mc_init(rdev);
2172 if (r)
2173 return r;
2174 /* Memory manager */
2175 r = radeon_bo_init(rdev);
2176 if (r)
2177 return r;
2178
2179 if (rdev->flags & RADEON_IS_IGP) {
2180 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2181 r = ni_init_microcode(rdev);
2182 if (r) {
2183 DRM_ERROR("Failed to load firmware!\n");
2184 return r;
2185 }
2186 }
2187 } else {
2188 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2189 r = ni_init_microcode(rdev);
2190 if (r) {
2191 DRM_ERROR("Failed to load firmware!\n");
2192 return r;
2193 }
2194 }
2195 }
2196
2197 /* Initialize power management */
2198 radeon_pm_init(rdev);
2199
2200 ring->ring_obj = NULL;
2201 r600_ring_init(rdev, ring, 1024 * 1024);
2202
2203 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2204 ring->ring_obj = NULL;
2205 r600_ring_init(rdev, ring, 64 * 1024);
2206
2207 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2208 ring->ring_obj = NULL;
2209 r600_ring_init(rdev, ring, 64 * 1024);
2210
2211 r = radeon_uvd_init(rdev);
2212 if (!r) {
2213 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2214 ring->ring_obj = NULL;
2215 r600_ring_init(rdev, ring, 4096);
2216 }
2217
2218 rdev->ih.ring_obj = NULL;
2219 r600_ih_ring_init(rdev, 64 * 1024);
2220
2221 r = r600_pcie_gart_init(rdev);
2222 if (r)
2223 return r;
2224
2225 rdev->accel_working = true;
2226 r = cayman_startup(rdev);
2227 if (r) {
2228 dev_err(rdev->dev, "disabling GPU acceleration\n");
2229 cayman_cp_fini(rdev);
2230 cayman_dma_fini(rdev);
2231 r600_irq_fini(rdev);
2232 if (rdev->flags & RADEON_IS_IGP)
2233 sumo_rlc_fini(rdev);
2234 radeon_wb_fini(rdev);
2235 radeon_ib_pool_fini(rdev);
2236 radeon_vm_manager_fini(rdev);
2237 radeon_irq_kms_fini(rdev);
2238 cayman_pcie_gart_fini(rdev);
2239 rdev->accel_working = false;
2240 }
2241
2242 /* Don't start up if the MC ucode is missing.
2243 * The default clocks and voltages before the MC ucode
2244 * is loaded are not suffient for advanced operations.
2245 *
2246 * We can skip this check for TN, because there is no MC
2247 * ucode.
2248 */
2249 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2250 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2251 return -EINVAL;
2252 }
2253
2254 return 0;
2255 }
2256
2257 void cayman_fini(struct radeon_device *rdev)
2258 {
2259 radeon_pm_fini(rdev);
2260 cayman_cp_fini(rdev);
2261 cayman_dma_fini(rdev);
2262 r600_irq_fini(rdev);
2263 if (rdev->flags & RADEON_IS_IGP)
2264 sumo_rlc_fini(rdev);
2265 radeon_wb_fini(rdev);
2266 radeon_vm_manager_fini(rdev);
2267 radeon_ib_pool_fini(rdev);
2268 radeon_irq_kms_fini(rdev);
2269 uvd_v1_0_fini(rdev);
2270 radeon_uvd_fini(rdev);
2271 cayman_pcie_gart_fini(rdev);
2272 r600_vram_scratch_fini(rdev);
2273 radeon_gem_fini(rdev);
2274 radeon_fence_driver_fini(rdev);
2275 radeon_bo_fini(rdev);
2276 radeon_atombios_fini(rdev);
2277 kfree(rdev->bios);
2278 rdev->bios = NULL;
2279 }
2280
2281 /*
2282 * vm
2283 */
2284 int cayman_vm_init(struct radeon_device *rdev)
2285 {
2286 /* number of VMs */
2287 rdev->vm_manager.nvm = 8;
2288 /* base offset of vram pages */
2289 if (rdev->flags & RADEON_IS_IGP) {
2290 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2291 tmp <<= 22;
2292 rdev->vm_manager.vram_base_offset = tmp;
2293 } else
2294 rdev->vm_manager.vram_base_offset = 0;
2295 return 0;
2296 }
2297
2298 void cayman_vm_fini(struct radeon_device *rdev)
2299 {
2300 }
2301
2302 /**
2303 * cayman_vm_decode_fault - print human readable fault info
2304 *
2305 * @rdev: radeon_device pointer
2306 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2307 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2308 *
2309 * Print human readable fault information (cayman/TN).
2310 */
2311 void cayman_vm_decode_fault(struct radeon_device *rdev,
2312 u32 status, u32 addr)
2313 {
2314 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2315 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2316 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2317 char *block;
2318
2319 switch (mc_id) {
2320 case 32:
2321 case 16:
2322 case 96:
2323 case 80:
2324 case 160:
2325 case 144:
2326 case 224:
2327 case 208:
2328 block = "CB";
2329 break;
2330 case 33:
2331 case 17:
2332 case 97:
2333 case 81:
2334 case 161:
2335 case 145:
2336 case 225:
2337 case 209:
2338 block = "CB_FMASK";
2339 break;
2340 case 34:
2341 case 18:
2342 case 98:
2343 case 82:
2344 case 162:
2345 case 146:
2346 case 226:
2347 case 210:
2348 block = "CB_CMASK";
2349 break;
2350 case 35:
2351 case 19:
2352 case 99:
2353 case 83:
2354 case 163:
2355 case 147:
2356 case 227:
2357 case 211:
2358 block = "CB_IMMED";
2359 break;
2360 case 36:
2361 case 20:
2362 case 100:
2363 case 84:
2364 case 164:
2365 case 148:
2366 case 228:
2367 case 212:
2368 block = "DB";
2369 break;
2370 case 37:
2371 case 21:
2372 case 101:
2373 case 85:
2374 case 165:
2375 case 149:
2376 case 229:
2377 case 213:
2378 block = "DB_HTILE";
2379 break;
2380 case 38:
2381 case 22:
2382 case 102:
2383 case 86:
2384 case 166:
2385 case 150:
2386 case 230:
2387 case 214:
2388 block = "SX";
2389 break;
2390 case 39:
2391 case 23:
2392 case 103:
2393 case 87:
2394 case 167:
2395 case 151:
2396 case 231:
2397 case 215:
2398 block = "DB_STEN";
2399 break;
2400 case 40:
2401 case 24:
2402 case 104:
2403 case 88:
2404 case 232:
2405 case 216:
2406 case 168:
2407 case 152:
2408 block = "TC_TFETCH";
2409 break;
2410 case 41:
2411 case 25:
2412 case 105:
2413 case 89:
2414 case 233:
2415 case 217:
2416 case 169:
2417 case 153:
2418 block = "TC_VFETCH";
2419 break;
2420 case 42:
2421 case 26:
2422 case 106:
2423 case 90:
2424 case 234:
2425 case 218:
2426 case 170:
2427 case 154:
2428 block = "VC";
2429 break;
2430 case 112:
2431 block = "CP";
2432 break;
2433 case 113:
2434 case 114:
2435 block = "SH";
2436 break;
2437 case 115:
2438 block = "VGT";
2439 break;
2440 case 178:
2441 block = "IH";
2442 break;
2443 case 51:
2444 block = "RLC";
2445 break;
2446 case 55:
2447 block = "DMA";
2448 break;
2449 case 56:
2450 block = "HDP";
2451 break;
2452 default:
2453 block = "unknown";
2454 break;
2455 }
2456
2457 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2458 protections, vmid, addr,
2459 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2460 block, mc_id);
2461 }
2462
2463 /**
2464 * cayman_vm_flush - vm flush using the CP
2465 *
2466 * @rdev: radeon_device pointer
2467 *
2468 * Update the page table base and flush the VM TLB
2469 * using the CP (cayman-si).
2470 */
2471 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2472 {
2473 struct radeon_ring *ring = &rdev->ring[ridx];
2474
2475 if (vm == NULL)
2476 return;
2477
2478 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2479 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2480
2481 /* flush hdp cache */
2482 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2483 radeon_ring_write(ring, 0x1);
2484
2485 /* bits 0-7 are the VM contexts0-7 */
2486 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2487 radeon_ring_write(ring, 1 << vm->id);
2488
2489 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2490 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2491 radeon_ring_write(ring, 0x0);
2492 }
Linux kernel - Deliverables
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