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Merge tag 'sound-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[deliverable/linux.git] / drivers / gpu / drm / radeon / ni.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <drm/drmP.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include <drm/radeon_drm.h>
32 #include "nid.h"
33 #include "atom.h"
34 #include "ni_reg.h"
35 #include "cayman_blit_shaders.h"
36
37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
40 extern void evergreen_mc_program(struct radeon_device *rdev);
41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
42 extern int evergreen_mc_init(struct radeon_device *rdev);
43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
45 extern void si_rlc_fini(struct radeon_device *rdev);
46 extern int si_rlc_init(struct radeon_device *rdev);
47
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define BTC_MC_UCODE_SIZE 6024
52
53 #define CAYMAN_PFP_UCODE_SIZE 2176
54 #define CAYMAN_PM4_UCODE_SIZE 2176
55 #define CAYMAN_RLC_UCODE_SIZE 1024
56 #define CAYMAN_MC_UCODE_SIZE 6037
57
58 #define ARUBA_RLC_UCODE_SIZE 1536
59
60 /* Firmware Names */
61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62 MODULE_FIRMWARE("radeon/BARTS_me.bin");
63 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66 MODULE_FIRMWARE("radeon/TURKS_me.bin");
67 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
78
79 #define BTC_IO_MC_REGS_SIZE 29
80
81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82 {0x00000077, 0xff010100},
83 {0x00000078, 0x00000000},
84 {0x00000079, 0x00001434},
85 {0x0000007a, 0xcc08ec08},
86 {0x0000007b, 0x00040000},
87 {0x0000007c, 0x000080c0},
88 {0x0000007d, 0x09000000},
89 {0x0000007e, 0x00210404},
90 {0x00000081, 0x08a8e800},
91 {0x00000082, 0x00030444},
92 {0x00000083, 0x00000000},
93 {0x00000085, 0x00000001},
94 {0x00000086, 0x00000002},
95 {0x00000087, 0x48490000},
96 {0x00000088, 0x20244647},
97 {0x00000089, 0x00000005},
98 {0x0000008b, 0x66030000},
99 {0x0000008c, 0x00006603},
100 {0x0000008d, 0x00000100},
101 {0x0000008f, 0x00001c0a},
102 {0x00000090, 0xff000001},
103 {0x00000094, 0x00101101},
104 {0x00000095, 0x00000fff},
105 {0x00000096, 0x00116fff},
106 {0x00000097, 0x60010000},
107 {0x00000098, 0x10010000},
108 {0x00000099, 0x00006000},
109 {0x0000009a, 0x00001000},
110 {0x0000009f, 0x00946a00}
111 };
112
113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114 {0x00000077, 0xff010100},
115 {0x00000078, 0x00000000},
116 {0x00000079, 0x00001434},
117 {0x0000007a, 0xcc08ec08},
118 {0x0000007b, 0x00040000},
119 {0x0000007c, 0x000080c0},
120 {0x0000007d, 0x09000000},
121 {0x0000007e, 0x00210404},
122 {0x00000081, 0x08a8e800},
123 {0x00000082, 0x00030444},
124 {0x00000083, 0x00000000},
125 {0x00000085, 0x00000001},
126 {0x00000086, 0x00000002},
127 {0x00000087, 0x48490000},
128 {0x00000088, 0x20244647},
129 {0x00000089, 0x00000005},
130 {0x0000008b, 0x66030000},
131 {0x0000008c, 0x00006603},
132 {0x0000008d, 0x00000100},
133 {0x0000008f, 0x00001c0a},
134 {0x00000090, 0xff000001},
135 {0x00000094, 0x00101101},
136 {0x00000095, 0x00000fff},
137 {0x00000096, 0x00116fff},
138 {0x00000097, 0x60010000},
139 {0x00000098, 0x10010000},
140 {0x00000099, 0x00006000},
141 {0x0000009a, 0x00001000},
142 {0x0000009f, 0x00936a00}
143 };
144
145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146 {0x00000077, 0xff010100},
147 {0x00000078, 0x00000000},
148 {0x00000079, 0x00001434},
149 {0x0000007a, 0xcc08ec08},
150 {0x0000007b, 0x00040000},
151 {0x0000007c, 0x000080c0},
152 {0x0000007d, 0x09000000},
153 {0x0000007e, 0x00210404},
154 {0x00000081, 0x08a8e800},
155 {0x00000082, 0x00030444},
156 {0x00000083, 0x00000000},
157 {0x00000085, 0x00000001},
158 {0x00000086, 0x00000002},
159 {0x00000087, 0x48490000},
160 {0x00000088, 0x20244647},
161 {0x00000089, 0x00000005},
162 {0x0000008b, 0x66030000},
163 {0x0000008c, 0x00006603},
164 {0x0000008d, 0x00000100},
165 {0x0000008f, 0x00001c0a},
166 {0x00000090, 0xff000001},
167 {0x00000094, 0x00101101},
168 {0x00000095, 0x00000fff},
169 {0x00000096, 0x00116fff},
170 {0x00000097, 0x60010000},
171 {0x00000098, 0x10010000},
172 {0x00000099, 0x00006000},
173 {0x0000009a, 0x00001000},
174 {0x0000009f, 0x00916a00}
175 };
176
177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178 {0x00000077, 0xff010100},
179 {0x00000078, 0x00000000},
180 {0x00000079, 0x00001434},
181 {0x0000007a, 0xcc08ec08},
182 {0x0000007b, 0x00040000},
183 {0x0000007c, 0x000080c0},
184 {0x0000007d, 0x09000000},
185 {0x0000007e, 0x00210404},
186 {0x00000081, 0x08a8e800},
187 {0x00000082, 0x00030444},
188 {0x00000083, 0x00000000},
189 {0x00000085, 0x00000001},
190 {0x00000086, 0x00000002},
191 {0x00000087, 0x48490000},
192 {0x00000088, 0x20244647},
193 {0x00000089, 0x00000005},
194 {0x0000008b, 0x66030000},
195 {0x0000008c, 0x00006603},
196 {0x0000008d, 0x00000100},
197 {0x0000008f, 0x00001c0a},
198 {0x00000090, 0xff000001},
199 {0x00000094, 0x00101101},
200 {0x00000095, 0x00000fff},
201 {0x00000096, 0x00116fff},
202 {0x00000097, 0x60010000},
203 {0x00000098, 0x10010000},
204 {0x00000099, 0x00006000},
205 {0x0000009a, 0x00001000},
206 {0x0000009f, 0x00976b00}
207 };
208
209 int ni_mc_load_microcode(struct radeon_device *rdev)
210 {
211 const __be32 *fw_data;
212 u32 mem_type, running, blackout = 0;
213 u32 *io_mc_regs;
214 int i, ucode_size, regs_size;
215
216 if (!rdev->mc_fw)
217 return -EINVAL;
218
219 switch (rdev->family) {
220 case CHIP_BARTS:
221 io_mc_regs = (u32 *)&barts_io_mc_regs;
222 ucode_size = BTC_MC_UCODE_SIZE;
223 regs_size = BTC_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_TURKS:
226 io_mc_regs = (u32 *)&turks_io_mc_regs;
227 ucode_size = BTC_MC_UCODE_SIZE;
228 regs_size = BTC_IO_MC_REGS_SIZE;
229 break;
230 case CHIP_CAICOS:
231 default:
232 io_mc_regs = (u32 *)&caicos_io_mc_regs;
233 ucode_size = BTC_MC_UCODE_SIZE;
234 regs_size = BTC_IO_MC_REGS_SIZE;
235 break;
236 case CHIP_CAYMAN:
237 io_mc_regs = (u32 *)&cayman_io_mc_regs;
238 ucode_size = CAYMAN_MC_UCODE_SIZE;
239 regs_size = BTC_IO_MC_REGS_SIZE;
240 break;
241 }
242
243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247 if (running) {
248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250 }
251
252 /* reset the engine and set to writable */
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
256 /* load mc io regs */
257 for (i = 0; i < regs_size; i++) {
258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260 }
261 /* load the MC ucode */
262 fw_data = (const __be32 *)rdev->mc_fw->data;
263 for (i = 0; i < ucode_size; i++)
264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
266 /* put the engine back into the active state */
267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
271 /* wait for training to complete */
272 for (i = 0; i < rdev->usec_timeout; i++) {
273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274 break;
275 udelay(1);
276 }
277
278 if (running)
279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280 }
281
282 return 0;
283 }
284
285 int ni_init_microcode(struct radeon_device *rdev)
286 {
287 struct platform_device *pdev;
288 const char *chip_name;
289 const char *rlc_chip_name;
290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291 char fw_name[30];
292 int err;
293
294 DRM_DEBUG("\n");
295
296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297 err = IS_ERR(pdev);
298 if (err) {
299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300 return -EINVAL;
301 }
302
303 switch (rdev->family) {
304 case CHIP_BARTS:
305 chip_name = "BARTS";
306 rlc_chip_name = "BTC";
307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310 mc_req_size = BTC_MC_UCODE_SIZE * 4;
311 break;
312 case CHIP_TURKS:
313 chip_name = "TURKS";
314 rlc_chip_name = "BTC";
315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318 mc_req_size = BTC_MC_UCODE_SIZE * 4;
319 break;
320 case CHIP_CAICOS:
321 chip_name = "CAICOS";
322 rlc_chip_name = "BTC";
323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326 mc_req_size = BTC_MC_UCODE_SIZE * 4;
327 break;
328 case CHIP_CAYMAN:
329 chip_name = "CAYMAN";
330 rlc_chip_name = "CAYMAN";
331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
335 break;
336 case CHIP_ARUBA:
337 chip_name = "ARUBA";
338 rlc_chip_name = "ARUBA";
339 /* pfp/me same size as CAYMAN */
340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343 mc_req_size = 0;
344 break;
345 default: BUG();
346 }
347
348 DRM_INFO("Loading %s Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (rdev->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357 rdev->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (rdev->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369 rdev->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372
373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375 if (err)
376 goto out;
377 if (rdev->rlc_fw->size != rlc_req_size) {
378 printk(KERN_ERR
379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380 rdev->rlc_fw->size, fw_name);
381 err = -EINVAL;
382 }
383
384 /* no MC ucode on TN */
385 if (!(rdev->flags & RADEON_IS_IGP)) {
386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388 if (err)
389 goto out;
390 if (rdev->mc_fw->size != mc_req_size) {
391 printk(KERN_ERR
392 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393 rdev->mc_fw->size, fw_name);
394 err = -EINVAL;
395 }
396 }
397 out:
398 platform_device_unregister(pdev);
399
400 if (err) {
401 if (err != -EINVAL)
402 printk(KERN_ERR
403 "ni_cp: Failed to load firmware \"%s\"\n",
404 fw_name);
405 release_firmware(rdev->pfp_fw);
406 rdev->pfp_fw = NULL;
407 release_firmware(rdev->me_fw);
408 rdev->me_fw = NULL;
409 release_firmware(rdev->rlc_fw);
410 rdev->rlc_fw = NULL;
411 release_firmware(rdev->mc_fw);
412 rdev->mc_fw = NULL;
413 }
414 return err;
415 }
416
417 /*
418 * Core functions
419 */
420 static void cayman_gpu_init(struct radeon_device *rdev)
421 {
422 u32 gb_addr_config = 0;
423 u32 mc_shared_chmap, mc_arb_ramcfg;
424 u32 cgts_tcc_disable;
425 u32 sx_debug_1;
426 u32 smx_dc_ctl0;
427 u32 cgts_sm_ctrl_reg;
428 u32 hdp_host_path_cntl;
429 u32 tmp;
430 u32 disabled_rb_mask;
431 int i, j;
432
433 switch (rdev->family) {
434 case CHIP_CAYMAN:
435 rdev->config.cayman.max_shader_engines = 2;
436 rdev->config.cayman.max_pipes_per_simd = 4;
437 rdev->config.cayman.max_tile_pipes = 8;
438 rdev->config.cayman.max_simds_per_se = 12;
439 rdev->config.cayman.max_backends_per_se = 4;
440 rdev->config.cayman.max_texture_channel_caches = 8;
441 rdev->config.cayman.max_gprs = 256;
442 rdev->config.cayman.max_threads = 256;
443 rdev->config.cayman.max_gs_threads = 32;
444 rdev->config.cayman.max_stack_entries = 512;
445 rdev->config.cayman.sx_num_of_sets = 8;
446 rdev->config.cayman.sx_max_export_size = 256;
447 rdev->config.cayman.sx_max_export_pos_size = 64;
448 rdev->config.cayman.sx_max_export_smx_size = 192;
449 rdev->config.cayman.max_hw_contexts = 8;
450 rdev->config.cayman.sq_num_cf_insts = 2;
451
452 rdev->config.cayman.sc_prim_fifo_size = 0x100;
453 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
454 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
455 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
456 break;
457 case CHIP_ARUBA:
458 default:
459 rdev->config.cayman.max_shader_engines = 1;
460 rdev->config.cayman.max_pipes_per_simd = 4;
461 rdev->config.cayman.max_tile_pipes = 2;
462 if ((rdev->pdev->device == 0x9900) ||
463 (rdev->pdev->device == 0x9901) ||
464 (rdev->pdev->device == 0x9905) ||
465 (rdev->pdev->device == 0x9906) ||
466 (rdev->pdev->device == 0x9907) ||
467 (rdev->pdev->device == 0x9908) ||
468 (rdev->pdev->device == 0x9909) ||
469 (rdev->pdev->device == 0x9910) ||
470 (rdev->pdev->device == 0x9917)) {
471 rdev->config.cayman.max_simds_per_se = 6;
472 rdev->config.cayman.max_backends_per_se = 2;
473 } else if ((rdev->pdev->device == 0x9903) ||
474 (rdev->pdev->device == 0x9904) ||
475 (rdev->pdev->device == 0x990A) ||
476 (rdev->pdev->device == 0x9913) ||
477 (rdev->pdev->device == 0x9918)) {
478 rdev->config.cayman.max_simds_per_se = 4;
479 rdev->config.cayman.max_backends_per_se = 2;
480 } else if ((rdev->pdev->device == 0x9919) ||
481 (rdev->pdev->device == 0x9990) ||
482 (rdev->pdev->device == 0x9991) ||
483 (rdev->pdev->device == 0x9994) ||
484 (rdev->pdev->device == 0x99A0)) {
485 rdev->config.cayman.max_simds_per_se = 3;
486 rdev->config.cayman.max_backends_per_se = 1;
487 } else {
488 rdev->config.cayman.max_simds_per_se = 2;
489 rdev->config.cayman.max_backends_per_se = 1;
490 }
491 rdev->config.cayman.max_texture_channel_caches = 2;
492 rdev->config.cayman.max_gprs = 256;
493 rdev->config.cayman.max_threads = 256;
494 rdev->config.cayman.max_gs_threads = 32;
495 rdev->config.cayman.max_stack_entries = 512;
496 rdev->config.cayman.sx_num_of_sets = 8;
497 rdev->config.cayman.sx_max_export_size = 256;
498 rdev->config.cayman.sx_max_export_pos_size = 64;
499 rdev->config.cayman.sx_max_export_smx_size = 192;
500 rdev->config.cayman.max_hw_contexts = 8;
501 rdev->config.cayman.sq_num_cf_insts = 2;
502
503 rdev->config.cayman.sc_prim_fifo_size = 0x40;
504 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
505 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
506 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
507 break;
508 }
509
510 /* Initialize HDP */
511 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
512 WREG32((0x2c14 + j), 0x00000000);
513 WREG32((0x2c18 + j), 0x00000000);
514 WREG32((0x2c1c + j), 0x00000000);
515 WREG32((0x2c20 + j), 0x00000000);
516 WREG32((0x2c24 + j), 0x00000000);
517 }
518
519 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
520
521 evergreen_fix_pci_max_read_req_size(rdev);
522
523 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
524 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
525
526 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
527 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
528 if (rdev->config.cayman.mem_row_size_in_kb > 4)
529 rdev->config.cayman.mem_row_size_in_kb = 4;
530 /* XXX use MC settings? */
531 rdev->config.cayman.shader_engine_tile_size = 32;
532 rdev->config.cayman.num_gpus = 1;
533 rdev->config.cayman.multi_gpu_tile_size = 64;
534
535 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
536 rdev->config.cayman.num_tile_pipes = (1 << tmp);
537 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
538 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
539 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
540 rdev->config.cayman.num_shader_engines = tmp + 1;
541 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
542 rdev->config.cayman.num_gpus = tmp + 1;
543 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
544 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
545 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
546 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
547
548
549 /* setup tiling info dword. gb_addr_config is not adequate since it does
550 * not have bank info, so create a custom tiling dword.
551 * bits 3:0 num_pipes
552 * bits 7:4 num_banks
553 * bits 11:8 group_size
554 * bits 15:12 row_size
555 */
556 rdev->config.cayman.tile_config = 0;
557 switch (rdev->config.cayman.num_tile_pipes) {
558 case 1:
559 default:
560 rdev->config.cayman.tile_config |= (0 << 0);
561 break;
562 case 2:
563 rdev->config.cayman.tile_config |= (1 << 0);
564 break;
565 case 4:
566 rdev->config.cayman.tile_config |= (2 << 0);
567 break;
568 case 8:
569 rdev->config.cayman.tile_config |= (3 << 0);
570 break;
571 }
572
573 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
574 if (rdev->flags & RADEON_IS_IGP)
575 rdev->config.cayman.tile_config |= 1 << 4;
576 else {
577 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578 case 0: /* four banks */
579 rdev->config.cayman.tile_config |= 0 << 4;
580 break;
581 case 1: /* eight banks */
582 rdev->config.cayman.tile_config |= 1 << 4;
583 break;
584 case 2: /* sixteen banks */
585 default:
586 rdev->config.cayman.tile_config |= 2 << 4;
587 break;
588 }
589 }
590 rdev->config.cayman.tile_config |=
591 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
592 rdev->config.cayman.tile_config |=
593 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
594
595 tmp = 0;
596 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
597 u32 rb_disable_bitmap;
598
599 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
600 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
601 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
602 tmp <<= 4;
603 tmp |= rb_disable_bitmap;
604 }
605 /* enabled rb are just the one not disabled :) */
606 disabled_rb_mask = tmp;
607
608 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
609 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
610
611 WREG32(GB_ADDR_CONFIG, gb_addr_config);
612 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
613 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
614
615 tmp = gb_addr_config & NUM_PIPES_MASK;
616 tmp = r6xx_remap_render_backend(rdev, tmp,
617 rdev->config.cayman.max_backends_per_se *
618 rdev->config.cayman.max_shader_engines,
619 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
620 WREG32(GB_BACKEND_MAP, tmp);
621
622 cgts_tcc_disable = 0xffff0000;
623 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
624 cgts_tcc_disable &= ~(1 << (16 + i));
625 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
626 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
627 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
628 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
629
630 /* reprogram the shader complex */
631 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
632 for (i = 0; i < 16; i++)
633 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
634 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
635
636 /* set HW defaults for 3D engine */
637 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
638
639 sx_debug_1 = RREG32(SX_DEBUG_1);
640 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
641 WREG32(SX_DEBUG_1, sx_debug_1);
642
643 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
644 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
645 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
646 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
647
648 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
649
650 /* need to be explicitly zero-ed */
651 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
652 WREG32(SQ_LSTMP_RING_BASE, 0);
653 WREG32(SQ_HSTMP_RING_BASE, 0);
654 WREG32(SQ_ESTMP_RING_BASE, 0);
655 WREG32(SQ_GSTMP_RING_BASE, 0);
656 WREG32(SQ_VSTMP_RING_BASE, 0);
657 WREG32(SQ_PSTMP_RING_BASE, 0);
658
659 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
660
661 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
662 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
663 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
664
665 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
666 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
667 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
668
669
670 WREG32(VGT_NUM_INSTANCES, 1);
671
672 WREG32(CP_PERFMON_CNTL, 0);
673
674 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
675 FETCH_FIFO_HIWATER(0x4) |
676 DONE_FIFO_HIWATER(0xe0) |
677 ALU_UPDATE_FIFO_HIWATER(0x8)));
678
679 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
680 WREG32(SQ_CONFIG, (VC_ENABLE |
681 EXPORT_SRC_C |
682 GFX_PRIO(0) |
683 CS1_PRIO(0) |
684 CS2_PRIO(1)));
685 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
686
687 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
688 FORCE_EOV_MAX_REZ_CNT(255)));
689
690 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
691 AUTO_INVLD_EN(ES_AND_GS_AUTO));
692
693 WREG32(VGT_GS_VERTEX_REUSE, 16);
694 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
695
696 WREG32(CB_PERF_CTR0_SEL_0, 0);
697 WREG32(CB_PERF_CTR0_SEL_1, 0);
698 WREG32(CB_PERF_CTR1_SEL_0, 0);
699 WREG32(CB_PERF_CTR1_SEL_1, 0);
700 WREG32(CB_PERF_CTR2_SEL_0, 0);
701 WREG32(CB_PERF_CTR2_SEL_1, 0);
702 WREG32(CB_PERF_CTR3_SEL_0, 0);
703 WREG32(CB_PERF_CTR3_SEL_1, 0);
704
705 tmp = RREG32(HDP_MISC_CNTL);
706 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
707 WREG32(HDP_MISC_CNTL, tmp);
708
709 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
710 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
711
712 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
713
714 udelay(50);
715 }
716
717 /*
718 * GART
719 */
720 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
721 {
722 /* flush hdp cache */
723 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
724
725 /* bits 0-7 are the VM contexts0-7 */
726 WREG32(VM_INVALIDATE_REQUEST, 1);
727 }
728
729 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
730 {
731 int i, r;
732
733 if (rdev->gart.robj == NULL) {
734 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
735 return -EINVAL;
736 }
737 r = radeon_gart_table_vram_pin(rdev);
738 if (r)
739 return r;
740 radeon_gart_restore(rdev);
741 /* Setup TLB control */
742 WREG32(MC_VM_MX_L1_TLB_CNTL,
743 (0xA << 7) |
744 ENABLE_L1_TLB |
745 ENABLE_L1_FRAGMENT_PROCESSING |
746 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
747 ENABLE_ADVANCED_DRIVER_MODEL |
748 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
749 /* Setup L2 cache */
750 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
751 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
752 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
753 EFFECTIVE_L2_QUEUE_SIZE(7) |
754 CONTEXT1_IDENTITY_ACCESS_MODE(1));
755 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
756 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
757 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
758 /* setup context0 */
759 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
760 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
761 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
762 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
763 (u32)(rdev->dummy_page.addr >> 12));
764 WREG32(VM_CONTEXT0_CNTL2, 0);
765 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
766 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
767
768 WREG32(0x15D4, 0);
769 WREG32(0x15D8, 0);
770 WREG32(0x15DC, 0);
771
772 /* empty context1-7 */
773 /* Assign the pt base to something valid for now; the pts used for
774 * the VMs are determined by the application and setup and assigned
775 * on the fly in the vm part of radeon_gart.c
776 */
777 for (i = 1; i < 8; i++) {
778 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
779 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
780 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
781 rdev->gart.table_addr >> 12);
782 }
783
784 /* enable context1-7 */
785 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
786 (u32)(rdev->dummy_page.addr >> 12));
787 WREG32(VM_CONTEXT1_CNTL2, 0);
788 WREG32(VM_CONTEXT1_CNTL, 0);
789 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
790 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
791
792 cayman_pcie_gart_tlb_flush(rdev);
793 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
794 (unsigned)(rdev->mc.gtt_size >> 20),
795 (unsigned long long)rdev->gart.table_addr);
796 rdev->gart.ready = true;
797 return 0;
798 }
799
800 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
801 {
802 /* Disable all tables */
803 WREG32(VM_CONTEXT0_CNTL, 0);
804 WREG32(VM_CONTEXT1_CNTL, 0);
805 /* Setup TLB control */
806 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
807 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
808 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
809 /* Setup L2 cache */
810 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
811 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
812 EFFECTIVE_L2_QUEUE_SIZE(7) |
813 CONTEXT1_IDENTITY_ACCESS_MODE(1));
814 WREG32(VM_L2_CNTL2, 0);
815 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
816 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
817 radeon_gart_table_vram_unpin(rdev);
818 }
819
820 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
821 {
822 cayman_pcie_gart_disable(rdev);
823 radeon_gart_table_vram_free(rdev);
824 radeon_gart_fini(rdev);
825 }
826
827 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
828 int ring, u32 cp_int_cntl)
829 {
830 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
831
832 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
833 WREG32(CP_INT_CNTL, cp_int_cntl);
834 }
835
836 /*
837 * CP.
838 */
839 void cayman_fence_ring_emit(struct radeon_device *rdev,
840 struct radeon_fence *fence)
841 {
842 struct radeon_ring *ring = &rdev->ring[fence->ring];
843 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
844
845 /* flush read cache over gart for this vmid */
846 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
847 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
848 radeon_ring_write(ring, 0);
849 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
850 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
851 radeon_ring_write(ring, 0xFFFFFFFF);
852 radeon_ring_write(ring, 0);
853 radeon_ring_write(ring, 10); /* poll interval */
854 /* EVENT_WRITE_EOP - flush caches, send int */
855 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
856 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
857 radeon_ring_write(ring, addr & 0xffffffff);
858 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
859 radeon_ring_write(ring, fence->seq);
860 radeon_ring_write(ring, 0);
861 }
862
863 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
864 {
865 struct radeon_ring *ring = &rdev->ring[ib->ring];
866
867 /* set to DX10/11 mode */
868 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
869 radeon_ring_write(ring, 1);
870
871 if (ring->rptr_save_reg) {
872 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
873 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
874 radeon_ring_write(ring, ((ring->rptr_save_reg -
875 PACKET3_SET_CONFIG_REG_START) >> 2));
876 radeon_ring_write(ring, next_rptr);
877 }
878
879 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
880 radeon_ring_write(ring,
881 #ifdef __BIG_ENDIAN
882 (2 << 0) |
883 #endif
884 (ib->gpu_addr & 0xFFFFFFFC));
885 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
886 radeon_ring_write(ring, ib->length_dw |
887 (ib->vm ? (ib->vm->id << 24) : 0));
888
889 /* flush read cache over gart for this vmid */
890 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
891 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
892 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
894 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
895 radeon_ring_write(ring, 0xFFFFFFFF);
896 radeon_ring_write(ring, 0);
897 radeon_ring_write(ring, 10); /* poll interval */
898 }
899
900 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
901 {
902 if (enable)
903 WREG32(CP_ME_CNTL, 0);
904 else {
905 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
906 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
907 WREG32(SCRATCH_UMSK, 0);
908 }
909 }
910
911 static int cayman_cp_load_microcode(struct radeon_device *rdev)
912 {
913 const __be32 *fw_data;
914 int i;
915
916 if (!rdev->me_fw || !rdev->pfp_fw)
917 return -EINVAL;
918
919 cayman_cp_enable(rdev, false);
920
921 fw_data = (const __be32 *)rdev->pfp_fw->data;
922 WREG32(CP_PFP_UCODE_ADDR, 0);
923 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
924 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
925 WREG32(CP_PFP_UCODE_ADDR, 0);
926
927 fw_data = (const __be32 *)rdev->me_fw->data;
928 WREG32(CP_ME_RAM_WADDR, 0);
929 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
930 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
931
932 WREG32(CP_PFP_UCODE_ADDR, 0);
933 WREG32(CP_ME_RAM_WADDR, 0);
934 WREG32(CP_ME_RAM_RADDR, 0);
935 return 0;
936 }
937
938 static int cayman_cp_start(struct radeon_device *rdev)
939 {
940 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
941 int r, i;
942
943 r = radeon_ring_lock(rdev, ring, 7);
944 if (r) {
945 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
946 return r;
947 }
948 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
949 radeon_ring_write(ring, 0x1);
950 radeon_ring_write(ring, 0x0);
951 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
952 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
953 radeon_ring_write(ring, 0);
954 radeon_ring_write(ring, 0);
955 radeon_ring_unlock_commit(rdev, ring);
956
957 cayman_cp_enable(rdev, true);
958
959 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
960 if (r) {
961 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
962 return r;
963 }
964
965 /* setup clear context state */
966 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
967 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
968
969 for (i = 0; i < cayman_default_size; i++)
970 radeon_ring_write(ring, cayman_default_state[i]);
971
972 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
973 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
974
975 /* set clear context state */
976 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
977 radeon_ring_write(ring, 0);
978
979 /* SQ_VTX_BASE_VTX_LOC */
980 radeon_ring_write(ring, 0xc0026f00);
981 radeon_ring_write(ring, 0x00000000);
982 radeon_ring_write(ring, 0x00000000);
983 radeon_ring_write(ring, 0x00000000);
984
985 /* Clear consts */
986 radeon_ring_write(ring, 0xc0036f00);
987 radeon_ring_write(ring, 0x00000bc4);
988 radeon_ring_write(ring, 0xffffffff);
989 radeon_ring_write(ring, 0xffffffff);
990 radeon_ring_write(ring, 0xffffffff);
991
992 radeon_ring_write(ring, 0xc0026900);
993 radeon_ring_write(ring, 0x00000316);
994 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
995 radeon_ring_write(ring, 0x00000010); /* */
996
997 radeon_ring_unlock_commit(rdev, ring);
998
999 /* XXX init other rings */
1000
1001 return 0;
1002 }
1003
1004 static void cayman_cp_fini(struct radeon_device *rdev)
1005 {
1006 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1007 cayman_cp_enable(rdev, false);
1008 radeon_ring_fini(rdev, ring);
1009 radeon_scratch_free(rdev, ring->rptr_save_reg);
1010 }
1011
1012 static int cayman_cp_resume(struct radeon_device *rdev)
1013 {
1014 static const int ridx[] = {
1015 RADEON_RING_TYPE_GFX_INDEX,
1016 CAYMAN_RING_TYPE_CP1_INDEX,
1017 CAYMAN_RING_TYPE_CP2_INDEX
1018 };
1019 static const unsigned cp_rb_cntl[] = {
1020 CP_RB0_CNTL,
1021 CP_RB1_CNTL,
1022 CP_RB2_CNTL,
1023 };
1024 static const unsigned cp_rb_rptr_addr[] = {
1025 CP_RB0_RPTR_ADDR,
1026 CP_RB1_RPTR_ADDR,
1027 CP_RB2_RPTR_ADDR
1028 };
1029 static const unsigned cp_rb_rptr_addr_hi[] = {
1030 CP_RB0_RPTR_ADDR_HI,
1031 CP_RB1_RPTR_ADDR_HI,
1032 CP_RB2_RPTR_ADDR_HI
1033 };
1034 static const unsigned cp_rb_base[] = {
1035 CP_RB0_BASE,
1036 CP_RB1_BASE,
1037 CP_RB2_BASE
1038 };
1039 struct radeon_ring *ring;
1040 int i, r;
1041
1042 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1043 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1044 SOFT_RESET_PA |
1045 SOFT_RESET_SH |
1046 SOFT_RESET_VGT |
1047 SOFT_RESET_SPI |
1048 SOFT_RESET_SX));
1049 RREG32(GRBM_SOFT_RESET);
1050 mdelay(15);
1051 WREG32(GRBM_SOFT_RESET, 0);
1052 RREG32(GRBM_SOFT_RESET);
1053
1054 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1055 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1056
1057 /* Set the write pointer delay */
1058 WREG32(CP_RB_WPTR_DELAY, 0);
1059
1060 WREG32(CP_DEBUG, (1 << 27));
1061
1062 /* set the wb address wether it's enabled or not */
1063 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1064 WREG32(SCRATCH_UMSK, 0xff);
1065
1066 for (i = 0; i < 3; ++i) {
1067 uint32_t rb_cntl;
1068 uint64_t addr;
1069
1070 /* Set ring buffer size */
1071 ring = &rdev->ring[ridx[i]];
1072 rb_cntl = drm_order(ring->ring_size / 8);
1073 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
1074 #ifdef __BIG_ENDIAN
1075 rb_cntl |= BUF_SWAP_32BIT;
1076 #endif
1077 WREG32(cp_rb_cntl[i], rb_cntl);
1078
1079 /* set the wb address wether it's enabled or not */
1080 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1081 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1082 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1083 }
1084
1085 /* set the rb base addr, this causes an internal reset of ALL rings */
1086 for (i = 0; i < 3; ++i) {
1087 ring = &rdev->ring[ridx[i]];
1088 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1089 }
1090
1091 for (i = 0; i < 3; ++i) {
1092 /* Initialize the ring buffer's read and write pointers */
1093 ring = &rdev->ring[ridx[i]];
1094 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1095
1096 ring->rptr = ring->wptr = 0;
1097 WREG32(ring->rptr_reg, ring->rptr);
1098 WREG32(ring->wptr_reg, ring->wptr);
1099
1100 mdelay(1);
1101 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1102 }
1103
1104 /* start the rings */
1105 cayman_cp_start(rdev);
1106 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1107 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1108 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1109 /* this only test cp0 */
1110 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1111 if (r) {
1112 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1113 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1114 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1115 return r;
1116 }
1117
1118 return 0;
1119 }
1120
1121 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1122 {
1123 struct evergreen_mc_save save;
1124 u32 grbm_reset = 0;
1125
1126 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1127 return 0;
1128
1129 dev_info(rdev->dev, "GPU softreset \n");
1130 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1131 RREG32(GRBM_STATUS));
1132 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1133 RREG32(GRBM_STATUS_SE0));
1134 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1135 RREG32(GRBM_STATUS_SE1));
1136 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1137 RREG32(SRBM_STATUS));
1138 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1139 RREG32(CP_STALLED_STAT1));
1140 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1141 RREG32(CP_STALLED_STAT2));
1142 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1143 RREG32(CP_BUSY_STAT));
1144 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1145 RREG32(CP_STAT));
1146 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1147 RREG32(0x14F8));
1148 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1149 RREG32(0x14D8));
1150 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1151 RREG32(0x14FC));
1152 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1153 RREG32(0x14DC));
1154
1155 evergreen_mc_stop(rdev, &save);
1156 if (evergreen_mc_wait_for_idle(rdev)) {
1157 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1158 }
1159 /* Disable CP parsing/prefetching */
1160 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1161
1162 /* reset all the gfx blocks */
1163 grbm_reset = (SOFT_RESET_CP |
1164 SOFT_RESET_CB |
1165 SOFT_RESET_DB |
1166 SOFT_RESET_GDS |
1167 SOFT_RESET_PA |
1168 SOFT_RESET_SC |
1169 SOFT_RESET_SPI |
1170 SOFT_RESET_SH |
1171 SOFT_RESET_SX |
1172 SOFT_RESET_TC |
1173 SOFT_RESET_TA |
1174 SOFT_RESET_VGT |
1175 SOFT_RESET_IA);
1176
1177 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1178 WREG32(GRBM_SOFT_RESET, grbm_reset);
1179 (void)RREG32(GRBM_SOFT_RESET);
1180 udelay(50);
1181 WREG32(GRBM_SOFT_RESET, 0);
1182 (void)RREG32(GRBM_SOFT_RESET);
1183 /* Wait a little for things to settle down */
1184 udelay(50);
1185
1186 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1187 RREG32(GRBM_STATUS));
1188 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1189 RREG32(GRBM_STATUS_SE0));
1190 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1191 RREG32(GRBM_STATUS_SE1));
1192 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1193 RREG32(SRBM_STATUS));
1194 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1195 RREG32(CP_STALLED_STAT1));
1196 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1197 RREG32(CP_STALLED_STAT2));
1198 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1199 RREG32(CP_BUSY_STAT));
1200 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1201 RREG32(CP_STAT));
1202 evergreen_mc_resume(rdev, &save);
1203 return 0;
1204 }
1205
1206 int cayman_asic_reset(struct radeon_device *rdev)
1207 {
1208 return cayman_gpu_soft_reset(rdev);
1209 }
1210
1211 static int cayman_startup(struct radeon_device *rdev)
1212 {
1213 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1214 int r;
1215
1216 /* enable pcie gen2 link */
1217 evergreen_pcie_gen2_enable(rdev);
1218
1219 if (rdev->flags & RADEON_IS_IGP) {
1220 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1221 r = ni_init_microcode(rdev);
1222 if (r) {
1223 DRM_ERROR("Failed to load firmware!\n");
1224 return r;
1225 }
1226 }
1227 } else {
1228 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1229 r = ni_init_microcode(rdev);
1230 if (r) {
1231 DRM_ERROR("Failed to load firmware!\n");
1232 return r;
1233 }
1234 }
1235
1236 r = ni_mc_load_microcode(rdev);
1237 if (r) {
1238 DRM_ERROR("Failed to load MC firmware!\n");
1239 return r;
1240 }
1241 }
1242
1243 r = r600_vram_scratch_init(rdev);
1244 if (r)
1245 return r;
1246
1247 evergreen_mc_program(rdev);
1248 r = cayman_pcie_gart_enable(rdev);
1249 if (r)
1250 return r;
1251 cayman_gpu_init(rdev);
1252
1253 r = evergreen_blit_init(rdev);
1254 if (r) {
1255 r600_blit_fini(rdev);
1256 rdev->asic->copy.copy = NULL;
1257 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1258 }
1259
1260 /* allocate rlc buffers */
1261 if (rdev->flags & RADEON_IS_IGP) {
1262 r = si_rlc_init(rdev);
1263 if (r) {
1264 DRM_ERROR("Failed to init rlc BOs!\n");
1265 return r;
1266 }
1267 }
1268
1269 /* allocate wb buffer */
1270 r = radeon_wb_init(rdev);
1271 if (r)
1272 return r;
1273
1274 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1275 if (r) {
1276 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1277 return r;
1278 }
1279
1280 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1281 if (r) {
1282 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1283 return r;
1284 }
1285
1286 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1287 if (r) {
1288 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1289 return r;
1290 }
1291
1292 /* Enable IRQ */
1293 r = r600_irq_init(rdev);
1294 if (r) {
1295 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1296 radeon_irq_kms_fini(rdev);
1297 return r;
1298 }
1299 evergreen_irq_set(rdev);
1300
1301 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1302 CP_RB0_RPTR, CP_RB0_WPTR,
1303 0, 0xfffff, RADEON_CP_PACKET2);
1304 if (r)
1305 return r;
1306 r = cayman_cp_load_microcode(rdev);
1307 if (r)
1308 return r;
1309 r = cayman_cp_resume(rdev);
1310 if (r)
1311 return r;
1312
1313 r = radeon_ib_pool_init(rdev);
1314 if (r) {
1315 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1316 return r;
1317 }
1318
1319 r = radeon_vm_manager_init(rdev);
1320 if (r) {
1321 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1322 return r;
1323 }
1324
1325 r = r600_audio_init(rdev);
1326 if (r)
1327 return r;
1328
1329 return 0;
1330 }
1331
1332 int cayman_resume(struct radeon_device *rdev)
1333 {
1334 int r;
1335
1336 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1337 * posting will perform necessary task to bring back GPU into good
1338 * shape.
1339 */
1340 /* post card */
1341 atom_asic_init(rdev->mode_info.atom_context);
1342
1343 rdev->accel_working = true;
1344 r = cayman_startup(rdev);
1345 if (r) {
1346 DRM_ERROR("cayman startup failed on resume\n");
1347 rdev->accel_working = false;
1348 return r;
1349 }
1350 return r;
1351 }
1352
1353 int cayman_suspend(struct radeon_device *rdev)
1354 {
1355 r600_audio_fini(rdev);
1356 cayman_cp_enable(rdev, false);
1357 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1358 evergreen_irq_suspend(rdev);
1359 radeon_wb_disable(rdev);
1360 cayman_pcie_gart_disable(rdev);
1361 return 0;
1362 }
1363
1364 /* Plan is to move initialization in that function and use
1365 * helper function so that radeon_device_init pretty much
1366 * do nothing more than calling asic specific function. This
1367 * should also allow to remove a bunch of callback function
1368 * like vram_info.
1369 */
1370 int cayman_init(struct radeon_device *rdev)
1371 {
1372 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1373 int r;
1374
1375 /* Read BIOS */
1376 if (!radeon_get_bios(rdev)) {
1377 if (ASIC_IS_AVIVO(rdev))
1378 return -EINVAL;
1379 }
1380 /* Must be an ATOMBIOS */
1381 if (!rdev->is_atom_bios) {
1382 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1383 return -EINVAL;
1384 }
1385 r = radeon_atombios_init(rdev);
1386 if (r)
1387 return r;
1388
1389 /* Post card if necessary */
1390 if (!radeon_card_posted(rdev)) {
1391 if (!rdev->bios) {
1392 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1393 return -EINVAL;
1394 }
1395 DRM_INFO("GPU not posted. posting now...\n");
1396 atom_asic_init(rdev->mode_info.atom_context);
1397 }
1398 /* Initialize scratch registers */
1399 r600_scratch_init(rdev);
1400 /* Initialize surface registers */
1401 radeon_surface_init(rdev);
1402 /* Initialize clocks */
1403 radeon_get_clock_info(rdev->ddev);
1404 /* Fence driver */
1405 r = radeon_fence_driver_init(rdev);
1406 if (r)
1407 return r;
1408 /* initialize memory controller */
1409 r = evergreen_mc_init(rdev);
1410 if (r)
1411 return r;
1412 /* Memory manager */
1413 r = radeon_bo_init(rdev);
1414 if (r)
1415 return r;
1416
1417 r = radeon_irq_kms_init(rdev);
1418 if (r)
1419 return r;
1420
1421 ring->ring_obj = NULL;
1422 r600_ring_init(rdev, ring, 1024 * 1024);
1423
1424 rdev->ih.ring_obj = NULL;
1425 r600_ih_ring_init(rdev, 64 * 1024);
1426
1427 r = r600_pcie_gart_init(rdev);
1428 if (r)
1429 return r;
1430
1431 rdev->accel_working = true;
1432 r = cayman_startup(rdev);
1433 if (r) {
1434 dev_err(rdev->dev, "disabling GPU acceleration\n");
1435 cayman_cp_fini(rdev);
1436 r600_irq_fini(rdev);
1437 if (rdev->flags & RADEON_IS_IGP)
1438 si_rlc_fini(rdev);
1439 radeon_wb_fini(rdev);
1440 radeon_ib_pool_fini(rdev);
1441 radeon_vm_manager_fini(rdev);
1442 radeon_irq_kms_fini(rdev);
1443 cayman_pcie_gart_fini(rdev);
1444 rdev->accel_working = false;
1445 }
1446
1447 /* Don't start up if the MC ucode is missing.
1448 * The default clocks and voltages before the MC ucode
1449 * is loaded are not suffient for advanced operations.
1450 *
1451 * We can skip this check for TN, because there is no MC
1452 * ucode.
1453 */
1454 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1455 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1456 return -EINVAL;
1457 }
1458
1459 return 0;
1460 }
1461
1462 void cayman_fini(struct radeon_device *rdev)
1463 {
1464 r600_blit_fini(rdev);
1465 cayman_cp_fini(rdev);
1466 r600_irq_fini(rdev);
1467 if (rdev->flags & RADEON_IS_IGP)
1468 si_rlc_fini(rdev);
1469 radeon_wb_fini(rdev);
1470 radeon_vm_manager_fini(rdev);
1471 radeon_ib_pool_fini(rdev);
1472 radeon_irq_kms_fini(rdev);
1473 cayman_pcie_gart_fini(rdev);
1474 r600_vram_scratch_fini(rdev);
1475 radeon_gem_fini(rdev);
1476 radeon_fence_driver_fini(rdev);
1477 radeon_bo_fini(rdev);
1478 radeon_atombios_fini(rdev);
1479 kfree(rdev->bios);
1480 rdev->bios = NULL;
1481 }
1482
1483 /*
1484 * vm
1485 */
1486 int cayman_vm_init(struct radeon_device *rdev)
1487 {
1488 /* number of VMs */
1489 rdev->vm_manager.nvm = 8;
1490 /* base offset of vram pages */
1491 if (rdev->flags & RADEON_IS_IGP) {
1492 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1493 tmp <<= 22;
1494 rdev->vm_manager.vram_base_offset = tmp;
1495 } else
1496 rdev->vm_manager.vram_base_offset = 0;
1497 return 0;
1498 }
1499
1500 void cayman_vm_fini(struct radeon_device *rdev)
1501 {
1502 }
1503
1504 #define R600_ENTRY_VALID (1 << 0)
1505 #define R600_PTE_SYSTEM (1 << 1)
1506 #define R600_PTE_SNOOPED (1 << 2)
1507 #define R600_PTE_READABLE (1 << 5)
1508 #define R600_PTE_WRITEABLE (1 << 6)
1509
1510 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
1511 {
1512 uint32_t r600_flags = 0;
1513 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
1514 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1515 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1516 if (flags & RADEON_VM_PAGE_SYSTEM) {
1517 r600_flags |= R600_PTE_SYSTEM;
1518 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1519 }
1520 return r600_flags;
1521 }
1522
1523 /**
1524 * cayman_vm_set_page - update the page tables using the CP
1525 *
1526 * @rdev: radeon_device pointer
1527 * @pe: addr of the page entry
1528 * @addr: dst addr to write into pe
1529 * @count: number of page entries to update
1530 * @incr: increase next addr by incr bytes
1531 * @flags: access flags
1532 *
1533 * Update the page tables using the CP (cayman-si).
1534 */
1535 void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1536 uint64_t addr, unsigned count,
1537 uint32_t incr, uint32_t flags)
1538 {
1539 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1540 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
1541
1542 while (count) {
1543 unsigned ndw = 1 + count * 2;
1544 if (ndw > 0x3FFF)
1545 ndw = 0x3FFF;
1546
1547 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1548 radeon_ring_write(ring, pe);
1549 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1550 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1551 uint64_t value = 0;
1552 if (flags & RADEON_VM_PAGE_SYSTEM) {
1553 value = radeon_vm_map_gart(rdev, addr);
1554 value &= 0xFFFFFFFFFFFFF000ULL;
1555 addr += incr;
1556
1557 } else if (flags & RADEON_VM_PAGE_VALID) {
1558 value = addr;
1559 addr += incr;
1560 }
1561
1562 value |= r600_flags;
1563 radeon_ring_write(ring, value);
1564 radeon_ring_write(ring, upper_32_bits(value));
1565 }
1566 }
1567 }
1568
1569 /**
1570 * cayman_vm_flush - vm flush using the CP
1571 *
1572 * @rdev: radeon_device pointer
1573 *
1574 * Update the page table base and flush the VM TLB
1575 * using the CP (cayman-si).
1576 */
1577 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1578 {
1579 struct radeon_ring *ring = &rdev->ring[ridx];
1580
1581 if (vm == NULL)
1582 return;
1583
1584 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1585 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1586
1587 /* flush hdp cache */
1588 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1589 radeon_ring_write(ring, 0x1);
1590
1591 /* bits 0-7 are the VM contexts0-7 */
1592 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
1593 radeon_ring_write(ring, 1 << vm->id);
1594
1595 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1596 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1597 radeon_ring_write(ring, 0x0);
1598 }
Linux kernel - Deliverables
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