2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define CAYMAN_MAX_SH_GPRS 256
28 #define CAYMAN_MAX_TEMP_GPRS 16
29 #define CAYMAN_MAX_SH_THREADS 256
30 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31 #define CAYMAN_MAX_FRC_EOV_CNT 16384
32 #define CAYMAN_MAX_BACKENDS 8
33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35 #define CAYMAN_MAX_SIMDS 16
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38 #define CAYMAN_MAX_PIPES 8
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
41 #define CAYMAN_MAX_TCC 16
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
50 #define DMIF_ADDR_CALC 0xC00
52 #define SRBM_GFX_CNTL 0x0E44
53 #define RINGID(x) (((x) & 0x3) << 0)
54 #define VMID(x) (((x) & 0x7) << 0)
55 #define SRBM_STATUS 0x0E50
56 #define RLC_RQ_PENDING (1 << 3)
57 #define GRBM_RQ_PENDING (1 << 5)
58 #define VMC_BUSY (1 << 8)
59 #define MCB_BUSY (1 << 9)
60 #define MCB_NON_DISPLAY_BUSY (1 << 10)
61 #define MCC_BUSY (1 << 11)
62 #define MCD_BUSY (1 << 12)
63 #define SEM_BUSY (1 << 14)
64 #define RLC_BUSY (1 << 15)
65 #define IH_BUSY (1 << 17)
67 #define SRBM_SOFT_RESET 0x0E60
68 #define SOFT_RESET_BIF (1 << 1)
69 #define SOFT_RESET_CG (1 << 2)
70 #define SOFT_RESET_DC (1 << 5)
71 #define SOFT_RESET_DMA1 (1 << 6)
72 #define SOFT_RESET_GRBM (1 << 8)
73 #define SOFT_RESET_HDP (1 << 9)
74 #define SOFT_RESET_IH (1 << 10)
75 #define SOFT_RESET_MC (1 << 11)
76 #define SOFT_RESET_RLC (1 << 13)
77 #define SOFT_RESET_ROM (1 << 14)
78 #define SOFT_RESET_SEM (1 << 15)
79 #define SOFT_RESET_VMC (1 << 17)
80 #define SOFT_RESET_DMA (1 << 20)
81 #define SOFT_RESET_TST (1 << 21)
82 #define SOFT_RESET_REGBB (1 << 22)
83 #define SOFT_RESET_ORB (1 << 23)
85 #define SRBM_STATUS2 0x0EC4
86 #define DMA_BUSY (1 << 5)
87 #define DMA1_BUSY (1 << 6)
89 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
90 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
91 #define RESPONSE_TYPE_MASK 0x000000F0
92 #define RESPONSE_TYPE_SHIFT 4
93 #define VM_L2_CNTL 0x1400
94 #define ENABLE_L2_CACHE (1 << 0)
95 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
96 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
97 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
98 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
99 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
100 /* CONTEXT1_IDENTITY_ACCESS_MODE
101 * 0 physical = logical
102 * 1 logical via context1 page table
103 * 2 inside identity aperture use translation, outside physical = logical
104 * 3 inside identity aperture physical = logical, outside use translation
106 #define VM_L2_CNTL2 0x1404
107 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
108 #define INVALIDATE_L2_CACHE (1 << 1)
109 #define VM_L2_CNTL3 0x1408
110 #define BANK_SELECT(x) ((x) << 0)
111 #define CACHE_UPDATE_MODE(x) ((x) << 6)
112 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
113 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
114 #define VM_L2_STATUS 0x140C
115 #define L2_BUSY (1 << 0)
116 #define VM_CONTEXT0_CNTL 0x1410
117 #define ENABLE_CONTEXT (1 << 0)
118 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
119 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
120 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
121 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
122 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
123 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
124 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
125 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
126 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
127 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
128 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
129 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
130 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
131 #define VM_CONTEXT1_CNTL 0x1414
132 #define VM_CONTEXT0_CNTL2 0x1430
133 #define VM_CONTEXT1_CNTL2 0x1434
134 #define VM_INVALIDATE_REQUEST 0x1478
135 #define VM_INVALIDATE_RESPONSE 0x147c
136 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
137 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
138 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
139 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
140 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
142 #define MC_SHARED_CHMAP 0x2004
143 #define NOOFCHAN_SHIFT 12
144 #define NOOFCHAN_MASK 0x00003000
145 #define MC_SHARED_CHREMAP 0x2008
147 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
148 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
149 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
150 #define MC_VM_MX_L1_TLB_CNTL 0x2064
151 #define ENABLE_L1_TLB (1 << 0)
152 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
153 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
154 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
155 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
156 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
157 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
158 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
159 #define FUS_MC_VM_FB_OFFSET 0x2068
161 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
162 #define MC_ARB_RAMCFG 0x2760
163 #define NOOFBANK_SHIFT 0
164 #define NOOFBANK_MASK 0x00000003
165 #define NOOFRANK_SHIFT 2
166 #define NOOFRANK_MASK 0x00000004
167 #define NOOFROWS_SHIFT 3
168 #define NOOFROWS_MASK 0x00000038
169 #define NOOFCOLS_SHIFT 6
170 #define NOOFCOLS_MASK 0x000000C0
171 #define CHANSIZE_SHIFT 8
172 #define CHANSIZE_MASK 0x00000100
173 #define BURSTLENGTH_SHIFT 9
174 #define BURSTLENGTH_MASK 0x00000200
175 #define CHANSIZE_OVERRIDE (1 << 11)
176 #define MC_SEQ_SUP_CNTL 0x28c8
177 #define RUN_MASK (1 << 0)
178 #define MC_SEQ_SUP_PGM 0x28cc
179 #define MC_IO_PAD_CNTL_D0 0x29d0
180 #define MEM_FALL_OUT_CMD (1 << 8)
181 #define MC_SEQ_MISC0 0x2a00
182 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
183 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
184 #define MC_SEQ_MISC0_GDDR5_VALUE 5
185 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
186 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
188 #define HDP_HOST_PATH_CNTL 0x2C00
189 #define HDP_NONSURFACE_BASE 0x2C04
190 #define HDP_NONSURFACE_INFO 0x2C08
191 #define HDP_NONSURFACE_SIZE 0x2C0C
192 #define HDP_ADDR_CONFIG 0x2F48
193 #define HDP_MISC_CNTL 0x2F4C
194 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
196 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
197 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
198 #define CGTS_SYS_TCC_DISABLE 0x3F90
199 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
201 #define RLC_GFX_INDEX 0x3FC4
203 #define CONFIG_MEMSIZE 0x5428
205 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
206 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
208 #define GRBM_CNTL 0x8000
209 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
210 #define GRBM_STATUS 0x8010
211 #define CMDFIFO_AVAIL_MASK 0x0000000F
212 #define RING2_RQ_PENDING (1 << 4)
213 #define SRBM_RQ_PENDING (1 << 5)
214 #define RING1_RQ_PENDING (1 << 6)
215 #define CF_RQ_PENDING (1 << 7)
216 #define PF_RQ_PENDING (1 << 8)
217 #define GDS_DMA_RQ_PENDING (1 << 9)
218 #define GRBM_EE_BUSY (1 << 10)
219 #define SX_CLEAN (1 << 11)
220 #define DB_CLEAN (1 << 12)
221 #define CB_CLEAN (1 << 13)
222 #define TA_BUSY (1 << 14)
223 #define GDS_BUSY (1 << 15)
224 #define VGT_BUSY_NO_DMA (1 << 16)
225 #define VGT_BUSY (1 << 17)
226 #define IA_BUSY_NO_DMA (1 << 18)
227 #define IA_BUSY (1 << 19)
228 #define SX_BUSY (1 << 20)
229 #define SH_BUSY (1 << 21)
230 #define SPI_BUSY (1 << 22)
231 #define SC_BUSY (1 << 24)
232 #define PA_BUSY (1 << 25)
233 #define DB_BUSY (1 << 26)
234 #define CP_COHERENCY_BUSY (1 << 28)
235 #define CP_BUSY (1 << 29)
236 #define CB_BUSY (1 << 30)
237 #define GUI_ACTIVE (1 << 31)
238 #define GRBM_STATUS_SE0 0x8014
239 #define GRBM_STATUS_SE1 0x8018
240 #define SE_SX_CLEAN (1 << 0)
241 #define SE_DB_CLEAN (1 << 1)
242 #define SE_CB_CLEAN (1 << 2)
243 #define SE_VGT_BUSY (1 << 23)
244 #define SE_PA_BUSY (1 << 24)
245 #define SE_TA_BUSY (1 << 25)
246 #define SE_SX_BUSY (1 << 26)
247 #define SE_SPI_BUSY (1 << 27)
248 #define SE_SH_BUSY (1 << 28)
249 #define SE_SC_BUSY (1 << 29)
250 #define SE_DB_BUSY (1 << 30)
251 #define SE_CB_BUSY (1 << 31)
252 #define GRBM_SOFT_RESET 0x8020
253 #define SOFT_RESET_CP (1 << 0)
254 #define SOFT_RESET_CB (1 << 1)
255 #define SOFT_RESET_DB (1 << 3)
256 #define SOFT_RESET_GDS (1 << 4)
257 #define SOFT_RESET_PA (1 << 5)
258 #define SOFT_RESET_SC (1 << 6)
259 #define SOFT_RESET_SPI (1 << 8)
260 #define SOFT_RESET_SH (1 << 9)
261 #define SOFT_RESET_SX (1 << 10)
262 #define SOFT_RESET_TC (1 << 11)
263 #define SOFT_RESET_TA (1 << 12)
264 #define SOFT_RESET_VGT (1 << 14)
265 #define SOFT_RESET_IA (1 << 15)
267 #define GRBM_GFX_INDEX 0x802C
268 #define INSTANCE_INDEX(x) ((x) << 0)
269 #define SE_INDEX(x) ((x) << 16)
270 #define INSTANCE_BROADCAST_WRITES (1 << 30)
271 #define SE_BROADCAST_WRITES (1 << 31)
273 #define SCRATCH_REG0 0x8500
274 #define SCRATCH_REG1 0x8504
275 #define SCRATCH_REG2 0x8508
276 #define SCRATCH_REG3 0x850C
277 #define SCRATCH_REG4 0x8510
278 #define SCRATCH_REG5 0x8514
279 #define SCRATCH_REG6 0x8518
280 #define SCRATCH_REG7 0x851C
281 #define SCRATCH_UMSK 0x8540
282 #define SCRATCH_ADDR 0x8544
283 #define CP_SEM_WAIT_TIMER 0x85BC
284 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
285 #define CP_COHER_CNTL2 0x85E8
286 #define CP_STALLED_STAT1 0x8674
287 #define CP_STALLED_STAT2 0x8678
288 #define CP_BUSY_STAT 0x867C
289 #define CP_STAT 0x8680
290 #define CP_ME_CNTL 0x86D8
291 #define CP_ME_HALT (1 << 28)
292 #define CP_PFP_HALT (1 << 26)
293 #define CP_RB2_RPTR 0x86f8
294 #define CP_RB1_RPTR 0x86fc
295 #define CP_RB0_RPTR 0x8700
296 #define CP_RB_WPTR_DELAY 0x8704
297 #define CP_MEQ_THRESHOLDS 0x8764
298 #define MEQ1_START(x) ((x) << 0)
299 #define MEQ2_START(x) ((x) << 8)
300 #define CP_PERFMON_CNTL 0x87FC
302 #define VGT_CACHE_INVALIDATION 0x88C4
303 #define CACHE_INVALIDATION(x) ((x) << 0)
307 #define AUTO_INVLD_EN(x) ((x) << 6)
311 #define ES_AND_GS_AUTO 3
312 #define VGT_GS_VERTEX_REUSE 0x88D4
314 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
315 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
316 #define INACTIVE_QD_PIPES(x) ((x) << 8)
317 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
318 #define INACTIVE_QD_PIPES_SHIFT 8
319 #define INACTIVE_SIMDS(x) ((x) << 16)
320 #define INACTIVE_SIMDS_MASK 0xFFFF0000
321 #define INACTIVE_SIMDS_SHIFT 16
323 #define VGT_PRIMITIVE_TYPE 0x8958
324 #define VGT_NUM_INSTANCES 0x8974
325 #define VGT_TF_RING_SIZE 0x8988
326 #define VGT_OFFCHIP_LDS_BASE 0x89b4
328 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
329 #define PA_CL_ENHANCE 0x8A14
330 #define CLIP_VTX_REORDER_ENA (1 << 0)
331 #define NUM_CLIP_SEQ(x) ((x) << 1)
332 #define PA_SC_FIFO_SIZE 0x8BCC
333 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
334 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
335 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
336 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
337 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
338 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
340 #define SQ_CONFIG 0x8C00
341 #define VC_ENABLE (1 << 0)
342 #define EXPORT_SRC_C (1 << 1)
343 #define GFX_PRIO(x) ((x) << 2)
344 #define CS1_PRIO(x) ((x) << 4)
345 #define CS2_PRIO(x) ((x) << 6)
346 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
347 #define NUM_PS_GPRS(x) ((x) << 0)
348 #define NUM_VS_GPRS(x) ((x) << 16)
349 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
350 #define SQ_ESGS_RING_SIZE 0x8c44
351 #define SQ_GSVS_RING_SIZE 0x8c4c
352 #define SQ_ESTMP_RING_BASE 0x8c50
353 #define SQ_ESTMP_RING_SIZE 0x8c54
354 #define SQ_GSTMP_RING_BASE 0x8c58
355 #define SQ_GSTMP_RING_SIZE 0x8c5c
356 #define SQ_VSTMP_RING_BASE 0x8c60
357 #define SQ_VSTMP_RING_SIZE 0x8c64
358 #define SQ_PSTMP_RING_BASE 0x8c68
359 #define SQ_PSTMP_RING_SIZE 0x8c6c
360 #define SQ_MS_FIFO_SIZES 0x8CF0
361 #define CACHE_FIFO_SIZE(x) ((x) << 0)
362 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
363 #define DONE_FIFO_HIWATER(x) ((x) << 16)
364 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
365 #define SQ_LSTMP_RING_BASE 0x8e10
366 #define SQ_LSTMP_RING_SIZE 0x8e14
367 #define SQ_HSTMP_RING_BASE 0x8e18
368 #define SQ_HSTMP_RING_SIZE 0x8e1c
369 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
370 #define DYN_GPR_ENABLE (1 << 8)
371 #define SQ_CONST_MEM_BASE 0x8df8
373 #define SX_EXPORT_BUFFER_SIZES 0x900C
374 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
375 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
376 #define SMX_BUFFER_SIZE(x) ((x) << 16)
377 #define SX_DEBUG_1 0x9058
378 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
380 #define SPI_CONFIG_CNTL 0x9100
381 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
382 #define SPI_CONFIG_CNTL_1 0x913C
383 #define VTX_DONE_DELAY(x) ((x) << 0)
384 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
385 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
387 #define CGTS_TCC_DISABLE 0x9148
388 #define CGTS_USER_TCC_DISABLE 0x914C
389 #define TCC_DISABLE_MASK 0xFFFF0000
390 #define TCC_DISABLE_SHIFT 16
391 #define CGTS_SM_CTRL_REG 0x9150
392 #define OVERRIDE (1 << 21)
394 #define TA_CNTL_AUX 0x9508
395 #define DISABLE_CUBE_WRAP (1 << 0)
396 #define DISABLE_CUBE_ANISO (1 << 1)
398 #define TCP_CHAN_STEER_LO 0x960c
399 #define TCP_CHAN_STEER_HI 0x9610
401 #define CC_RB_BACKEND_DISABLE 0x98F4
402 #define BACKEND_DISABLE(x) ((x) << 16)
403 #define GB_ADDR_CONFIG 0x98F8
404 #define NUM_PIPES(x) ((x) << 0)
405 #define NUM_PIPES_MASK 0x00000007
406 #define NUM_PIPES_SHIFT 0
407 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
408 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
409 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
410 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
411 #define NUM_SHADER_ENGINES(x) ((x) << 12)
412 #define NUM_SHADER_ENGINES_MASK 0x00003000
413 #define NUM_SHADER_ENGINES_SHIFT 12
414 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
415 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
416 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
417 #define NUM_GPUS(x) ((x) << 20)
418 #define NUM_GPUS_MASK 0x00700000
419 #define NUM_GPUS_SHIFT 20
420 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
421 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
422 #define MULTI_GPU_TILE_SIZE_SHIFT 24
423 #define ROW_SIZE(x) ((x) << 28)
424 #define ROW_SIZE_MASK 0x30000000
425 #define ROW_SIZE_SHIFT 28
426 #define NUM_LOWER_PIPES(x) ((x) << 30)
427 #define NUM_LOWER_PIPES_MASK 0x40000000
428 #define NUM_LOWER_PIPES_SHIFT 30
429 #define GB_BACKEND_MAP 0x98FC
431 #define CB_PERF_CTR0_SEL_0 0x9A20
432 #define CB_PERF_CTR0_SEL_1 0x9A24
433 #define CB_PERF_CTR1_SEL_0 0x9A28
434 #define CB_PERF_CTR1_SEL_1 0x9A2C
435 #define CB_PERF_CTR2_SEL_0 0x9A30
436 #define CB_PERF_CTR2_SEL_1 0x9A34
437 #define CB_PERF_CTR3_SEL_0 0x9A38
438 #define CB_PERF_CTR3_SEL_1 0x9A3C
440 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
441 #define BACKEND_DISABLE_MASK 0x00FF0000
442 #define BACKEND_DISABLE_SHIFT 16
444 #define SMX_DC_CTL0 0xA020
445 #define USE_HASH_FUNCTION (1 << 0)
446 #define NUMBER_OF_SETS(x) ((x) << 1)
447 #define FLUSH_ALL_ON_EVENT (1 << 10)
448 #define STALL_ON_EVENT (1 << 11)
449 #define SMX_EVENT_CTL 0xA02C
450 #define ES_FLUSH_CTL(x) ((x) << 0)
451 #define GS_FLUSH_CTL(x) ((x) << 3)
452 #define ACK_FLUSH_CTL(x) ((x) << 6)
453 #define SYNC_FLUSH_CTL (1 << 8)
455 #define CP_RB0_BASE 0xC100
456 #define CP_RB0_CNTL 0xC104
457 #define RB_BUFSZ(x) ((x) << 0)
458 #define RB_BLKSZ(x) ((x) << 8)
459 #define RB_NO_UPDATE (1 << 27)
460 #define RB_RPTR_WR_ENA (1 << 31)
461 #define BUF_SWAP_32BIT (2 << 16)
462 #define CP_RB0_RPTR_ADDR 0xC10C
463 #define CP_RB0_RPTR_ADDR_HI 0xC110
464 #define CP_RB0_WPTR 0xC114
466 #define CP_INT_CNTL 0xC124
467 # define CNTX_BUSY_INT_ENABLE (1 << 19)
468 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
469 # define TIME_STAMP_INT_ENABLE (1 << 26)
471 #define CP_RB1_BASE 0xC180
472 #define CP_RB1_CNTL 0xC184
473 #define CP_RB1_RPTR_ADDR 0xC188
474 #define CP_RB1_RPTR_ADDR_HI 0xC18C
475 #define CP_RB1_WPTR 0xC190
476 #define CP_RB2_BASE 0xC194
477 #define CP_RB2_CNTL 0xC198
478 #define CP_RB2_RPTR_ADDR 0xC19C
479 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
480 #define CP_RB2_WPTR 0xC1A4
481 #define CP_PFP_UCODE_ADDR 0xC150
482 #define CP_PFP_UCODE_DATA 0xC154
483 #define CP_ME_RAM_RADDR 0xC158
484 #define CP_ME_RAM_WADDR 0xC15C
485 #define CP_ME_RAM_DATA 0xC160
486 #define CP_DEBUG 0xC1FC
488 #define VGT_EVENT_INITIATOR 0x28a90
489 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
490 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
492 /* TN SMU registers */
493 #define TN_CURRENT_GNB_TEMP 0x1F390
498 #define UVD_SEMA_ADDR_LOW 0xEF00
499 #define UVD_SEMA_ADDR_HIGH 0xEF04
500 #define UVD_SEMA_CMD 0xEF08
501 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
502 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
503 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
504 #define UVD_RBC_RB_RPTR 0xF690
505 #define UVD_RBC_RB_WPTR 0xF694
510 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
511 (((reg) >> 2) & 0xFFFF) | \
512 ((n) & 0x3FFF) << 16)
513 #define CP_PACKET2 0x80000000
514 #define PACKET2_PAD_SHIFT 0
515 #define PACKET2_PAD_MASK (0x3fffffff << 0)
517 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
519 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
520 (((op) & 0xFF) << 8) | \
521 ((n) & 0x3FFF) << 16)
524 #define PACKET3_NOP 0x10
525 #define PACKET3_SET_BASE 0x11
526 #define PACKET3_CLEAR_STATE 0x12
527 #define PACKET3_INDEX_BUFFER_SIZE 0x13
528 #define PACKET3_DEALLOC_STATE 0x14
529 #define PACKET3_DISPATCH_DIRECT 0x15
530 #define PACKET3_DISPATCH_INDIRECT 0x16
531 #define PACKET3_INDIRECT_BUFFER_END 0x17
532 #define PACKET3_MODE_CONTROL 0x18
533 #define PACKET3_SET_PREDICATION 0x20
534 #define PACKET3_REG_RMW 0x21
535 #define PACKET3_COND_EXEC 0x22
536 #define PACKET3_PRED_EXEC 0x23
537 #define PACKET3_DRAW_INDIRECT 0x24
538 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
539 #define PACKET3_INDEX_BASE 0x26
540 #define PACKET3_DRAW_INDEX_2 0x27
541 #define PACKET3_CONTEXT_CONTROL 0x28
542 #define PACKET3_DRAW_INDEX_OFFSET 0x29
543 #define PACKET3_INDEX_TYPE 0x2A
544 #define PACKET3_DRAW_INDEX 0x2B
545 #define PACKET3_DRAW_INDEX_AUTO 0x2D
546 #define PACKET3_DRAW_INDEX_IMMD 0x2E
547 #define PACKET3_NUM_INSTANCES 0x2F
548 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
549 #define PACKET3_INDIRECT_BUFFER 0x32
550 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
551 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
552 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
553 #define PACKET3_WRITE_DATA 0x37
554 #define PACKET3_MEM_SEMAPHORE 0x39
555 #define PACKET3_MPEG_INDEX 0x3A
556 #define PACKET3_WAIT_REG_MEM 0x3C
557 #define PACKET3_MEM_WRITE 0x3D
558 #define PACKET3_PFP_SYNC_ME 0x42
559 #define PACKET3_SURFACE_SYNC 0x43
560 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
561 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
562 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
563 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
564 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
565 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
566 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
567 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
568 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
569 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
570 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
571 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
572 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
573 # define PACKET3_FULL_CACHE_ENA (1 << 20)
574 # define PACKET3_TC_ACTION_ENA (1 << 23)
575 # define PACKET3_CB_ACTION_ENA (1 << 25)
576 # define PACKET3_DB_ACTION_ENA (1 << 26)
577 # define PACKET3_SH_ACTION_ENA (1 << 27)
578 # define PACKET3_SX_ACTION_ENA (1 << 28)
579 #define PACKET3_ME_INITIALIZE 0x44
580 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
581 #define PACKET3_COND_WRITE 0x45
582 #define PACKET3_EVENT_WRITE 0x46
583 #define EVENT_TYPE(x) ((x) << 0)
584 #define EVENT_INDEX(x) ((x) << 8)
585 /* 0 - any non-TS event
587 * 2 - SAMPLE_PIPELINESTAT
588 * 3 - SAMPLE_STREAMOUTSTAT*
589 * 4 - *S_PARTIAL_FLUSH
592 #define PACKET3_EVENT_WRITE_EOP 0x47
593 #define DATA_SEL(x) ((x) << 29)
595 * 1 - send low 32bit data
596 * 2 - send 64bit data
597 * 3 - send 64bit counter value
599 #define INT_SEL(x) ((x) << 24)
601 * 1 - interrupt only (DATA_SEL = 0)
602 * 2 - interrupt when data write is confirmed
604 #define PACKET3_EVENT_WRITE_EOS 0x48
605 #define PACKET3_PREAMBLE_CNTL 0x4A
606 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
607 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
608 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
609 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
610 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
611 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
612 #define PACKET3_ONE_REG_WRITE 0x57
613 #define PACKET3_SET_CONFIG_REG 0x68
614 #define PACKET3_SET_CONFIG_REG_START 0x00008000
615 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
616 #define PACKET3_SET_CONTEXT_REG 0x69
617 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
618 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
619 #define PACKET3_SET_ALU_CONST 0x6A
620 /* alu const buffers only; no reg file */
621 #define PACKET3_SET_BOOL_CONST 0x6B
622 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
623 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
624 #define PACKET3_SET_LOOP_CONST 0x6C
625 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
626 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
627 #define PACKET3_SET_RESOURCE 0x6D
628 #define PACKET3_SET_RESOURCE_START 0x00030000
629 #define PACKET3_SET_RESOURCE_END 0x00038000
630 #define PACKET3_SET_SAMPLER 0x6E
631 #define PACKET3_SET_SAMPLER_START 0x0003c000
632 #define PACKET3_SET_SAMPLER_END 0x0003c600
633 #define PACKET3_SET_CTL_CONST 0x6F
634 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
635 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
636 #define PACKET3_SET_RESOURCE_OFFSET 0x70
637 #define PACKET3_SET_ALU_CONST_VS 0x71
638 #define PACKET3_SET_ALU_CONST_DI 0x72
639 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
640 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
641 #define PACKET3_SET_APPEND_CNT 0x75
642 #define PACKET3_ME_WRITE 0x7A
644 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
645 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
646 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
648 #define DMA_RB_CNTL 0xd000
649 # define DMA_RB_ENABLE (1 << 0)
650 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
651 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
652 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
653 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
654 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
655 #define DMA_RB_BASE 0xd004
656 #define DMA_RB_RPTR 0xd008
657 #define DMA_RB_WPTR 0xd00c
659 #define DMA_RB_RPTR_ADDR_HI 0xd01c
660 #define DMA_RB_RPTR_ADDR_LO 0xd020
662 #define DMA_IB_CNTL 0xd024
663 # define DMA_IB_ENABLE (1 << 0)
664 # define DMA_IB_SWAP_ENABLE (1 << 4)
665 # define CMD_VMID_FORCE (1 << 31)
666 #define DMA_IB_RPTR 0xd028
667 #define DMA_CNTL 0xd02c
668 # define TRAP_ENABLE (1 << 0)
669 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
670 # define SEM_WAIT_INT_ENABLE (1 << 2)
671 # define DATA_SWAP_ENABLE (1 << 3)
672 # define FENCE_SWAP_ENABLE (1 << 4)
673 # define CTXEMPTY_INT_ENABLE (1 << 28)
674 #define DMA_STATUS_REG 0xd034
675 # define DMA_IDLE (1 << 0)
676 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
677 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
678 #define DMA_TILING_CONFIG 0xd0b8
679 #define DMA_MODE 0xd0bc
681 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
682 (((t) & 0x1) << 23) | \
683 (((s) & 0x1) << 22) | \
684 (((n) & 0xFFFFF) << 0))
686 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
687 (((vmid) & 0xF) << 20) | \
688 (((n) & 0xFFFFF) << 0))
690 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
693 (((n) & 0xFFFFF) << 0))
695 /* async DMA Packet types */
696 #define DMA_PACKET_WRITE 0x2
697 #define DMA_PACKET_COPY 0x3
698 #define DMA_PACKET_INDIRECT_BUFFER 0x4
699 #define DMA_PACKET_SEMAPHORE 0x5
700 #define DMA_PACKET_FENCE 0x6
701 #define DMA_PACKET_TRAP 0x7
702 #define DMA_PACKET_SRBM_WRITE 0x9
703 #define DMA_PACKET_CONSTANT_FILL 0xd
704 #define DMA_PACKET_NOP 0xf
This page took 0.045715 seconds and 5 git commands to generate.
projects / deliverable / linux.git / blob