2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
40 #include <linux/firmware.h>
41 #include <linux/platform_device.h>
43 #include "r100_reg_safe.h"
44 #include "rn50_reg_safe.h"
47 #define FIRMWARE_R100 "radeon/R100_cp.bin"
48 #define FIRMWARE_R200 "radeon/R200_cp.bin"
49 #define FIRMWARE_R300 "radeon/R300_cp.bin"
50 #define FIRMWARE_R420 "radeon/R420_cp.bin"
51 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
52 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
53 #define FIRMWARE_R520 "radeon/R520_cp.bin"
55 MODULE_FIRMWARE(FIRMWARE_R100
);
56 MODULE_FIRMWARE(FIRMWARE_R200
);
57 MODULE_FIRMWARE(FIRMWARE_R300
);
58 MODULE_FIRMWARE(FIRMWARE_R420
);
59 MODULE_FIRMWARE(FIRMWARE_RS690
);
60 MODULE_FIRMWARE(FIRMWARE_RS600
);
61 MODULE_FIRMWARE(FIRMWARE_R520
);
63 #include "r100_track.h"
65 /* This files gather functions specifics to:
66 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 /* hpd for digital panel detect/disconnect */
70 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
72 bool connected
= false;
76 if (RREG32(RADEON_FP_GEN_CNTL
) & RADEON_FP_DETECT_SENSE
)
80 if (RREG32(RADEON_FP2_GEN_CNTL
) & RADEON_FP2_DETECT_SENSE
)
89 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
90 enum radeon_hpd_id hpd
)
93 bool connected
= r100_hpd_sense(rdev
, hpd
);
97 tmp
= RREG32(RADEON_FP_GEN_CNTL
);
99 tmp
&= ~RADEON_FP_DETECT_INT_POL
;
101 tmp
|= RADEON_FP_DETECT_INT_POL
;
102 WREG32(RADEON_FP_GEN_CNTL
, tmp
);
105 tmp
= RREG32(RADEON_FP2_GEN_CNTL
);
107 tmp
&= ~RADEON_FP2_DETECT_INT_POL
;
109 tmp
|= RADEON_FP2_DETECT_INT_POL
;
110 WREG32(RADEON_FP2_GEN_CNTL
, tmp
);
117 void r100_hpd_init(struct radeon_device
*rdev
)
119 struct drm_device
*dev
= rdev
->ddev
;
120 struct drm_connector
*connector
;
122 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
123 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
124 switch (radeon_connector
->hpd
.hpd
) {
126 rdev
->irq
.hpd
[0] = true;
129 rdev
->irq
.hpd
[1] = true;
135 if (rdev
->irq
.installed
)
139 void r100_hpd_fini(struct radeon_device
*rdev
)
141 struct drm_device
*dev
= rdev
->ddev
;
142 struct drm_connector
*connector
;
144 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
145 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
146 switch (radeon_connector
->hpd
.hpd
) {
148 rdev
->irq
.hpd
[0] = false;
151 rdev
->irq
.hpd
[1] = false;
162 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
)
164 /* TODO: can we do somethings here ? */
165 /* It seems hw only cache one entry so we should discard this
166 * entry otherwise if first GPU GART read hit this entry it
167 * could end up in wrong address. */
170 int r100_pci_gart_init(struct radeon_device
*rdev
)
174 if (rdev
->gart
.table
.ram
.ptr
) {
175 WARN(1, "R100 PCI GART already initialized.\n");
178 /* Initialize common gart structure */
179 r
= radeon_gart_init(rdev
);
182 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
183 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
184 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
185 return radeon_gart_table_ram_alloc(rdev
);
188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189 void r100_enable_bm(struct radeon_device
*rdev
)
192 /* Enable bus mastering */
193 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
194 WREG32(RADEON_BUS_CNTL
, tmp
);
197 int r100_pci_gart_enable(struct radeon_device
*rdev
)
201 radeon_gart_restore(rdev
);
202 /* discard memory request outside of configured range */
203 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
204 WREG32(RADEON_AIC_CNTL
, tmp
);
205 /* set address range for PCI address translate */
206 WREG32(RADEON_AIC_LO_ADDR
, rdev
->mc
.gtt_start
);
207 WREG32(RADEON_AIC_HI_ADDR
, rdev
->mc
.gtt_end
);
208 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE
, rdev
->gart
.table_addr
);
210 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_PCIGART_TRANSLATE_EN
;
211 WREG32(RADEON_AIC_CNTL
, tmp
);
212 r100_pci_gart_tlb_flush(rdev
);
213 rdev
->gart
.ready
= true;
217 void r100_pci_gart_disable(struct radeon_device
*rdev
)
221 /* discard memory request outside of configured range */
222 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
223 WREG32(RADEON_AIC_CNTL
, tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
224 WREG32(RADEON_AIC_LO_ADDR
, 0);
225 WREG32(RADEON_AIC_HI_ADDR
, 0);
228 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
230 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
233 rdev
->gart
.table
.ram
.ptr
[i
] = cpu_to_le32(lower_32_bits(addr
));
237 void r100_pci_gart_fini(struct radeon_device
*rdev
)
239 radeon_gart_fini(rdev
);
240 r100_pci_gart_disable(rdev
);
241 radeon_gart_table_ram_free(rdev
);
244 int r100_irq_set(struct radeon_device
*rdev
)
248 if (!rdev
->irq
.installed
) {
249 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250 WREG32(R_000040_GEN_INT_CNTL
, 0);
253 if (rdev
->irq
.sw_int
) {
254 tmp
|= RADEON_SW_INT_ENABLE
;
256 if (rdev
->irq
.crtc_vblank_int
[0]) {
257 tmp
|= RADEON_CRTC_VBLANK_MASK
;
259 if (rdev
->irq
.crtc_vblank_int
[1]) {
260 tmp
|= RADEON_CRTC2_VBLANK_MASK
;
262 if (rdev
->irq
.hpd
[0]) {
263 tmp
|= RADEON_FP_DETECT_MASK
;
265 if (rdev
->irq
.hpd
[1]) {
266 tmp
|= RADEON_FP2_DETECT_MASK
;
268 WREG32(RADEON_GEN_INT_CNTL
, tmp
);
272 void r100_irq_disable(struct radeon_device
*rdev
)
276 WREG32(R_000040_GEN_INT_CNTL
, 0);
277 /* Wait and acknowledge irq */
279 tmp
= RREG32(R_000044_GEN_INT_STATUS
);
280 WREG32(R_000044_GEN_INT_STATUS
, tmp
);
283 static inline uint32_t r100_irq_ack(struct radeon_device
*rdev
)
285 uint32_t irqs
= RREG32(RADEON_GEN_INT_STATUS
);
286 uint32_t irq_mask
= RADEON_SW_INT_TEST
|
287 RADEON_CRTC_VBLANK_STAT
| RADEON_CRTC2_VBLANK_STAT
|
288 RADEON_FP_DETECT_STAT
| RADEON_FP2_DETECT_STAT
;
291 WREG32(RADEON_GEN_INT_STATUS
, irqs
);
293 return irqs
& irq_mask
;
296 int r100_irq_process(struct radeon_device
*rdev
)
298 uint32_t status
, msi_rearm
;
299 bool queue_hotplug
= false;
301 status
= r100_irq_ack(rdev
);
305 if (rdev
->shutdown
) {
310 if (status
& RADEON_SW_INT_TEST
) {
311 radeon_fence_process(rdev
);
313 /* Vertical blank interrupts */
314 if (status
& RADEON_CRTC_VBLANK_STAT
) {
315 drm_handle_vblank(rdev
->ddev
, 0);
316 rdev
->pm
.vblank_sync
= true;
317 wake_up(&rdev
->irq
.vblank_queue
);
319 if (status
& RADEON_CRTC2_VBLANK_STAT
) {
320 drm_handle_vblank(rdev
->ddev
, 1);
321 rdev
->pm
.vblank_sync
= true;
322 wake_up(&rdev
->irq
.vblank_queue
);
324 if (status
& RADEON_FP_DETECT_STAT
) {
325 queue_hotplug
= true;
328 if (status
& RADEON_FP2_DETECT_STAT
) {
329 queue_hotplug
= true;
332 status
= r100_irq_ack(rdev
);
335 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
336 if (rdev
->msi_enabled
) {
337 switch (rdev
->family
) {
340 msi_rearm
= RREG32(RADEON_AIC_CNTL
) & ~RS400_MSI_REARM
;
341 WREG32(RADEON_AIC_CNTL
, msi_rearm
);
342 WREG32(RADEON_AIC_CNTL
, msi_rearm
| RS400_MSI_REARM
);
345 msi_rearm
= RREG32(RADEON_MSI_REARM_EN
) & ~RV370_MSI_REARM_EN
;
346 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
);
347 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
| RV370_MSI_REARM_EN
);
354 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
357 return RREG32(RADEON_CRTC_CRNT_FRAME
);
359 return RREG32(RADEON_CRTC2_CRNT_FRAME
);
362 /* Who ever call radeon_fence_emit should call ring_lock and ask
363 * for enough space (today caller are ib schedule and buffer move) */
364 void r100_fence_ring_emit(struct radeon_device
*rdev
,
365 struct radeon_fence
*fence
)
367 /* We have to make sure that caches are flushed before
368 * CPU might read something from VRAM. */
369 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT
, 0));
370 radeon_ring_write(rdev
, RADEON_RB3D_DC_FLUSH_ALL
);
371 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT
, 0));
372 radeon_ring_write(rdev
, RADEON_RB3D_ZC_FLUSH_ALL
);
373 /* Wait until IDLE & CLEAN */
374 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
375 radeon_ring_write(rdev
, RADEON_WAIT_2D_IDLECLEAN
| RADEON_WAIT_3D_IDLECLEAN
);
376 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
377 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
|
378 RADEON_HDP_READ_BUFFER_INVALIDATE
);
379 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
380 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
);
381 /* Emit fence sequence & fire IRQ */
382 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
383 radeon_ring_write(rdev
, fence
->seq
);
384 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
385 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
388 int r100_wb_init(struct radeon_device
*rdev
)
392 if (rdev
->wb
.wb_obj
== NULL
) {
393 r
= radeon_bo_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
, true,
394 RADEON_GEM_DOMAIN_GTT
,
397 dev_err(rdev
->dev
, "(%d) create WB buffer failed\n", r
);
400 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
401 if (unlikely(r
!= 0))
403 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
406 dev_err(rdev
->dev
, "(%d) pin WB buffer failed\n", r
);
407 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
410 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
411 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
413 dev_err(rdev
->dev
, "(%d) map WB buffer failed\n", r
);
417 WREG32(R_000774_SCRATCH_ADDR
, rdev
->wb
.gpu_addr
);
418 WREG32(R_00070C_CP_RB_RPTR_ADDR
,
419 S_00070C_RB_RPTR_ADDR((rdev
->wb
.gpu_addr
+ 1024) >> 2));
420 WREG32(R_000770_SCRATCH_UMSK
, 0xff);
424 void r100_wb_disable(struct radeon_device
*rdev
)
426 WREG32(R_000770_SCRATCH_UMSK
, 0);
429 void r100_wb_fini(struct radeon_device
*rdev
)
433 r100_wb_disable(rdev
);
434 if (rdev
->wb
.wb_obj
) {
435 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
436 if (unlikely(r
!= 0)) {
437 dev_err(rdev
->dev
, "(%d) can't finish WB\n", r
);
440 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
441 radeon_bo_unpin(rdev
->wb
.wb_obj
);
442 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
443 radeon_bo_unref(&rdev
->wb
.wb_obj
);
445 rdev
->wb
.wb_obj
= NULL
;
449 int r100_copy_blit(struct radeon_device
*rdev
,
453 struct radeon_fence
*fence
)
456 uint32_t stride_bytes
= PAGE_SIZE
;
458 uint32_t stride_pixels
;
463 /* radeon limited to 16k stride */
464 stride_bytes
&= 0x3fff;
465 /* radeon pitch is /64 */
466 pitch
= stride_bytes
/ 64;
467 stride_pixels
= stride_bytes
/ 4;
468 num_loops
= DIV_ROUND_UP(num_pages
, 8191);
470 /* Ask for enough room for blit + flush + fence */
471 ndw
= 64 + (10 * num_loops
);
472 r
= radeon_ring_lock(rdev
, ndw
);
474 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r
, ndw
);
477 while (num_pages
> 0) {
478 cur_pages
= num_pages
;
479 if (cur_pages
> 8191) {
482 num_pages
-= cur_pages
;
484 /* pages are in Y direction - height
485 page width in X direction - width */
486 radeon_ring_write(rdev
, PACKET3(PACKET3_BITBLT_MULTI
, 8));
487 radeon_ring_write(rdev
,
488 RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
489 RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
490 RADEON_GMC_SRC_CLIPPING
|
491 RADEON_GMC_DST_CLIPPING
|
492 RADEON_GMC_BRUSH_NONE
|
493 (RADEON_COLOR_FORMAT_ARGB8888
<< 8) |
494 RADEON_GMC_SRC_DATATYPE_COLOR
|
496 RADEON_DP_SRC_SOURCE_MEMORY
|
497 RADEON_GMC_CLR_CMP_CNTL_DIS
|
498 RADEON_GMC_WR_MSK_DIS
);
499 radeon_ring_write(rdev
, (pitch
<< 22) | (src_offset
>> 10));
500 radeon_ring_write(rdev
, (pitch
<< 22) | (dst_offset
>> 10));
501 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
502 radeon_ring_write(rdev
, 0);
503 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
504 radeon_ring_write(rdev
, num_pages
);
505 radeon_ring_write(rdev
, num_pages
);
506 radeon_ring_write(rdev
, cur_pages
| (stride_pixels
<< 16));
508 radeon_ring_write(rdev
, PACKET0(RADEON_DSTCACHE_CTLSTAT
, 0));
509 radeon_ring_write(rdev
, RADEON_RB2D_DC_FLUSH_ALL
);
510 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
511 radeon_ring_write(rdev
,
512 RADEON_WAIT_2D_IDLECLEAN
|
513 RADEON_WAIT_HOST_IDLECLEAN
|
514 RADEON_WAIT_DMA_GUI_IDLE
);
516 r
= radeon_fence_emit(rdev
, fence
);
518 radeon_ring_unlock_commit(rdev
);
522 static int r100_cp_wait_for_idle(struct radeon_device
*rdev
)
527 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
528 tmp
= RREG32(R_000E40_RBBM_STATUS
);
529 if (!G_000E40_CP_CMDSTRM_BUSY(tmp
)) {
537 void r100_ring_start(struct radeon_device
*rdev
)
541 r
= radeon_ring_lock(rdev
, 2);
545 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
546 radeon_ring_write(rdev
,
547 RADEON_ISYNC_ANY2D_IDLE3D
|
548 RADEON_ISYNC_ANY3D_IDLE2D
|
549 RADEON_ISYNC_WAIT_IDLEGUI
|
550 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
551 radeon_ring_unlock_commit(rdev
);
555 /* Load the microcode for the CP */
556 static int r100_cp_init_microcode(struct radeon_device
*rdev
)
558 struct platform_device
*pdev
;
559 const char *fw_name
= NULL
;
564 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
567 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
570 if ((rdev
->family
== CHIP_R100
) || (rdev
->family
== CHIP_RV100
) ||
571 (rdev
->family
== CHIP_RV200
) || (rdev
->family
== CHIP_RS100
) ||
572 (rdev
->family
== CHIP_RS200
)) {
573 DRM_INFO("Loading R100 Microcode\n");
574 fw_name
= FIRMWARE_R100
;
575 } else if ((rdev
->family
== CHIP_R200
) ||
576 (rdev
->family
== CHIP_RV250
) ||
577 (rdev
->family
== CHIP_RV280
) ||
578 (rdev
->family
== CHIP_RS300
)) {
579 DRM_INFO("Loading R200 Microcode\n");
580 fw_name
= FIRMWARE_R200
;
581 } else if ((rdev
->family
== CHIP_R300
) ||
582 (rdev
->family
== CHIP_R350
) ||
583 (rdev
->family
== CHIP_RV350
) ||
584 (rdev
->family
== CHIP_RV380
) ||
585 (rdev
->family
== CHIP_RS400
) ||
586 (rdev
->family
== CHIP_RS480
)) {
587 DRM_INFO("Loading R300 Microcode\n");
588 fw_name
= FIRMWARE_R300
;
589 } else if ((rdev
->family
== CHIP_R420
) ||
590 (rdev
->family
== CHIP_R423
) ||
591 (rdev
->family
== CHIP_RV410
)) {
592 DRM_INFO("Loading R400 Microcode\n");
593 fw_name
= FIRMWARE_R420
;
594 } else if ((rdev
->family
== CHIP_RS690
) ||
595 (rdev
->family
== CHIP_RS740
)) {
596 DRM_INFO("Loading RS690/RS740 Microcode\n");
597 fw_name
= FIRMWARE_RS690
;
598 } else if (rdev
->family
== CHIP_RS600
) {
599 DRM_INFO("Loading RS600 Microcode\n");
600 fw_name
= FIRMWARE_RS600
;
601 } else if ((rdev
->family
== CHIP_RV515
) ||
602 (rdev
->family
== CHIP_R520
) ||
603 (rdev
->family
== CHIP_RV530
) ||
604 (rdev
->family
== CHIP_R580
) ||
605 (rdev
->family
== CHIP_RV560
) ||
606 (rdev
->family
== CHIP_RV570
)) {
607 DRM_INFO("Loading R500 Microcode\n");
608 fw_name
= FIRMWARE_R520
;
611 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
612 platform_device_unregister(pdev
);
614 printk(KERN_ERR
"radeon_cp: Failed to load firmware \"%s\"\n",
616 } else if (rdev
->me_fw
->size
% 8) {
618 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
619 rdev
->me_fw
->size
, fw_name
);
621 release_firmware(rdev
->me_fw
);
627 static void r100_cp_load_microcode(struct radeon_device
*rdev
)
629 const __be32
*fw_data
;
632 if (r100_gui_wait_for_idle(rdev
)) {
633 printk(KERN_WARNING
"Failed to wait GUI idle while "
634 "programming pipes. Bad things might happen.\n");
638 size
= rdev
->me_fw
->size
/ 4;
639 fw_data
= (const __be32
*)&rdev
->me_fw
->data
[0];
640 WREG32(RADEON_CP_ME_RAM_ADDR
, 0);
641 for (i
= 0; i
< size
; i
+= 2) {
642 WREG32(RADEON_CP_ME_RAM_DATAH
,
643 be32_to_cpup(&fw_data
[i
]));
644 WREG32(RADEON_CP_ME_RAM_DATAL
,
645 be32_to_cpup(&fw_data
[i
+ 1]));
650 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
)
655 unsigned pre_write_timer
;
656 unsigned pre_write_limit
;
657 unsigned indirect2_start
;
658 unsigned indirect1_start
;
662 if (r100_debugfs_cp_init(rdev
)) {
663 DRM_ERROR("Failed to register debugfs file for CP !\n");
666 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
667 if ((tmp
& (1 << 31))) {
668 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp
);
669 WREG32(RADEON_CP_CSQ_MODE
, 0);
670 WREG32(RADEON_CP_CSQ_CNTL
, 0);
671 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
672 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
674 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
675 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
677 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
678 if ((tmp
& (1 << 31))) {
679 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp
);
682 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp
);
686 r
= r100_cp_init_microcode(rdev
);
688 DRM_ERROR("Failed to load firmware!\n");
693 /* Align ring size */
694 rb_bufsz
= drm_order(ring_size
/ 8);
695 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
696 r100_cp_load_microcode(rdev
);
697 r
= radeon_ring_init(rdev
, ring_size
);
701 /* Each time the cp read 1024 bytes (16 dword/quadword) update
702 * the rptr copy in system ram */
704 /* cp will read 128bytes at a time (4 dwords) */
706 rdev
->cp
.align_mask
= 16 - 1;
707 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
708 pre_write_timer
= 64;
709 /* Force CP_RB_WPTR write if written more than one time before the
713 /* Setup the cp cache like this (cache size is 96 dwords) :
717 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
719 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
720 * Idea being that most of the gpu cmd will be through indirect1 buffer
721 * so it gets the bigger cache.
723 indirect2_start
= 80;
724 indirect1_start
= 16;
726 WREG32(0x718, pre_write_timer
| (pre_write_limit
<< 28));
727 tmp
= (REG_SET(RADEON_RB_BUFSZ
, rb_bufsz
) |
728 REG_SET(RADEON_RB_BLKSZ
, rb_blksz
) |
729 REG_SET(RADEON_MAX_FETCH
, max_fetch
) |
730 RADEON_RB_NO_UPDATE
);
732 tmp
|= RADEON_BUF_SWAP_32BIT
;
734 WREG32(RADEON_CP_RB_CNTL
, tmp
);
736 /* Set ring address */
737 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev
->cp
.gpu_addr
);
738 WREG32(RADEON_CP_RB_BASE
, rdev
->cp
.gpu_addr
);
739 /* Force read & write ptr to 0 */
740 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
741 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
742 WREG32(RADEON_CP_RB_WPTR
, 0);
743 WREG32(RADEON_CP_RB_CNTL
, tmp
);
745 rdev
->cp
.rptr
= RREG32(RADEON_CP_RB_RPTR
);
746 rdev
->cp
.wptr
= RREG32(RADEON_CP_RB_WPTR
);
747 /* protect against crazy HW on resume */
748 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
749 /* Set cp mode to bus mastering & enable cp*/
750 WREG32(RADEON_CP_CSQ_MODE
,
751 REG_SET(RADEON_INDIRECT2_START
, indirect2_start
) |
752 REG_SET(RADEON_INDIRECT1_START
, indirect1_start
));
754 WREG32(0x744, 0x00004D4D);
755 WREG32(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIBM_INDBM
);
756 radeon_ring_start(rdev
);
757 r
= radeon_ring_test(rdev
);
759 DRM_ERROR("radeon: cp isn't working (%d).\n", r
);
762 rdev
->cp
.ready
= true;
766 void r100_cp_fini(struct radeon_device
*rdev
)
768 if (r100_cp_wait_for_idle(rdev
)) {
769 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
772 r100_cp_disable(rdev
);
773 radeon_ring_fini(rdev
);
774 DRM_INFO("radeon: cp finalized\n");
777 void r100_cp_disable(struct radeon_device
*rdev
)
780 rdev
->cp
.ready
= false;
781 WREG32(RADEON_CP_CSQ_MODE
, 0);
782 WREG32(RADEON_CP_CSQ_CNTL
, 0);
783 if (r100_gui_wait_for_idle(rdev
)) {
784 printk(KERN_WARNING
"Failed to wait GUI idle while "
785 "programming pipes. Bad things might happen.\n");
789 int r100_cp_reset(struct radeon_device
*rdev
)
795 reinit_cp
= rdev
->cp
.ready
;
796 rdev
->cp
.ready
= false;
797 WREG32(RADEON_CP_CSQ_MODE
, 0);
798 WREG32(RADEON_CP_CSQ_CNTL
, 0);
799 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
800 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
802 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
803 /* Wait to prevent race in RBBM_STATUS */
805 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
806 tmp
= RREG32(RADEON_RBBM_STATUS
);
807 if (!(tmp
& (1 << 16))) {
808 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
811 return r100_cp_init(rdev
, rdev
->cp
.ring_size
);
817 tmp
= RREG32(RADEON_RBBM_STATUS
);
818 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp
);
822 void r100_cp_commit(struct radeon_device
*rdev
)
824 WREG32(RADEON_CP_RB_WPTR
, rdev
->cp
.wptr
);
825 (void)RREG32(RADEON_CP_RB_WPTR
);
832 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
833 struct radeon_cs_packet
*pkt
,
834 const unsigned *auth
, unsigned n
,
835 radeon_packet0_check_t check
)
844 /* Check that register fall into register range
845 * determined by the number of entry (n) in the
846 * safe register bitmap.
848 if (pkt
->one_reg_wr
) {
849 if ((reg
>> 7) > n
) {
853 if (((reg
+ (pkt
->count
<< 2)) >> 7) > n
) {
857 for (i
= 0; i
<= pkt
->count
; i
++, idx
++) {
859 m
= 1 << ((reg
>> 2) & 31);
861 r
= check(p
, pkt
, idx
, reg
);
866 if (pkt
->one_reg_wr
) {
867 if (!(auth
[j
] & m
)) {
877 void r100_cs_dump_packet(struct radeon_cs_parser
*p
,
878 struct radeon_cs_packet
*pkt
)
880 volatile uint32_t *ib
;
886 for (i
= 0; i
<= (pkt
->count
+ 1); i
++, idx
++) {
887 DRM_INFO("ib[%d]=0x%08X\n", idx
, ib
[idx
]);
892 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
893 * @parser: parser structure holding parsing context.
894 * @pkt: where to store packet informations
896 * Assume that chunk_ib_index is properly set. Will return -EINVAL
897 * if packet is bigger than remaining ib size. or if packets is unknown.
899 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
900 struct radeon_cs_packet
*pkt
,
903 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
906 if (idx
>= ib_chunk
->length_dw
) {
907 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
908 idx
, ib_chunk
->length_dw
);
911 header
= radeon_get_ib_value(p
, idx
);
913 pkt
->type
= CP_PACKET_GET_TYPE(header
);
914 pkt
->count
= CP_PACKET_GET_COUNT(header
);
917 pkt
->reg
= CP_PACKET0_GET_REG(header
);
918 pkt
->one_reg_wr
= CP_PACKET0_GET_ONE_REG_WR(header
);
921 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
927 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
930 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
931 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
932 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
939 * r100_cs_packet_next_vline() - parse userspace VLINE packet
940 * @parser: parser structure holding parsing context.
942 * Userspace sends a special sequence for VLINE waits.
943 * PACKET0 - VLINE_START_END + value
944 * PACKET0 - WAIT_UNTIL +_value
945 * RELOC (P3) - crtc_id in reloc.
947 * This function parses this and relocates the VLINE START END
948 * and WAIT UNTIL packets to the correct crtc.
949 * It also detects a switched off crtc and nulls out the
952 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
954 struct drm_mode_object
*obj
;
955 struct drm_crtc
*crtc
;
956 struct radeon_crtc
*radeon_crtc
;
957 struct radeon_cs_packet p3reloc
, waitreloc
;
960 uint32_t header
, h_idx
, reg
;
961 volatile uint32_t *ib
;
965 /* parse the wait until */
966 r
= r100_cs_packet_parse(p
, &waitreloc
, p
->idx
);
970 /* check its a wait until and only 1 count */
971 if (waitreloc
.reg
!= RADEON_WAIT_UNTIL
||
972 waitreloc
.count
!= 0) {
973 DRM_ERROR("vline wait had illegal wait until segment\n");
978 if (radeon_get_ib_value(p
, waitreloc
.idx
+ 1) != RADEON_WAIT_CRTC_VLINE
) {
979 DRM_ERROR("vline wait had illegal wait until\n");
984 /* jump over the NOP */
985 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
+ waitreloc
.count
+ 2);
990 p
->idx
+= waitreloc
.count
+ 2;
991 p
->idx
+= p3reloc
.count
+ 2;
993 header
= radeon_get_ib_value(p
, h_idx
);
994 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 5);
995 reg
= CP_PACKET0_GET_REG(header
);
996 mutex_lock(&p
->rdev
->ddev
->mode_config
.mutex
);
997 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
999 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
1003 crtc
= obj_to_crtc(obj
);
1004 radeon_crtc
= to_radeon_crtc(crtc
);
1005 crtc_id
= radeon_crtc
->crtc_id
;
1007 if (!crtc
->enabled
) {
1008 /* if the CRTC isn't enabled - we need to nop out the wait until */
1009 ib
[h_idx
+ 2] = PACKET2(0);
1010 ib
[h_idx
+ 3] = PACKET2(0);
1011 } else if (crtc_id
== 1) {
1013 case AVIVO_D1MODE_VLINE_START_END
:
1014 header
&= ~R300_CP_PACKET0_REG_MASK
;
1015 header
|= AVIVO_D2MODE_VLINE_START_END
>> 2;
1017 case RADEON_CRTC_GUI_TRIG_VLINE
:
1018 header
&= ~R300_CP_PACKET0_REG_MASK
;
1019 header
|= RADEON_CRTC2_GUI_TRIG_VLINE
>> 2;
1022 DRM_ERROR("unknown crtc reloc\n");
1027 ib
[h_idx
+ 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1
;
1030 mutex_unlock(&p
->rdev
->ddev
->mode_config
.mutex
);
1035 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1036 * @parser: parser structure holding parsing context.
1037 * @data: pointer to relocation data
1038 * @offset_start: starting offset
1039 * @offset_mask: offset mask (to align start offset on)
1040 * @reloc: reloc informations
1042 * Check next packet is relocation packet3, do bo validation and compute
1043 * GPU offset using the provided start.
1045 int r100_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
1046 struct radeon_cs_reloc
**cs_reloc
)
1048 struct radeon_cs_chunk
*relocs_chunk
;
1049 struct radeon_cs_packet p3reloc
;
1053 if (p
->chunk_relocs_idx
== -1) {
1054 DRM_ERROR("No relocation chunk !\n");
1058 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
1059 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
);
1063 p
->idx
+= p3reloc
.count
+ 2;
1064 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
1065 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1067 r100_cs_dump_packet(p
, &p3reloc
);
1070 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
1071 if (idx
>= relocs_chunk
->length_dw
) {
1072 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1073 idx
, relocs_chunk
->length_dw
);
1074 r100_cs_dump_packet(p
, &p3reloc
);
1077 /* FIXME: we assume reloc size is 4 dwords */
1078 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
1082 static int r100_get_vtx_size(uint32_t vtx_fmt
)
1086 /* ordered according to bits in spec */
1087 if (vtx_fmt
& RADEON_SE_VTX_FMT_W0
)
1089 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPCOLOR
)
1091 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPALPHA
)
1093 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKCOLOR
)
1095 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPSPEC
)
1097 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPFOG
)
1099 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKSPEC
)
1101 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST0
)
1103 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST1
)
1105 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q1
)
1107 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST2
)
1109 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q2
)
1111 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST3
)
1113 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q3
)
1115 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q0
)
1118 if (vtx_fmt
& (0x7 << 15))
1119 vtx_size
+= (vtx_fmt
>> 15) & 0x7;
1120 if (vtx_fmt
& RADEON_SE_VTX_FMT_N0
)
1122 if (vtx_fmt
& RADEON_SE_VTX_FMT_XY1
)
1124 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z1
)
1126 if (vtx_fmt
& RADEON_SE_VTX_FMT_W1
)
1128 if (vtx_fmt
& RADEON_SE_VTX_FMT_N1
)
1130 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z
)
1135 static int r100_packet0_check(struct radeon_cs_parser
*p
,
1136 struct radeon_cs_packet
*pkt
,
1137 unsigned idx
, unsigned reg
)
1139 struct radeon_cs_reloc
*reloc
;
1140 struct r100_cs_track
*track
;
1141 volatile uint32_t *ib
;
1149 track
= (struct r100_cs_track
*)p
->track
;
1151 idx_value
= radeon_get_ib_value(p
, idx
);
1154 case RADEON_CRTC_GUI_TRIG_VLINE
:
1155 r
= r100_cs_packet_parse_vline(p
);
1157 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1159 r100_cs_dump_packet(p
, pkt
);
1163 /* FIXME: only allow PACKET3 blit? easier to check for out of
1165 case RADEON_DST_PITCH_OFFSET
:
1166 case RADEON_SRC_PITCH_OFFSET
:
1167 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
1171 case RADEON_RB3D_DEPTHOFFSET
:
1172 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1174 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1176 r100_cs_dump_packet(p
, pkt
);
1179 track
->zb
.robj
= reloc
->robj
;
1180 track
->zb
.offset
= idx_value
;
1181 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1183 case RADEON_RB3D_COLOROFFSET
:
1184 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1186 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1188 r100_cs_dump_packet(p
, pkt
);
1191 track
->cb
[0].robj
= reloc
->robj
;
1192 track
->cb
[0].offset
= idx_value
;
1193 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1195 case RADEON_PP_TXOFFSET_0
:
1196 case RADEON_PP_TXOFFSET_1
:
1197 case RADEON_PP_TXOFFSET_2
:
1198 i
= (reg
- RADEON_PP_TXOFFSET_0
) / 24;
1199 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1201 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1203 r100_cs_dump_packet(p
, pkt
);
1206 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1207 track
->textures
[i
].robj
= reloc
->robj
;
1209 case RADEON_PP_CUBIC_OFFSET_T0_0
:
1210 case RADEON_PP_CUBIC_OFFSET_T0_1
:
1211 case RADEON_PP_CUBIC_OFFSET_T0_2
:
1212 case RADEON_PP_CUBIC_OFFSET_T0_3
:
1213 case RADEON_PP_CUBIC_OFFSET_T0_4
:
1214 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T0_0
) / 4;
1215 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1217 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1219 r100_cs_dump_packet(p
, pkt
);
1222 track
->textures
[0].cube_info
[i
].offset
= idx_value
;
1223 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1224 track
->textures
[0].cube_info
[i
].robj
= reloc
->robj
;
1226 case RADEON_PP_CUBIC_OFFSET_T1_0
:
1227 case RADEON_PP_CUBIC_OFFSET_T1_1
:
1228 case RADEON_PP_CUBIC_OFFSET_T1_2
:
1229 case RADEON_PP_CUBIC_OFFSET_T1_3
:
1230 case RADEON_PP_CUBIC_OFFSET_T1_4
:
1231 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T1_0
) / 4;
1232 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1234 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1236 r100_cs_dump_packet(p
, pkt
);
1239 track
->textures
[1].cube_info
[i
].offset
= idx_value
;
1240 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1241 track
->textures
[1].cube_info
[i
].robj
= reloc
->robj
;
1243 case RADEON_PP_CUBIC_OFFSET_T2_0
:
1244 case RADEON_PP_CUBIC_OFFSET_T2_1
:
1245 case RADEON_PP_CUBIC_OFFSET_T2_2
:
1246 case RADEON_PP_CUBIC_OFFSET_T2_3
:
1247 case RADEON_PP_CUBIC_OFFSET_T2_4
:
1248 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T2_0
) / 4;
1249 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1251 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1253 r100_cs_dump_packet(p
, pkt
);
1256 track
->textures
[2].cube_info
[i
].offset
= idx_value
;
1257 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1258 track
->textures
[2].cube_info
[i
].robj
= reloc
->robj
;
1260 case RADEON_RE_WIDTH_HEIGHT
:
1261 track
->maxy
= ((idx_value
>> 16) & 0x7FF);
1263 case RADEON_RB3D_COLORPITCH
:
1264 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1266 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1268 r100_cs_dump_packet(p
, pkt
);
1272 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1273 tile_flags
|= RADEON_COLOR_TILE_ENABLE
;
1274 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1275 tile_flags
|= RADEON_COLOR_MICROTILE_ENABLE
;
1277 tmp
= idx_value
& ~(0x7 << 16);
1281 track
->cb
[0].pitch
= idx_value
& RADEON_COLORPITCH_MASK
;
1283 case RADEON_RB3D_DEPTHPITCH
:
1284 track
->zb
.pitch
= idx_value
& RADEON_DEPTHPITCH_MASK
;
1286 case RADEON_RB3D_CNTL
:
1287 switch ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f) {
1293 track
->cb
[0].cpp
= 1;
1298 track
->cb
[0].cpp
= 2;
1301 track
->cb
[0].cpp
= 4;
1304 DRM_ERROR("Invalid color buffer format (%d) !\n",
1305 ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f));
1308 track
->z_enabled
= !!(idx_value
& RADEON_Z_ENABLE
);
1310 case RADEON_RB3D_ZSTENCILCNTL
:
1311 switch (idx_value
& 0xf) {
1327 case RADEON_RB3D_ZPASS_ADDR
:
1328 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1330 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1332 r100_cs_dump_packet(p
, pkt
);
1335 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1337 case RADEON_PP_CNTL
:
1339 uint32_t temp
= idx_value
>> 4;
1340 for (i
= 0; i
< track
->num_texture
; i
++)
1341 track
->textures
[i
].enabled
= !!(temp
& (1 << i
));
1344 case RADEON_SE_VF_CNTL
:
1345 track
->vap_vf_cntl
= idx_value
;
1347 case RADEON_SE_VTX_FMT
:
1348 track
->vtx_size
= r100_get_vtx_size(idx_value
);
1350 case RADEON_PP_TEX_SIZE_0
:
1351 case RADEON_PP_TEX_SIZE_1
:
1352 case RADEON_PP_TEX_SIZE_2
:
1353 i
= (reg
- RADEON_PP_TEX_SIZE_0
) / 8;
1354 track
->textures
[i
].width
= (idx_value
& RADEON_TEX_USIZE_MASK
) + 1;
1355 track
->textures
[i
].height
= ((idx_value
& RADEON_TEX_VSIZE_MASK
) >> RADEON_TEX_VSIZE_SHIFT
) + 1;
1357 case RADEON_PP_TEX_PITCH_0
:
1358 case RADEON_PP_TEX_PITCH_1
:
1359 case RADEON_PP_TEX_PITCH_2
:
1360 i
= (reg
- RADEON_PP_TEX_PITCH_0
) / 8;
1361 track
->textures
[i
].pitch
= idx_value
+ 32;
1363 case RADEON_PP_TXFILTER_0
:
1364 case RADEON_PP_TXFILTER_1
:
1365 case RADEON_PP_TXFILTER_2
:
1366 i
= (reg
- RADEON_PP_TXFILTER_0
) / 24;
1367 track
->textures
[i
].num_levels
= ((idx_value
& RADEON_MAX_MIP_LEVEL_MASK
)
1368 >> RADEON_MAX_MIP_LEVEL_SHIFT
);
1369 tmp
= (idx_value
>> 23) & 0x7;
1370 if (tmp
== 2 || tmp
== 6)
1371 track
->textures
[i
].roundup_w
= false;
1372 tmp
= (idx_value
>> 27) & 0x7;
1373 if (tmp
== 2 || tmp
== 6)
1374 track
->textures
[i
].roundup_h
= false;
1376 case RADEON_PP_TXFORMAT_0
:
1377 case RADEON_PP_TXFORMAT_1
:
1378 case RADEON_PP_TXFORMAT_2
:
1379 i
= (reg
- RADEON_PP_TXFORMAT_0
) / 24;
1380 if (idx_value
& RADEON_TXFORMAT_NON_POWER2
) {
1381 track
->textures
[i
].use_pitch
= 1;
1383 track
->textures
[i
].use_pitch
= 0;
1384 track
->textures
[i
].width
= 1 << ((idx_value
>> RADEON_TXFORMAT_WIDTH_SHIFT
) & RADEON_TXFORMAT_WIDTH_MASK
);
1385 track
->textures
[i
].height
= 1 << ((idx_value
>> RADEON_TXFORMAT_HEIGHT_SHIFT
) & RADEON_TXFORMAT_HEIGHT_MASK
);
1387 if (idx_value
& RADEON_TXFORMAT_CUBIC_MAP_ENABLE
)
1388 track
->textures
[i
].tex_coord_type
= 2;
1389 switch ((idx_value
& RADEON_TXFORMAT_FORMAT_MASK
)) {
1390 case RADEON_TXFORMAT_I8
:
1391 case RADEON_TXFORMAT_RGB332
:
1392 case RADEON_TXFORMAT_Y8
:
1393 track
->textures
[i
].cpp
= 1;
1395 case RADEON_TXFORMAT_AI88
:
1396 case RADEON_TXFORMAT_ARGB1555
:
1397 case RADEON_TXFORMAT_RGB565
:
1398 case RADEON_TXFORMAT_ARGB4444
:
1399 case RADEON_TXFORMAT_VYUY422
:
1400 case RADEON_TXFORMAT_YVYU422
:
1401 case RADEON_TXFORMAT_SHADOW16
:
1402 case RADEON_TXFORMAT_LDUDV655
:
1403 case RADEON_TXFORMAT_DUDV88
:
1404 track
->textures
[i
].cpp
= 2;
1406 case RADEON_TXFORMAT_ARGB8888
:
1407 case RADEON_TXFORMAT_RGBA8888
:
1408 case RADEON_TXFORMAT_SHADOW32
:
1409 case RADEON_TXFORMAT_LDUDUV8888
:
1410 track
->textures
[i
].cpp
= 4;
1412 case RADEON_TXFORMAT_DXT1
:
1413 track
->textures
[i
].cpp
= 1;
1414 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
1416 case RADEON_TXFORMAT_DXT23
:
1417 case RADEON_TXFORMAT_DXT45
:
1418 track
->textures
[i
].cpp
= 1;
1419 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT35
;
1422 track
->textures
[i
].cube_info
[4].width
= 1 << ((idx_value
>> 16) & 0xf);
1423 track
->textures
[i
].cube_info
[4].height
= 1 << ((idx_value
>> 20) & 0xf);
1425 case RADEON_PP_CUBIC_FACES_0
:
1426 case RADEON_PP_CUBIC_FACES_1
:
1427 case RADEON_PP_CUBIC_FACES_2
:
1429 i
= (reg
- RADEON_PP_CUBIC_FACES_0
) / 4;
1430 for (face
= 0; face
< 4; face
++) {
1431 track
->textures
[i
].cube_info
[face
].width
= 1 << ((tmp
>> (face
* 8)) & 0xf);
1432 track
->textures
[i
].cube_info
[face
].height
= 1 << ((tmp
>> ((face
* 8) + 4)) & 0xf);
1436 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1443 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1444 struct radeon_cs_packet
*pkt
,
1445 struct radeon_bo
*robj
)
1450 value
= radeon_get_ib_value(p
, idx
+ 2);
1451 if ((value
+ 1) > radeon_bo_size(robj
)) {
1452 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1453 "(need %u have %lu) !\n",
1455 radeon_bo_size(robj
));
1461 static int r100_packet3_check(struct radeon_cs_parser
*p
,
1462 struct radeon_cs_packet
*pkt
)
1464 struct radeon_cs_reloc
*reloc
;
1465 struct r100_cs_track
*track
;
1467 volatile uint32_t *ib
;
1472 track
= (struct r100_cs_track
*)p
->track
;
1473 switch (pkt
->opcode
) {
1474 case PACKET3_3D_LOAD_VBPNTR
:
1475 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1479 case PACKET3_INDX_BUFFER
:
1480 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1482 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1483 r100_cs_dump_packet(p
, pkt
);
1486 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+1) + ((u32
)reloc
->lobj
.gpu_offset
);
1487 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1493 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1494 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1496 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1497 r100_cs_dump_packet(p
, pkt
);
1500 ib
[idx
] = radeon_get_ib_value(p
, idx
) + ((u32
)reloc
->lobj
.gpu_offset
);
1501 track
->num_arrays
= 1;
1502 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 2));
1504 track
->arrays
[0].robj
= reloc
->robj
;
1505 track
->arrays
[0].esize
= track
->vtx_size
;
1507 track
->max_indx
= radeon_get_ib_value(p
, idx
+1);
1509 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+3);
1510 track
->immd_dwords
= pkt
->count
- 1;
1511 r
= r100_cs_track_check(p
->rdev
, track
);
1515 case PACKET3_3D_DRAW_IMMD
:
1516 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1517 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1520 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 0));
1521 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1522 track
->immd_dwords
= pkt
->count
- 1;
1523 r
= r100_cs_track_check(p
->rdev
, track
);
1527 /* triggers drawing using in-packet vertex data */
1528 case PACKET3_3D_DRAW_IMMD_2
:
1529 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1530 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1533 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1534 track
->immd_dwords
= pkt
->count
;
1535 r
= r100_cs_track_check(p
->rdev
, track
);
1539 /* triggers drawing using in-packet vertex data */
1540 case PACKET3_3D_DRAW_VBUF_2
:
1541 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1542 r
= r100_cs_track_check(p
->rdev
, track
);
1546 /* triggers drawing of vertex buffers setup elsewhere */
1547 case PACKET3_3D_DRAW_INDX_2
:
1548 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1549 r
= r100_cs_track_check(p
->rdev
, track
);
1553 /* triggers drawing using indices to vertex buffer */
1554 case PACKET3_3D_DRAW_VBUF
:
1555 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1556 r
= r100_cs_track_check(p
->rdev
, track
);
1560 /* triggers drawing of vertex buffers setup elsewhere */
1561 case PACKET3_3D_DRAW_INDX
:
1562 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1563 r
= r100_cs_track_check(p
->rdev
, track
);
1567 /* triggers drawing using indices to vertex buffer */
1571 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1577 int r100_cs_parse(struct radeon_cs_parser
*p
)
1579 struct radeon_cs_packet pkt
;
1580 struct r100_cs_track
*track
;
1583 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1584 r100_cs_track_clear(p
->rdev
, track
);
1587 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1591 p
->idx
+= pkt
.count
+ 2;
1594 if (p
->rdev
->family
>= CHIP_R200
)
1595 r
= r100_cs_parse_packet0(p
, &pkt
,
1596 p
->rdev
->config
.r100
.reg_safe_bm
,
1597 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1598 &r200_packet0_check
);
1600 r
= r100_cs_parse_packet0(p
, &pkt
,
1601 p
->rdev
->config
.r100
.reg_safe_bm
,
1602 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1603 &r100_packet0_check
);
1608 r
= r100_packet3_check(p
, &pkt
);
1611 DRM_ERROR("Unknown packet type %d !\n",
1618 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1624 * Global GPU functions
1626 void r100_errata(struct radeon_device
*rdev
)
1628 rdev
->pll_errata
= 0;
1630 if (rdev
->family
== CHIP_RV200
|| rdev
->family
== CHIP_RS200
) {
1631 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DUMMYREADS
;
1634 if (rdev
->family
== CHIP_RV100
||
1635 rdev
->family
== CHIP_RS100
||
1636 rdev
->family
== CHIP_RS200
) {
1637 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DELAY
;
1641 /* Wait for vertical sync on primary CRTC */
1642 void r100_gpu_wait_for_vsync(struct radeon_device
*rdev
)
1644 uint32_t crtc_gen_cntl
, tmp
;
1647 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
1648 if ((crtc_gen_cntl
& RADEON_CRTC_DISP_REQ_EN_B
) ||
1649 !(crtc_gen_cntl
& RADEON_CRTC_EN
)) {
1652 /* Clear the CRTC_VBLANK_SAVE bit */
1653 WREG32(RADEON_CRTC_STATUS
, RADEON_CRTC_VBLANK_SAVE_CLEAR
);
1654 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1655 tmp
= RREG32(RADEON_CRTC_STATUS
);
1656 if (tmp
& RADEON_CRTC_VBLANK_SAVE
) {
1663 /* Wait for vertical sync on secondary CRTC */
1664 void r100_gpu_wait_for_vsync2(struct radeon_device
*rdev
)
1666 uint32_t crtc2_gen_cntl
, tmp
;
1669 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
1670 if ((crtc2_gen_cntl
& RADEON_CRTC2_DISP_REQ_EN_B
) ||
1671 !(crtc2_gen_cntl
& RADEON_CRTC2_EN
))
1674 /* Clear the CRTC_VBLANK_SAVE bit */
1675 WREG32(RADEON_CRTC2_STATUS
, RADEON_CRTC2_VBLANK_SAVE_CLEAR
);
1676 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1677 tmp
= RREG32(RADEON_CRTC2_STATUS
);
1678 if (tmp
& RADEON_CRTC2_VBLANK_SAVE
) {
1685 int r100_rbbm_fifo_wait_for_entry(struct radeon_device
*rdev
, unsigned n
)
1690 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1691 tmp
= RREG32(RADEON_RBBM_STATUS
) & RADEON_RBBM_FIFOCNT_MASK
;
1700 int r100_gui_wait_for_idle(struct radeon_device
*rdev
)
1705 if (r100_rbbm_fifo_wait_for_entry(rdev
, 64)) {
1706 printk(KERN_WARNING
"radeon: wait for empty RBBM fifo failed !"
1707 " Bad things might happen.\n");
1709 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1710 tmp
= RREG32(RADEON_RBBM_STATUS
);
1711 if (!(tmp
& RADEON_RBBM_ACTIVE
)) {
1719 int r100_mc_wait_for_idle(struct radeon_device
*rdev
)
1724 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1725 /* read MC_STATUS */
1726 tmp
= RREG32(RADEON_MC_STATUS
);
1727 if (tmp
& RADEON_MC_IDLE
) {
1735 void r100_gpu_init(struct radeon_device
*rdev
)
1737 /* TODO: anythings to do here ? pipes ? */
1738 r100_hdp_reset(rdev
);
1741 void r100_hdp_reset(struct radeon_device
*rdev
)
1745 tmp
= RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
;
1747 WREG32(RADEON_HOST_PATH_CNTL
, tmp
| RADEON_HDP_SOFT_RESET
| RADEON_HDP_READ_BUFFER_INVALIDATE
);
1748 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1750 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1751 WREG32(RADEON_HOST_PATH_CNTL
, tmp
);
1752 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1755 int r100_rb2d_reset(struct radeon_device
*rdev
)
1760 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_E2
);
1761 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
1763 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1764 /* Wait to prevent race in RBBM_STATUS */
1766 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1767 tmp
= RREG32(RADEON_RBBM_STATUS
);
1768 if (!(tmp
& (1 << 26))) {
1769 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1775 tmp
= RREG32(RADEON_RBBM_STATUS
);
1776 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp
);
1780 int r100_gpu_reset(struct radeon_device
*rdev
)
1784 /* reset order likely matter */
1785 status
= RREG32(RADEON_RBBM_STATUS
);
1787 r100_hdp_reset(rdev
);
1789 if (status
& ((1 << 17) | (1 << 18) | (1 << 27))) {
1790 r100_rb2d_reset(rdev
);
1792 /* TODO: reset 3D engine */
1794 status
= RREG32(RADEON_RBBM_STATUS
);
1795 if (status
& (1 << 16)) {
1796 r100_cp_reset(rdev
);
1798 /* Check if GPU is idle */
1799 status
= RREG32(RADEON_RBBM_STATUS
);
1800 if (status
& RADEON_RBBM_ACTIVE
) {
1801 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status
);
1804 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status
);
1808 void r100_set_common_regs(struct radeon_device
*rdev
)
1810 struct drm_device
*dev
= rdev
->ddev
;
1811 bool force_dac2
= false;
1814 /* set these so they don't interfere with anything */
1815 WREG32(RADEON_OV0_SCALE_CNTL
, 0);
1816 WREG32(RADEON_SUBPIC_CNTL
, 0);
1817 WREG32(RADEON_VIPH_CONTROL
, 0);
1818 WREG32(RADEON_I2C_CNTL_1
, 0);
1819 WREG32(RADEON_DVI_I2C_CNTL_1
, 0);
1820 WREG32(RADEON_CAP0_TRIG_CNTL
, 0);
1821 WREG32(RADEON_CAP1_TRIG_CNTL
, 0);
1823 /* always set up dac2 on rn50 and some rv100 as lots
1824 * of servers seem to wire it up to a VGA port but
1825 * don't report it in the bios connector
1828 switch (dev
->pdev
->device
) {
1837 /* DELL triple head servers */
1838 if ((dev
->pdev
->subsystem_vendor
== 0x1028 /* DELL */) &&
1839 ((dev
->pdev
->subsystem_device
== 0x016c) ||
1840 (dev
->pdev
->subsystem_device
== 0x016d) ||
1841 (dev
->pdev
->subsystem_device
== 0x016e) ||
1842 (dev
->pdev
->subsystem_device
== 0x016f) ||
1843 (dev
->pdev
->subsystem_device
== 0x0170) ||
1844 (dev
->pdev
->subsystem_device
== 0x017d) ||
1845 (dev
->pdev
->subsystem_device
== 0x017e) ||
1846 (dev
->pdev
->subsystem_device
== 0x0183) ||
1847 (dev
->pdev
->subsystem_device
== 0x018a) ||
1848 (dev
->pdev
->subsystem_device
== 0x019a)))
1854 u32 disp_hw_debug
= RREG32(RADEON_DISP_HW_DEBUG
);
1855 u32 tv_dac_cntl
= RREG32(RADEON_TV_DAC_CNTL
);
1856 u32 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
1858 /* For CRT on DAC2, don't turn it on if BIOS didn't
1859 enable it, even it's detected.
1862 /* force it to crtc0 */
1863 dac2_cntl
&= ~RADEON_DAC2_DAC_CLK_SEL
;
1864 dac2_cntl
|= RADEON_DAC2_DAC2_CLK_SEL
;
1865 disp_hw_debug
|= RADEON_CRT2_DISP1_SEL
;
1867 /* set up the TV DAC */
1868 tv_dac_cntl
&= ~(RADEON_TV_DAC_PEDESTAL
|
1869 RADEON_TV_DAC_STD_MASK
|
1870 RADEON_TV_DAC_RDACPD
|
1871 RADEON_TV_DAC_GDACPD
|
1872 RADEON_TV_DAC_BDACPD
|
1873 RADEON_TV_DAC_BGADJ_MASK
|
1874 RADEON_TV_DAC_DACADJ_MASK
);
1875 tv_dac_cntl
|= (RADEON_TV_DAC_NBLANK
|
1876 RADEON_TV_DAC_NHOLD
|
1877 RADEON_TV_DAC_STD_PS2
|
1880 WREG32(RADEON_TV_DAC_CNTL
, tv_dac_cntl
);
1881 WREG32(RADEON_DISP_HW_DEBUG
, disp_hw_debug
);
1882 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
1885 /* switch PM block to ACPI mode */
1886 tmp
= RREG32_PLL(RADEON_PLL_PWRMGT_CNTL
);
1887 tmp
&= ~RADEON_PM_MODE_SEL
;
1888 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL
, tmp
);
1895 static void r100_vram_get_type(struct radeon_device
*rdev
)
1899 rdev
->mc
.vram_is_ddr
= false;
1900 if (rdev
->flags
& RADEON_IS_IGP
)
1901 rdev
->mc
.vram_is_ddr
= true;
1902 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG
) & RADEON_MEM_CFG_TYPE_DDR
)
1903 rdev
->mc
.vram_is_ddr
= true;
1904 if ((rdev
->family
== CHIP_RV100
) ||
1905 (rdev
->family
== CHIP_RS100
) ||
1906 (rdev
->family
== CHIP_RS200
)) {
1907 tmp
= RREG32(RADEON_MEM_CNTL
);
1908 if (tmp
& RV100_HALF_MODE
) {
1909 rdev
->mc
.vram_width
= 32;
1911 rdev
->mc
.vram_width
= 64;
1913 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1914 rdev
->mc
.vram_width
/= 4;
1915 rdev
->mc
.vram_is_ddr
= true;
1917 } else if (rdev
->family
<= CHIP_RV280
) {
1918 tmp
= RREG32(RADEON_MEM_CNTL
);
1919 if (tmp
& RADEON_MEM_NUM_CHANNELS_MASK
) {
1920 rdev
->mc
.vram_width
= 128;
1922 rdev
->mc
.vram_width
= 64;
1926 rdev
->mc
.vram_width
= 128;
1930 static u32
r100_get_accessible_vram(struct radeon_device
*rdev
)
1935 aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1937 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1938 * that is has the 2nd generation multifunction PCI interface
1940 if (rdev
->family
== CHIP_RV280
||
1941 rdev
->family
>= CHIP_RV350
) {
1942 WREG32_P(RADEON_HOST_PATH_CNTL
, RADEON_HDP_APER_CNTL
,
1943 ~RADEON_HDP_APER_CNTL
);
1944 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1945 return aper_size
* 2;
1948 /* Older cards have all sorts of funny issues to deal with. First
1949 * check if it's a multifunction card by reading the PCI config
1950 * header type... Limit those to one aperture size
1952 pci_read_config_byte(rdev
->pdev
, 0xe, &byte
);
1954 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1955 DRM_INFO("Limiting VRAM to one aperture\n");
1959 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1960 * have set it up. We don't write this as it's broken on some ASICs but
1961 * we expect the BIOS to have done the right thing (might be too optimistic...)
1963 if (RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
)
1964 return aper_size
* 2;
1968 void r100_vram_init_sizes(struct radeon_device
*rdev
)
1970 u64 config_aper_size
;
1972 /* work out accessible VRAM */
1973 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
1974 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
1975 rdev
->mc
.visible_vram_size
= r100_get_accessible_vram(rdev
);
1976 /* FIXME we don't use the second aperture yet when we could use it */
1977 if (rdev
->mc
.visible_vram_size
> rdev
->mc
.aper_size
)
1978 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1979 config_aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1980 if (rdev
->flags
& RADEON_IS_IGP
) {
1982 /* read NB_TOM to get the amount of ram stolen for the GPU */
1983 tom
= RREG32(RADEON_NB_TOM
);
1984 rdev
->mc
.real_vram_size
= (((tom
>> 16) - (tom
& 0xffff) + 1) << 16);
1985 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1986 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
1988 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
1989 /* Some production boards of m6 will report 0
1992 if (rdev
->mc
.real_vram_size
== 0) {
1993 rdev
->mc
.real_vram_size
= 8192 * 1024;
1994 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1996 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1997 * Novell bug 204882 + along with lots of ubuntu ones
1999 if (config_aper_size
> rdev
->mc
.real_vram_size
)
2000 rdev
->mc
.mc_vram_size
= config_aper_size
;
2002 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
2004 /* FIXME remove this once we support unmappable VRAM */
2005 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
) {
2006 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
2007 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
2011 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
)
2015 temp
= RREG32(RADEON_CONFIG_CNTL
);
2016 if (state
== false) {
2022 WREG32(RADEON_CONFIG_CNTL
, temp
);
2025 void r100_mc_init(struct radeon_device
*rdev
)
2029 r100_vram_get_type(rdev
);
2030 r100_vram_init_sizes(rdev
);
2031 base
= rdev
->mc
.aper_base
;
2032 if (rdev
->flags
& RADEON_IS_IGP
)
2033 base
= (RREG32(RADEON_NB_TOM
) & 0xffff) << 16;
2034 radeon_vram_location(rdev
, &rdev
->mc
, base
);
2035 if (!(rdev
->flags
& RADEON_IS_AGP
))
2036 radeon_gtt_location(rdev
, &rdev
->mc
);
2037 radeon_update_bandwidth_info(rdev
);
2042 * Indirect registers accessor
2044 void r100_pll_errata_after_index(struct radeon_device
*rdev
)
2046 if (!(rdev
->pll_errata
& CHIP_ERRATA_PLL_DUMMYREADS
)) {
2049 (void)RREG32(RADEON_CLOCK_CNTL_DATA
);
2050 (void)RREG32(RADEON_CRTC_GEN_CNTL
);
2053 static void r100_pll_errata_after_data(struct radeon_device
*rdev
)
2055 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2056 * or the chip could hang on a subsequent access
2058 if (rdev
->pll_errata
& CHIP_ERRATA_PLL_DELAY
) {
2062 /* This function is required to workaround a hardware bug in some (all?)
2063 * revisions of the R300. This workaround should be called after every
2064 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2065 * may not be correct.
2067 if (rdev
->pll_errata
& CHIP_ERRATA_R300_CG
) {
2070 save
= RREG32(RADEON_CLOCK_CNTL_INDEX
);
2071 tmp
= save
& ~(0x3f | RADEON_PLL_WR_EN
);
2072 WREG32(RADEON_CLOCK_CNTL_INDEX
, tmp
);
2073 tmp
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2074 WREG32(RADEON_CLOCK_CNTL_INDEX
, save
);
2078 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
)
2082 WREG8(RADEON_CLOCK_CNTL_INDEX
, reg
& 0x3f);
2083 r100_pll_errata_after_index(rdev
);
2084 data
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2085 r100_pll_errata_after_data(rdev
);
2089 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
2091 WREG8(RADEON_CLOCK_CNTL_INDEX
, ((reg
& 0x3f) | RADEON_PLL_WR_EN
));
2092 r100_pll_errata_after_index(rdev
);
2093 WREG32(RADEON_CLOCK_CNTL_DATA
, v
);
2094 r100_pll_errata_after_data(rdev
);
2097 void r100_set_safe_registers(struct radeon_device
*rdev
)
2099 if (ASIC_IS_RN50(rdev
)) {
2100 rdev
->config
.r100
.reg_safe_bm
= rn50_reg_safe_bm
;
2101 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(rn50_reg_safe_bm
);
2102 } else if (rdev
->family
< CHIP_R200
) {
2103 rdev
->config
.r100
.reg_safe_bm
= r100_reg_safe_bm
;
2104 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(r100_reg_safe_bm
);
2106 r200_set_safe_registers(rdev
);
2113 #if defined(CONFIG_DEBUG_FS)
2114 static int r100_debugfs_rbbm_info(struct seq_file
*m
, void *data
)
2116 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2117 struct drm_device
*dev
= node
->minor
->dev
;
2118 struct radeon_device
*rdev
= dev
->dev_private
;
2119 uint32_t reg
, value
;
2122 seq_printf(m
, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS
));
2123 seq_printf(m
, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2124 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2125 for (i
= 0; i
< 64; i
++) {
2126 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
| 0x100);
2127 reg
= (RREG32(RADEON_RBBM_CMDFIFO_DATA
) - 1) >> 2;
2128 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
);
2129 value
= RREG32(RADEON_RBBM_CMDFIFO_DATA
);
2130 seq_printf(m
, "[0x%03X] 0x%04X=0x%08X\n", i
, reg
, value
);
2135 static int r100_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
2137 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2138 struct drm_device
*dev
= node
->minor
->dev
;
2139 struct radeon_device
*rdev
= dev
->dev_private
;
2141 unsigned count
, i
, j
;
2143 radeon_ring_free_size(rdev
);
2144 rdp
= RREG32(RADEON_CP_RB_RPTR
);
2145 wdp
= RREG32(RADEON_CP_RB_WPTR
);
2146 count
= (rdp
+ rdev
->cp
.ring_size
- wdp
) & rdev
->cp
.ptr_mask
;
2147 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2148 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", wdp
);
2149 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", rdp
);
2150 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
2151 seq_printf(m
, "%u dwords in ring\n", count
);
2152 for (j
= 0; j
<= count
; j
++) {
2153 i
= (rdp
+ j
) & rdev
->cp
.ptr_mask
;
2154 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
2160 static int r100_debugfs_cp_csq_fifo(struct seq_file
*m
, void *data
)
2162 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2163 struct drm_device
*dev
= node
->minor
->dev
;
2164 struct radeon_device
*rdev
= dev
->dev_private
;
2165 uint32_t csq_stat
, csq2_stat
, tmp
;
2166 unsigned r_rptr
, r_wptr
, ib1_rptr
, ib1_wptr
, ib2_rptr
, ib2_wptr
;
2169 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2170 seq_printf(m
, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE
));
2171 csq_stat
= RREG32(RADEON_CP_CSQ_STAT
);
2172 csq2_stat
= RREG32(RADEON_CP_CSQ2_STAT
);
2173 r_rptr
= (csq_stat
>> 0) & 0x3ff;
2174 r_wptr
= (csq_stat
>> 10) & 0x3ff;
2175 ib1_rptr
= (csq_stat
>> 20) & 0x3ff;
2176 ib1_wptr
= (csq2_stat
>> 0) & 0x3ff;
2177 ib2_rptr
= (csq2_stat
>> 10) & 0x3ff;
2178 ib2_wptr
= (csq2_stat
>> 20) & 0x3ff;
2179 seq_printf(m
, "CP_CSQ_STAT 0x%08x\n", csq_stat
);
2180 seq_printf(m
, "CP_CSQ2_STAT 0x%08x\n", csq2_stat
);
2181 seq_printf(m
, "Ring rptr %u\n", r_rptr
);
2182 seq_printf(m
, "Ring wptr %u\n", r_wptr
);
2183 seq_printf(m
, "Indirect1 rptr %u\n", ib1_rptr
);
2184 seq_printf(m
, "Indirect1 wptr %u\n", ib1_wptr
);
2185 seq_printf(m
, "Indirect2 rptr %u\n", ib2_rptr
);
2186 seq_printf(m
, "Indirect2 wptr %u\n", ib2_wptr
);
2187 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2188 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2189 seq_printf(m
, "Ring fifo:\n");
2190 for (i
= 0; i
< 256; i
++) {
2191 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2192 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2193 seq_printf(m
, "rfifo[%04d]=0x%08X\n", i
, tmp
);
2195 seq_printf(m
, "Indirect1 fifo:\n");
2196 for (i
= 256; i
<= 512; i
++) {
2197 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2198 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2199 seq_printf(m
, "ib1fifo[%04d]=0x%08X\n", i
, tmp
);
2201 seq_printf(m
, "Indirect2 fifo:\n");
2202 for (i
= 640; i
< ib1_wptr
; i
++) {
2203 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2204 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2205 seq_printf(m
, "ib2fifo[%04d]=0x%08X\n", i
, tmp
);
2210 static int r100_debugfs_mc_info(struct seq_file
*m
, void *data
)
2212 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2213 struct drm_device
*dev
= node
->minor
->dev
;
2214 struct radeon_device
*rdev
= dev
->dev_private
;
2217 tmp
= RREG32(RADEON_CONFIG_MEMSIZE
);
2218 seq_printf(m
, "CONFIG_MEMSIZE 0x%08x\n", tmp
);
2219 tmp
= RREG32(RADEON_MC_FB_LOCATION
);
2220 seq_printf(m
, "MC_FB_LOCATION 0x%08x\n", tmp
);
2221 tmp
= RREG32(RADEON_BUS_CNTL
);
2222 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
2223 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
2224 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
2225 tmp
= RREG32(RADEON_AGP_BASE
);
2226 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
2227 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
2228 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
2229 tmp
= RREG32(0x01D0);
2230 seq_printf(m
, "AIC_CTRL 0x%08x\n", tmp
);
2231 tmp
= RREG32(RADEON_AIC_LO_ADDR
);
2232 seq_printf(m
, "AIC_LO_ADDR 0x%08x\n", tmp
);
2233 tmp
= RREG32(RADEON_AIC_HI_ADDR
);
2234 seq_printf(m
, "AIC_HI_ADDR 0x%08x\n", tmp
);
2235 tmp
= RREG32(0x01E4);
2236 seq_printf(m
, "AIC_TLB_ADDR 0x%08x\n", tmp
);
2240 static struct drm_info_list r100_debugfs_rbbm_list
[] = {
2241 {"r100_rbbm_info", r100_debugfs_rbbm_info
, 0, NULL
},
2244 static struct drm_info_list r100_debugfs_cp_list
[] = {
2245 {"r100_cp_ring_info", r100_debugfs_cp_ring_info
, 0, NULL
},
2246 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo
, 0, NULL
},
2249 static struct drm_info_list r100_debugfs_mc_info_list
[] = {
2250 {"r100_mc_info", r100_debugfs_mc_info
, 0, NULL
},
2254 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
)
2256 #if defined(CONFIG_DEBUG_FS)
2257 return radeon_debugfs_add_files(rdev
, r100_debugfs_rbbm_list
, 1);
2263 int r100_debugfs_cp_init(struct radeon_device
*rdev
)
2265 #if defined(CONFIG_DEBUG_FS)
2266 return radeon_debugfs_add_files(rdev
, r100_debugfs_cp_list
, 2);
2272 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
)
2274 #if defined(CONFIG_DEBUG_FS)
2275 return radeon_debugfs_add_files(rdev
, r100_debugfs_mc_info_list
, 1);
2281 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2282 uint32_t tiling_flags
, uint32_t pitch
,
2283 uint32_t offset
, uint32_t obj_size
)
2285 int surf_index
= reg
* 16;
2288 /* r100/r200 divide by 16 */
2289 if (rdev
->family
< CHIP_R300
)
2294 if (rdev
->family
<= CHIP_RS200
) {
2295 if ((tiling_flags
& (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2296 == (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2297 flags
|= RADEON_SURF_TILE_COLOR_BOTH
;
2298 if (tiling_flags
& RADEON_TILING_MACRO
)
2299 flags
|= RADEON_SURF_TILE_COLOR_MACRO
;
2300 } else if (rdev
->family
<= CHIP_RV280
) {
2301 if (tiling_flags
& (RADEON_TILING_MACRO
))
2302 flags
|= R200_SURF_TILE_COLOR_MACRO
;
2303 if (tiling_flags
& RADEON_TILING_MICRO
)
2304 flags
|= R200_SURF_TILE_COLOR_MICRO
;
2306 if (tiling_flags
& RADEON_TILING_MACRO
)
2307 flags
|= R300_SURF_TILE_MACRO
;
2308 if (tiling_flags
& RADEON_TILING_MICRO
)
2309 flags
|= R300_SURF_TILE_MICRO
;
2312 if (tiling_flags
& RADEON_TILING_SWAP_16BIT
)
2313 flags
|= RADEON_SURF_AP0_SWP_16BPP
| RADEON_SURF_AP1_SWP_16BPP
;
2314 if (tiling_flags
& RADEON_TILING_SWAP_32BIT
)
2315 flags
|= RADEON_SURF_AP0_SWP_32BPP
| RADEON_SURF_AP1_SWP_32BPP
;
2317 DRM_DEBUG("writing surface %d %d %x %x\n", reg
, flags
, offset
, offset
+obj_size
-1);
2318 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, flags
);
2319 WREG32(RADEON_SURFACE0_LOWER_BOUND
+ surf_index
, offset
);
2320 WREG32(RADEON_SURFACE0_UPPER_BOUND
+ surf_index
, offset
+ obj_size
- 1);
2324 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2326 int surf_index
= reg
* 16;
2327 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, 0);
2330 void r100_bandwidth_update(struct radeon_device
*rdev
)
2332 fixed20_12 trcd_ff
, trp_ff
, tras_ff
, trbs_ff
, tcas_ff
;
2333 fixed20_12 sclk_ff
, mclk_ff
, sclk_eff_ff
, sclk_delay_ff
;
2334 fixed20_12 peak_disp_bw
, mem_bw
, pix_clk
, pix_clk2
, temp_ff
, crit_point_ff
;
2335 uint32_t temp
, data
, mem_trcd
, mem_trp
, mem_tras
;
2336 fixed20_12 memtcas_ff
[8] = {
2345 fixed20_12 memtcas_rs480_ff
[8] = {
2355 fixed20_12 memtcas2_ff
[8] = {
2365 fixed20_12 memtrbs
[8] = {
2375 fixed20_12 memtrbs_r4xx
[8] = {
2385 fixed20_12 min_mem_eff
;
2386 fixed20_12 mc_latency_sclk
, mc_latency_mclk
, k1
;
2387 fixed20_12 cur_latency_mclk
, cur_latency_sclk
;
2388 fixed20_12 disp_latency
, disp_latency_overhead
, disp_drain_rate
,
2389 disp_drain_rate2
, read_return_rate
;
2390 fixed20_12 time_disp1_drop_priority
;
2392 int cur_size
= 16; /* in octawords */
2393 int critical_point
= 0, critical_point2
;
2394 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2395 int stop_req
, max_stop_req
;
2396 struct drm_display_mode
*mode1
= NULL
;
2397 struct drm_display_mode
*mode2
= NULL
;
2398 uint32_t pixel_bytes1
= 0;
2399 uint32_t pixel_bytes2
= 0;
2401 radeon_update_display_priority(rdev
);
2403 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
) {
2404 mode1
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
2405 pixel_bytes1
= rdev
->mode_info
.crtcs
[0]->base
.fb
->bits_per_pixel
/ 8;
2407 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2408 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
) {
2409 mode2
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
2410 pixel_bytes2
= rdev
->mode_info
.crtcs
[1]->base
.fb
->bits_per_pixel
/ 8;
2414 min_mem_eff
.full
= rfixed_const_8(0);
2416 if ((rdev
->disp_priority
== 2) && ASIC_IS_R300(rdev
)) {
2417 uint32_t mc_init_misc_lat_timer
= RREG32(R300_MC_INIT_MISC_LAT_TIMER
);
2418 mc_init_misc_lat_timer
&= ~(R300_MC_DISP1R_INIT_LAT_MASK
<< R300_MC_DISP1R_INIT_LAT_SHIFT
);
2419 mc_init_misc_lat_timer
&= ~(R300_MC_DISP0R_INIT_LAT_MASK
<< R300_MC_DISP0R_INIT_LAT_SHIFT
);
2420 /* check crtc enables */
2422 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT
);
2424 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT
);
2425 WREG32(R300_MC_INIT_MISC_LAT_TIMER
, mc_init_misc_lat_timer
);
2429 * determine is there is enough bw for current mode
2431 sclk_ff
= rdev
->pm
.sclk
;
2432 mclk_ff
= rdev
->pm
.mclk
;
2434 temp
= (rdev
->mc
.vram_width
/ 8) * (rdev
->mc
.vram_is_ddr
? 2 : 1);
2435 temp_ff
.full
= rfixed_const(temp
);
2436 mem_bw
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2440 peak_disp_bw
.full
= 0;
2442 temp_ff
.full
= rfixed_const(1000);
2443 pix_clk
.full
= rfixed_const(mode1
->clock
); /* convert to fixed point */
2444 pix_clk
.full
= rfixed_div(pix_clk
, temp_ff
);
2445 temp_ff
.full
= rfixed_const(pixel_bytes1
);
2446 peak_disp_bw
.full
+= rfixed_mul(pix_clk
, temp_ff
);
2449 temp_ff
.full
= rfixed_const(1000);
2450 pix_clk2
.full
= rfixed_const(mode2
->clock
); /* convert to fixed point */
2451 pix_clk2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2452 temp_ff
.full
= rfixed_const(pixel_bytes2
);
2453 peak_disp_bw
.full
+= rfixed_mul(pix_clk2
, temp_ff
);
2456 mem_bw
.full
= rfixed_mul(mem_bw
, min_mem_eff
);
2457 if (peak_disp_bw
.full
>= mem_bw
.full
) {
2458 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2459 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2462 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2463 temp
= RREG32(RADEON_MEM_TIMING_CNTL
);
2464 if ((rdev
->family
== CHIP_RV100
) || (rdev
->flags
& RADEON_IS_IGP
)) { /* RV100, M6, IGPs */
2465 mem_trcd
= ((temp
>> 2) & 0x3) + 1;
2466 mem_trp
= ((temp
& 0x3)) + 1;
2467 mem_tras
= ((temp
& 0x70) >> 4) + 1;
2468 } else if (rdev
->family
== CHIP_R300
||
2469 rdev
->family
== CHIP_R350
) { /* r300, r350 */
2470 mem_trcd
= (temp
& 0x7) + 1;
2471 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2472 mem_tras
= ((temp
>> 11) & 0xf) + 4;
2473 } else if (rdev
->family
== CHIP_RV350
||
2474 rdev
->family
<= CHIP_RV380
) {
2476 mem_trcd
= (temp
& 0x7) + 3;
2477 mem_trp
= ((temp
>> 8) & 0x7) + 3;
2478 mem_tras
= ((temp
>> 11) & 0xf) + 6;
2479 } else if (rdev
->family
== CHIP_R420
||
2480 rdev
->family
== CHIP_R423
||
2481 rdev
->family
== CHIP_RV410
) {
2483 mem_trcd
= (temp
& 0xf) + 3;
2486 mem_trp
= ((temp
>> 8) & 0xf) + 3;
2489 mem_tras
= ((temp
>> 12) & 0x1f) + 6;
2492 } else { /* RV200, R200 */
2493 mem_trcd
= (temp
& 0x7) + 1;
2494 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2495 mem_tras
= ((temp
>> 12) & 0xf) + 4;
2498 trcd_ff
.full
= rfixed_const(mem_trcd
);
2499 trp_ff
.full
= rfixed_const(mem_trp
);
2500 tras_ff
.full
= rfixed_const(mem_tras
);
2502 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2503 temp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2504 data
= (temp
& (7 << 20)) >> 20;
2505 if ((rdev
->family
== CHIP_RV100
) || rdev
->flags
& RADEON_IS_IGP
) {
2506 if (rdev
->family
== CHIP_RS480
) /* don't think rs400 */
2507 tcas_ff
= memtcas_rs480_ff
[data
];
2509 tcas_ff
= memtcas_ff
[data
];
2511 tcas_ff
= memtcas2_ff
[data
];
2513 if (rdev
->family
== CHIP_RS400
||
2514 rdev
->family
== CHIP_RS480
) {
2515 /* extra cas latency stored in bits 23-25 0-4 clocks */
2516 data
= (temp
>> 23) & 0x7;
2518 tcas_ff
.full
+= rfixed_const(data
);
2521 if (ASIC_IS_R300(rdev
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2522 /* on the R300, Tcas is included in Trbs.
2524 temp
= RREG32(RADEON_MEM_CNTL
);
2525 data
= (R300_MEM_NUM_CHANNELS_MASK
& temp
);
2527 if (R300_MEM_USE_CD_CH_ONLY
& temp
) {
2528 temp
= RREG32(R300_MC_IND_INDEX
);
2529 temp
&= ~R300_MC_IND_ADDR_MASK
;
2530 temp
|= R300_MC_READ_CNTL_CD_mcind
;
2531 WREG32(R300_MC_IND_INDEX
, temp
);
2532 temp
= RREG32(R300_MC_IND_DATA
);
2533 data
= (R300_MEM_RBS_POSITION_C_MASK
& temp
);
2535 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2536 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2539 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2540 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2542 if (rdev
->family
== CHIP_RV410
||
2543 rdev
->family
== CHIP_R420
||
2544 rdev
->family
== CHIP_R423
)
2545 trbs_ff
= memtrbs_r4xx
[data
];
2547 trbs_ff
= memtrbs
[data
];
2548 tcas_ff
.full
+= trbs_ff
.full
;
2551 sclk_eff_ff
.full
= sclk_ff
.full
;
2553 if (rdev
->flags
& RADEON_IS_AGP
) {
2554 fixed20_12 agpmode_ff
;
2555 agpmode_ff
.full
= rfixed_const(radeon_agpmode
);
2556 temp_ff
.full
= rfixed_const_666(16);
2557 sclk_eff_ff
.full
-= rfixed_mul(agpmode_ff
, temp_ff
);
2559 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2561 if (ASIC_IS_R300(rdev
)) {
2562 sclk_delay_ff
.full
= rfixed_const(250);
2564 if ((rdev
->family
== CHIP_RV100
) ||
2565 rdev
->flags
& RADEON_IS_IGP
) {
2566 if (rdev
->mc
.vram_is_ddr
)
2567 sclk_delay_ff
.full
= rfixed_const(41);
2569 sclk_delay_ff
.full
= rfixed_const(33);
2571 if (rdev
->mc
.vram_width
== 128)
2572 sclk_delay_ff
.full
= rfixed_const(57);
2574 sclk_delay_ff
.full
= rfixed_const(41);
2578 mc_latency_sclk
.full
= rfixed_div(sclk_delay_ff
, sclk_eff_ff
);
2580 if (rdev
->mc
.vram_is_ddr
) {
2581 if (rdev
->mc
.vram_width
== 32) {
2582 k1
.full
= rfixed_const(40);
2585 k1
.full
= rfixed_const(20);
2589 k1
.full
= rfixed_const(40);
2593 temp_ff
.full
= rfixed_const(2);
2594 mc_latency_mclk
.full
= rfixed_mul(trcd_ff
, temp_ff
);
2595 temp_ff
.full
= rfixed_const(c
);
2596 mc_latency_mclk
.full
+= rfixed_mul(tcas_ff
, temp_ff
);
2597 temp_ff
.full
= rfixed_const(4);
2598 mc_latency_mclk
.full
+= rfixed_mul(tras_ff
, temp_ff
);
2599 mc_latency_mclk
.full
+= rfixed_mul(trp_ff
, temp_ff
);
2600 mc_latency_mclk
.full
+= k1
.full
;
2602 mc_latency_mclk
.full
= rfixed_div(mc_latency_mclk
, mclk_ff
);
2603 mc_latency_mclk
.full
+= rfixed_div(temp_ff
, sclk_eff_ff
);
2606 HW cursor time assuming worst case of full size colour cursor.
2608 temp_ff
.full
= rfixed_const((2 * (cur_size
- (rdev
->mc
.vram_is_ddr
+ 1))));
2609 temp_ff
.full
+= trcd_ff
.full
;
2610 if (temp_ff
.full
< tras_ff
.full
)
2611 temp_ff
.full
= tras_ff
.full
;
2612 cur_latency_mclk
.full
= rfixed_div(temp_ff
, mclk_ff
);
2614 temp_ff
.full
= rfixed_const(cur_size
);
2615 cur_latency_sclk
.full
= rfixed_div(temp_ff
, sclk_eff_ff
);
2617 Find the total latency for the display data.
2619 disp_latency_overhead
.full
= rfixed_const(8);
2620 disp_latency_overhead
.full
= rfixed_div(disp_latency_overhead
, sclk_ff
);
2621 mc_latency_mclk
.full
+= disp_latency_overhead
.full
+ cur_latency_mclk
.full
;
2622 mc_latency_sclk
.full
+= disp_latency_overhead
.full
+ cur_latency_sclk
.full
;
2624 if (mc_latency_mclk
.full
> mc_latency_sclk
.full
)
2625 disp_latency
.full
= mc_latency_mclk
.full
;
2627 disp_latency
.full
= mc_latency_sclk
.full
;
2629 /* setup Max GRPH_STOP_REQ default value */
2630 if (ASIC_IS_RV100(rdev
))
2631 max_stop_req
= 0x5c;
2633 max_stop_req
= 0x7c;
2637 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2638 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2640 stop_req
= mode1
->hdisplay
* pixel_bytes1
/ 16;
2642 if (stop_req
> max_stop_req
)
2643 stop_req
= max_stop_req
;
2646 Find the drain rate of the display buffer.
2648 temp_ff
.full
= rfixed_const((16/pixel_bytes1
));
2649 disp_drain_rate
.full
= rfixed_div(pix_clk
, temp_ff
);
2652 Find the critical point of the display buffer.
2654 crit_point_ff
.full
= rfixed_mul(disp_drain_rate
, disp_latency
);
2655 crit_point_ff
.full
+= rfixed_const_half(0);
2657 critical_point
= rfixed_trunc(crit_point_ff
);
2659 if (rdev
->disp_priority
== 2) {
2664 The critical point should never be above max_stop_req-4. Setting
2665 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2667 if (max_stop_req
- critical_point
< 4)
2670 if (critical_point
== 0 && mode2
&& rdev
->family
== CHIP_R300
) {
2671 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2672 critical_point
= 0x10;
2675 temp
= RREG32(RADEON_GRPH_BUFFER_CNTL
);
2676 temp
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2677 temp
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2678 temp
&= ~(RADEON_GRPH_START_REQ_MASK
);
2679 if ((rdev
->family
== CHIP_R350
) &&
2680 (stop_req
> 0x15)) {
2683 temp
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2684 temp
|= RADEON_GRPH_BUFFER_SIZE
;
2685 temp
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2686 RADEON_GRPH_CRITICAL_AT_SOF
|
2687 RADEON_GRPH_STOP_CNTL
);
2689 Write the result into the register.
2691 WREG32(RADEON_GRPH_BUFFER_CNTL
, ((temp
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2692 (critical_point
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2695 if ((rdev
->family
== CHIP_RS400
) ||
2696 (rdev
->family
== CHIP_RS480
)) {
2697 /* attempt to program RS400 disp regs correctly ??? */
2698 temp
= RREG32(RS400_DISP1_REG_CNTL
);
2699 temp
&= ~(RS400_DISP1_START_REQ_LEVEL_MASK
|
2700 RS400_DISP1_STOP_REQ_LEVEL_MASK
);
2701 WREG32(RS400_DISP1_REQ_CNTL1
, (temp
|
2702 (critical_point
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2703 (critical_point
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2704 temp
= RREG32(RS400_DMIF_MEM_CNTL1
);
2705 temp
&= ~(RS400_DISP1_CRITICAL_POINT_START_MASK
|
2706 RS400_DISP1_CRITICAL_POINT_STOP_MASK
);
2707 WREG32(RS400_DMIF_MEM_CNTL1
, (temp
|
2708 (critical_point
<< RS400_DISP1_CRITICAL_POINT_START_SHIFT
) |
2709 (critical_point
<< RS400_DISP1_CRITICAL_POINT_STOP_SHIFT
)));
2713 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2714 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2715 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL
));
2720 stop_req
= mode2
->hdisplay
* pixel_bytes2
/ 16;
2722 if (stop_req
> max_stop_req
)
2723 stop_req
= max_stop_req
;
2726 Find the drain rate of the display buffer.
2728 temp_ff
.full
= rfixed_const((16/pixel_bytes2
));
2729 disp_drain_rate2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2731 grph2_cntl
= RREG32(RADEON_GRPH2_BUFFER_CNTL
);
2732 grph2_cntl
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2733 grph2_cntl
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2734 grph2_cntl
&= ~(RADEON_GRPH_START_REQ_MASK
);
2735 if ((rdev
->family
== CHIP_R350
) &&
2736 (stop_req
> 0x15)) {
2739 grph2_cntl
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2740 grph2_cntl
|= RADEON_GRPH_BUFFER_SIZE
;
2741 grph2_cntl
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2742 RADEON_GRPH_CRITICAL_AT_SOF
|
2743 RADEON_GRPH_STOP_CNTL
);
2745 if ((rdev
->family
== CHIP_RS100
) ||
2746 (rdev
->family
== CHIP_RS200
))
2747 critical_point2
= 0;
2749 temp
= (rdev
->mc
.vram_width
* rdev
->mc
.vram_is_ddr
+ 1)/128;
2750 temp_ff
.full
= rfixed_const(temp
);
2751 temp_ff
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2752 if (sclk_ff
.full
< temp_ff
.full
)
2753 temp_ff
.full
= sclk_ff
.full
;
2755 read_return_rate
.full
= temp_ff
.full
;
2758 temp_ff
.full
= read_return_rate
.full
- disp_drain_rate
.full
;
2759 time_disp1_drop_priority
.full
= rfixed_div(crit_point_ff
, temp_ff
);
2761 time_disp1_drop_priority
.full
= 0;
2763 crit_point_ff
.full
= disp_latency
.full
+ time_disp1_drop_priority
.full
+ disp_latency
.full
;
2764 crit_point_ff
.full
= rfixed_mul(crit_point_ff
, disp_drain_rate2
);
2765 crit_point_ff
.full
+= rfixed_const_half(0);
2767 critical_point2
= rfixed_trunc(crit_point_ff
);
2769 if (rdev
->disp_priority
== 2) {
2770 critical_point2
= 0;
2773 if (max_stop_req
- critical_point2
< 4)
2774 critical_point2
= 0;
2778 if (critical_point2
== 0 && rdev
->family
== CHIP_R300
) {
2779 /* some R300 cards have problem with this set to 0 */
2780 critical_point2
= 0x10;
2783 WREG32(RADEON_GRPH2_BUFFER_CNTL
, ((grph2_cntl
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2784 (critical_point2
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2786 if ((rdev
->family
== CHIP_RS400
) ||
2787 (rdev
->family
== CHIP_RS480
)) {
2789 /* attempt to program RS400 disp2 regs correctly ??? */
2790 temp
= RREG32(RS400_DISP2_REQ_CNTL1
);
2791 temp
&= ~(RS400_DISP2_START_REQ_LEVEL_MASK
|
2792 RS400_DISP2_STOP_REQ_LEVEL_MASK
);
2793 WREG32(RS400_DISP2_REQ_CNTL1
, (temp
|
2794 (critical_point2
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2795 (critical_point2
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2796 temp
= RREG32(RS400_DISP2_REQ_CNTL2
);
2797 temp
&= ~(RS400_DISP2_CRITICAL_POINT_START_MASK
|
2798 RS400_DISP2_CRITICAL_POINT_STOP_MASK
);
2799 WREG32(RS400_DISP2_REQ_CNTL2
, (temp
|
2800 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_START_SHIFT
) |
2801 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_STOP_SHIFT
)));
2803 WREG32(RS400_DISP2_REQ_CNTL1
, 0x105DC1CC);
2804 WREG32(RS400_DISP2_REQ_CNTL2
, 0x2749D000);
2805 WREG32(RS400_DMIF_MEM_CNTL1
, 0x29CA71DC);
2806 WREG32(RS400_DISP1_REQ_CNTL1
, 0x28FBC3AC);
2809 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2810 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL
));
2814 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture
*t
)
2816 DRM_ERROR("pitch %d\n", t
->pitch
);
2817 DRM_ERROR("use_pitch %d\n", t
->use_pitch
);
2818 DRM_ERROR("width %d\n", t
->width
);
2819 DRM_ERROR("width_11 %d\n", t
->width_11
);
2820 DRM_ERROR("height %d\n", t
->height
);
2821 DRM_ERROR("height_11 %d\n", t
->height_11
);
2822 DRM_ERROR("num levels %d\n", t
->num_levels
);
2823 DRM_ERROR("depth %d\n", t
->txdepth
);
2824 DRM_ERROR("bpp %d\n", t
->cpp
);
2825 DRM_ERROR("coordinate type %d\n", t
->tex_coord_type
);
2826 DRM_ERROR("width round to power of 2 %d\n", t
->roundup_w
);
2827 DRM_ERROR("height round to power of 2 %d\n", t
->roundup_h
);
2828 DRM_ERROR("compress format %d\n", t
->compress_format
);
2831 static int r100_cs_track_cube(struct radeon_device
*rdev
,
2832 struct r100_cs_track
*track
, unsigned idx
)
2834 unsigned face
, w
, h
;
2835 struct radeon_bo
*cube_robj
;
2838 for (face
= 0; face
< 5; face
++) {
2839 cube_robj
= track
->textures
[idx
].cube_info
[face
].robj
;
2840 w
= track
->textures
[idx
].cube_info
[face
].width
;
2841 h
= track
->textures
[idx
].cube_info
[face
].height
;
2844 size
*= track
->textures
[idx
].cpp
;
2846 size
+= track
->textures
[idx
].cube_info
[face
].offset
;
2848 if (size
> radeon_bo_size(cube_robj
)) {
2849 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2850 size
, radeon_bo_size(cube_robj
));
2851 r100_cs_track_texture_print(&track
->textures
[idx
]);
2858 static int r100_track_compress_size(int compress_format
, int w
, int h
)
2860 int block_width
, block_height
, block_bytes
;
2861 int wblocks
, hblocks
;
2868 switch (compress_format
) {
2869 case R100_TRACK_COMP_DXT1
:
2874 case R100_TRACK_COMP_DXT35
:
2880 hblocks
= (h
+ block_height
- 1) / block_height
;
2881 wblocks
= (w
+ block_width
- 1) / block_width
;
2882 if (wblocks
< min_wblocks
)
2883 wblocks
= min_wblocks
;
2884 sz
= wblocks
* hblocks
* block_bytes
;
2888 static int r100_cs_track_texture_check(struct radeon_device
*rdev
,
2889 struct r100_cs_track
*track
)
2891 struct radeon_bo
*robj
;
2893 unsigned u
, i
, w
, h
, d
;
2896 for (u
= 0; u
< track
->num_texture
; u
++) {
2897 if (!track
->textures
[u
].enabled
)
2899 robj
= track
->textures
[u
].robj
;
2901 DRM_ERROR("No texture bound to unit %u\n", u
);
2905 for (i
= 0; i
<= track
->textures
[u
].num_levels
; i
++) {
2906 if (track
->textures
[u
].use_pitch
) {
2907 if (rdev
->family
< CHIP_R300
)
2908 w
= (track
->textures
[u
].pitch
/ track
->textures
[u
].cpp
) / (1 << i
);
2910 w
= track
->textures
[u
].pitch
/ (1 << i
);
2912 w
= track
->textures
[u
].width
;
2913 if (rdev
->family
>= CHIP_RV515
)
2914 w
|= track
->textures
[u
].width_11
;
2916 if (track
->textures
[u
].roundup_w
)
2917 w
= roundup_pow_of_two(w
);
2919 h
= track
->textures
[u
].height
;
2920 if (rdev
->family
>= CHIP_RV515
)
2921 h
|= track
->textures
[u
].height_11
;
2923 if (track
->textures
[u
].roundup_h
)
2924 h
= roundup_pow_of_two(h
);
2925 if (track
->textures
[u
].tex_coord_type
== 1) {
2926 d
= (1 << track
->textures
[u
].txdepth
) / (1 << i
);
2932 if (track
->textures
[u
].compress_format
) {
2934 size
+= r100_track_compress_size(track
->textures
[u
].compress_format
, w
, h
) * d
;
2935 /* compressed textures are block based */
2939 size
*= track
->textures
[u
].cpp
;
2941 switch (track
->textures
[u
].tex_coord_type
) {
2946 if (track
->separate_cube
) {
2947 ret
= r100_cs_track_cube(rdev
, track
, u
);
2954 DRM_ERROR("Invalid texture coordinate type %u for unit "
2955 "%u\n", track
->textures
[u
].tex_coord_type
, u
);
2958 if (size
> radeon_bo_size(robj
)) {
2959 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2960 "%lu\n", u
, size
, radeon_bo_size(robj
));
2961 r100_cs_track_texture_print(&track
->textures
[u
]);
2968 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
2975 for (i
= 0; i
< track
->num_cb
; i
++) {
2976 if (track
->cb
[i
].robj
== NULL
) {
2977 if (!(track
->fastfill
|| track
->color_channel_mask
||
2978 track
->blend_read_enable
)) {
2981 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i
);
2984 size
= track
->cb
[i
].pitch
* track
->cb
[i
].cpp
* track
->maxy
;
2985 size
+= track
->cb
[i
].offset
;
2986 if (size
> radeon_bo_size(track
->cb
[i
].robj
)) {
2987 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2988 "(need %lu have %lu) !\n", i
, size
,
2989 radeon_bo_size(track
->cb
[i
].robj
));
2990 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2991 i
, track
->cb
[i
].pitch
, track
->cb
[i
].cpp
,
2992 track
->cb
[i
].offset
, track
->maxy
);
2996 if (track
->z_enabled
) {
2997 if (track
->zb
.robj
== NULL
) {
2998 DRM_ERROR("[drm] No buffer for z buffer !\n");
3001 size
= track
->zb
.pitch
* track
->zb
.cpp
* track
->maxy
;
3002 size
+= track
->zb
.offset
;
3003 if (size
> radeon_bo_size(track
->zb
.robj
)) {
3004 DRM_ERROR("[drm] Buffer too small for z buffer "
3005 "(need %lu have %lu) !\n", size
,
3006 radeon_bo_size(track
->zb
.robj
));
3007 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3008 track
->zb
.pitch
, track
->zb
.cpp
,
3009 track
->zb
.offset
, track
->maxy
);
3013 prim_walk
= (track
->vap_vf_cntl
>> 4) & 0x3;
3014 if (track
->vap_vf_cntl
& (1 << 14)) {
3015 nverts
= track
->vap_alt_nverts
;
3017 nverts
= (track
->vap_vf_cntl
>> 16) & 0xFFFF;
3019 switch (prim_walk
) {
3021 for (i
= 0; i
< track
->num_arrays
; i
++) {
3022 size
= track
->arrays
[i
].esize
* track
->max_indx
* 4;
3023 if (track
->arrays
[i
].robj
== NULL
) {
3024 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3025 "bound\n", prim_walk
, i
);
3028 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3029 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3030 "need %lu dwords have %lu dwords\n",
3031 prim_walk
, i
, size
>> 2,
3032 radeon_bo_size(track
->arrays
[i
].robj
)
3034 DRM_ERROR("Max indices %u\n", track
->max_indx
);
3040 for (i
= 0; i
< track
->num_arrays
; i
++) {
3041 size
= track
->arrays
[i
].esize
* (nverts
- 1) * 4;
3042 if (track
->arrays
[i
].robj
== NULL
) {
3043 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3044 "bound\n", prim_walk
, i
);
3047 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3048 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3049 "need %lu dwords have %lu dwords\n",
3050 prim_walk
, i
, size
>> 2,
3051 radeon_bo_size(track
->arrays
[i
].robj
)
3058 size
= track
->vtx_size
* nverts
;
3059 if (size
!= track
->immd_dwords
) {
3060 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3061 track
->immd_dwords
, size
);
3062 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3063 nverts
, track
->vtx_size
);
3068 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3072 return r100_cs_track_texture_check(rdev
, track
);
3075 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
3079 if (rdev
->family
< CHIP_R300
) {
3081 if (rdev
->family
<= CHIP_RS200
)
3082 track
->num_texture
= 3;
3084 track
->num_texture
= 6;
3086 track
->separate_cube
= 1;
3089 track
->num_texture
= 16;
3091 track
->separate_cube
= 0;
3094 for (i
= 0; i
< track
->num_cb
; i
++) {
3095 track
->cb
[i
].robj
= NULL
;
3096 track
->cb
[i
].pitch
= 8192;
3097 track
->cb
[i
].cpp
= 16;
3098 track
->cb
[i
].offset
= 0;
3100 track
->z_enabled
= true;
3101 track
->zb
.robj
= NULL
;
3102 track
->zb
.pitch
= 8192;
3104 track
->zb
.offset
= 0;
3105 track
->vtx_size
= 0x7F;
3106 track
->immd_dwords
= 0xFFFFFFFFUL
;
3107 track
->num_arrays
= 11;
3108 track
->max_indx
= 0x00FFFFFFUL
;
3109 for (i
= 0; i
< track
->num_arrays
; i
++) {
3110 track
->arrays
[i
].robj
= NULL
;
3111 track
->arrays
[i
].esize
= 0x7F;
3113 for (i
= 0; i
< track
->num_texture
; i
++) {
3114 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
3115 track
->textures
[i
].pitch
= 16536;
3116 track
->textures
[i
].width
= 16536;
3117 track
->textures
[i
].height
= 16536;
3118 track
->textures
[i
].width_11
= 1 << 11;
3119 track
->textures
[i
].height_11
= 1 << 11;
3120 track
->textures
[i
].num_levels
= 12;
3121 if (rdev
->family
<= CHIP_RS200
) {
3122 track
->textures
[i
].tex_coord_type
= 0;
3123 track
->textures
[i
].txdepth
= 0;
3125 track
->textures
[i
].txdepth
= 16;
3126 track
->textures
[i
].tex_coord_type
= 1;
3128 track
->textures
[i
].cpp
= 64;
3129 track
->textures
[i
].robj
= NULL
;
3130 /* CS IB emission code makes sure texture unit are disabled */
3131 track
->textures
[i
].enabled
= false;
3132 track
->textures
[i
].roundup_w
= true;
3133 track
->textures
[i
].roundup_h
= true;
3134 if (track
->separate_cube
)
3135 for (face
= 0; face
< 5; face
++) {
3136 track
->textures
[i
].cube_info
[face
].robj
= NULL
;
3137 track
->textures
[i
].cube_info
[face
].width
= 16536;
3138 track
->textures
[i
].cube_info
[face
].height
= 16536;
3139 track
->textures
[i
].cube_info
[face
].offset
= 0;
3144 int r100_ring_test(struct radeon_device
*rdev
)
3151 r
= radeon_scratch_get(rdev
, &scratch
);
3153 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
3156 WREG32(scratch
, 0xCAFEDEAD);
3157 r
= radeon_ring_lock(rdev
, 2);
3159 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
3160 radeon_scratch_free(rdev
, scratch
);
3163 radeon_ring_write(rdev
, PACKET0(scratch
, 0));
3164 radeon_ring_write(rdev
, 0xDEADBEEF);
3165 radeon_ring_unlock_commit(rdev
);
3166 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3167 tmp
= RREG32(scratch
);
3168 if (tmp
== 0xDEADBEEF) {
3173 if (i
< rdev
->usec_timeout
) {
3174 DRM_INFO("ring test succeeded in %d usecs\n", i
);
3176 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3180 radeon_scratch_free(rdev
, scratch
);
3184 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3186 radeon_ring_write(rdev
, PACKET0(RADEON_CP_IB_BASE
, 1));
3187 radeon_ring_write(rdev
, ib
->gpu_addr
);
3188 radeon_ring_write(rdev
, ib
->length_dw
);
3191 int r100_ib_test(struct radeon_device
*rdev
)
3193 struct radeon_ib
*ib
;
3199 r
= radeon_scratch_get(rdev
, &scratch
);
3201 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
3204 WREG32(scratch
, 0xCAFEDEAD);
3205 r
= radeon_ib_get(rdev
, &ib
);
3209 ib
->ptr
[0] = PACKET0(scratch
, 0);
3210 ib
->ptr
[1] = 0xDEADBEEF;
3211 ib
->ptr
[2] = PACKET2(0);
3212 ib
->ptr
[3] = PACKET2(0);
3213 ib
->ptr
[4] = PACKET2(0);
3214 ib
->ptr
[5] = PACKET2(0);
3215 ib
->ptr
[6] = PACKET2(0);
3216 ib
->ptr
[7] = PACKET2(0);
3218 r
= radeon_ib_schedule(rdev
, ib
);
3220 radeon_scratch_free(rdev
, scratch
);
3221 radeon_ib_free(rdev
, &ib
);
3224 r
= radeon_fence_wait(ib
->fence
, false);
3228 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3229 tmp
= RREG32(scratch
);
3230 if (tmp
== 0xDEADBEEF) {
3235 if (i
< rdev
->usec_timeout
) {
3236 DRM_INFO("ib test succeeded in %u usecs\n", i
);
3238 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3242 radeon_scratch_free(rdev
, scratch
);
3243 radeon_ib_free(rdev
, &ib
);
3247 void r100_ib_fini(struct radeon_device
*rdev
)
3249 radeon_ib_pool_fini(rdev
);
3252 int r100_ib_init(struct radeon_device
*rdev
)
3256 r
= radeon_ib_pool_init(rdev
);
3258 dev_err(rdev
->dev
, "failled initializing IB pool (%d).\n", r
);
3262 r
= r100_ib_test(rdev
);
3264 dev_err(rdev
->dev
, "failled testing IB (%d).\n", r
);
3271 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3273 /* Shutdown CP we shouldn't need to do that but better be safe than
3276 rdev
->cp
.ready
= false;
3277 WREG32(R_000740_CP_CSQ_CNTL
, 0);
3279 /* Save few CRTC registers */
3280 save
->GENMO_WT
= RREG8(R_0003C2_GENMO_WT
);
3281 save
->CRTC_EXT_CNTL
= RREG32(R_000054_CRTC_EXT_CNTL
);
3282 save
->CRTC_GEN_CNTL
= RREG32(R_000050_CRTC_GEN_CNTL
);
3283 save
->CUR_OFFSET
= RREG32(R_000260_CUR_OFFSET
);
3284 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3285 save
->CRTC2_GEN_CNTL
= RREG32(R_0003F8_CRTC2_GEN_CNTL
);
3286 save
->CUR2_OFFSET
= RREG32(R_000360_CUR2_OFFSET
);
3289 /* Disable VGA aperture access */
3290 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& save
->GENMO_WT
);
3291 /* Disable cursor, overlay, crtc */
3292 WREG32(R_000260_CUR_OFFSET
, save
->CUR_OFFSET
| S_000260_CUR_LOCK(1));
3293 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
|
3294 S_000054_CRTC_DISPLAY_DIS(1));
3295 WREG32(R_000050_CRTC_GEN_CNTL
,
3296 (C_000050_CRTC_CUR_EN
& save
->CRTC_GEN_CNTL
) |
3297 S_000050_CRTC_DISP_REQ_EN_B(1));
3298 WREG32(R_000420_OV0_SCALE_CNTL
,
3299 C_000420_OV0_OVERLAY_EN
& RREG32(R_000420_OV0_SCALE_CNTL
));
3300 WREG32(R_000260_CUR_OFFSET
, C_000260_CUR_LOCK
& save
->CUR_OFFSET
);
3301 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3302 WREG32(R_000360_CUR2_OFFSET
, save
->CUR2_OFFSET
|
3303 S_000360_CUR2_LOCK(1));
3304 WREG32(R_0003F8_CRTC2_GEN_CNTL
,
3305 (C_0003F8_CRTC2_CUR_EN
& save
->CRTC2_GEN_CNTL
) |
3306 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3307 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3308 WREG32(R_000360_CUR2_OFFSET
,
3309 C_000360_CUR2_LOCK
& save
->CUR2_OFFSET
);
3313 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3315 /* Update base address for crtc */
3316 WREG32(R_00023C_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_start
);
3317 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3318 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_start
);
3320 /* Restore CRTC registers */
3321 WREG8(R_0003C2_GENMO_WT
, save
->GENMO_WT
);
3322 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
);
3323 WREG32(R_000050_CRTC_GEN_CNTL
, save
->CRTC_GEN_CNTL
);
3324 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3325 WREG32(R_0003F8_CRTC2_GEN_CNTL
, save
->CRTC2_GEN_CNTL
);
3329 void r100_vga_render_disable(struct radeon_device
*rdev
)
3333 tmp
= RREG8(R_0003C2_GENMO_WT
);
3334 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& tmp
);
3337 static void r100_debugfs(struct radeon_device
*rdev
)
3341 r
= r100_debugfs_mc_info_init(rdev
);
3343 dev_warn(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
3346 static void r100_mc_program(struct radeon_device
*rdev
)
3348 struct r100_mc_save save
;
3350 /* Stops all mc clients */
3351 r100_mc_stop(rdev
, &save
);
3352 if (rdev
->flags
& RADEON_IS_AGP
) {
3353 WREG32(R_00014C_MC_AGP_LOCATION
,
3354 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
3355 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
3356 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
3357 if (rdev
->family
> CHIP_RV200
)
3358 WREG32(R_00015C_AGP_BASE_2
,
3359 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
3361 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
3362 WREG32(R_000170_AGP_BASE
, 0);
3363 if (rdev
->family
> CHIP_RV200
)
3364 WREG32(R_00015C_AGP_BASE_2
, 0);
3366 /* Wait for mc idle */
3367 if (r100_mc_wait_for_idle(rdev
))
3368 dev_warn(rdev
->dev
, "Wait for MC idle timeout.\n");
3369 /* Program MC, should be a 32bits limited address space */
3370 WREG32(R_000148_MC_FB_LOCATION
,
3371 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
3372 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
3373 r100_mc_resume(rdev
, &save
);
3376 void r100_clock_startup(struct radeon_device
*rdev
)
3380 if (radeon_dynclks
!= -1 && radeon_dynclks
)
3381 radeon_legacy_set_clock_gating(rdev
, 1);
3382 /* We need to force on some of the block */
3383 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
3384 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3385 if ((rdev
->family
== CHIP_RV250
) || (rdev
->family
== CHIP_RV280
))
3386 tmp
|= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3387 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
3390 static int r100_startup(struct radeon_device
*rdev
)
3394 /* set common regs */
3395 r100_set_common_regs(rdev
);
3397 r100_mc_program(rdev
);
3399 r100_clock_startup(rdev
);
3400 /* Initialize GPU configuration (# pipes, ...) */
3401 r100_gpu_init(rdev
);
3402 /* Initialize GART (initialize after TTM so we can allocate
3403 * memory through TTM but finalize after TTM) */
3404 r100_enable_bm(rdev
);
3405 if (rdev
->flags
& RADEON_IS_PCI
) {
3406 r
= r100_pci_gart_enable(rdev
);
3412 rdev
->config
.r100
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
3413 /* 1M ring buffer */
3414 r
= r100_cp_init(rdev
, 1024 * 1024);
3416 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
3419 r
= r100_wb_init(rdev
);
3421 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
3422 r
= r100_ib_init(rdev
);
3424 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
3430 int r100_resume(struct radeon_device
*rdev
)
3432 /* Make sur GART are not working */
3433 if (rdev
->flags
& RADEON_IS_PCI
)
3434 r100_pci_gart_disable(rdev
);
3435 /* Resume clock before doing reset */
3436 r100_clock_startup(rdev
);
3437 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3438 if (radeon_gpu_reset(rdev
)) {
3439 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3440 RREG32(R_000E40_RBBM_STATUS
),
3441 RREG32(R_0007C0_CP_STAT
));
3444 radeon_combios_asic_init(rdev
->ddev
);
3445 /* Resume clock after posting */
3446 r100_clock_startup(rdev
);
3447 /* Initialize surface registers */
3448 radeon_surface_init(rdev
);
3449 return r100_startup(rdev
);
3452 int r100_suspend(struct radeon_device
*rdev
)
3454 r100_cp_disable(rdev
);
3455 r100_wb_disable(rdev
);
3456 r100_irq_disable(rdev
);
3457 if (rdev
->flags
& RADEON_IS_PCI
)
3458 r100_pci_gart_disable(rdev
);
3462 void r100_fini(struct radeon_device
*rdev
)
3464 radeon_pm_fini(rdev
);
3468 radeon_gem_fini(rdev
);
3469 if (rdev
->flags
& RADEON_IS_PCI
)
3470 r100_pci_gart_fini(rdev
);
3471 radeon_agp_fini(rdev
);
3472 radeon_irq_kms_fini(rdev
);
3473 radeon_fence_driver_fini(rdev
);
3474 radeon_bo_fini(rdev
);
3475 radeon_atombios_fini(rdev
);
3480 int r100_init(struct radeon_device
*rdev
)
3484 /* Register debugfs file specific to this group of asics */
3487 r100_vga_render_disable(rdev
);
3488 /* Initialize scratch registers */
3489 radeon_scratch_init(rdev
);
3490 /* Initialize surface registers */
3491 radeon_surface_init(rdev
);
3492 /* TODO: disable VGA need to use VGA request */
3494 if (!radeon_get_bios(rdev
)) {
3495 if (ASIC_IS_AVIVO(rdev
))
3498 if (rdev
->is_atom_bios
) {
3499 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
3502 r
= radeon_combios_init(rdev
);
3506 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3507 if (radeon_gpu_reset(rdev
)) {
3509 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3510 RREG32(R_000E40_RBBM_STATUS
),
3511 RREG32(R_0007C0_CP_STAT
));
3513 /* check if cards are posted or not */
3514 if (radeon_boot_test_post_card(rdev
) == false)
3516 /* Set asic errata */
3518 /* Initialize clocks */
3519 radeon_get_clock_info(rdev
->ddev
);
3520 /* Initialize power management */
3521 radeon_pm_init(rdev
);
3522 /* initialize AGP */
3523 if (rdev
->flags
& RADEON_IS_AGP
) {
3524 r
= radeon_agp_init(rdev
);
3526 radeon_agp_disable(rdev
);
3529 /* initialize VRAM */
3532 r
= radeon_fence_driver_init(rdev
);
3535 r
= radeon_irq_kms_init(rdev
);
3538 /* Memory manager */
3539 r
= radeon_bo_init(rdev
);
3542 if (rdev
->flags
& RADEON_IS_PCI
) {
3543 r
= r100_pci_gart_init(rdev
);
3547 r100_set_safe_registers(rdev
);
3548 rdev
->accel_working
= true;
3549 r
= r100_startup(rdev
);
3551 /* Somethings want wront with the accel init stop accel */
3552 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
3556 radeon_irq_kms_fini(rdev
);
3557 if (rdev
->flags
& RADEON_IS_PCI
)
3558 r100_pci_gart_fini(rdev
);
3559 rdev
->accel_working
= false;