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Merge branch 'upstream-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 /* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 * and others in some cases.
71 */
72
73 /**
74 * r100_wait_for_vblank - vblank wait asic callback.
75 *
76 * @rdev: radeon_device pointer
77 * @crtc: crtc to wait for vblank on
78 *
79 * Wait for vblank on the requested crtc (r1xx-r4xx).
80 */
81 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
82 {
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
84 int i;
85
86 if (radeon_crtc->crtc_id == 0) {
87 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
90 break;
91 udelay(1);
92 }
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
95 break;
96 udelay(1);
97 }
98 }
99 } else {
100 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
101 for (i = 0; i < rdev->usec_timeout; i++) {
102 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
103 break;
104 udelay(1);
105 }
106 for (i = 0; i < rdev->usec_timeout; i++) {
107 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
108 break;
109 udelay(1);
110 }
111 }
112 }
113 }
114
115 /**
116 * r100_pre_page_flip - pre-pageflip callback.
117 *
118 * @rdev: radeon_device pointer
119 * @crtc: crtc to prepare for pageflip on
120 *
121 * Pre-pageflip callback (r1xx-r4xx).
122 * Enables the pageflip irq (vblank irq).
123 */
124 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
125 {
126 /* enable the pflip int */
127 radeon_irq_kms_pflip_irq_get(rdev, crtc);
128 }
129
130 /**
131 * r100_post_page_flip - pos-pageflip callback.
132 *
133 * @rdev: radeon_device pointer
134 * @crtc: crtc to cleanup pageflip on
135 *
136 * Post-pageflip callback (r1xx-r4xx).
137 * Disables the pageflip irq (vblank irq).
138 */
139 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
140 {
141 /* disable the pflip int */
142 radeon_irq_kms_pflip_irq_put(rdev, crtc);
143 }
144
145 /**
146 * r100_page_flip - pageflip callback.
147 *
148 * @rdev: radeon_device pointer
149 * @crtc_id: crtc to cleanup pageflip on
150 * @crtc_base: new address of the crtc (GPU MC address)
151 *
152 * Does the actual pageflip (r1xx-r4xx).
153 * During vblank we take the crtc lock and wait for the update_pending
154 * bit to go high, when it does, we release the lock, and allow the
155 * double buffered update to take place.
156 * Returns the current update pending status.
157 */
158 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
159 {
160 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
161 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
162 int i;
163
164 /* Lock the graphics update lock */
165 /* update the scanout addresses */
166 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
167
168 /* Wait for update_pending to go high. */
169 for (i = 0; i < rdev->usec_timeout; i++) {
170 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
171 break;
172 udelay(1);
173 }
174 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
175
176 /* Unlock the lock, so double-buffering can take place inside vblank */
177 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
178 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
179
180 /* Return current update_pending status: */
181 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
182 }
183
184 /**
185 * r100_pm_get_dynpm_state - look up dynpm power state callback.
186 *
187 * @rdev: radeon_device pointer
188 *
189 * Look up the optimal power state based on the
190 * current state of the GPU (r1xx-r5xx).
191 * Used for dynpm only.
192 */
193 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
194 {
195 int i;
196 rdev->pm.dynpm_can_upclock = true;
197 rdev->pm.dynpm_can_downclock = true;
198
199 switch (rdev->pm.dynpm_planned_action) {
200 case DYNPM_ACTION_MINIMUM:
201 rdev->pm.requested_power_state_index = 0;
202 rdev->pm.dynpm_can_downclock = false;
203 break;
204 case DYNPM_ACTION_DOWNCLOCK:
205 if (rdev->pm.current_power_state_index == 0) {
206 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
207 rdev->pm.dynpm_can_downclock = false;
208 } else {
209 if (rdev->pm.active_crtc_count > 1) {
210 for (i = 0; i < rdev->pm.num_power_states; i++) {
211 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
212 continue;
213 else if (i >= rdev->pm.current_power_state_index) {
214 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
215 break;
216 } else {
217 rdev->pm.requested_power_state_index = i;
218 break;
219 }
220 }
221 } else
222 rdev->pm.requested_power_state_index =
223 rdev->pm.current_power_state_index - 1;
224 }
225 /* don't use the power state if crtcs are active and no display flag is set */
226 if ((rdev->pm.active_crtc_count > 0) &&
227 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
228 RADEON_PM_MODE_NO_DISPLAY)) {
229 rdev->pm.requested_power_state_index++;
230 }
231 break;
232 case DYNPM_ACTION_UPCLOCK:
233 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
234 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
235 rdev->pm.dynpm_can_upclock = false;
236 } else {
237 if (rdev->pm.active_crtc_count > 1) {
238 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
239 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
240 continue;
241 else if (i <= rdev->pm.current_power_state_index) {
242 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
243 break;
244 } else {
245 rdev->pm.requested_power_state_index = i;
246 break;
247 }
248 }
249 } else
250 rdev->pm.requested_power_state_index =
251 rdev->pm.current_power_state_index + 1;
252 }
253 break;
254 case DYNPM_ACTION_DEFAULT:
255 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
256 rdev->pm.dynpm_can_upclock = false;
257 break;
258 case DYNPM_ACTION_NONE:
259 default:
260 DRM_ERROR("Requested mode for not defined action\n");
261 return;
262 }
263 /* only one clock mode per power state */
264 rdev->pm.requested_clock_mode_index = 0;
265
266 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].
268 clock_info[rdev->pm.requested_clock_mode_index].sclk,
269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].mclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 pcie_lanes);
273 }
274
275 /**
276 * r100_pm_init_profile - Initialize power profiles callback.
277 *
278 * @rdev: radeon_device pointer
279 *
280 * Initialize the power states used in profile mode
281 * (r1xx-r3xx).
282 * Used for profile mode only.
283 */
284 void r100_pm_init_profile(struct radeon_device *rdev)
285 {
286 /* default */
287 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
289 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
290 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
291 /* low sh */
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
296 /* mid sh */
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
301 /* high sh */
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
304 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
306 /* low mh */
307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
309 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
311 /* mid mh */
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
316 /* high mh */
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
321 }
322
323 /**
324 * r100_pm_misc - set additional pm hw parameters callback.
325 *
326 * @rdev: radeon_device pointer
327 *
328 * Set non-clock parameters associated with a power state
329 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
330 */
331 void r100_pm_misc(struct radeon_device *rdev)
332 {
333 int requested_index = rdev->pm.requested_power_state_index;
334 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
335 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
336 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
337
338 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
339 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
340 tmp = RREG32(voltage->gpio.reg);
341 if (voltage->active_high)
342 tmp |= voltage->gpio.mask;
343 else
344 tmp &= ~(voltage->gpio.mask);
345 WREG32(voltage->gpio.reg, tmp);
346 if (voltage->delay)
347 udelay(voltage->delay);
348 } else {
349 tmp = RREG32(voltage->gpio.reg);
350 if (voltage->active_high)
351 tmp &= ~voltage->gpio.mask;
352 else
353 tmp |= voltage->gpio.mask;
354 WREG32(voltage->gpio.reg, tmp);
355 if (voltage->delay)
356 udelay(voltage->delay);
357 }
358 }
359
360 sclk_cntl = RREG32_PLL(SCLK_CNTL);
361 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
362 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
363 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
364 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
365 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
366 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
367 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
368 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
369 else
370 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
371 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
372 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
373 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
375 } else
376 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
377
378 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
379 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
380 if (voltage->delay) {
381 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
382 switch (voltage->delay) {
383 case 33:
384 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
385 break;
386 case 66:
387 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
388 break;
389 case 99:
390 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
391 break;
392 case 132:
393 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
394 break;
395 }
396 } else
397 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
398 } else
399 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
400
401 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
402 sclk_cntl &= ~FORCE_HDP;
403 else
404 sclk_cntl |= FORCE_HDP;
405
406 WREG32_PLL(SCLK_CNTL, sclk_cntl);
407 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
408 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
409
410 /* set pcie lanes */
411 if ((rdev->flags & RADEON_IS_PCIE) &&
412 !(rdev->flags & RADEON_IS_IGP) &&
413 rdev->asic->pm.set_pcie_lanes &&
414 (ps->pcie_lanes !=
415 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
416 radeon_set_pcie_lanes(rdev,
417 ps->pcie_lanes);
418 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
419 }
420 }
421
422 /**
423 * r100_pm_prepare - pre-power state change callback.
424 *
425 * @rdev: radeon_device pointer
426 *
427 * Prepare for a power state change (r1xx-r4xx).
428 */
429 void r100_pm_prepare(struct radeon_device *rdev)
430 {
431 struct drm_device *ddev = rdev->ddev;
432 struct drm_crtc *crtc;
433 struct radeon_crtc *radeon_crtc;
434 u32 tmp;
435
436 /* disable any active CRTCs */
437 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
438 radeon_crtc = to_radeon_crtc(crtc);
439 if (radeon_crtc->enabled) {
440 if (radeon_crtc->crtc_id) {
441 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
442 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
443 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
444 } else {
445 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
446 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
447 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
448 }
449 }
450 }
451 }
452
453 /**
454 * r100_pm_finish - post-power state change callback.
455 *
456 * @rdev: radeon_device pointer
457 *
458 * Clean up after a power state change (r1xx-r4xx).
459 */
460 void r100_pm_finish(struct radeon_device *rdev)
461 {
462 struct drm_device *ddev = rdev->ddev;
463 struct drm_crtc *crtc;
464 struct radeon_crtc *radeon_crtc;
465 u32 tmp;
466
467 /* enable any active CRTCs */
468 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
469 radeon_crtc = to_radeon_crtc(crtc);
470 if (radeon_crtc->enabled) {
471 if (radeon_crtc->crtc_id) {
472 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
473 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
474 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
475 } else {
476 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
477 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
478 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
479 }
480 }
481 }
482 }
483
484 /**
485 * r100_gui_idle - gui idle callback.
486 *
487 * @rdev: radeon_device pointer
488 *
489 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
490 * Returns true if idle, false if not.
491 */
492 bool r100_gui_idle(struct radeon_device *rdev)
493 {
494 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
495 return false;
496 else
497 return true;
498 }
499
500 /* hpd for digital panel detect/disconnect */
501 /**
502 * r100_hpd_sense - hpd sense callback.
503 *
504 * @rdev: radeon_device pointer
505 * @hpd: hpd (hotplug detect) pin
506 *
507 * Checks if a digital monitor is connected (r1xx-r4xx).
508 * Returns true if connected, false if not connected.
509 */
510 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
511 {
512 bool connected = false;
513
514 switch (hpd) {
515 case RADEON_HPD_1:
516 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
517 connected = true;
518 break;
519 case RADEON_HPD_2:
520 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
521 connected = true;
522 break;
523 default:
524 break;
525 }
526 return connected;
527 }
528
529 /**
530 * r100_hpd_set_polarity - hpd set polarity callback.
531 *
532 * @rdev: radeon_device pointer
533 * @hpd: hpd (hotplug detect) pin
534 *
535 * Set the polarity of the hpd pin (r1xx-r4xx).
536 */
537 void r100_hpd_set_polarity(struct radeon_device *rdev,
538 enum radeon_hpd_id hpd)
539 {
540 u32 tmp;
541 bool connected = r100_hpd_sense(rdev, hpd);
542
543 switch (hpd) {
544 case RADEON_HPD_1:
545 tmp = RREG32(RADEON_FP_GEN_CNTL);
546 if (connected)
547 tmp &= ~RADEON_FP_DETECT_INT_POL;
548 else
549 tmp |= RADEON_FP_DETECT_INT_POL;
550 WREG32(RADEON_FP_GEN_CNTL, tmp);
551 break;
552 case RADEON_HPD_2:
553 tmp = RREG32(RADEON_FP2_GEN_CNTL);
554 if (connected)
555 tmp &= ~RADEON_FP2_DETECT_INT_POL;
556 else
557 tmp |= RADEON_FP2_DETECT_INT_POL;
558 WREG32(RADEON_FP2_GEN_CNTL, tmp);
559 break;
560 default:
561 break;
562 }
563 }
564
565 /**
566 * r100_hpd_init - hpd setup callback.
567 *
568 * @rdev: radeon_device pointer
569 *
570 * Setup the hpd pins used by the card (r1xx-r4xx).
571 * Set the polarity, and enable the hpd interrupts.
572 */
573 void r100_hpd_init(struct radeon_device *rdev)
574 {
575 struct drm_device *dev = rdev->ddev;
576 struct drm_connector *connector;
577 unsigned enable = 0;
578
579 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
580 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
581 enable |= 1 << radeon_connector->hpd.hpd;
582 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
583 }
584 radeon_irq_kms_enable_hpd(rdev, enable);
585 }
586
587 /**
588 * r100_hpd_fini - hpd tear down callback.
589 *
590 * @rdev: radeon_device pointer
591 *
592 * Tear down the hpd pins used by the card (r1xx-r4xx).
593 * Disable the hpd interrupts.
594 */
595 void r100_hpd_fini(struct radeon_device *rdev)
596 {
597 struct drm_device *dev = rdev->ddev;
598 struct drm_connector *connector;
599 unsigned disable = 0;
600
601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
602 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
603 disable |= 1 << radeon_connector->hpd.hpd;
604 }
605 radeon_irq_kms_disable_hpd(rdev, disable);
606 }
607
608 /*
609 * PCI GART
610 */
611 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
612 {
613 /* TODO: can we do somethings here ? */
614 /* It seems hw only cache one entry so we should discard this
615 * entry otherwise if first GPU GART read hit this entry it
616 * could end up in wrong address. */
617 }
618
619 int r100_pci_gart_init(struct radeon_device *rdev)
620 {
621 int r;
622
623 if (rdev->gart.ptr) {
624 WARN(1, "R100 PCI GART already initialized\n");
625 return 0;
626 }
627 /* Initialize common gart structure */
628 r = radeon_gart_init(rdev);
629 if (r)
630 return r;
631 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
632 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
633 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
634 return radeon_gart_table_ram_alloc(rdev);
635 }
636
637 int r100_pci_gart_enable(struct radeon_device *rdev)
638 {
639 uint32_t tmp;
640
641 radeon_gart_restore(rdev);
642 /* discard memory request outside of configured range */
643 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
644 WREG32(RADEON_AIC_CNTL, tmp);
645 /* set address range for PCI address translate */
646 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
647 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
648 /* set PCI GART page-table base address */
649 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
650 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
651 WREG32(RADEON_AIC_CNTL, tmp);
652 r100_pci_gart_tlb_flush(rdev);
653 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
654 (unsigned)(rdev->mc.gtt_size >> 20),
655 (unsigned long long)rdev->gart.table_addr);
656 rdev->gart.ready = true;
657 return 0;
658 }
659
660 void r100_pci_gart_disable(struct radeon_device *rdev)
661 {
662 uint32_t tmp;
663
664 /* discard memory request outside of configured range */
665 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
666 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
667 WREG32(RADEON_AIC_LO_ADDR, 0);
668 WREG32(RADEON_AIC_HI_ADDR, 0);
669 }
670
671 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
672 {
673 u32 *gtt = rdev->gart.ptr;
674
675 if (i < 0 || i > rdev->gart.num_gpu_pages) {
676 return -EINVAL;
677 }
678 gtt[i] = cpu_to_le32(lower_32_bits(addr));
679 return 0;
680 }
681
682 void r100_pci_gart_fini(struct radeon_device *rdev)
683 {
684 radeon_gart_fini(rdev);
685 r100_pci_gart_disable(rdev);
686 radeon_gart_table_ram_free(rdev);
687 }
688
689 int r100_irq_set(struct radeon_device *rdev)
690 {
691 uint32_t tmp = 0;
692
693 if (!rdev->irq.installed) {
694 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
695 WREG32(R_000040_GEN_INT_CNTL, 0);
696 return -EINVAL;
697 }
698 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
699 tmp |= RADEON_SW_INT_ENABLE;
700 }
701 if (rdev->irq.gui_idle) {
702 tmp |= RADEON_GUI_IDLE_MASK;
703 }
704 if (rdev->irq.crtc_vblank_int[0] ||
705 atomic_read(&rdev->irq.pflip[0])) {
706 tmp |= RADEON_CRTC_VBLANK_MASK;
707 }
708 if (rdev->irq.crtc_vblank_int[1] ||
709 atomic_read(&rdev->irq.pflip[1])) {
710 tmp |= RADEON_CRTC2_VBLANK_MASK;
711 }
712 if (rdev->irq.hpd[0]) {
713 tmp |= RADEON_FP_DETECT_MASK;
714 }
715 if (rdev->irq.hpd[1]) {
716 tmp |= RADEON_FP2_DETECT_MASK;
717 }
718 WREG32(RADEON_GEN_INT_CNTL, tmp);
719 return 0;
720 }
721
722 void r100_irq_disable(struct radeon_device *rdev)
723 {
724 u32 tmp;
725
726 WREG32(R_000040_GEN_INT_CNTL, 0);
727 /* Wait and acknowledge irq */
728 mdelay(1);
729 tmp = RREG32(R_000044_GEN_INT_STATUS);
730 WREG32(R_000044_GEN_INT_STATUS, tmp);
731 }
732
733 static uint32_t r100_irq_ack(struct radeon_device *rdev)
734 {
735 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
736 uint32_t irq_mask = RADEON_SW_INT_TEST |
737 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
738 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
739
740 /* the interrupt works, but the status bit is permanently asserted */
741 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
742 if (!rdev->irq.gui_idle_acked)
743 irq_mask |= RADEON_GUI_IDLE_STAT;
744 }
745
746 if (irqs) {
747 WREG32(RADEON_GEN_INT_STATUS, irqs);
748 }
749 return irqs & irq_mask;
750 }
751
752 int r100_irq_process(struct radeon_device *rdev)
753 {
754 uint32_t status, msi_rearm;
755 bool queue_hotplug = false;
756
757 /* reset gui idle ack. the status bit is broken */
758 rdev->irq.gui_idle_acked = false;
759
760 status = r100_irq_ack(rdev);
761 if (!status) {
762 return IRQ_NONE;
763 }
764 if (rdev->shutdown) {
765 return IRQ_NONE;
766 }
767 while (status) {
768 /* SW interrupt */
769 if (status & RADEON_SW_INT_TEST) {
770 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
771 }
772 /* gui idle interrupt */
773 if (status & RADEON_GUI_IDLE_STAT) {
774 rdev->irq.gui_idle_acked = true;
775 wake_up(&rdev->irq.idle_queue);
776 }
777 /* Vertical blank interrupts */
778 if (status & RADEON_CRTC_VBLANK_STAT) {
779 if (rdev->irq.crtc_vblank_int[0]) {
780 drm_handle_vblank(rdev->ddev, 0);
781 rdev->pm.vblank_sync = true;
782 wake_up(&rdev->irq.vblank_queue);
783 }
784 if (atomic_read(&rdev->irq.pflip[0]))
785 radeon_crtc_handle_flip(rdev, 0);
786 }
787 if (status & RADEON_CRTC2_VBLANK_STAT) {
788 if (rdev->irq.crtc_vblank_int[1]) {
789 drm_handle_vblank(rdev->ddev, 1);
790 rdev->pm.vblank_sync = true;
791 wake_up(&rdev->irq.vblank_queue);
792 }
793 if (atomic_read(&rdev->irq.pflip[1]))
794 radeon_crtc_handle_flip(rdev, 1);
795 }
796 if (status & RADEON_FP_DETECT_STAT) {
797 queue_hotplug = true;
798 DRM_DEBUG("HPD1\n");
799 }
800 if (status & RADEON_FP2_DETECT_STAT) {
801 queue_hotplug = true;
802 DRM_DEBUG("HPD2\n");
803 }
804 status = r100_irq_ack(rdev);
805 }
806 /* reset gui idle ack. the status bit is broken */
807 rdev->irq.gui_idle_acked = false;
808 if (queue_hotplug)
809 schedule_work(&rdev->hotplug_work);
810 if (rdev->msi_enabled) {
811 switch (rdev->family) {
812 case CHIP_RS400:
813 case CHIP_RS480:
814 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
815 WREG32(RADEON_AIC_CNTL, msi_rearm);
816 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
817 break;
818 default:
819 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
820 break;
821 }
822 }
823 return IRQ_HANDLED;
824 }
825
826 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
827 {
828 if (crtc == 0)
829 return RREG32(RADEON_CRTC_CRNT_FRAME);
830 else
831 return RREG32(RADEON_CRTC2_CRNT_FRAME);
832 }
833
834 /* Who ever call radeon_fence_emit should call ring_lock and ask
835 * for enough space (today caller are ib schedule and buffer move) */
836 void r100_fence_ring_emit(struct radeon_device *rdev,
837 struct radeon_fence *fence)
838 {
839 struct radeon_ring *ring = &rdev->ring[fence->ring];
840
841 /* We have to make sure that caches are flushed before
842 * CPU might read something from VRAM. */
843 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
844 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
845 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
846 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
847 /* Wait until IDLE & CLEAN */
848 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
849 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
850 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
851 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
852 RADEON_HDP_READ_BUFFER_INVALIDATE);
853 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
854 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
855 /* Emit fence sequence & fire IRQ */
856 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
857 radeon_ring_write(ring, fence->seq);
858 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
859 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
860 }
861
862 void r100_semaphore_ring_emit(struct radeon_device *rdev,
863 struct radeon_ring *ring,
864 struct radeon_semaphore *semaphore,
865 bool emit_wait)
866 {
867 /* Unused on older asics, since we don't have semaphores or multiple rings */
868 BUG();
869 }
870
871 int r100_copy_blit(struct radeon_device *rdev,
872 uint64_t src_offset,
873 uint64_t dst_offset,
874 unsigned num_gpu_pages,
875 struct radeon_fence **fence)
876 {
877 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
878 uint32_t cur_pages;
879 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
880 uint32_t pitch;
881 uint32_t stride_pixels;
882 unsigned ndw;
883 int num_loops;
884 int r = 0;
885
886 /* radeon limited to 16k stride */
887 stride_bytes &= 0x3fff;
888 /* radeon pitch is /64 */
889 pitch = stride_bytes / 64;
890 stride_pixels = stride_bytes / 4;
891 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
892
893 /* Ask for enough room for blit + flush + fence */
894 ndw = 64 + (10 * num_loops);
895 r = radeon_ring_lock(rdev, ring, ndw);
896 if (r) {
897 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
898 return -EINVAL;
899 }
900 while (num_gpu_pages > 0) {
901 cur_pages = num_gpu_pages;
902 if (cur_pages > 8191) {
903 cur_pages = 8191;
904 }
905 num_gpu_pages -= cur_pages;
906
907 /* pages are in Y direction - height
908 page width in X direction - width */
909 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
910 radeon_ring_write(ring,
911 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
912 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
913 RADEON_GMC_SRC_CLIPPING |
914 RADEON_GMC_DST_CLIPPING |
915 RADEON_GMC_BRUSH_NONE |
916 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
917 RADEON_GMC_SRC_DATATYPE_COLOR |
918 RADEON_ROP3_S |
919 RADEON_DP_SRC_SOURCE_MEMORY |
920 RADEON_GMC_CLR_CMP_CNTL_DIS |
921 RADEON_GMC_WR_MSK_DIS);
922 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
923 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
924 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
925 radeon_ring_write(ring, 0);
926 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
927 radeon_ring_write(ring, num_gpu_pages);
928 radeon_ring_write(ring, num_gpu_pages);
929 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
930 }
931 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
932 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
933 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
934 radeon_ring_write(ring,
935 RADEON_WAIT_2D_IDLECLEAN |
936 RADEON_WAIT_HOST_IDLECLEAN |
937 RADEON_WAIT_DMA_GUI_IDLE);
938 if (fence) {
939 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
940 }
941 radeon_ring_unlock_commit(rdev, ring);
942 return r;
943 }
944
945 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
946 {
947 unsigned i;
948 u32 tmp;
949
950 for (i = 0; i < rdev->usec_timeout; i++) {
951 tmp = RREG32(R_000E40_RBBM_STATUS);
952 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
953 return 0;
954 }
955 udelay(1);
956 }
957 return -1;
958 }
959
960 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
961 {
962 int r;
963
964 r = radeon_ring_lock(rdev, ring, 2);
965 if (r) {
966 return;
967 }
968 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
969 radeon_ring_write(ring,
970 RADEON_ISYNC_ANY2D_IDLE3D |
971 RADEON_ISYNC_ANY3D_IDLE2D |
972 RADEON_ISYNC_WAIT_IDLEGUI |
973 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
974 radeon_ring_unlock_commit(rdev, ring);
975 }
976
977
978 /* Load the microcode for the CP */
979 static int r100_cp_init_microcode(struct radeon_device *rdev)
980 {
981 struct platform_device *pdev;
982 const char *fw_name = NULL;
983 int err;
984
985 DRM_DEBUG_KMS("\n");
986
987 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
988 err = IS_ERR(pdev);
989 if (err) {
990 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
991 return -EINVAL;
992 }
993 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
994 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
995 (rdev->family == CHIP_RS200)) {
996 DRM_INFO("Loading R100 Microcode\n");
997 fw_name = FIRMWARE_R100;
998 } else if ((rdev->family == CHIP_R200) ||
999 (rdev->family == CHIP_RV250) ||
1000 (rdev->family == CHIP_RV280) ||
1001 (rdev->family == CHIP_RS300)) {
1002 DRM_INFO("Loading R200 Microcode\n");
1003 fw_name = FIRMWARE_R200;
1004 } else if ((rdev->family == CHIP_R300) ||
1005 (rdev->family == CHIP_R350) ||
1006 (rdev->family == CHIP_RV350) ||
1007 (rdev->family == CHIP_RV380) ||
1008 (rdev->family == CHIP_RS400) ||
1009 (rdev->family == CHIP_RS480)) {
1010 DRM_INFO("Loading R300 Microcode\n");
1011 fw_name = FIRMWARE_R300;
1012 } else if ((rdev->family == CHIP_R420) ||
1013 (rdev->family == CHIP_R423) ||
1014 (rdev->family == CHIP_RV410)) {
1015 DRM_INFO("Loading R400 Microcode\n");
1016 fw_name = FIRMWARE_R420;
1017 } else if ((rdev->family == CHIP_RS690) ||
1018 (rdev->family == CHIP_RS740)) {
1019 DRM_INFO("Loading RS690/RS740 Microcode\n");
1020 fw_name = FIRMWARE_RS690;
1021 } else if (rdev->family == CHIP_RS600) {
1022 DRM_INFO("Loading RS600 Microcode\n");
1023 fw_name = FIRMWARE_RS600;
1024 } else if ((rdev->family == CHIP_RV515) ||
1025 (rdev->family == CHIP_R520) ||
1026 (rdev->family == CHIP_RV530) ||
1027 (rdev->family == CHIP_R580) ||
1028 (rdev->family == CHIP_RV560) ||
1029 (rdev->family == CHIP_RV570)) {
1030 DRM_INFO("Loading R500 Microcode\n");
1031 fw_name = FIRMWARE_R520;
1032 }
1033
1034 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1035 platform_device_unregister(pdev);
1036 if (err) {
1037 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1038 fw_name);
1039 } else if (rdev->me_fw->size % 8) {
1040 printk(KERN_ERR
1041 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1042 rdev->me_fw->size, fw_name);
1043 err = -EINVAL;
1044 release_firmware(rdev->me_fw);
1045 rdev->me_fw = NULL;
1046 }
1047 return err;
1048 }
1049
1050 static void r100_cp_load_microcode(struct radeon_device *rdev)
1051 {
1052 const __be32 *fw_data;
1053 int i, size;
1054
1055 if (r100_gui_wait_for_idle(rdev)) {
1056 printk(KERN_WARNING "Failed to wait GUI idle while "
1057 "programming pipes. Bad things might happen.\n");
1058 }
1059
1060 if (rdev->me_fw) {
1061 size = rdev->me_fw->size / 4;
1062 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1063 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1064 for (i = 0; i < size; i += 2) {
1065 WREG32(RADEON_CP_ME_RAM_DATAH,
1066 be32_to_cpup(&fw_data[i]));
1067 WREG32(RADEON_CP_ME_RAM_DATAL,
1068 be32_to_cpup(&fw_data[i + 1]));
1069 }
1070 }
1071 }
1072
1073 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1074 {
1075 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1076 unsigned rb_bufsz;
1077 unsigned rb_blksz;
1078 unsigned max_fetch;
1079 unsigned pre_write_timer;
1080 unsigned pre_write_limit;
1081 unsigned indirect2_start;
1082 unsigned indirect1_start;
1083 uint32_t tmp;
1084 int r;
1085
1086 if (r100_debugfs_cp_init(rdev)) {
1087 DRM_ERROR("Failed to register debugfs file for CP !\n");
1088 }
1089 if (!rdev->me_fw) {
1090 r = r100_cp_init_microcode(rdev);
1091 if (r) {
1092 DRM_ERROR("Failed to load firmware!\n");
1093 return r;
1094 }
1095 }
1096
1097 /* Align ring size */
1098 rb_bufsz = drm_order(ring_size / 8);
1099 ring_size = (1 << (rb_bufsz + 1)) * 4;
1100 r100_cp_load_microcode(rdev);
1101 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1102 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1103 0, 0x7fffff, RADEON_CP_PACKET2);
1104 if (r) {
1105 return r;
1106 }
1107 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1108 * the rptr copy in system ram */
1109 rb_blksz = 9;
1110 /* cp will read 128bytes at a time (4 dwords) */
1111 max_fetch = 1;
1112 ring->align_mask = 16 - 1;
1113 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1114 pre_write_timer = 64;
1115 /* Force CP_RB_WPTR write if written more than one time before the
1116 * delay expire
1117 */
1118 pre_write_limit = 0;
1119 /* Setup the cp cache like this (cache size is 96 dwords) :
1120 * RING 0 to 15
1121 * INDIRECT1 16 to 79
1122 * INDIRECT2 80 to 95
1123 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1124 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1125 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126 * Idea being that most of the gpu cmd will be through indirect1 buffer
1127 * so it gets the bigger cache.
1128 */
1129 indirect2_start = 80;
1130 indirect1_start = 16;
1131 /* cp setup */
1132 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1133 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1134 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1135 REG_SET(RADEON_MAX_FETCH, max_fetch));
1136 #ifdef __BIG_ENDIAN
1137 tmp |= RADEON_BUF_SWAP_32BIT;
1138 #endif
1139 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1140
1141 /* Set ring address */
1142 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1143 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1144 /* Force read & write ptr to 0 */
1145 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1146 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1147 ring->wptr = 0;
1148 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1149
1150 /* set the wb address whether it's enabled or not */
1151 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1152 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1153 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1154
1155 if (rdev->wb.enabled)
1156 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1157 else {
1158 tmp |= RADEON_RB_NO_UPDATE;
1159 WREG32(R_000770_SCRATCH_UMSK, 0);
1160 }
1161
1162 WREG32(RADEON_CP_RB_CNTL, tmp);
1163 udelay(10);
1164 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1165 /* Set cp mode to bus mastering & enable cp*/
1166 WREG32(RADEON_CP_CSQ_MODE,
1167 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1168 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1169 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1170 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1171 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1172
1173 /* at this point everything should be setup correctly to enable master */
1174 pci_set_master(rdev->pdev);
1175
1176 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1177 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1178 if (r) {
1179 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1180 return r;
1181 }
1182 ring->ready = true;
1183 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1184
1185 if (!ring->rptr_save_reg /* not resuming from suspend */
1186 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1187 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1188 if (r) {
1189 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1190 ring->rptr_save_reg = 0;
1191 }
1192 }
1193 return 0;
1194 }
1195
1196 void r100_cp_fini(struct radeon_device *rdev)
1197 {
1198 if (r100_cp_wait_for_idle(rdev)) {
1199 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1200 }
1201 /* Disable ring */
1202 r100_cp_disable(rdev);
1203 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1204 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1205 DRM_INFO("radeon: cp finalized\n");
1206 }
1207
1208 void r100_cp_disable(struct radeon_device *rdev)
1209 {
1210 /* Disable ring */
1211 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1212 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1213 WREG32(RADEON_CP_CSQ_MODE, 0);
1214 WREG32(RADEON_CP_CSQ_CNTL, 0);
1215 WREG32(R_000770_SCRATCH_UMSK, 0);
1216 if (r100_gui_wait_for_idle(rdev)) {
1217 printk(KERN_WARNING "Failed to wait GUI idle while "
1218 "programming pipes. Bad things might happen.\n");
1219 }
1220 }
1221
1222 /*
1223 * CS functions
1224 */
1225 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1226 struct radeon_cs_packet *pkt,
1227 unsigned idx,
1228 unsigned reg)
1229 {
1230 int r;
1231 u32 tile_flags = 0;
1232 u32 tmp;
1233 struct radeon_cs_reloc *reloc;
1234 u32 value;
1235
1236 r = r100_cs_packet_next_reloc(p, &reloc);
1237 if (r) {
1238 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1239 idx, reg);
1240 r100_cs_dump_packet(p, pkt);
1241 return r;
1242 }
1243
1244 value = radeon_get_ib_value(p, idx);
1245 tmp = value & 0x003fffff;
1246 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1247
1248 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1249 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1250 tile_flags |= RADEON_DST_TILE_MACRO;
1251 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1252 if (reg == RADEON_SRC_PITCH_OFFSET) {
1253 DRM_ERROR("Cannot src blit from microtiled surface\n");
1254 r100_cs_dump_packet(p, pkt);
1255 return -EINVAL;
1256 }
1257 tile_flags |= RADEON_DST_TILE_MICRO;
1258 }
1259
1260 tmp |= tile_flags;
1261 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1262 } else
1263 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1264 return 0;
1265 }
1266
1267 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1268 struct radeon_cs_packet *pkt,
1269 int idx)
1270 {
1271 unsigned c, i;
1272 struct radeon_cs_reloc *reloc;
1273 struct r100_cs_track *track;
1274 int r = 0;
1275 volatile uint32_t *ib;
1276 u32 idx_value;
1277
1278 ib = p->ib.ptr;
1279 track = (struct r100_cs_track *)p->track;
1280 c = radeon_get_ib_value(p, idx++) & 0x1F;
1281 if (c > 16) {
1282 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1283 pkt->opcode);
1284 r100_cs_dump_packet(p, pkt);
1285 return -EINVAL;
1286 }
1287 track->num_arrays = c;
1288 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1289 r = r100_cs_packet_next_reloc(p, &reloc);
1290 if (r) {
1291 DRM_ERROR("No reloc for packet3 %d\n",
1292 pkt->opcode);
1293 r100_cs_dump_packet(p, pkt);
1294 return r;
1295 }
1296 idx_value = radeon_get_ib_value(p, idx);
1297 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1298
1299 track->arrays[i + 0].esize = idx_value >> 8;
1300 track->arrays[i + 0].robj = reloc->robj;
1301 track->arrays[i + 0].esize &= 0x7F;
1302 r = r100_cs_packet_next_reloc(p, &reloc);
1303 if (r) {
1304 DRM_ERROR("No reloc for packet3 %d\n",
1305 pkt->opcode);
1306 r100_cs_dump_packet(p, pkt);
1307 return r;
1308 }
1309 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1310 track->arrays[i + 1].robj = reloc->robj;
1311 track->arrays[i + 1].esize = idx_value >> 24;
1312 track->arrays[i + 1].esize &= 0x7F;
1313 }
1314 if (c & 1) {
1315 r = r100_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 DRM_ERROR("No reloc for packet3 %d\n",
1318 pkt->opcode);
1319 r100_cs_dump_packet(p, pkt);
1320 return r;
1321 }
1322 idx_value = radeon_get_ib_value(p, idx);
1323 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1324 track->arrays[i + 0].robj = reloc->robj;
1325 track->arrays[i + 0].esize = idx_value >> 8;
1326 track->arrays[i + 0].esize &= 0x7F;
1327 }
1328 return r;
1329 }
1330
1331 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1332 struct radeon_cs_packet *pkt,
1333 const unsigned *auth, unsigned n,
1334 radeon_packet0_check_t check)
1335 {
1336 unsigned reg;
1337 unsigned i, j, m;
1338 unsigned idx;
1339 int r;
1340
1341 idx = pkt->idx + 1;
1342 reg = pkt->reg;
1343 /* Check that register fall into register range
1344 * determined by the number of entry (n) in the
1345 * safe register bitmap.
1346 */
1347 if (pkt->one_reg_wr) {
1348 if ((reg >> 7) > n) {
1349 return -EINVAL;
1350 }
1351 } else {
1352 if (((reg + (pkt->count << 2)) >> 7) > n) {
1353 return -EINVAL;
1354 }
1355 }
1356 for (i = 0; i <= pkt->count; i++, idx++) {
1357 j = (reg >> 7);
1358 m = 1 << ((reg >> 2) & 31);
1359 if (auth[j] & m) {
1360 r = check(p, pkt, idx, reg);
1361 if (r) {
1362 return r;
1363 }
1364 }
1365 if (pkt->one_reg_wr) {
1366 if (!(auth[j] & m)) {
1367 break;
1368 }
1369 } else {
1370 reg += 4;
1371 }
1372 }
1373 return 0;
1374 }
1375
1376 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1377 struct radeon_cs_packet *pkt)
1378 {
1379 volatile uint32_t *ib;
1380 unsigned i;
1381 unsigned idx;
1382
1383 ib = p->ib.ptr;
1384 idx = pkt->idx;
1385 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1386 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1387 }
1388 }
1389
1390 /**
1391 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1392 * @parser: parser structure holding parsing context.
1393 * @pkt: where to store packet informations
1394 *
1395 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1396 * if packet is bigger than remaining ib size. or if packets is unknown.
1397 **/
1398 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1399 struct radeon_cs_packet *pkt,
1400 unsigned idx)
1401 {
1402 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1403 uint32_t header;
1404
1405 if (idx >= ib_chunk->length_dw) {
1406 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1407 idx, ib_chunk->length_dw);
1408 return -EINVAL;
1409 }
1410 header = radeon_get_ib_value(p, idx);
1411 pkt->idx = idx;
1412 pkt->type = CP_PACKET_GET_TYPE(header);
1413 pkt->count = CP_PACKET_GET_COUNT(header);
1414 switch (pkt->type) {
1415 case PACKET_TYPE0:
1416 pkt->reg = CP_PACKET0_GET_REG(header);
1417 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1418 break;
1419 case PACKET_TYPE3:
1420 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1421 break;
1422 case PACKET_TYPE2:
1423 pkt->count = -1;
1424 break;
1425 default:
1426 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1427 return -EINVAL;
1428 }
1429 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1430 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1431 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1432 return -EINVAL;
1433 }
1434 return 0;
1435 }
1436
1437 /**
1438 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1439 * @parser: parser structure holding parsing context.
1440 *
1441 * Userspace sends a special sequence for VLINE waits.
1442 * PACKET0 - VLINE_START_END + value
1443 * PACKET0 - WAIT_UNTIL +_value
1444 * RELOC (P3) - crtc_id in reloc.
1445 *
1446 * This function parses this and relocates the VLINE START END
1447 * and WAIT UNTIL packets to the correct crtc.
1448 * It also detects a switched off crtc and nulls out the
1449 * wait in that case.
1450 */
1451 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1452 {
1453 struct drm_mode_object *obj;
1454 struct drm_crtc *crtc;
1455 struct radeon_crtc *radeon_crtc;
1456 struct radeon_cs_packet p3reloc, waitreloc;
1457 int crtc_id;
1458 int r;
1459 uint32_t header, h_idx, reg;
1460 volatile uint32_t *ib;
1461
1462 ib = p->ib.ptr;
1463
1464 /* parse the wait until */
1465 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1466 if (r)
1467 return r;
1468
1469 /* check its a wait until and only 1 count */
1470 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1471 waitreloc.count != 0) {
1472 DRM_ERROR("vline wait had illegal wait until segment\n");
1473 return -EINVAL;
1474 }
1475
1476 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1477 DRM_ERROR("vline wait had illegal wait until\n");
1478 return -EINVAL;
1479 }
1480
1481 /* jump over the NOP */
1482 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1483 if (r)
1484 return r;
1485
1486 h_idx = p->idx - 2;
1487 p->idx += waitreloc.count + 2;
1488 p->idx += p3reloc.count + 2;
1489
1490 header = radeon_get_ib_value(p, h_idx);
1491 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1492 reg = CP_PACKET0_GET_REG(header);
1493 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1494 if (!obj) {
1495 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1496 return -EINVAL;
1497 }
1498 crtc = obj_to_crtc(obj);
1499 radeon_crtc = to_radeon_crtc(crtc);
1500 crtc_id = radeon_crtc->crtc_id;
1501
1502 if (!crtc->enabled) {
1503 /* if the CRTC isn't enabled - we need to nop out the wait until */
1504 ib[h_idx + 2] = PACKET2(0);
1505 ib[h_idx + 3] = PACKET2(0);
1506 } else if (crtc_id == 1) {
1507 switch (reg) {
1508 case AVIVO_D1MODE_VLINE_START_END:
1509 header &= ~R300_CP_PACKET0_REG_MASK;
1510 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1511 break;
1512 case RADEON_CRTC_GUI_TRIG_VLINE:
1513 header &= ~R300_CP_PACKET0_REG_MASK;
1514 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1515 break;
1516 default:
1517 DRM_ERROR("unknown crtc reloc\n");
1518 return -EINVAL;
1519 }
1520 ib[h_idx] = header;
1521 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1522 }
1523
1524 return 0;
1525 }
1526
1527 /**
1528 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1529 * @parser: parser structure holding parsing context.
1530 * @data: pointer to relocation data
1531 * @offset_start: starting offset
1532 * @offset_mask: offset mask (to align start offset on)
1533 * @reloc: reloc informations
1534 *
1535 * Check next packet is relocation packet3, do bo validation and compute
1536 * GPU offset using the provided start.
1537 **/
1538 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1539 struct radeon_cs_reloc **cs_reloc)
1540 {
1541 struct radeon_cs_chunk *relocs_chunk;
1542 struct radeon_cs_packet p3reloc;
1543 unsigned idx;
1544 int r;
1545
1546 if (p->chunk_relocs_idx == -1) {
1547 DRM_ERROR("No relocation chunk !\n");
1548 return -EINVAL;
1549 }
1550 *cs_reloc = NULL;
1551 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1552 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1553 if (r) {
1554 return r;
1555 }
1556 p->idx += p3reloc.count + 2;
1557 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1558 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1559 p3reloc.idx);
1560 r100_cs_dump_packet(p, &p3reloc);
1561 return -EINVAL;
1562 }
1563 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1564 if (idx >= relocs_chunk->length_dw) {
1565 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1566 idx, relocs_chunk->length_dw);
1567 r100_cs_dump_packet(p, &p3reloc);
1568 return -EINVAL;
1569 }
1570 /* FIXME: we assume reloc size is 4 dwords */
1571 *cs_reloc = p->relocs_ptr[(idx / 4)];
1572 return 0;
1573 }
1574
1575 static int r100_get_vtx_size(uint32_t vtx_fmt)
1576 {
1577 int vtx_size;
1578 vtx_size = 2;
1579 /* ordered according to bits in spec */
1580 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1581 vtx_size++;
1582 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1583 vtx_size += 3;
1584 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1585 vtx_size++;
1586 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1587 vtx_size++;
1588 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1589 vtx_size += 3;
1590 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1591 vtx_size++;
1592 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1593 vtx_size++;
1594 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1595 vtx_size += 2;
1596 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1597 vtx_size += 2;
1598 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1599 vtx_size++;
1600 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1601 vtx_size += 2;
1602 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1603 vtx_size++;
1604 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1605 vtx_size += 2;
1606 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1607 vtx_size++;
1608 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1609 vtx_size++;
1610 /* blend weight */
1611 if (vtx_fmt & (0x7 << 15))
1612 vtx_size += (vtx_fmt >> 15) & 0x7;
1613 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1614 vtx_size += 3;
1615 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1616 vtx_size += 2;
1617 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1618 vtx_size++;
1619 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1620 vtx_size++;
1621 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1622 vtx_size++;
1623 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1624 vtx_size++;
1625 return vtx_size;
1626 }
1627
1628 static int r100_packet0_check(struct radeon_cs_parser *p,
1629 struct radeon_cs_packet *pkt,
1630 unsigned idx, unsigned reg)
1631 {
1632 struct radeon_cs_reloc *reloc;
1633 struct r100_cs_track *track;
1634 volatile uint32_t *ib;
1635 uint32_t tmp;
1636 int r;
1637 int i, face;
1638 u32 tile_flags = 0;
1639 u32 idx_value;
1640
1641 ib = p->ib.ptr;
1642 track = (struct r100_cs_track *)p->track;
1643
1644 idx_value = radeon_get_ib_value(p, idx);
1645
1646 switch (reg) {
1647 case RADEON_CRTC_GUI_TRIG_VLINE:
1648 r = r100_cs_packet_parse_vline(p);
1649 if (r) {
1650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1651 idx, reg);
1652 r100_cs_dump_packet(p, pkt);
1653 return r;
1654 }
1655 break;
1656 /* FIXME: only allow PACKET3 blit? easier to check for out of
1657 * range access */
1658 case RADEON_DST_PITCH_OFFSET:
1659 case RADEON_SRC_PITCH_OFFSET:
1660 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1661 if (r)
1662 return r;
1663 break;
1664 case RADEON_RB3D_DEPTHOFFSET:
1665 r = r100_cs_packet_next_reloc(p, &reloc);
1666 if (r) {
1667 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1668 idx, reg);
1669 r100_cs_dump_packet(p, pkt);
1670 return r;
1671 }
1672 track->zb.robj = reloc->robj;
1673 track->zb.offset = idx_value;
1674 track->zb_dirty = true;
1675 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1676 break;
1677 case RADEON_RB3D_COLOROFFSET:
1678 r = r100_cs_packet_next_reloc(p, &reloc);
1679 if (r) {
1680 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1681 idx, reg);
1682 r100_cs_dump_packet(p, pkt);
1683 return r;
1684 }
1685 track->cb[0].robj = reloc->robj;
1686 track->cb[0].offset = idx_value;
1687 track->cb_dirty = true;
1688 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1689 break;
1690 case RADEON_PP_TXOFFSET_0:
1691 case RADEON_PP_TXOFFSET_1:
1692 case RADEON_PP_TXOFFSET_2:
1693 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1694 r = r100_cs_packet_next_reloc(p, &reloc);
1695 if (r) {
1696 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1697 idx, reg);
1698 r100_cs_dump_packet(p, pkt);
1699 return r;
1700 }
1701 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1702 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1703 tile_flags |= RADEON_TXO_MACRO_TILE;
1704 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1705 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1706
1707 tmp = idx_value & ~(0x7 << 2);
1708 tmp |= tile_flags;
1709 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1710 } else
1711 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1712 track->textures[i].robj = reloc->robj;
1713 track->tex_dirty = true;
1714 break;
1715 case RADEON_PP_CUBIC_OFFSET_T0_0:
1716 case RADEON_PP_CUBIC_OFFSET_T0_1:
1717 case RADEON_PP_CUBIC_OFFSET_T0_2:
1718 case RADEON_PP_CUBIC_OFFSET_T0_3:
1719 case RADEON_PP_CUBIC_OFFSET_T0_4:
1720 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1721 r = r100_cs_packet_next_reloc(p, &reloc);
1722 if (r) {
1723 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1724 idx, reg);
1725 r100_cs_dump_packet(p, pkt);
1726 return r;
1727 }
1728 track->textures[0].cube_info[i].offset = idx_value;
1729 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1730 track->textures[0].cube_info[i].robj = reloc->robj;
1731 track->tex_dirty = true;
1732 break;
1733 case RADEON_PP_CUBIC_OFFSET_T1_0:
1734 case RADEON_PP_CUBIC_OFFSET_T1_1:
1735 case RADEON_PP_CUBIC_OFFSET_T1_2:
1736 case RADEON_PP_CUBIC_OFFSET_T1_3:
1737 case RADEON_PP_CUBIC_OFFSET_T1_4:
1738 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1739 r = r100_cs_packet_next_reloc(p, &reloc);
1740 if (r) {
1741 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1742 idx, reg);
1743 r100_cs_dump_packet(p, pkt);
1744 return r;
1745 }
1746 track->textures[1].cube_info[i].offset = idx_value;
1747 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1748 track->textures[1].cube_info[i].robj = reloc->robj;
1749 track->tex_dirty = true;
1750 break;
1751 case RADEON_PP_CUBIC_OFFSET_T2_0:
1752 case RADEON_PP_CUBIC_OFFSET_T2_1:
1753 case RADEON_PP_CUBIC_OFFSET_T2_2:
1754 case RADEON_PP_CUBIC_OFFSET_T2_3:
1755 case RADEON_PP_CUBIC_OFFSET_T2_4:
1756 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1757 r = r100_cs_packet_next_reloc(p, &reloc);
1758 if (r) {
1759 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1760 idx, reg);
1761 r100_cs_dump_packet(p, pkt);
1762 return r;
1763 }
1764 track->textures[2].cube_info[i].offset = idx_value;
1765 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1766 track->textures[2].cube_info[i].robj = reloc->robj;
1767 track->tex_dirty = true;
1768 break;
1769 case RADEON_RE_WIDTH_HEIGHT:
1770 track->maxy = ((idx_value >> 16) & 0x7FF);
1771 track->cb_dirty = true;
1772 track->zb_dirty = true;
1773 break;
1774 case RADEON_RB3D_COLORPITCH:
1775 r = r100_cs_packet_next_reloc(p, &reloc);
1776 if (r) {
1777 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1778 idx, reg);
1779 r100_cs_dump_packet(p, pkt);
1780 return r;
1781 }
1782 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1783 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1784 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1785 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1786 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1787
1788 tmp = idx_value & ~(0x7 << 16);
1789 tmp |= tile_flags;
1790 ib[idx] = tmp;
1791 } else
1792 ib[idx] = idx_value;
1793
1794 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1795 track->cb_dirty = true;
1796 break;
1797 case RADEON_RB3D_DEPTHPITCH:
1798 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1799 track->zb_dirty = true;
1800 break;
1801 case RADEON_RB3D_CNTL:
1802 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1803 case 7:
1804 case 8:
1805 case 9:
1806 case 11:
1807 case 12:
1808 track->cb[0].cpp = 1;
1809 break;
1810 case 3:
1811 case 4:
1812 case 15:
1813 track->cb[0].cpp = 2;
1814 break;
1815 case 6:
1816 track->cb[0].cpp = 4;
1817 break;
1818 default:
1819 DRM_ERROR("Invalid color buffer format (%d) !\n",
1820 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1821 return -EINVAL;
1822 }
1823 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1824 track->cb_dirty = true;
1825 track->zb_dirty = true;
1826 break;
1827 case RADEON_RB3D_ZSTENCILCNTL:
1828 switch (idx_value & 0xf) {
1829 case 0:
1830 track->zb.cpp = 2;
1831 break;
1832 case 2:
1833 case 3:
1834 case 4:
1835 case 5:
1836 case 9:
1837 case 11:
1838 track->zb.cpp = 4;
1839 break;
1840 default:
1841 break;
1842 }
1843 track->zb_dirty = true;
1844 break;
1845 case RADEON_RB3D_ZPASS_ADDR:
1846 r = r100_cs_packet_next_reloc(p, &reloc);
1847 if (r) {
1848 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1849 idx, reg);
1850 r100_cs_dump_packet(p, pkt);
1851 return r;
1852 }
1853 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1854 break;
1855 case RADEON_PP_CNTL:
1856 {
1857 uint32_t temp = idx_value >> 4;
1858 for (i = 0; i < track->num_texture; i++)
1859 track->textures[i].enabled = !!(temp & (1 << i));
1860 track->tex_dirty = true;
1861 }
1862 break;
1863 case RADEON_SE_VF_CNTL:
1864 track->vap_vf_cntl = idx_value;
1865 break;
1866 case RADEON_SE_VTX_FMT:
1867 track->vtx_size = r100_get_vtx_size(idx_value);
1868 break;
1869 case RADEON_PP_TEX_SIZE_0:
1870 case RADEON_PP_TEX_SIZE_1:
1871 case RADEON_PP_TEX_SIZE_2:
1872 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1873 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1874 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1875 track->tex_dirty = true;
1876 break;
1877 case RADEON_PP_TEX_PITCH_0:
1878 case RADEON_PP_TEX_PITCH_1:
1879 case RADEON_PP_TEX_PITCH_2:
1880 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1881 track->textures[i].pitch = idx_value + 32;
1882 track->tex_dirty = true;
1883 break;
1884 case RADEON_PP_TXFILTER_0:
1885 case RADEON_PP_TXFILTER_1:
1886 case RADEON_PP_TXFILTER_2:
1887 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1888 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1889 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1890 tmp = (idx_value >> 23) & 0x7;
1891 if (tmp == 2 || tmp == 6)
1892 track->textures[i].roundup_w = false;
1893 tmp = (idx_value >> 27) & 0x7;
1894 if (tmp == 2 || tmp == 6)
1895 track->textures[i].roundup_h = false;
1896 track->tex_dirty = true;
1897 break;
1898 case RADEON_PP_TXFORMAT_0:
1899 case RADEON_PP_TXFORMAT_1:
1900 case RADEON_PP_TXFORMAT_2:
1901 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1902 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1903 track->textures[i].use_pitch = 1;
1904 } else {
1905 track->textures[i].use_pitch = 0;
1906 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1907 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1908 }
1909 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1910 track->textures[i].tex_coord_type = 2;
1911 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1912 case RADEON_TXFORMAT_I8:
1913 case RADEON_TXFORMAT_RGB332:
1914 case RADEON_TXFORMAT_Y8:
1915 track->textures[i].cpp = 1;
1916 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1917 break;
1918 case RADEON_TXFORMAT_AI88:
1919 case RADEON_TXFORMAT_ARGB1555:
1920 case RADEON_TXFORMAT_RGB565:
1921 case RADEON_TXFORMAT_ARGB4444:
1922 case RADEON_TXFORMAT_VYUY422:
1923 case RADEON_TXFORMAT_YVYU422:
1924 case RADEON_TXFORMAT_SHADOW16:
1925 case RADEON_TXFORMAT_LDUDV655:
1926 case RADEON_TXFORMAT_DUDV88:
1927 track->textures[i].cpp = 2;
1928 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1929 break;
1930 case RADEON_TXFORMAT_ARGB8888:
1931 case RADEON_TXFORMAT_RGBA8888:
1932 case RADEON_TXFORMAT_SHADOW32:
1933 case RADEON_TXFORMAT_LDUDUV8888:
1934 track->textures[i].cpp = 4;
1935 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1936 break;
1937 case RADEON_TXFORMAT_DXT1:
1938 track->textures[i].cpp = 1;
1939 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1940 break;
1941 case RADEON_TXFORMAT_DXT23:
1942 case RADEON_TXFORMAT_DXT45:
1943 track->textures[i].cpp = 1;
1944 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1945 break;
1946 }
1947 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1948 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1949 track->tex_dirty = true;
1950 break;
1951 case RADEON_PP_CUBIC_FACES_0:
1952 case RADEON_PP_CUBIC_FACES_1:
1953 case RADEON_PP_CUBIC_FACES_2:
1954 tmp = idx_value;
1955 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1956 for (face = 0; face < 4; face++) {
1957 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1958 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1959 }
1960 track->tex_dirty = true;
1961 break;
1962 default:
1963 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1964 reg, idx);
1965 return -EINVAL;
1966 }
1967 return 0;
1968 }
1969
1970 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1971 struct radeon_cs_packet *pkt,
1972 struct radeon_bo *robj)
1973 {
1974 unsigned idx;
1975 u32 value;
1976 idx = pkt->idx + 1;
1977 value = radeon_get_ib_value(p, idx + 2);
1978 if ((value + 1) > radeon_bo_size(robj)) {
1979 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1980 "(need %u have %lu) !\n",
1981 value + 1,
1982 radeon_bo_size(robj));
1983 return -EINVAL;
1984 }
1985 return 0;
1986 }
1987
1988 static int r100_packet3_check(struct radeon_cs_parser *p,
1989 struct radeon_cs_packet *pkt)
1990 {
1991 struct radeon_cs_reloc *reloc;
1992 struct r100_cs_track *track;
1993 unsigned idx;
1994 volatile uint32_t *ib;
1995 int r;
1996
1997 ib = p->ib.ptr;
1998 idx = pkt->idx + 1;
1999 track = (struct r100_cs_track *)p->track;
2000 switch (pkt->opcode) {
2001 case PACKET3_3D_LOAD_VBPNTR:
2002 r = r100_packet3_load_vbpntr(p, pkt, idx);
2003 if (r)
2004 return r;
2005 break;
2006 case PACKET3_INDX_BUFFER:
2007 r = r100_cs_packet_next_reloc(p, &reloc);
2008 if (r) {
2009 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2010 r100_cs_dump_packet(p, pkt);
2011 return r;
2012 }
2013 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
2014 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
2015 if (r) {
2016 return r;
2017 }
2018 break;
2019 case 0x23:
2020 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2021 r = r100_cs_packet_next_reloc(p, &reloc);
2022 if (r) {
2023 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2024 r100_cs_dump_packet(p, pkt);
2025 return r;
2026 }
2027 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
2028 track->num_arrays = 1;
2029 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
2030
2031 track->arrays[0].robj = reloc->robj;
2032 track->arrays[0].esize = track->vtx_size;
2033
2034 track->max_indx = radeon_get_ib_value(p, idx+1);
2035
2036 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
2037 track->immd_dwords = pkt->count - 1;
2038 r = r100_cs_track_check(p->rdev, track);
2039 if (r)
2040 return r;
2041 break;
2042 case PACKET3_3D_DRAW_IMMD:
2043 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
2044 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2045 return -EINVAL;
2046 }
2047 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
2048 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2049 track->immd_dwords = pkt->count - 1;
2050 r = r100_cs_track_check(p->rdev, track);
2051 if (r)
2052 return r;
2053 break;
2054 /* triggers drawing using in-packet vertex data */
2055 case PACKET3_3D_DRAW_IMMD_2:
2056 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
2057 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2058 return -EINVAL;
2059 }
2060 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2061 track->immd_dwords = pkt->count;
2062 r = r100_cs_track_check(p->rdev, track);
2063 if (r)
2064 return r;
2065 break;
2066 /* triggers drawing using in-packet vertex data */
2067 case PACKET3_3D_DRAW_VBUF_2:
2068 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2069 r = r100_cs_track_check(p->rdev, track);
2070 if (r)
2071 return r;
2072 break;
2073 /* triggers drawing of vertex buffers setup elsewhere */
2074 case PACKET3_3D_DRAW_INDX_2:
2075 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2076 r = r100_cs_track_check(p->rdev, track);
2077 if (r)
2078 return r;
2079 break;
2080 /* triggers drawing using indices to vertex buffer */
2081 case PACKET3_3D_DRAW_VBUF:
2082 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2083 r = r100_cs_track_check(p->rdev, track);
2084 if (r)
2085 return r;
2086 break;
2087 /* triggers drawing of vertex buffers setup elsewhere */
2088 case PACKET3_3D_DRAW_INDX:
2089 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2090 r = r100_cs_track_check(p->rdev, track);
2091 if (r)
2092 return r;
2093 break;
2094 /* triggers drawing using indices to vertex buffer */
2095 case PACKET3_3D_CLEAR_HIZ:
2096 case PACKET3_3D_CLEAR_ZMASK:
2097 if (p->rdev->hyperz_filp != p->filp)
2098 return -EINVAL;
2099 break;
2100 case PACKET3_NOP:
2101 break;
2102 default:
2103 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2104 return -EINVAL;
2105 }
2106 return 0;
2107 }
2108
2109 int r100_cs_parse(struct radeon_cs_parser *p)
2110 {
2111 struct radeon_cs_packet pkt;
2112 struct r100_cs_track *track;
2113 int r;
2114
2115 track = kzalloc(sizeof(*track), GFP_KERNEL);
2116 if (!track)
2117 return -ENOMEM;
2118 r100_cs_track_clear(p->rdev, track);
2119 p->track = track;
2120 do {
2121 r = r100_cs_packet_parse(p, &pkt, p->idx);
2122 if (r) {
2123 return r;
2124 }
2125 p->idx += pkt.count + 2;
2126 switch (pkt.type) {
2127 case PACKET_TYPE0:
2128 if (p->rdev->family >= CHIP_R200)
2129 r = r100_cs_parse_packet0(p, &pkt,
2130 p->rdev->config.r100.reg_safe_bm,
2131 p->rdev->config.r100.reg_safe_bm_size,
2132 &r200_packet0_check);
2133 else
2134 r = r100_cs_parse_packet0(p, &pkt,
2135 p->rdev->config.r100.reg_safe_bm,
2136 p->rdev->config.r100.reg_safe_bm_size,
2137 &r100_packet0_check);
2138 break;
2139 case PACKET_TYPE2:
2140 break;
2141 case PACKET_TYPE3:
2142 r = r100_packet3_check(p, &pkt);
2143 break;
2144 default:
2145 DRM_ERROR("Unknown packet type %d !\n",
2146 pkt.type);
2147 return -EINVAL;
2148 }
2149 if (r) {
2150 return r;
2151 }
2152 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2153 return 0;
2154 }
2155
2156 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2157 {
2158 DRM_ERROR("pitch %d\n", t->pitch);
2159 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2160 DRM_ERROR("width %d\n", t->width);
2161 DRM_ERROR("width_11 %d\n", t->width_11);
2162 DRM_ERROR("height %d\n", t->height);
2163 DRM_ERROR("height_11 %d\n", t->height_11);
2164 DRM_ERROR("num levels %d\n", t->num_levels);
2165 DRM_ERROR("depth %d\n", t->txdepth);
2166 DRM_ERROR("bpp %d\n", t->cpp);
2167 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2168 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2169 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2170 DRM_ERROR("compress format %d\n", t->compress_format);
2171 }
2172
2173 static int r100_track_compress_size(int compress_format, int w, int h)
2174 {
2175 int block_width, block_height, block_bytes;
2176 int wblocks, hblocks;
2177 int min_wblocks;
2178 int sz;
2179
2180 block_width = 4;
2181 block_height = 4;
2182
2183 switch (compress_format) {
2184 case R100_TRACK_COMP_DXT1:
2185 block_bytes = 8;
2186 min_wblocks = 4;
2187 break;
2188 default:
2189 case R100_TRACK_COMP_DXT35:
2190 block_bytes = 16;
2191 min_wblocks = 2;
2192 break;
2193 }
2194
2195 hblocks = (h + block_height - 1) / block_height;
2196 wblocks = (w + block_width - 1) / block_width;
2197 if (wblocks < min_wblocks)
2198 wblocks = min_wblocks;
2199 sz = wblocks * hblocks * block_bytes;
2200 return sz;
2201 }
2202
2203 static int r100_cs_track_cube(struct radeon_device *rdev,
2204 struct r100_cs_track *track, unsigned idx)
2205 {
2206 unsigned face, w, h;
2207 struct radeon_bo *cube_robj;
2208 unsigned long size;
2209 unsigned compress_format = track->textures[idx].compress_format;
2210
2211 for (face = 0; face < 5; face++) {
2212 cube_robj = track->textures[idx].cube_info[face].robj;
2213 w = track->textures[idx].cube_info[face].width;
2214 h = track->textures[idx].cube_info[face].height;
2215
2216 if (compress_format) {
2217 size = r100_track_compress_size(compress_format, w, h);
2218 } else
2219 size = w * h;
2220 size *= track->textures[idx].cpp;
2221
2222 size += track->textures[idx].cube_info[face].offset;
2223
2224 if (size > radeon_bo_size(cube_robj)) {
2225 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2226 size, radeon_bo_size(cube_robj));
2227 r100_cs_track_texture_print(&track->textures[idx]);
2228 return -1;
2229 }
2230 }
2231 return 0;
2232 }
2233
2234 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2235 struct r100_cs_track *track)
2236 {
2237 struct radeon_bo *robj;
2238 unsigned long size;
2239 unsigned u, i, w, h, d;
2240 int ret;
2241
2242 for (u = 0; u < track->num_texture; u++) {
2243 if (!track->textures[u].enabled)
2244 continue;
2245 if (track->textures[u].lookup_disable)
2246 continue;
2247 robj = track->textures[u].robj;
2248 if (robj == NULL) {
2249 DRM_ERROR("No texture bound to unit %u\n", u);
2250 return -EINVAL;
2251 }
2252 size = 0;
2253 for (i = 0; i <= track->textures[u].num_levels; i++) {
2254 if (track->textures[u].use_pitch) {
2255 if (rdev->family < CHIP_R300)
2256 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2257 else
2258 w = track->textures[u].pitch / (1 << i);
2259 } else {
2260 w = track->textures[u].width;
2261 if (rdev->family >= CHIP_RV515)
2262 w |= track->textures[u].width_11;
2263 w = w / (1 << i);
2264 if (track->textures[u].roundup_w)
2265 w = roundup_pow_of_two(w);
2266 }
2267 h = track->textures[u].height;
2268 if (rdev->family >= CHIP_RV515)
2269 h |= track->textures[u].height_11;
2270 h = h / (1 << i);
2271 if (track->textures[u].roundup_h)
2272 h = roundup_pow_of_two(h);
2273 if (track->textures[u].tex_coord_type == 1) {
2274 d = (1 << track->textures[u].txdepth) / (1 << i);
2275 if (!d)
2276 d = 1;
2277 } else {
2278 d = 1;
2279 }
2280 if (track->textures[u].compress_format) {
2281
2282 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2283 /* compressed textures are block based */
2284 } else
2285 size += w * h * d;
2286 }
2287 size *= track->textures[u].cpp;
2288
2289 switch (track->textures[u].tex_coord_type) {
2290 case 0:
2291 case 1:
2292 break;
2293 case 2:
2294 if (track->separate_cube) {
2295 ret = r100_cs_track_cube(rdev, track, u);
2296 if (ret)
2297 return ret;
2298 } else
2299 size *= 6;
2300 break;
2301 default:
2302 DRM_ERROR("Invalid texture coordinate type %u for unit "
2303 "%u\n", track->textures[u].tex_coord_type, u);
2304 return -EINVAL;
2305 }
2306 if (size > radeon_bo_size(robj)) {
2307 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2308 "%lu\n", u, size, radeon_bo_size(robj));
2309 r100_cs_track_texture_print(&track->textures[u]);
2310 return -EINVAL;
2311 }
2312 }
2313 return 0;
2314 }
2315
2316 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2317 {
2318 unsigned i;
2319 unsigned long size;
2320 unsigned prim_walk;
2321 unsigned nverts;
2322 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2323
2324 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2325 !track->blend_read_enable)
2326 num_cb = 0;
2327
2328 for (i = 0; i < num_cb; i++) {
2329 if (track->cb[i].robj == NULL) {
2330 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2331 return -EINVAL;
2332 }
2333 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2334 size += track->cb[i].offset;
2335 if (size > radeon_bo_size(track->cb[i].robj)) {
2336 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2337 "(need %lu have %lu) !\n", i, size,
2338 radeon_bo_size(track->cb[i].robj));
2339 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2340 i, track->cb[i].pitch, track->cb[i].cpp,
2341 track->cb[i].offset, track->maxy);
2342 return -EINVAL;
2343 }
2344 }
2345 track->cb_dirty = false;
2346
2347 if (track->zb_dirty && track->z_enabled) {
2348 if (track->zb.robj == NULL) {
2349 DRM_ERROR("[drm] No buffer for z buffer !\n");
2350 return -EINVAL;
2351 }
2352 size = track->zb.pitch * track->zb.cpp * track->maxy;
2353 size += track->zb.offset;
2354 if (size > radeon_bo_size(track->zb.robj)) {
2355 DRM_ERROR("[drm] Buffer too small for z buffer "
2356 "(need %lu have %lu) !\n", size,
2357 radeon_bo_size(track->zb.robj));
2358 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2359 track->zb.pitch, track->zb.cpp,
2360 track->zb.offset, track->maxy);
2361 return -EINVAL;
2362 }
2363 }
2364 track->zb_dirty = false;
2365
2366 if (track->aa_dirty && track->aaresolve) {
2367 if (track->aa.robj == NULL) {
2368 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2369 return -EINVAL;
2370 }
2371 /* I believe the format comes from colorbuffer0. */
2372 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2373 size += track->aa.offset;
2374 if (size > radeon_bo_size(track->aa.robj)) {
2375 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2376 "(need %lu have %lu) !\n", i, size,
2377 radeon_bo_size(track->aa.robj));
2378 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2379 i, track->aa.pitch, track->cb[0].cpp,
2380 track->aa.offset, track->maxy);
2381 return -EINVAL;
2382 }
2383 }
2384 track->aa_dirty = false;
2385
2386 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2387 if (track->vap_vf_cntl & (1 << 14)) {
2388 nverts = track->vap_alt_nverts;
2389 } else {
2390 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2391 }
2392 switch (prim_walk) {
2393 case 1:
2394 for (i = 0; i < track->num_arrays; i++) {
2395 size = track->arrays[i].esize * track->max_indx * 4;
2396 if (track->arrays[i].robj == NULL) {
2397 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2398 "bound\n", prim_walk, i);
2399 return -EINVAL;
2400 }
2401 if (size > radeon_bo_size(track->arrays[i].robj)) {
2402 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2403 "need %lu dwords have %lu dwords\n",
2404 prim_walk, i, size >> 2,
2405 radeon_bo_size(track->arrays[i].robj)
2406 >> 2);
2407 DRM_ERROR("Max indices %u\n", track->max_indx);
2408 return -EINVAL;
2409 }
2410 }
2411 break;
2412 case 2:
2413 for (i = 0; i < track->num_arrays; i++) {
2414 size = track->arrays[i].esize * (nverts - 1) * 4;
2415 if (track->arrays[i].robj == NULL) {
2416 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2417 "bound\n", prim_walk, i);
2418 return -EINVAL;
2419 }
2420 if (size > radeon_bo_size(track->arrays[i].robj)) {
2421 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2422 "need %lu dwords have %lu dwords\n",
2423 prim_walk, i, size >> 2,
2424 radeon_bo_size(track->arrays[i].robj)
2425 >> 2);
2426 return -EINVAL;
2427 }
2428 }
2429 break;
2430 case 3:
2431 size = track->vtx_size * nverts;
2432 if (size != track->immd_dwords) {
2433 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2434 track->immd_dwords, size);
2435 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2436 nverts, track->vtx_size);
2437 return -EINVAL;
2438 }
2439 break;
2440 default:
2441 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2442 prim_walk);
2443 return -EINVAL;
2444 }
2445
2446 if (track->tex_dirty) {
2447 track->tex_dirty = false;
2448 return r100_cs_track_texture_check(rdev, track);
2449 }
2450 return 0;
2451 }
2452
2453 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2454 {
2455 unsigned i, face;
2456
2457 track->cb_dirty = true;
2458 track->zb_dirty = true;
2459 track->tex_dirty = true;
2460 track->aa_dirty = true;
2461
2462 if (rdev->family < CHIP_R300) {
2463 track->num_cb = 1;
2464 if (rdev->family <= CHIP_RS200)
2465 track->num_texture = 3;
2466 else
2467 track->num_texture = 6;
2468 track->maxy = 2048;
2469 track->separate_cube = 1;
2470 } else {
2471 track->num_cb = 4;
2472 track->num_texture = 16;
2473 track->maxy = 4096;
2474 track->separate_cube = 0;
2475 track->aaresolve = false;
2476 track->aa.robj = NULL;
2477 }
2478
2479 for (i = 0; i < track->num_cb; i++) {
2480 track->cb[i].robj = NULL;
2481 track->cb[i].pitch = 8192;
2482 track->cb[i].cpp = 16;
2483 track->cb[i].offset = 0;
2484 }
2485 track->z_enabled = true;
2486 track->zb.robj = NULL;
2487 track->zb.pitch = 8192;
2488 track->zb.cpp = 4;
2489 track->zb.offset = 0;
2490 track->vtx_size = 0x7F;
2491 track->immd_dwords = 0xFFFFFFFFUL;
2492 track->num_arrays = 11;
2493 track->max_indx = 0x00FFFFFFUL;
2494 for (i = 0; i < track->num_arrays; i++) {
2495 track->arrays[i].robj = NULL;
2496 track->arrays[i].esize = 0x7F;
2497 }
2498 for (i = 0; i < track->num_texture; i++) {
2499 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2500 track->textures[i].pitch = 16536;
2501 track->textures[i].width = 16536;
2502 track->textures[i].height = 16536;
2503 track->textures[i].width_11 = 1 << 11;
2504 track->textures[i].height_11 = 1 << 11;
2505 track->textures[i].num_levels = 12;
2506 if (rdev->family <= CHIP_RS200) {
2507 track->textures[i].tex_coord_type = 0;
2508 track->textures[i].txdepth = 0;
2509 } else {
2510 track->textures[i].txdepth = 16;
2511 track->textures[i].tex_coord_type = 1;
2512 }
2513 track->textures[i].cpp = 64;
2514 track->textures[i].robj = NULL;
2515 /* CS IB emission code makes sure texture unit are disabled */
2516 track->textures[i].enabled = false;
2517 track->textures[i].lookup_disable = false;
2518 track->textures[i].roundup_w = true;
2519 track->textures[i].roundup_h = true;
2520 if (track->separate_cube)
2521 for (face = 0; face < 5; face++) {
2522 track->textures[i].cube_info[face].robj = NULL;
2523 track->textures[i].cube_info[face].width = 16536;
2524 track->textures[i].cube_info[face].height = 16536;
2525 track->textures[i].cube_info[face].offset = 0;
2526 }
2527 }
2528 }
2529
2530 /*
2531 * Global GPU functions
2532 */
2533 void r100_errata(struct radeon_device *rdev)
2534 {
2535 rdev->pll_errata = 0;
2536
2537 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2538 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2539 }
2540
2541 if (rdev->family == CHIP_RV100 ||
2542 rdev->family == CHIP_RS100 ||
2543 rdev->family == CHIP_RS200) {
2544 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2545 }
2546 }
2547
2548 /* Wait for vertical sync on primary CRTC */
2549 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2550 {
2551 uint32_t crtc_gen_cntl, tmp;
2552 int i;
2553
2554 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2555 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2556 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2557 return;
2558 }
2559 /* Clear the CRTC_VBLANK_SAVE bit */
2560 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2561 for (i = 0; i < rdev->usec_timeout; i++) {
2562 tmp = RREG32(RADEON_CRTC_STATUS);
2563 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2564 return;
2565 }
2566 DRM_UDELAY(1);
2567 }
2568 }
2569
2570 /* Wait for vertical sync on secondary CRTC */
2571 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2572 {
2573 uint32_t crtc2_gen_cntl, tmp;
2574 int i;
2575
2576 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2577 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2578 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2579 return;
2580
2581 /* Clear the CRTC_VBLANK_SAVE bit */
2582 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2583 for (i = 0; i < rdev->usec_timeout; i++) {
2584 tmp = RREG32(RADEON_CRTC2_STATUS);
2585 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2586 return;
2587 }
2588 DRM_UDELAY(1);
2589 }
2590 }
2591
2592 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2593 {
2594 unsigned i;
2595 uint32_t tmp;
2596
2597 for (i = 0; i < rdev->usec_timeout; i++) {
2598 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2599 if (tmp >= n) {
2600 return 0;
2601 }
2602 DRM_UDELAY(1);
2603 }
2604 return -1;
2605 }
2606
2607 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2608 {
2609 unsigned i;
2610 uint32_t tmp;
2611
2612 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2613 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2614 " Bad things might happen.\n");
2615 }
2616 for (i = 0; i < rdev->usec_timeout; i++) {
2617 tmp = RREG32(RADEON_RBBM_STATUS);
2618 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2619 return 0;
2620 }
2621 DRM_UDELAY(1);
2622 }
2623 return -1;
2624 }
2625
2626 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2627 {
2628 unsigned i;
2629 uint32_t tmp;
2630
2631 for (i = 0; i < rdev->usec_timeout; i++) {
2632 /* read MC_STATUS */
2633 tmp = RREG32(RADEON_MC_STATUS);
2634 if (tmp & RADEON_MC_IDLE) {
2635 return 0;
2636 }
2637 DRM_UDELAY(1);
2638 }
2639 return -1;
2640 }
2641
2642 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2643 {
2644 u32 rbbm_status;
2645
2646 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2647 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2648 radeon_ring_lockup_update(ring);
2649 return false;
2650 }
2651 /* force CP activities */
2652 radeon_ring_force_activity(rdev, ring);
2653 return radeon_ring_test_lockup(rdev, ring);
2654 }
2655
2656 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2657 void r100_enable_bm(struct radeon_device *rdev)
2658 {
2659 uint32_t tmp;
2660 /* Enable bus mastering */
2661 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2662 WREG32(RADEON_BUS_CNTL, tmp);
2663 }
2664
2665 void r100_bm_disable(struct radeon_device *rdev)
2666 {
2667 u32 tmp;
2668
2669 /* disable bus mastering */
2670 tmp = RREG32(R_000030_BUS_CNTL);
2671 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2672 mdelay(1);
2673 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2674 mdelay(1);
2675 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2676 tmp = RREG32(RADEON_BUS_CNTL);
2677 mdelay(1);
2678 pci_clear_master(rdev->pdev);
2679 mdelay(1);
2680 }
2681
2682 int r100_asic_reset(struct radeon_device *rdev)
2683 {
2684 struct r100_mc_save save;
2685 u32 status, tmp;
2686 int ret = 0;
2687
2688 status = RREG32(R_000E40_RBBM_STATUS);
2689 if (!G_000E40_GUI_ACTIVE(status)) {
2690 return 0;
2691 }
2692 r100_mc_stop(rdev, &save);
2693 status = RREG32(R_000E40_RBBM_STATUS);
2694 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2695 /* stop CP */
2696 WREG32(RADEON_CP_CSQ_CNTL, 0);
2697 tmp = RREG32(RADEON_CP_RB_CNTL);
2698 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2699 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2700 WREG32(RADEON_CP_RB_WPTR, 0);
2701 WREG32(RADEON_CP_RB_CNTL, tmp);
2702 /* save PCI state */
2703 pci_save_state(rdev->pdev);
2704 /* disable bus mastering */
2705 r100_bm_disable(rdev);
2706 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2707 S_0000F0_SOFT_RESET_RE(1) |
2708 S_0000F0_SOFT_RESET_PP(1) |
2709 S_0000F0_SOFT_RESET_RB(1));
2710 RREG32(R_0000F0_RBBM_SOFT_RESET);
2711 mdelay(500);
2712 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2713 mdelay(1);
2714 status = RREG32(R_000E40_RBBM_STATUS);
2715 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2716 /* reset CP */
2717 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2718 RREG32(R_0000F0_RBBM_SOFT_RESET);
2719 mdelay(500);
2720 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2721 mdelay(1);
2722 status = RREG32(R_000E40_RBBM_STATUS);
2723 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2724 /* restore PCI & busmastering */
2725 pci_restore_state(rdev->pdev);
2726 r100_enable_bm(rdev);
2727 /* Check if GPU is idle */
2728 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2729 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2730 dev_err(rdev->dev, "failed to reset GPU\n");
2731 ret = -1;
2732 } else
2733 dev_info(rdev->dev, "GPU reset succeed\n");
2734 r100_mc_resume(rdev, &save);
2735 return ret;
2736 }
2737
2738 void r100_set_common_regs(struct radeon_device *rdev)
2739 {
2740 struct drm_device *dev = rdev->ddev;
2741 bool force_dac2 = false;
2742 u32 tmp;
2743
2744 /* set these so they don't interfere with anything */
2745 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2746 WREG32(RADEON_SUBPIC_CNTL, 0);
2747 WREG32(RADEON_VIPH_CONTROL, 0);
2748 WREG32(RADEON_I2C_CNTL_1, 0);
2749 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2750 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2751 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2752
2753 /* always set up dac2 on rn50 and some rv100 as lots
2754 * of servers seem to wire it up to a VGA port but
2755 * don't report it in the bios connector
2756 * table.
2757 */
2758 switch (dev->pdev->device) {
2759 /* RN50 */
2760 case 0x515e:
2761 case 0x5969:
2762 force_dac2 = true;
2763 break;
2764 /* RV100*/
2765 case 0x5159:
2766 case 0x515a:
2767 /* DELL triple head servers */
2768 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2769 ((dev->pdev->subsystem_device == 0x016c) ||
2770 (dev->pdev->subsystem_device == 0x016d) ||
2771 (dev->pdev->subsystem_device == 0x016e) ||
2772 (dev->pdev->subsystem_device == 0x016f) ||
2773 (dev->pdev->subsystem_device == 0x0170) ||
2774 (dev->pdev->subsystem_device == 0x017d) ||
2775 (dev->pdev->subsystem_device == 0x017e) ||
2776 (dev->pdev->subsystem_device == 0x0183) ||
2777 (dev->pdev->subsystem_device == 0x018a) ||
2778 (dev->pdev->subsystem_device == 0x019a)))
2779 force_dac2 = true;
2780 break;
2781 }
2782
2783 if (force_dac2) {
2784 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2785 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2786 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2787
2788 /* For CRT on DAC2, don't turn it on if BIOS didn't
2789 enable it, even it's detected.
2790 */
2791
2792 /* force it to crtc0 */
2793 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2794 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2795 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2796
2797 /* set up the TV DAC */
2798 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2799 RADEON_TV_DAC_STD_MASK |
2800 RADEON_TV_DAC_RDACPD |
2801 RADEON_TV_DAC_GDACPD |
2802 RADEON_TV_DAC_BDACPD |
2803 RADEON_TV_DAC_BGADJ_MASK |
2804 RADEON_TV_DAC_DACADJ_MASK);
2805 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2806 RADEON_TV_DAC_NHOLD |
2807 RADEON_TV_DAC_STD_PS2 |
2808 (0x58 << 16));
2809
2810 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2811 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2812 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2813 }
2814
2815 /* switch PM block to ACPI mode */
2816 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2817 tmp &= ~RADEON_PM_MODE_SEL;
2818 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2819
2820 }
2821
2822 /*
2823 * VRAM info
2824 */
2825 static void r100_vram_get_type(struct radeon_device *rdev)
2826 {
2827 uint32_t tmp;
2828
2829 rdev->mc.vram_is_ddr = false;
2830 if (rdev->flags & RADEON_IS_IGP)
2831 rdev->mc.vram_is_ddr = true;
2832 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2833 rdev->mc.vram_is_ddr = true;
2834 if ((rdev->family == CHIP_RV100) ||
2835 (rdev->family == CHIP_RS100) ||
2836 (rdev->family == CHIP_RS200)) {
2837 tmp = RREG32(RADEON_MEM_CNTL);
2838 if (tmp & RV100_HALF_MODE) {
2839 rdev->mc.vram_width = 32;
2840 } else {
2841 rdev->mc.vram_width = 64;
2842 }
2843 if (rdev->flags & RADEON_SINGLE_CRTC) {
2844 rdev->mc.vram_width /= 4;
2845 rdev->mc.vram_is_ddr = true;
2846 }
2847 } else if (rdev->family <= CHIP_RV280) {
2848 tmp = RREG32(RADEON_MEM_CNTL);
2849 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2850 rdev->mc.vram_width = 128;
2851 } else {
2852 rdev->mc.vram_width = 64;
2853 }
2854 } else {
2855 /* newer IGPs */
2856 rdev->mc.vram_width = 128;
2857 }
2858 }
2859
2860 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2861 {
2862 u32 aper_size;
2863 u8 byte;
2864
2865 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2866
2867 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2868 * that is has the 2nd generation multifunction PCI interface
2869 */
2870 if (rdev->family == CHIP_RV280 ||
2871 rdev->family >= CHIP_RV350) {
2872 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2873 ~RADEON_HDP_APER_CNTL);
2874 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2875 return aper_size * 2;
2876 }
2877
2878 /* Older cards have all sorts of funny issues to deal with. First
2879 * check if it's a multifunction card by reading the PCI config
2880 * header type... Limit those to one aperture size
2881 */
2882 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2883 if (byte & 0x80) {
2884 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2885 DRM_INFO("Limiting VRAM to one aperture\n");
2886 return aper_size;
2887 }
2888
2889 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2890 * have set it up. We don't write this as it's broken on some ASICs but
2891 * we expect the BIOS to have done the right thing (might be too optimistic...)
2892 */
2893 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2894 return aper_size * 2;
2895 return aper_size;
2896 }
2897
2898 void r100_vram_init_sizes(struct radeon_device *rdev)
2899 {
2900 u64 config_aper_size;
2901
2902 /* work out accessible VRAM */
2903 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2904 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2905 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2906 /* FIXME we don't use the second aperture yet when we could use it */
2907 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2908 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2909 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2910 if (rdev->flags & RADEON_IS_IGP) {
2911 uint32_t tom;
2912 /* read NB_TOM to get the amount of ram stolen for the GPU */
2913 tom = RREG32(RADEON_NB_TOM);
2914 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2915 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2916 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2917 } else {
2918 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2919 /* Some production boards of m6 will report 0
2920 * if it's 8 MB
2921 */
2922 if (rdev->mc.real_vram_size == 0) {
2923 rdev->mc.real_vram_size = 8192 * 1024;
2924 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2925 }
2926 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2927 * Novell bug 204882 + along with lots of ubuntu ones
2928 */
2929 if (rdev->mc.aper_size > config_aper_size)
2930 config_aper_size = rdev->mc.aper_size;
2931
2932 if (config_aper_size > rdev->mc.real_vram_size)
2933 rdev->mc.mc_vram_size = config_aper_size;
2934 else
2935 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2936 }
2937 }
2938
2939 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2940 {
2941 uint32_t temp;
2942
2943 temp = RREG32(RADEON_CONFIG_CNTL);
2944 if (state == false) {
2945 temp &= ~RADEON_CFG_VGA_RAM_EN;
2946 temp |= RADEON_CFG_VGA_IO_DIS;
2947 } else {
2948 temp &= ~RADEON_CFG_VGA_IO_DIS;
2949 }
2950 WREG32(RADEON_CONFIG_CNTL, temp);
2951 }
2952
2953 void r100_mc_init(struct radeon_device *rdev)
2954 {
2955 u64 base;
2956
2957 r100_vram_get_type(rdev);
2958 r100_vram_init_sizes(rdev);
2959 base = rdev->mc.aper_base;
2960 if (rdev->flags & RADEON_IS_IGP)
2961 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2962 radeon_vram_location(rdev, &rdev->mc, base);
2963 rdev->mc.gtt_base_align = 0;
2964 if (!(rdev->flags & RADEON_IS_AGP))
2965 radeon_gtt_location(rdev, &rdev->mc);
2966 radeon_update_bandwidth_info(rdev);
2967 }
2968
2969
2970 /*
2971 * Indirect registers accessor
2972 */
2973 void r100_pll_errata_after_index(struct radeon_device *rdev)
2974 {
2975 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2976 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2977 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2978 }
2979 }
2980
2981 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2982 {
2983 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2984 * or the chip could hang on a subsequent access
2985 */
2986 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2987 mdelay(5);
2988 }
2989
2990 /* This function is required to workaround a hardware bug in some (all?)
2991 * revisions of the R300. This workaround should be called after every
2992 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2993 * may not be correct.
2994 */
2995 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2996 uint32_t save, tmp;
2997
2998 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2999 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
3000 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
3001 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
3002 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
3003 }
3004 }
3005
3006 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
3007 {
3008 uint32_t data;
3009
3010 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
3011 r100_pll_errata_after_index(rdev);
3012 data = RREG32(RADEON_CLOCK_CNTL_DATA);
3013 r100_pll_errata_after_data(rdev);
3014 return data;
3015 }
3016
3017 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3018 {
3019 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3020 r100_pll_errata_after_index(rdev);
3021 WREG32(RADEON_CLOCK_CNTL_DATA, v);
3022 r100_pll_errata_after_data(rdev);
3023 }
3024
3025 void r100_set_safe_registers(struct radeon_device *rdev)
3026 {
3027 if (ASIC_IS_RN50(rdev)) {
3028 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3029 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3030 } else if (rdev->family < CHIP_R200) {
3031 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3032 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
3033 } else {
3034 r200_set_safe_registers(rdev);
3035 }
3036 }
3037
3038 /*
3039 * Debugfs info
3040 */
3041 #if defined(CONFIG_DEBUG_FS)
3042 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
3043 {
3044 struct drm_info_node *node = (struct drm_info_node *) m->private;
3045 struct drm_device *dev = node->minor->dev;
3046 struct radeon_device *rdev = dev->dev_private;
3047 uint32_t reg, value;
3048 unsigned i;
3049
3050 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
3051 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
3052 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3053 for (i = 0; i < 64; i++) {
3054 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
3055 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
3056 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
3057 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
3058 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
3059 }
3060 return 0;
3061 }
3062
3063 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
3064 {
3065 struct drm_info_node *node = (struct drm_info_node *) m->private;
3066 struct drm_device *dev = node->minor->dev;
3067 struct radeon_device *rdev = dev->dev_private;
3068 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3069 uint32_t rdp, wdp;
3070 unsigned count, i, j;
3071
3072 radeon_ring_free_size(rdev, ring);
3073 rdp = RREG32(RADEON_CP_RB_RPTR);
3074 wdp = RREG32(RADEON_CP_RB_WPTR);
3075 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
3076 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3077 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
3078 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
3079 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
3080 seq_printf(m, "%u dwords in ring\n", count);
3081 for (j = 0; j <= count; j++) {
3082 i = (rdp + j) & ring->ptr_mask;
3083 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3084 }
3085 return 0;
3086 }
3087
3088
3089 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
3090 {
3091 struct drm_info_node *node = (struct drm_info_node *) m->private;
3092 struct drm_device *dev = node->minor->dev;
3093 struct radeon_device *rdev = dev->dev_private;
3094 uint32_t csq_stat, csq2_stat, tmp;
3095 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3096 unsigned i;
3097
3098 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3099 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3100 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3101 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3102 r_rptr = (csq_stat >> 0) & 0x3ff;
3103 r_wptr = (csq_stat >> 10) & 0x3ff;
3104 ib1_rptr = (csq_stat >> 20) & 0x3ff;
3105 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3106 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3107 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3108 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3109 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3110 seq_printf(m, "Ring rptr %u\n", r_rptr);
3111 seq_printf(m, "Ring wptr %u\n", r_wptr);
3112 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3113 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3114 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3115 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3116 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3117 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3118 seq_printf(m, "Ring fifo:\n");
3119 for (i = 0; i < 256; i++) {
3120 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3121 tmp = RREG32(RADEON_CP_CSQ_DATA);
3122 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3123 }
3124 seq_printf(m, "Indirect1 fifo:\n");
3125 for (i = 256; i <= 512; i++) {
3126 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3127 tmp = RREG32(RADEON_CP_CSQ_DATA);
3128 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3129 }
3130 seq_printf(m, "Indirect2 fifo:\n");
3131 for (i = 640; i < ib1_wptr; i++) {
3132 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3133 tmp = RREG32(RADEON_CP_CSQ_DATA);
3134 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3135 }
3136 return 0;
3137 }
3138
3139 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3140 {
3141 struct drm_info_node *node = (struct drm_info_node *) m->private;
3142 struct drm_device *dev = node->minor->dev;
3143 struct radeon_device *rdev = dev->dev_private;
3144 uint32_t tmp;
3145
3146 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3147 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3148 tmp = RREG32(RADEON_MC_FB_LOCATION);
3149 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3150 tmp = RREG32(RADEON_BUS_CNTL);
3151 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3152 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3153 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3154 tmp = RREG32(RADEON_AGP_BASE);
3155 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3156 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3157 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3158 tmp = RREG32(0x01D0);
3159 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3160 tmp = RREG32(RADEON_AIC_LO_ADDR);
3161 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3162 tmp = RREG32(RADEON_AIC_HI_ADDR);
3163 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3164 tmp = RREG32(0x01E4);
3165 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3166 return 0;
3167 }
3168
3169 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3170 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3171 };
3172
3173 static struct drm_info_list r100_debugfs_cp_list[] = {
3174 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3175 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3176 };
3177
3178 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3179 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3180 };
3181 #endif
3182
3183 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3184 {
3185 #if defined(CONFIG_DEBUG_FS)
3186 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3187 #else
3188 return 0;
3189 #endif
3190 }
3191
3192 int r100_debugfs_cp_init(struct radeon_device *rdev)
3193 {
3194 #if defined(CONFIG_DEBUG_FS)
3195 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3196 #else
3197 return 0;
3198 #endif
3199 }
3200
3201 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3202 {
3203 #if defined(CONFIG_DEBUG_FS)
3204 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3205 #else
3206 return 0;
3207 #endif
3208 }
3209
3210 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3211 uint32_t tiling_flags, uint32_t pitch,
3212 uint32_t offset, uint32_t obj_size)
3213 {
3214 int surf_index = reg * 16;
3215 int flags = 0;
3216
3217 if (rdev->family <= CHIP_RS200) {
3218 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3219 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3220 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3221 if (tiling_flags & RADEON_TILING_MACRO)
3222 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3223 } else if (rdev->family <= CHIP_RV280) {
3224 if (tiling_flags & (RADEON_TILING_MACRO))
3225 flags |= R200_SURF_TILE_COLOR_MACRO;
3226 if (tiling_flags & RADEON_TILING_MICRO)
3227 flags |= R200_SURF_TILE_COLOR_MICRO;
3228 } else {
3229 if (tiling_flags & RADEON_TILING_MACRO)
3230 flags |= R300_SURF_TILE_MACRO;
3231 if (tiling_flags & RADEON_TILING_MICRO)
3232 flags |= R300_SURF_TILE_MICRO;
3233 }
3234
3235 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3236 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3237 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3238 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3239
3240 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3241 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3242 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3243 if (ASIC_IS_RN50(rdev))
3244 pitch /= 16;
3245 }
3246
3247 /* r100/r200 divide by 16 */
3248 if (rdev->family < CHIP_R300)
3249 flags |= pitch / 16;
3250 else
3251 flags |= pitch / 8;
3252
3253
3254 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3255 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3256 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3257 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3258 return 0;
3259 }
3260
3261 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3262 {
3263 int surf_index = reg * 16;
3264 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3265 }
3266
3267 void r100_bandwidth_update(struct radeon_device *rdev)
3268 {
3269 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3270 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3271 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3272 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3273 fixed20_12 memtcas_ff[8] = {
3274 dfixed_init(1),
3275 dfixed_init(2),
3276 dfixed_init(3),
3277 dfixed_init(0),
3278 dfixed_init_half(1),
3279 dfixed_init_half(2),
3280 dfixed_init(0),
3281 };
3282 fixed20_12 memtcas_rs480_ff[8] = {
3283 dfixed_init(0),
3284 dfixed_init(1),
3285 dfixed_init(2),
3286 dfixed_init(3),
3287 dfixed_init(0),
3288 dfixed_init_half(1),
3289 dfixed_init_half(2),
3290 dfixed_init_half(3),
3291 };
3292 fixed20_12 memtcas2_ff[8] = {
3293 dfixed_init(0),
3294 dfixed_init(1),
3295 dfixed_init(2),
3296 dfixed_init(3),
3297 dfixed_init(4),
3298 dfixed_init(5),
3299 dfixed_init(6),
3300 dfixed_init(7),
3301 };
3302 fixed20_12 memtrbs[8] = {
3303 dfixed_init(1),
3304 dfixed_init_half(1),
3305 dfixed_init(2),
3306 dfixed_init_half(2),
3307 dfixed_init(3),
3308 dfixed_init_half(3),
3309 dfixed_init(4),
3310 dfixed_init_half(4)
3311 };
3312 fixed20_12 memtrbs_r4xx[8] = {
3313 dfixed_init(4),
3314 dfixed_init(5),
3315 dfixed_init(6),
3316 dfixed_init(7),
3317 dfixed_init(8),
3318 dfixed_init(9),
3319 dfixed_init(10),
3320 dfixed_init(11)
3321 };
3322 fixed20_12 min_mem_eff;
3323 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3324 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3325 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3326 disp_drain_rate2, read_return_rate;
3327 fixed20_12 time_disp1_drop_priority;
3328 int c;
3329 int cur_size = 16; /* in octawords */
3330 int critical_point = 0, critical_point2;
3331 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3332 int stop_req, max_stop_req;
3333 struct drm_display_mode *mode1 = NULL;
3334 struct drm_display_mode *mode2 = NULL;
3335 uint32_t pixel_bytes1 = 0;
3336 uint32_t pixel_bytes2 = 0;
3337
3338 radeon_update_display_priority(rdev);
3339
3340 if (rdev->mode_info.crtcs[0]->base.enabled) {
3341 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3342 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3343 }
3344 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3345 if (rdev->mode_info.crtcs[1]->base.enabled) {
3346 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3347 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3348 }
3349 }
3350
3351 min_mem_eff.full = dfixed_const_8(0);
3352 /* get modes */
3353 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3354 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3355 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3356 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3357 /* check crtc enables */
3358 if (mode2)
3359 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3360 if (mode1)
3361 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3362 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3363 }
3364
3365 /*
3366 * determine is there is enough bw for current mode
3367 */
3368 sclk_ff = rdev->pm.sclk;
3369 mclk_ff = rdev->pm.mclk;
3370
3371 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3372 temp_ff.full = dfixed_const(temp);
3373 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3374
3375 pix_clk.full = 0;
3376 pix_clk2.full = 0;
3377 peak_disp_bw.full = 0;
3378 if (mode1) {
3379 temp_ff.full = dfixed_const(1000);
3380 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3381 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3382 temp_ff.full = dfixed_const(pixel_bytes1);
3383 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3384 }
3385 if (mode2) {
3386 temp_ff.full = dfixed_const(1000);
3387 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3388 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3389 temp_ff.full = dfixed_const(pixel_bytes2);
3390 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3391 }
3392
3393 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3394 if (peak_disp_bw.full >= mem_bw.full) {
3395 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3396 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3397 }
3398
3399 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3400 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3401 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3402 mem_trcd = ((temp >> 2) & 0x3) + 1;
3403 mem_trp = ((temp & 0x3)) + 1;
3404 mem_tras = ((temp & 0x70) >> 4) + 1;
3405 } else if (rdev->family == CHIP_R300 ||
3406 rdev->family == CHIP_R350) { /* r300, r350 */
3407 mem_trcd = (temp & 0x7) + 1;
3408 mem_trp = ((temp >> 8) & 0x7) + 1;
3409 mem_tras = ((temp >> 11) & 0xf) + 4;
3410 } else if (rdev->family == CHIP_RV350 ||
3411 rdev->family <= CHIP_RV380) {
3412 /* rv3x0 */
3413 mem_trcd = (temp & 0x7) + 3;
3414 mem_trp = ((temp >> 8) & 0x7) + 3;
3415 mem_tras = ((temp >> 11) & 0xf) + 6;
3416 } else if (rdev->family == CHIP_R420 ||
3417 rdev->family == CHIP_R423 ||
3418 rdev->family == CHIP_RV410) {
3419 /* r4xx */
3420 mem_trcd = (temp & 0xf) + 3;
3421 if (mem_trcd > 15)
3422 mem_trcd = 15;
3423 mem_trp = ((temp >> 8) & 0xf) + 3;
3424 if (mem_trp > 15)
3425 mem_trp = 15;
3426 mem_tras = ((temp >> 12) & 0x1f) + 6;
3427 if (mem_tras > 31)
3428 mem_tras = 31;
3429 } else { /* RV200, R200 */
3430 mem_trcd = (temp & 0x7) + 1;
3431 mem_trp = ((temp >> 8) & 0x7) + 1;
3432 mem_tras = ((temp >> 12) & 0xf) + 4;
3433 }
3434 /* convert to FF */
3435 trcd_ff.full = dfixed_const(mem_trcd);
3436 trp_ff.full = dfixed_const(mem_trp);
3437 tras_ff.full = dfixed_const(mem_tras);
3438
3439 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3440 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3441 data = (temp & (7 << 20)) >> 20;
3442 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3443 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3444 tcas_ff = memtcas_rs480_ff[data];
3445 else
3446 tcas_ff = memtcas_ff[data];
3447 } else
3448 tcas_ff = memtcas2_ff[data];
3449
3450 if (rdev->family == CHIP_RS400 ||
3451 rdev->family == CHIP_RS480) {
3452 /* extra cas latency stored in bits 23-25 0-4 clocks */
3453 data = (temp >> 23) & 0x7;
3454 if (data < 5)
3455 tcas_ff.full += dfixed_const(data);
3456 }
3457
3458 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3459 /* on the R300, Tcas is included in Trbs.
3460 */
3461 temp = RREG32(RADEON_MEM_CNTL);
3462 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3463 if (data == 1) {
3464 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3465 temp = RREG32(R300_MC_IND_INDEX);
3466 temp &= ~R300_MC_IND_ADDR_MASK;
3467 temp |= R300_MC_READ_CNTL_CD_mcind;
3468 WREG32(R300_MC_IND_INDEX, temp);
3469 temp = RREG32(R300_MC_IND_DATA);
3470 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3471 } else {
3472 temp = RREG32(R300_MC_READ_CNTL_AB);
3473 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3474 }
3475 } else {
3476 temp = RREG32(R300_MC_READ_CNTL_AB);
3477 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3478 }
3479 if (rdev->family == CHIP_RV410 ||
3480 rdev->family == CHIP_R420 ||
3481 rdev->family == CHIP_R423)
3482 trbs_ff = memtrbs_r4xx[data];
3483 else
3484 trbs_ff = memtrbs[data];
3485 tcas_ff.full += trbs_ff.full;
3486 }
3487
3488 sclk_eff_ff.full = sclk_ff.full;
3489
3490 if (rdev->flags & RADEON_IS_AGP) {
3491 fixed20_12 agpmode_ff;
3492 agpmode_ff.full = dfixed_const(radeon_agpmode);
3493 temp_ff.full = dfixed_const_666(16);
3494 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3495 }
3496 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3497
3498 if (ASIC_IS_R300(rdev)) {
3499 sclk_delay_ff.full = dfixed_const(250);
3500 } else {
3501 if ((rdev->family == CHIP_RV100) ||
3502 rdev->flags & RADEON_IS_IGP) {
3503 if (rdev->mc.vram_is_ddr)
3504 sclk_delay_ff.full = dfixed_const(41);
3505 else
3506 sclk_delay_ff.full = dfixed_const(33);
3507 } else {
3508 if (rdev->mc.vram_width == 128)
3509 sclk_delay_ff.full = dfixed_const(57);
3510 else
3511 sclk_delay_ff.full = dfixed_const(41);
3512 }
3513 }
3514
3515 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3516
3517 if (rdev->mc.vram_is_ddr) {
3518 if (rdev->mc.vram_width == 32) {
3519 k1.full = dfixed_const(40);
3520 c = 3;
3521 } else {
3522 k1.full = dfixed_const(20);
3523 c = 1;
3524 }
3525 } else {
3526 k1.full = dfixed_const(40);
3527 c = 3;
3528 }
3529
3530 temp_ff.full = dfixed_const(2);
3531 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3532 temp_ff.full = dfixed_const(c);
3533 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3534 temp_ff.full = dfixed_const(4);
3535 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3536 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3537 mc_latency_mclk.full += k1.full;
3538
3539 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3540 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3541
3542 /*
3543 HW cursor time assuming worst case of full size colour cursor.
3544 */
3545 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3546 temp_ff.full += trcd_ff.full;
3547 if (temp_ff.full < tras_ff.full)
3548 temp_ff.full = tras_ff.full;
3549 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3550
3551 temp_ff.full = dfixed_const(cur_size);
3552 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3553 /*
3554 Find the total latency for the display data.
3555 */
3556 disp_latency_overhead.full = dfixed_const(8);
3557 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3558 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3559 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3560
3561 if (mc_latency_mclk.full > mc_latency_sclk.full)
3562 disp_latency.full = mc_latency_mclk.full;
3563 else
3564 disp_latency.full = mc_latency_sclk.full;
3565
3566 /* setup Max GRPH_STOP_REQ default value */
3567 if (ASIC_IS_RV100(rdev))
3568 max_stop_req = 0x5c;
3569 else
3570 max_stop_req = 0x7c;
3571
3572 if (mode1) {
3573 /* CRTC1
3574 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3575 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3576 */
3577 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3578
3579 if (stop_req > max_stop_req)
3580 stop_req = max_stop_req;
3581
3582 /*
3583 Find the drain rate of the display buffer.
3584 */
3585 temp_ff.full = dfixed_const((16/pixel_bytes1));
3586 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3587
3588 /*
3589 Find the critical point of the display buffer.
3590 */
3591 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3592 crit_point_ff.full += dfixed_const_half(0);
3593
3594 critical_point = dfixed_trunc(crit_point_ff);
3595
3596 if (rdev->disp_priority == 2) {
3597 critical_point = 0;
3598 }
3599
3600 /*
3601 The critical point should never be above max_stop_req-4. Setting
3602 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3603 */
3604 if (max_stop_req - critical_point < 4)
3605 critical_point = 0;
3606
3607 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3608 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3609 critical_point = 0x10;
3610 }
3611
3612 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3613 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3614 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3615 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3616 if ((rdev->family == CHIP_R350) &&
3617 (stop_req > 0x15)) {
3618 stop_req -= 0x10;
3619 }
3620 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3621 temp |= RADEON_GRPH_BUFFER_SIZE;
3622 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3623 RADEON_GRPH_CRITICAL_AT_SOF |
3624 RADEON_GRPH_STOP_CNTL);
3625 /*
3626 Write the result into the register.
3627 */
3628 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3629 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3630
3631 #if 0
3632 if ((rdev->family == CHIP_RS400) ||
3633 (rdev->family == CHIP_RS480)) {
3634 /* attempt to program RS400 disp regs correctly ??? */
3635 temp = RREG32(RS400_DISP1_REG_CNTL);
3636 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3637 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3638 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3639 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3640 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3641 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3642 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3643 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3644 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3645 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3646 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3647 }
3648 #endif
3649
3650 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3651 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3652 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3653 }
3654
3655 if (mode2) {
3656 u32 grph2_cntl;
3657 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3658
3659 if (stop_req > max_stop_req)
3660 stop_req = max_stop_req;
3661
3662 /*
3663 Find the drain rate of the display buffer.
3664 */
3665 temp_ff.full = dfixed_const((16/pixel_bytes2));
3666 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3667
3668 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3669 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3670 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3671 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3672 if ((rdev->family == CHIP_R350) &&
3673 (stop_req > 0x15)) {
3674 stop_req -= 0x10;
3675 }
3676 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3677 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3678 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3679 RADEON_GRPH_CRITICAL_AT_SOF |
3680 RADEON_GRPH_STOP_CNTL);
3681
3682 if ((rdev->family == CHIP_RS100) ||
3683 (rdev->family == CHIP_RS200))
3684 critical_point2 = 0;
3685 else {
3686 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3687 temp_ff.full = dfixed_const(temp);
3688 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3689 if (sclk_ff.full < temp_ff.full)
3690 temp_ff.full = sclk_ff.full;
3691
3692 read_return_rate.full = temp_ff.full;
3693
3694 if (mode1) {
3695 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3696 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3697 } else {
3698 time_disp1_drop_priority.full = 0;
3699 }
3700 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3701 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3702 crit_point_ff.full += dfixed_const_half(0);
3703
3704 critical_point2 = dfixed_trunc(crit_point_ff);
3705
3706 if (rdev->disp_priority == 2) {
3707 critical_point2 = 0;
3708 }
3709
3710 if (max_stop_req - critical_point2 < 4)
3711 critical_point2 = 0;
3712
3713 }
3714
3715 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3716 /* some R300 cards have problem with this set to 0 */
3717 critical_point2 = 0x10;
3718 }
3719
3720 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3721 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3722
3723 if ((rdev->family == CHIP_RS400) ||
3724 (rdev->family == CHIP_RS480)) {
3725 #if 0
3726 /* attempt to program RS400 disp2 regs correctly ??? */
3727 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3728 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3729 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3730 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3731 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3732 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3733 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3734 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3735 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3736 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3737 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3738 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3739 #endif
3740 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3741 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3742 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3743 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3744 }
3745
3746 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3747 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3748 }
3749 }
3750
3751 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3752 {
3753 uint32_t scratch;
3754 uint32_t tmp = 0;
3755 unsigned i;
3756 int r;
3757
3758 r = radeon_scratch_get(rdev, &scratch);
3759 if (r) {
3760 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3761 return r;
3762 }
3763 WREG32(scratch, 0xCAFEDEAD);
3764 r = radeon_ring_lock(rdev, ring, 2);
3765 if (r) {
3766 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3767 radeon_scratch_free(rdev, scratch);
3768 return r;
3769 }
3770 radeon_ring_write(ring, PACKET0(scratch, 0));
3771 radeon_ring_write(ring, 0xDEADBEEF);
3772 radeon_ring_unlock_commit(rdev, ring);
3773 for (i = 0; i < rdev->usec_timeout; i++) {
3774 tmp = RREG32(scratch);
3775 if (tmp == 0xDEADBEEF) {
3776 break;
3777 }
3778 DRM_UDELAY(1);
3779 }
3780 if (i < rdev->usec_timeout) {
3781 DRM_INFO("ring test succeeded in %d usecs\n", i);
3782 } else {
3783 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3784 scratch, tmp);
3785 r = -EINVAL;
3786 }
3787 radeon_scratch_free(rdev, scratch);
3788 return r;
3789 }
3790
3791 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3792 {
3793 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3794
3795 if (ring->rptr_save_reg) {
3796 u32 next_rptr = ring->wptr + 2 + 3;
3797 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3798 radeon_ring_write(ring, next_rptr);
3799 }
3800
3801 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3802 radeon_ring_write(ring, ib->gpu_addr);
3803 radeon_ring_write(ring, ib->length_dw);
3804 }
3805
3806 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3807 {
3808 struct radeon_ib ib;
3809 uint32_t scratch;
3810 uint32_t tmp = 0;
3811 unsigned i;
3812 int r;
3813
3814 r = radeon_scratch_get(rdev, &scratch);
3815 if (r) {
3816 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3817 return r;
3818 }
3819 WREG32(scratch, 0xCAFEDEAD);
3820 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3821 if (r) {
3822 return r;
3823 }
3824 ib.ptr[0] = PACKET0(scratch, 0);
3825 ib.ptr[1] = 0xDEADBEEF;
3826 ib.ptr[2] = PACKET2(0);
3827 ib.ptr[3] = PACKET2(0);
3828 ib.ptr[4] = PACKET2(0);
3829 ib.ptr[5] = PACKET2(0);
3830 ib.ptr[6] = PACKET2(0);
3831 ib.ptr[7] = PACKET2(0);
3832 ib.length_dw = 8;
3833 r = radeon_ib_schedule(rdev, &ib, NULL);
3834 if (r) {
3835 radeon_scratch_free(rdev, scratch);
3836 radeon_ib_free(rdev, &ib);
3837 return r;
3838 }
3839 r = radeon_fence_wait(ib.fence, false);
3840 if (r) {
3841 return r;
3842 }
3843 for (i = 0; i < rdev->usec_timeout; i++) {
3844 tmp = RREG32(scratch);
3845 if (tmp == 0xDEADBEEF) {
3846 break;
3847 }
3848 DRM_UDELAY(1);
3849 }
3850 if (i < rdev->usec_timeout) {
3851 DRM_INFO("ib test succeeded in %u usecs\n", i);
3852 } else {
3853 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3854 scratch, tmp);
3855 r = -EINVAL;
3856 }
3857 radeon_scratch_free(rdev, scratch);
3858 radeon_ib_free(rdev, &ib);
3859 return r;
3860 }
3861
3862 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3863 {
3864 /* Shutdown CP we shouldn't need to do that but better be safe than
3865 * sorry
3866 */
3867 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3868 WREG32(R_000740_CP_CSQ_CNTL, 0);
3869
3870 /* Save few CRTC registers */
3871 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3872 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3873 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3874 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3875 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3876 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3877 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3878 }
3879
3880 /* Disable VGA aperture access */
3881 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3882 /* Disable cursor, overlay, crtc */
3883 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3884 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3885 S_000054_CRTC_DISPLAY_DIS(1));
3886 WREG32(R_000050_CRTC_GEN_CNTL,
3887 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3888 S_000050_CRTC_DISP_REQ_EN_B(1));
3889 WREG32(R_000420_OV0_SCALE_CNTL,
3890 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3891 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3892 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3893 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3894 S_000360_CUR2_LOCK(1));
3895 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3896 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3897 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3898 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3899 WREG32(R_000360_CUR2_OFFSET,
3900 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3901 }
3902 }
3903
3904 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3905 {
3906 /* Update base address for crtc */
3907 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3908 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3909 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3910 }
3911 /* Restore CRTC registers */
3912 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3913 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3914 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3915 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3916 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3917 }
3918 }
3919
3920 void r100_vga_render_disable(struct radeon_device *rdev)
3921 {
3922 u32 tmp;
3923
3924 tmp = RREG8(R_0003C2_GENMO_WT);
3925 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3926 }
3927
3928 static void r100_debugfs(struct radeon_device *rdev)
3929 {
3930 int r;
3931
3932 r = r100_debugfs_mc_info_init(rdev);
3933 if (r)
3934 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3935 }
3936
3937 static void r100_mc_program(struct radeon_device *rdev)
3938 {
3939 struct r100_mc_save save;
3940
3941 /* Stops all mc clients */
3942 r100_mc_stop(rdev, &save);
3943 if (rdev->flags & RADEON_IS_AGP) {
3944 WREG32(R_00014C_MC_AGP_LOCATION,
3945 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3946 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3947 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3948 if (rdev->family > CHIP_RV200)
3949 WREG32(R_00015C_AGP_BASE_2,
3950 upper_32_bits(rdev->mc.agp_base) & 0xff);
3951 } else {
3952 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3953 WREG32(R_000170_AGP_BASE, 0);
3954 if (rdev->family > CHIP_RV200)
3955 WREG32(R_00015C_AGP_BASE_2, 0);
3956 }
3957 /* Wait for mc idle */
3958 if (r100_mc_wait_for_idle(rdev))
3959 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3960 /* Program MC, should be a 32bits limited address space */
3961 WREG32(R_000148_MC_FB_LOCATION,
3962 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3963 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3964 r100_mc_resume(rdev, &save);
3965 }
3966
3967 void r100_clock_startup(struct radeon_device *rdev)
3968 {
3969 u32 tmp;
3970
3971 if (radeon_dynclks != -1 && radeon_dynclks)
3972 radeon_legacy_set_clock_gating(rdev, 1);
3973 /* We need to force on some of the block */
3974 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3975 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3976 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3977 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3978 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3979 }
3980
3981 static int r100_startup(struct radeon_device *rdev)
3982 {
3983 int r;
3984
3985 /* set common regs */
3986 r100_set_common_regs(rdev);
3987 /* program mc */
3988 r100_mc_program(rdev);
3989 /* Resume clock */
3990 r100_clock_startup(rdev);
3991 /* Initialize GART (initialize after TTM so we can allocate
3992 * memory through TTM but finalize after TTM) */
3993 r100_enable_bm(rdev);
3994 if (rdev->flags & RADEON_IS_PCI) {
3995 r = r100_pci_gart_enable(rdev);
3996 if (r)
3997 return r;
3998 }
3999
4000 /* allocate wb buffer */
4001 r = radeon_wb_init(rdev);
4002 if (r)
4003 return r;
4004
4005 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4006 if (r) {
4007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4008 return r;
4009 }
4010
4011 /* Enable IRQ */
4012 r100_irq_set(rdev);
4013 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
4014 /* 1M ring buffer */
4015 r = r100_cp_init(rdev, 1024 * 1024);
4016 if (r) {
4017 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
4018 return r;
4019 }
4020
4021 r = radeon_ib_pool_init(rdev);
4022 if (r) {
4023 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4024 return r;
4025 }
4026
4027 return 0;
4028 }
4029
4030 int r100_resume(struct radeon_device *rdev)
4031 {
4032 int r;
4033
4034 /* Make sur GART are not working */
4035 if (rdev->flags & RADEON_IS_PCI)
4036 r100_pci_gart_disable(rdev);
4037 /* Resume clock before doing reset */
4038 r100_clock_startup(rdev);
4039 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4040 if (radeon_asic_reset(rdev)) {
4041 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4042 RREG32(R_000E40_RBBM_STATUS),
4043 RREG32(R_0007C0_CP_STAT));
4044 }
4045 /* post */
4046 radeon_combios_asic_init(rdev->ddev);
4047 /* Resume clock after posting */
4048 r100_clock_startup(rdev);
4049 /* Initialize surface registers */
4050 radeon_surface_init(rdev);
4051
4052 rdev->accel_working = true;
4053 r = r100_startup(rdev);
4054 if (r) {
4055 rdev->accel_working = false;
4056 }
4057 return r;
4058 }
4059
4060 int r100_suspend(struct radeon_device *rdev)
4061 {
4062 r100_cp_disable(rdev);
4063 radeon_wb_disable(rdev);
4064 r100_irq_disable(rdev);
4065 if (rdev->flags & RADEON_IS_PCI)
4066 r100_pci_gart_disable(rdev);
4067 return 0;
4068 }
4069
4070 void r100_fini(struct radeon_device *rdev)
4071 {
4072 r100_cp_fini(rdev);
4073 radeon_wb_fini(rdev);
4074 radeon_ib_pool_fini(rdev);
4075 radeon_gem_fini(rdev);
4076 if (rdev->flags & RADEON_IS_PCI)
4077 r100_pci_gart_fini(rdev);
4078 radeon_agp_fini(rdev);
4079 radeon_irq_kms_fini(rdev);
4080 radeon_fence_driver_fini(rdev);
4081 radeon_bo_fini(rdev);
4082 radeon_atombios_fini(rdev);
4083 kfree(rdev->bios);
4084 rdev->bios = NULL;
4085 }
4086
4087 /*
4088 * Due to how kexec works, it can leave the hw fully initialised when it
4089 * boots the new kernel. However doing our init sequence with the CP and
4090 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4091 * do some quick sanity checks and restore sane values to avoid this
4092 * problem.
4093 */
4094 void r100_restore_sanity(struct radeon_device *rdev)
4095 {
4096 u32 tmp;
4097
4098 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4099 if (tmp) {
4100 WREG32(RADEON_CP_CSQ_CNTL, 0);
4101 }
4102 tmp = RREG32(RADEON_CP_RB_CNTL);
4103 if (tmp) {
4104 WREG32(RADEON_CP_RB_CNTL, 0);
4105 }
4106 tmp = RREG32(RADEON_SCRATCH_UMSK);
4107 if (tmp) {
4108 WREG32(RADEON_SCRATCH_UMSK, 0);
4109 }
4110 }
4111
4112 int r100_init(struct radeon_device *rdev)
4113 {
4114 int r;
4115
4116 /* Register debugfs file specific to this group of asics */
4117 r100_debugfs(rdev);
4118 /* Disable VGA */
4119 r100_vga_render_disable(rdev);
4120 /* Initialize scratch registers */
4121 radeon_scratch_init(rdev);
4122 /* Initialize surface registers */
4123 radeon_surface_init(rdev);
4124 /* sanity check some register to avoid hangs like after kexec */
4125 r100_restore_sanity(rdev);
4126 /* TODO: disable VGA need to use VGA request */
4127 /* BIOS*/
4128 if (!radeon_get_bios(rdev)) {
4129 if (ASIC_IS_AVIVO(rdev))
4130 return -EINVAL;
4131 }
4132 if (rdev->is_atom_bios) {
4133 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4134 return -EINVAL;
4135 } else {
4136 r = radeon_combios_init(rdev);
4137 if (r)
4138 return r;
4139 }
4140 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4141 if (radeon_asic_reset(rdev)) {
4142 dev_warn(rdev->dev,
4143 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4144 RREG32(R_000E40_RBBM_STATUS),
4145 RREG32(R_0007C0_CP_STAT));
4146 }
4147 /* check if cards are posted or not */
4148 if (radeon_boot_test_post_card(rdev) == false)
4149 return -EINVAL;
4150 /* Set asic errata */
4151 r100_errata(rdev);
4152 /* Initialize clocks */
4153 radeon_get_clock_info(rdev->ddev);
4154 /* initialize AGP */
4155 if (rdev->flags & RADEON_IS_AGP) {
4156 r = radeon_agp_init(rdev);
4157 if (r) {
4158 radeon_agp_disable(rdev);
4159 }
4160 }
4161 /* initialize VRAM */
4162 r100_mc_init(rdev);
4163 /* Fence driver */
4164 r = radeon_fence_driver_init(rdev);
4165 if (r)
4166 return r;
4167 r = radeon_irq_kms_init(rdev);
4168 if (r)
4169 return r;
4170 /* Memory manager */
4171 r = radeon_bo_init(rdev);
4172 if (r)
4173 return r;
4174 if (rdev->flags & RADEON_IS_PCI) {
4175 r = r100_pci_gart_init(rdev);
4176 if (r)
4177 return r;
4178 }
4179 r100_set_safe_registers(rdev);
4180
4181 rdev->accel_working = true;
4182 r = r100_startup(rdev);
4183 if (r) {
4184 /* Somethings want wront with the accel init stop accel */
4185 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4186 r100_cp_fini(rdev);
4187 radeon_wb_fini(rdev);
4188 radeon_ib_pool_fini(rdev);
4189 radeon_irq_kms_fini(rdev);
4190 if (rdev->flags & RADEON_IS_PCI)
4191 r100_pci_gart_fini(rdev);
4192 rdev->accel_working = false;
4193 }
4194 return 0;
4195 }
4196
4197 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4198 {
4199 if (reg < rdev->rmmio_size)
4200 return readl(((void __iomem *)rdev->rmmio) + reg);
4201 else {
4202 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4203 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4204 }
4205 }
4206
4207 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4208 {
4209 if (reg < rdev->rmmio_size)
4210 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4211 else {
4212 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4213 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4214 }
4215 }
4216
4217 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4218 {
4219 if (reg < rdev->rio_mem_size)
4220 return ioread32(rdev->rio_mem + reg);
4221 else {
4222 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4223 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4224 }
4225 }
4226
4227 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4228 {
4229 if (reg < rdev->rio_mem_size)
4230 iowrite32(v, rdev->rio_mem + reg);
4231 else {
4232 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4233 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4234 }
4235 }
Linux kernel - Deliverables
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