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drm/radeon/kms: consolidate GART code, fix segfault after GPU lockup V2
[deliverable/linux.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm.h>
32 #include <drm/drm_crtc_helper.h>
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_drm.h"
37 #include "r100_track.h"
38 #include "r300d.h"
39 #include "rv350d.h"
40 #include "r300_reg_safe.h"
41
42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
43 *
44 * GPU Errata:
45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 * However, scheduling such write to the ring seems harmless, i suspect
48 * the CP read collide with the flush somehow, or maybe the MC, hard to
49 * tell. (Jerome Glisse)
50 */
51
52 /*
53 * rv370,rv380 PCIE GART
54 */
55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
56
57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
58 {
59 uint32_t tmp;
60 int i;
61
62 /* Workaround HW bug do flush 2 times */
63 for (i = 0; i < 2; i++) {
64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
68 }
69 mb();
70 }
71
72 #define R300_PTE_WRITEABLE (1 << 2)
73 #define R300_PTE_READABLE (1 << 3)
74
75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
76 {
77 void __iomem *ptr = rdev->gart.ptr;
78
79 if (i < 0 || i > rdev->gart.num_gpu_pages) {
80 return -EINVAL;
81 }
82 addr = (lower_32_bits(addr) >> 8) |
83 ((upper_32_bits(addr) & 0xff) << 24) |
84 R300_PTE_WRITEABLE | R300_PTE_READABLE;
85 /* on x86 we want this to be CPU endian, on powerpc
86 * on powerpc without HW swappers, it'll get swapped on way
87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
88 writel(addr, ((void __iomem *)ptr) + (i * 4));
89 return 0;
90 }
91
92 int rv370_pcie_gart_init(struct radeon_device *rdev)
93 {
94 int r;
95
96 if (rdev->gart.robj) {
97 WARN(1, "RV370 PCIE GART already initialized\n");
98 return 0;
99 }
100 /* Initialize common gart structure */
101 r = radeon_gart_init(rdev);
102 if (r)
103 return r;
104 r = rv370_debugfs_pcie_gart_info_init(rdev);
105 if (r)
106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
109 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
110 return radeon_gart_table_vram_alloc(rdev);
111 }
112
113 int rv370_pcie_gart_enable(struct radeon_device *rdev)
114 {
115 uint32_t table_addr;
116 uint32_t tmp;
117 int r;
118
119 if (rdev->gart.robj == NULL) {
120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
121 return -EINVAL;
122 }
123 r = radeon_gart_table_vram_pin(rdev);
124 if (r)
125 return r;
126 radeon_gart_restore(rdev);
127 /* discard memory request outside of configured range */
128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
135 table_addr = rdev->gart.table_addr;
136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
137 /* FIXME: setup default page */
138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
140 /* Clear error */
141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143 tmp |= RADEON_PCIE_TX_GART_EN;
144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
146 rv370_pcie_gart_tlb_flush(rdev);
147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
148 (unsigned)(rdev->mc.gtt_size >> 20),
149 (unsigned long long)table_addr);
150 rdev->gart.ready = true;
151 return 0;
152 }
153
154 void rv370_pcie_gart_disable(struct radeon_device *rdev)
155 {
156 u32 tmp;
157
158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
165 radeon_gart_table_vram_unpin(rdev);
166 }
167
168 void rv370_pcie_gart_fini(struct radeon_device *rdev)
169 {
170 radeon_gart_fini(rdev);
171 rv370_pcie_gart_disable(rdev);
172 radeon_gart_table_vram_free(rdev);
173 }
174
175 void r300_fence_ring_emit(struct radeon_device *rdev,
176 struct radeon_fence *fence)
177 {
178 /* Who ever call radeon_fence_emit should call ring_lock and ask
179 * for enough space (today caller are ib schedule and buffer move) */
180 /* Write SC register so SC & US assert idle */
181 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
182 radeon_ring_write(rdev, 0);
183 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
184 radeon_ring_write(rdev, 0);
185 /* Flush 3D cache */
186 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
187 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
188 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
189 radeon_ring_write(rdev, R300_ZC_FLUSH);
190 /* Wait until IDLE & CLEAN */
191 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
192 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
193 RADEON_WAIT_2D_IDLECLEAN |
194 RADEON_WAIT_DMA_GUI_IDLE));
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
197 RADEON_HDP_READ_BUFFER_INVALIDATE);
198 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
199 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
200 /* Emit fence sequence & fire IRQ */
201 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
202 radeon_ring_write(rdev, fence->seq);
203 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
204 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
205 }
206
207 void r300_ring_start(struct radeon_device *rdev)
208 {
209 unsigned gb_tile_config;
210 int r;
211
212 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
213 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
214 switch(rdev->num_gb_pipes) {
215 case 2:
216 gb_tile_config |= R300_PIPE_COUNT_R300;
217 break;
218 case 3:
219 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
220 break;
221 case 4:
222 gb_tile_config |= R300_PIPE_COUNT_R420;
223 break;
224 case 1:
225 default:
226 gb_tile_config |= R300_PIPE_COUNT_RV350;
227 break;
228 }
229
230 r = radeon_ring_lock(rdev, 64);
231 if (r) {
232 return;
233 }
234 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
235 radeon_ring_write(rdev,
236 RADEON_ISYNC_ANY2D_IDLE3D |
237 RADEON_ISYNC_ANY3D_IDLE2D |
238 RADEON_ISYNC_WAIT_IDLEGUI |
239 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
240 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
241 radeon_ring_write(rdev, gb_tile_config);
242 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
243 radeon_ring_write(rdev,
244 RADEON_WAIT_2D_IDLECLEAN |
245 RADEON_WAIT_3D_IDLECLEAN);
246 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
247 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
248 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
249 radeon_ring_write(rdev, 0);
250 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
251 radeon_ring_write(rdev, 0);
252 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
253 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
254 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
255 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
256 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
257 radeon_ring_write(rdev,
258 RADEON_WAIT_2D_IDLECLEAN |
259 RADEON_WAIT_3D_IDLECLEAN);
260 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
261 radeon_ring_write(rdev, 0);
262 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
263 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
264 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
265 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
266 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
267 radeon_ring_write(rdev,
268 ((6 << R300_MS_X0_SHIFT) |
269 (6 << R300_MS_Y0_SHIFT) |
270 (6 << R300_MS_X1_SHIFT) |
271 (6 << R300_MS_Y1_SHIFT) |
272 (6 << R300_MS_X2_SHIFT) |
273 (6 << R300_MS_Y2_SHIFT) |
274 (6 << R300_MSBD0_Y_SHIFT) |
275 (6 << R300_MSBD0_X_SHIFT)));
276 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
277 radeon_ring_write(rdev,
278 ((6 << R300_MS_X3_SHIFT) |
279 (6 << R300_MS_Y3_SHIFT) |
280 (6 << R300_MS_X4_SHIFT) |
281 (6 << R300_MS_Y4_SHIFT) |
282 (6 << R300_MS_X5_SHIFT) |
283 (6 << R300_MS_Y5_SHIFT) |
284 (6 << R300_MSBD1_SHIFT)));
285 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
286 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
287 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
288 radeon_ring_write(rdev,
289 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
290 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
291 radeon_ring_write(rdev,
292 R300_GEOMETRY_ROUND_NEAREST |
293 R300_COLOR_ROUND_NEAREST);
294 radeon_ring_unlock_commit(rdev);
295 }
296
297 void r300_errata(struct radeon_device *rdev)
298 {
299 rdev->pll_errata = 0;
300
301 if (rdev->family == CHIP_R300 &&
302 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
303 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
304 }
305 }
306
307 int r300_mc_wait_for_idle(struct radeon_device *rdev)
308 {
309 unsigned i;
310 uint32_t tmp;
311
312 for (i = 0; i < rdev->usec_timeout; i++) {
313 /* read MC_STATUS */
314 tmp = RREG32(RADEON_MC_STATUS);
315 if (tmp & R300_MC_IDLE) {
316 return 0;
317 }
318 DRM_UDELAY(1);
319 }
320 return -1;
321 }
322
323 void r300_gpu_init(struct radeon_device *rdev)
324 {
325 uint32_t gb_tile_config, tmp;
326
327 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
328 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
329 /* r300,r350 */
330 rdev->num_gb_pipes = 2;
331 } else {
332 /* rv350,rv370,rv380,r300 AD, r350 AH */
333 rdev->num_gb_pipes = 1;
334 }
335 rdev->num_z_pipes = 1;
336 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
337 switch (rdev->num_gb_pipes) {
338 case 2:
339 gb_tile_config |= R300_PIPE_COUNT_R300;
340 break;
341 case 3:
342 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
343 break;
344 case 4:
345 gb_tile_config |= R300_PIPE_COUNT_R420;
346 break;
347 default:
348 case 1:
349 gb_tile_config |= R300_PIPE_COUNT_RV350;
350 break;
351 }
352 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
353
354 if (r100_gui_wait_for_idle(rdev)) {
355 printk(KERN_WARNING "Failed to wait GUI idle while "
356 "programming pipes. Bad things might happen.\n");
357 }
358
359 tmp = RREG32(R300_DST_PIPE_CONFIG);
360 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
361
362 WREG32(R300_RB2D_DSTCACHE_MODE,
363 R300_DC_AUTOFLUSH_ENABLE |
364 R300_DC_DC_DISABLE_IGNORE_PE);
365
366 if (r100_gui_wait_for_idle(rdev)) {
367 printk(KERN_WARNING "Failed to wait GUI idle while "
368 "programming pipes. Bad things might happen.\n");
369 }
370 if (r300_mc_wait_for_idle(rdev)) {
371 printk(KERN_WARNING "Failed to wait MC idle while "
372 "programming pipes. Bad things might happen.\n");
373 }
374 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
375 rdev->num_gb_pipes, rdev->num_z_pipes);
376 }
377
378 bool r300_gpu_is_lockup(struct radeon_device *rdev)
379 {
380 u32 rbbm_status;
381 int r;
382
383 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
384 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
385 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
386 return false;
387 }
388 /* force CP activities */
389 r = radeon_ring_lock(rdev, 2);
390 if (!r) {
391 /* PACKET2 NOP */
392 radeon_ring_write(rdev, 0x80000000);
393 radeon_ring_write(rdev, 0x80000000);
394 radeon_ring_unlock_commit(rdev);
395 }
396 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
397 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
398 }
399
400 int r300_asic_reset(struct radeon_device *rdev)
401 {
402 struct r100_mc_save save;
403 u32 status, tmp;
404 int ret = 0;
405
406 status = RREG32(R_000E40_RBBM_STATUS);
407 if (!G_000E40_GUI_ACTIVE(status)) {
408 return 0;
409 }
410 r100_mc_stop(rdev, &save);
411 status = RREG32(R_000E40_RBBM_STATUS);
412 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
413 /* stop CP */
414 WREG32(RADEON_CP_CSQ_CNTL, 0);
415 tmp = RREG32(RADEON_CP_RB_CNTL);
416 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
417 WREG32(RADEON_CP_RB_RPTR_WR, 0);
418 WREG32(RADEON_CP_RB_WPTR, 0);
419 WREG32(RADEON_CP_RB_CNTL, tmp);
420 /* save PCI state */
421 pci_save_state(rdev->pdev);
422 /* disable bus mastering */
423 r100_bm_disable(rdev);
424 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
425 S_0000F0_SOFT_RESET_GA(1));
426 RREG32(R_0000F0_RBBM_SOFT_RESET);
427 mdelay(500);
428 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
429 mdelay(1);
430 status = RREG32(R_000E40_RBBM_STATUS);
431 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
432 /* resetting the CP seems to be problematic sometimes it end up
433 * hard locking the computer, but it's necessary for successful
434 * reset more test & playing is needed on R3XX/R4XX to find a
435 * reliable (if any solution)
436 */
437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
438 RREG32(R_0000F0_RBBM_SOFT_RESET);
439 mdelay(500);
440 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
441 mdelay(1);
442 status = RREG32(R_000E40_RBBM_STATUS);
443 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
444 /* restore PCI & busmastering */
445 pci_restore_state(rdev->pdev);
446 r100_enable_bm(rdev);
447 /* Check if GPU is idle */
448 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
449 dev_err(rdev->dev, "failed to reset GPU\n");
450 rdev->gpu_lockup = true;
451 ret = -1;
452 } else
453 dev_info(rdev->dev, "GPU reset succeed\n");
454 r100_mc_resume(rdev, &save);
455 return ret;
456 }
457
458 /*
459 * r300,r350,rv350,rv380 VRAM info
460 */
461 void r300_mc_init(struct radeon_device *rdev)
462 {
463 u64 base;
464 u32 tmp;
465
466 /* DDR for all card after R300 & IGP */
467 rdev->mc.vram_is_ddr = true;
468 tmp = RREG32(RADEON_MEM_CNTL);
469 tmp &= R300_MEM_NUM_CHANNELS_MASK;
470 switch (tmp) {
471 case 0: rdev->mc.vram_width = 64; break;
472 case 1: rdev->mc.vram_width = 128; break;
473 case 2: rdev->mc.vram_width = 256; break;
474 default: rdev->mc.vram_width = 128; break;
475 }
476 r100_vram_init_sizes(rdev);
477 base = rdev->mc.aper_base;
478 if (rdev->flags & RADEON_IS_IGP)
479 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
480 radeon_vram_location(rdev, &rdev->mc, base);
481 rdev->mc.gtt_base_align = 0;
482 if (!(rdev->flags & RADEON_IS_AGP))
483 radeon_gtt_location(rdev, &rdev->mc);
484 radeon_update_bandwidth_info(rdev);
485 }
486
487 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
488 {
489 uint32_t link_width_cntl, mask;
490
491 if (rdev->flags & RADEON_IS_IGP)
492 return;
493
494 if (!(rdev->flags & RADEON_IS_PCIE))
495 return;
496
497 /* FIXME wait for idle */
498
499 switch (lanes) {
500 case 0:
501 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
502 break;
503 case 1:
504 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
505 break;
506 case 2:
507 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
508 break;
509 case 4:
510 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
511 break;
512 case 8:
513 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
514 break;
515 case 12:
516 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
517 break;
518 case 16:
519 default:
520 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
521 break;
522 }
523
524 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
525
526 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
527 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
528 return;
529
530 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
531 RADEON_PCIE_LC_RECONFIG_NOW |
532 RADEON_PCIE_LC_RECONFIG_LATER |
533 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
534 link_width_cntl |= mask;
535 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
536 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
537 RADEON_PCIE_LC_RECONFIG_NOW));
538
539 /* wait for lane set to complete */
540 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
541 while (link_width_cntl == 0xffffffff)
542 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
543
544 }
545
546 int rv370_get_pcie_lanes(struct radeon_device *rdev)
547 {
548 u32 link_width_cntl;
549
550 if (rdev->flags & RADEON_IS_IGP)
551 return 0;
552
553 if (!(rdev->flags & RADEON_IS_PCIE))
554 return 0;
555
556 /* FIXME wait for idle */
557
558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
559
560 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
561 case RADEON_PCIE_LC_LINK_WIDTH_X0:
562 return 0;
563 case RADEON_PCIE_LC_LINK_WIDTH_X1:
564 return 1;
565 case RADEON_PCIE_LC_LINK_WIDTH_X2:
566 return 2;
567 case RADEON_PCIE_LC_LINK_WIDTH_X4:
568 return 4;
569 case RADEON_PCIE_LC_LINK_WIDTH_X8:
570 return 8;
571 case RADEON_PCIE_LC_LINK_WIDTH_X16:
572 default:
573 return 16;
574 }
575 }
576
577 #if defined(CONFIG_DEBUG_FS)
578 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
579 {
580 struct drm_info_node *node = (struct drm_info_node *) m->private;
581 struct drm_device *dev = node->minor->dev;
582 struct radeon_device *rdev = dev->dev_private;
583 uint32_t tmp;
584
585 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
586 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
588 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
590 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
592 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
594 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
596 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
598 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
599 return 0;
600 }
601
602 static struct drm_info_list rv370_pcie_gart_info_list[] = {
603 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
604 };
605 #endif
606
607 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
608 {
609 #if defined(CONFIG_DEBUG_FS)
610 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
611 #else
612 return 0;
613 #endif
614 }
615
616 static int r300_packet0_check(struct radeon_cs_parser *p,
617 struct radeon_cs_packet *pkt,
618 unsigned idx, unsigned reg)
619 {
620 struct radeon_cs_reloc *reloc;
621 struct r100_cs_track *track;
622 volatile uint32_t *ib;
623 uint32_t tmp, tile_flags = 0;
624 unsigned i;
625 int r;
626 u32 idx_value;
627
628 ib = p->ib->ptr;
629 track = (struct r100_cs_track *)p->track;
630 idx_value = radeon_get_ib_value(p, idx);
631
632 switch(reg) {
633 case AVIVO_D1MODE_VLINE_START_END:
634 case RADEON_CRTC_GUI_TRIG_VLINE:
635 r = r100_cs_packet_parse_vline(p);
636 if (r) {
637 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
638 idx, reg);
639 r100_cs_dump_packet(p, pkt);
640 return r;
641 }
642 break;
643 case RADEON_DST_PITCH_OFFSET:
644 case RADEON_SRC_PITCH_OFFSET:
645 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
646 if (r)
647 return r;
648 break;
649 case R300_RB3D_COLOROFFSET0:
650 case R300_RB3D_COLOROFFSET1:
651 case R300_RB3D_COLOROFFSET2:
652 case R300_RB3D_COLOROFFSET3:
653 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
654 r = r100_cs_packet_next_reloc(p, &reloc);
655 if (r) {
656 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
657 idx, reg);
658 r100_cs_dump_packet(p, pkt);
659 return r;
660 }
661 track->cb[i].robj = reloc->robj;
662 track->cb[i].offset = idx_value;
663 track->cb_dirty = true;
664 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
665 break;
666 case R300_ZB_DEPTHOFFSET:
667 r = r100_cs_packet_next_reloc(p, &reloc);
668 if (r) {
669 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
670 idx, reg);
671 r100_cs_dump_packet(p, pkt);
672 return r;
673 }
674 track->zb.robj = reloc->robj;
675 track->zb.offset = idx_value;
676 track->zb_dirty = true;
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
678 break;
679 case R300_TX_OFFSET_0:
680 case R300_TX_OFFSET_0+4:
681 case R300_TX_OFFSET_0+8:
682 case R300_TX_OFFSET_0+12:
683 case R300_TX_OFFSET_0+16:
684 case R300_TX_OFFSET_0+20:
685 case R300_TX_OFFSET_0+24:
686 case R300_TX_OFFSET_0+28:
687 case R300_TX_OFFSET_0+32:
688 case R300_TX_OFFSET_0+36:
689 case R300_TX_OFFSET_0+40:
690 case R300_TX_OFFSET_0+44:
691 case R300_TX_OFFSET_0+48:
692 case R300_TX_OFFSET_0+52:
693 case R300_TX_OFFSET_0+56:
694 case R300_TX_OFFSET_0+60:
695 i = (reg - R300_TX_OFFSET_0) >> 2;
696 r = r100_cs_packet_next_reloc(p, &reloc);
697 if (r) {
698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
699 idx, reg);
700 r100_cs_dump_packet(p, pkt);
701 return r;
702 }
703
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
705 tile_flags |= R300_TXO_MACRO_TILE;
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
707 tile_flags |= R300_TXO_MICRO_TILE;
708 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
709 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
710
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
712 tmp |= tile_flags;
713 ib[idx] = tmp;
714 track->textures[i].robj = reloc->robj;
715 track->tex_dirty = true;
716 break;
717 /* Tracked registers */
718 case 0x2084:
719 /* VAP_VF_CNTL */
720 track->vap_vf_cntl = idx_value;
721 break;
722 case 0x20B4:
723 /* VAP_VTX_SIZE */
724 track->vtx_size = idx_value & 0x7F;
725 break;
726 case 0x2134:
727 /* VAP_VF_MAX_VTX_INDX */
728 track->max_indx = idx_value & 0x00FFFFFFUL;
729 break;
730 case 0x2088:
731 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
732 if (p->rdev->family < CHIP_RV515)
733 goto fail;
734 track->vap_alt_nverts = idx_value & 0xFFFFFF;
735 break;
736 case 0x43E4:
737 /* SC_SCISSOR1 */
738 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
739 if (p->rdev->family < CHIP_RV515) {
740 track->maxy -= 1440;
741 }
742 track->cb_dirty = true;
743 track->zb_dirty = true;
744 break;
745 case 0x4E00:
746 /* RB3D_CCTL */
747 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
748 p->rdev->cmask_filp != p->filp) {
749 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
750 return -EINVAL;
751 }
752 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
753 track->cb_dirty = true;
754 break;
755 case 0x4E38:
756 case 0x4E3C:
757 case 0x4E40:
758 case 0x4E44:
759 /* RB3D_COLORPITCH0 */
760 /* RB3D_COLORPITCH1 */
761 /* RB3D_COLORPITCH2 */
762 /* RB3D_COLORPITCH3 */
763 r = r100_cs_packet_next_reloc(p, &reloc);
764 if (r) {
765 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
766 idx, reg);
767 r100_cs_dump_packet(p, pkt);
768 return r;
769 }
770
771 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
772 tile_flags |= R300_COLOR_TILE_ENABLE;
773 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
774 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
775 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
776 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
777
778 tmp = idx_value & ~(0x7 << 16);
779 tmp |= tile_flags;
780 ib[idx] = tmp;
781 i = (reg - 0x4E38) >> 2;
782 track->cb[i].pitch = idx_value & 0x3FFE;
783 switch (((idx_value >> 21) & 0xF)) {
784 case 9:
785 case 11:
786 case 12:
787 track->cb[i].cpp = 1;
788 break;
789 case 3:
790 case 4:
791 case 13:
792 case 15:
793 track->cb[i].cpp = 2;
794 break;
795 case 5:
796 if (p->rdev->family < CHIP_RV515) {
797 DRM_ERROR("Invalid color buffer format (%d)!\n",
798 ((idx_value >> 21) & 0xF));
799 return -EINVAL;
800 }
801 /* Pass through. */
802 case 6:
803 track->cb[i].cpp = 4;
804 break;
805 case 10:
806 track->cb[i].cpp = 8;
807 break;
808 case 7:
809 track->cb[i].cpp = 16;
810 break;
811 default:
812 DRM_ERROR("Invalid color buffer format (%d) !\n",
813 ((idx_value >> 21) & 0xF));
814 return -EINVAL;
815 }
816 track->cb_dirty = true;
817 break;
818 case 0x4F00:
819 /* ZB_CNTL */
820 if (idx_value & 2) {
821 track->z_enabled = true;
822 } else {
823 track->z_enabled = false;
824 }
825 track->zb_dirty = true;
826 break;
827 case 0x4F10:
828 /* ZB_FORMAT */
829 switch ((idx_value & 0xF)) {
830 case 0:
831 case 1:
832 track->zb.cpp = 2;
833 break;
834 case 2:
835 track->zb.cpp = 4;
836 break;
837 default:
838 DRM_ERROR("Invalid z buffer format (%d) !\n",
839 (idx_value & 0xF));
840 return -EINVAL;
841 }
842 track->zb_dirty = true;
843 break;
844 case 0x4F24:
845 /* ZB_DEPTHPITCH */
846 r = r100_cs_packet_next_reloc(p, &reloc);
847 if (r) {
848 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
849 idx, reg);
850 r100_cs_dump_packet(p, pkt);
851 return r;
852 }
853
854 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
855 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
856 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
857 tile_flags |= R300_DEPTHMICROTILE_TILED;
858 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
859 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
860
861 tmp = idx_value & ~(0x7 << 16);
862 tmp |= tile_flags;
863 ib[idx] = tmp;
864
865 track->zb.pitch = idx_value & 0x3FFC;
866 track->zb_dirty = true;
867 break;
868 case 0x4104:
869 /* TX_ENABLE */
870 for (i = 0; i < 16; i++) {
871 bool enabled;
872
873 enabled = !!(idx_value & (1 << i));
874 track->textures[i].enabled = enabled;
875 }
876 track->tex_dirty = true;
877 break;
878 case 0x44C0:
879 case 0x44C4:
880 case 0x44C8:
881 case 0x44CC:
882 case 0x44D0:
883 case 0x44D4:
884 case 0x44D8:
885 case 0x44DC:
886 case 0x44E0:
887 case 0x44E4:
888 case 0x44E8:
889 case 0x44EC:
890 case 0x44F0:
891 case 0x44F4:
892 case 0x44F8:
893 case 0x44FC:
894 /* TX_FORMAT1_[0-15] */
895 i = (reg - 0x44C0) >> 2;
896 tmp = (idx_value >> 25) & 0x3;
897 track->textures[i].tex_coord_type = tmp;
898 switch ((idx_value & 0x1F)) {
899 case R300_TX_FORMAT_X8:
900 case R300_TX_FORMAT_Y4X4:
901 case R300_TX_FORMAT_Z3Y3X2:
902 track->textures[i].cpp = 1;
903 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
904 break;
905 case R300_TX_FORMAT_X16:
906 case R300_TX_FORMAT_FL_I16:
907 case R300_TX_FORMAT_Y8X8:
908 case R300_TX_FORMAT_Z5Y6X5:
909 case R300_TX_FORMAT_Z6Y5X5:
910 case R300_TX_FORMAT_W4Z4Y4X4:
911 case R300_TX_FORMAT_W1Z5Y5X5:
912 case R300_TX_FORMAT_D3DMFT_CxV8U8:
913 case R300_TX_FORMAT_B8G8_B8G8:
914 case R300_TX_FORMAT_G8R8_G8B8:
915 track->textures[i].cpp = 2;
916 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
917 break;
918 case R300_TX_FORMAT_Y16X16:
919 case R300_TX_FORMAT_FL_I16A16:
920 case R300_TX_FORMAT_Z11Y11X10:
921 case R300_TX_FORMAT_Z10Y11X11:
922 case R300_TX_FORMAT_W8Z8Y8X8:
923 case R300_TX_FORMAT_W2Z10Y10X10:
924 case 0x17:
925 case R300_TX_FORMAT_FL_I32:
926 case 0x1e:
927 track->textures[i].cpp = 4;
928 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
929 break;
930 case R300_TX_FORMAT_W16Z16Y16X16:
931 case R300_TX_FORMAT_FL_R16G16B16A16:
932 case R300_TX_FORMAT_FL_I32A32:
933 track->textures[i].cpp = 8;
934 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
935 break;
936 case R300_TX_FORMAT_FL_R32G32B32A32:
937 track->textures[i].cpp = 16;
938 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
939 break;
940 case R300_TX_FORMAT_DXT1:
941 track->textures[i].cpp = 1;
942 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
943 break;
944 case R300_TX_FORMAT_ATI2N:
945 if (p->rdev->family < CHIP_R420) {
946 DRM_ERROR("Invalid texture format %u\n",
947 (idx_value & 0x1F));
948 return -EINVAL;
949 }
950 /* The same rules apply as for DXT3/5. */
951 /* Pass through. */
952 case R300_TX_FORMAT_DXT3:
953 case R300_TX_FORMAT_DXT5:
954 track->textures[i].cpp = 1;
955 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
956 break;
957 default:
958 DRM_ERROR("Invalid texture format %u\n",
959 (idx_value & 0x1F));
960 return -EINVAL;
961 }
962 track->tex_dirty = true;
963 break;
964 case 0x4400:
965 case 0x4404:
966 case 0x4408:
967 case 0x440C:
968 case 0x4410:
969 case 0x4414:
970 case 0x4418:
971 case 0x441C:
972 case 0x4420:
973 case 0x4424:
974 case 0x4428:
975 case 0x442C:
976 case 0x4430:
977 case 0x4434:
978 case 0x4438:
979 case 0x443C:
980 /* TX_FILTER0_[0-15] */
981 i = (reg - 0x4400) >> 2;
982 tmp = idx_value & 0x7;
983 if (tmp == 2 || tmp == 4 || tmp == 6) {
984 track->textures[i].roundup_w = false;
985 }
986 tmp = (idx_value >> 3) & 0x7;
987 if (tmp == 2 || tmp == 4 || tmp == 6) {
988 track->textures[i].roundup_h = false;
989 }
990 track->tex_dirty = true;
991 break;
992 case 0x4500:
993 case 0x4504:
994 case 0x4508:
995 case 0x450C:
996 case 0x4510:
997 case 0x4514:
998 case 0x4518:
999 case 0x451C:
1000 case 0x4520:
1001 case 0x4524:
1002 case 0x4528:
1003 case 0x452C:
1004 case 0x4530:
1005 case 0x4534:
1006 case 0x4538:
1007 case 0x453C:
1008 /* TX_FORMAT2_[0-15] */
1009 i = (reg - 0x4500) >> 2;
1010 tmp = idx_value & 0x3FFF;
1011 track->textures[i].pitch = tmp + 1;
1012 if (p->rdev->family >= CHIP_RV515) {
1013 tmp = ((idx_value >> 15) & 1) << 11;
1014 track->textures[i].width_11 = tmp;
1015 tmp = ((idx_value >> 16) & 1) << 11;
1016 track->textures[i].height_11 = tmp;
1017
1018 /* ATI1N */
1019 if (idx_value & (1 << 14)) {
1020 /* The same rules apply as for DXT1. */
1021 track->textures[i].compress_format =
1022 R100_TRACK_COMP_DXT1;
1023 }
1024 } else if (idx_value & (1 << 14)) {
1025 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1026 return -EINVAL;
1027 }
1028 track->tex_dirty = true;
1029 break;
1030 case 0x4480:
1031 case 0x4484:
1032 case 0x4488:
1033 case 0x448C:
1034 case 0x4490:
1035 case 0x4494:
1036 case 0x4498:
1037 case 0x449C:
1038 case 0x44A0:
1039 case 0x44A4:
1040 case 0x44A8:
1041 case 0x44AC:
1042 case 0x44B0:
1043 case 0x44B4:
1044 case 0x44B8:
1045 case 0x44BC:
1046 /* TX_FORMAT0_[0-15] */
1047 i = (reg - 0x4480) >> 2;
1048 tmp = idx_value & 0x7FF;
1049 track->textures[i].width = tmp + 1;
1050 tmp = (idx_value >> 11) & 0x7FF;
1051 track->textures[i].height = tmp + 1;
1052 tmp = (idx_value >> 26) & 0xF;
1053 track->textures[i].num_levels = tmp;
1054 tmp = idx_value & (1 << 31);
1055 track->textures[i].use_pitch = !!tmp;
1056 tmp = (idx_value >> 22) & 0xF;
1057 track->textures[i].txdepth = tmp;
1058 track->tex_dirty = true;
1059 break;
1060 case R300_ZB_ZPASS_ADDR:
1061 r = r100_cs_packet_next_reloc(p, &reloc);
1062 if (r) {
1063 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1064 idx, reg);
1065 r100_cs_dump_packet(p, pkt);
1066 return r;
1067 }
1068 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1069 break;
1070 case 0x4e0c:
1071 /* RB3D_COLOR_CHANNEL_MASK */
1072 track->color_channel_mask = idx_value;
1073 track->cb_dirty = true;
1074 break;
1075 case 0x43a4:
1076 /* SC_HYPERZ_EN */
1077 /* r300c emits this register - we need to disable hyperz for it
1078 * without complaining */
1079 if (p->rdev->hyperz_filp != p->filp) {
1080 if (idx_value & 0x1)
1081 ib[idx] = idx_value & ~1;
1082 }
1083 break;
1084 case 0x4f1c:
1085 /* ZB_BW_CNTL */
1086 track->zb_cb_clear = !!(idx_value & (1 << 5));
1087 track->cb_dirty = true;
1088 track->zb_dirty = true;
1089 if (p->rdev->hyperz_filp != p->filp) {
1090 if (idx_value & (R300_HIZ_ENABLE |
1091 R300_RD_COMP_ENABLE |
1092 R300_WR_COMP_ENABLE |
1093 R300_FAST_FILL_ENABLE))
1094 goto fail;
1095 }
1096 break;
1097 case 0x4e04:
1098 /* RB3D_BLENDCNTL */
1099 track->blend_read_enable = !!(idx_value & (1 << 2));
1100 track->cb_dirty = true;
1101 break;
1102 case R300_RB3D_AARESOLVE_OFFSET:
1103 r = r100_cs_packet_next_reloc(p, &reloc);
1104 if (r) {
1105 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1106 idx, reg);
1107 r100_cs_dump_packet(p, pkt);
1108 return r;
1109 }
1110 track->aa.robj = reloc->robj;
1111 track->aa.offset = idx_value;
1112 track->aa_dirty = true;
1113 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1114 break;
1115 case R300_RB3D_AARESOLVE_PITCH:
1116 track->aa.pitch = idx_value & 0x3FFE;
1117 track->aa_dirty = true;
1118 break;
1119 case R300_RB3D_AARESOLVE_CTL:
1120 track->aaresolve = idx_value & 0x1;
1121 track->aa_dirty = true;
1122 break;
1123 case 0x4f30: /* ZB_MASK_OFFSET */
1124 case 0x4f34: /* ZB_ZMASK_PITCH */
1125 case 0x4f44: /* ZB_HIZ_OFFSET */
1126 case 0x4f54: /* ZB_HIZ_PITCH */
1127 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1128 goto fail;
1129 break;
1130 case 0x4028:
1131 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1132 goto fail;
1133 /* GB_Z_PEQ_CONFIG */
1134 if (p->rdev->family >= CHIP_RV350)
1135 break;
1136 goto fail;
1137 break;
1138 case 0x4be8:
1139 /* valid register only on RV530 */
1140 if (p->rdev->family == CHIP_RV530)
1141 break;
1142 /* fallthrough do not move */
1143 default:
1144 goto fail;
1145 }
1146 return 0;
1147 fail:
1148 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1149 reg, idx, idx_value);
1150 return -EINVAL;
1151 }
1152
1153 static int r300_packet3_check(struct radeon_cs_parser *p,
1154 struct radeon_cs_packet *pkt)
1155 {
1156 struct radeon_cs_reloc *reloc;
1157 struct r100_cs_track *track;
1158 volatile uint32_t *ib;
1159 unsigned idx;
1160 int r;
1161
1162 ib = p->ib->ptr;
1163 idx = pkt->idx + 1;
1164 track = (struct r100_cs_track *)p->track;
1165 switch(pkt->opcode) {
1166 case PACKET3_3D_LOAD_VBPNTR:
1167 r = r100_packet3_load_vbpntr(p, pkt, idx);
1168 if (r)
1169 return r;
1170 break;
1171 case PACKET3_INDX_BUFFER:
1172 r = r100_cs_packet_next_reloc(p, &reloc);
1173 if (r) {
1174 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1175 r100_cs_dump_packet(p, pkt);
1176 return r;
1177 }
1178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1179 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1180 if (r) {
1181 return r;
1182 }
1183 break;
1184 /* Draw packet */
1185 case PACKET3_3D_DRAW_IMMD:
1186 /* Number of dwords is vtx_size * (num_vertices - 1)
1187 * PRIM_WALK must be equal to 3 vertex data in embedded
1188 * in cmd stream */
1189 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1190 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1191 return -EINVAL;
1192 }
1193 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1194 track->immd_dwords = pkt->count - 1;
1195 r = r100_cs_track_check(p->rdev, track);
1196 if (r) {
1197 return r;
1198 }
1199 break;
1200 case PACKET3_3D_DRAW_IMMD_2:
1201 /* Number of dwords is vtx_size * (num_vertices - 1)
1202 * PRIM_WALK must be equal to 3 vertex data in embedded
1203 * in cmd stream */
1204 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1205 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1206 return -EINVAL;
1207 }
1208 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1209 track->immd_dwords = pkt->count;
1210 r = r100_cs_track_check(p->rdev, track);
1211 if (r) {
1212 return r;
1213 }
1214 break;
1215 case PACKET3_3D_DRAW_VBUF:
1216 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1217 r = r100_cs_track_check(p->rdev, track);
1218 if (r) {
1219 return r;
1220 }
1221 break;
1222 case PACKET3_3D_DRAW_VBUF_2:
1223 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1224 r = r100_cs_track_check(p->rdev, track);
1225 if (r) {
1226 return r;
1227 }
1228 break;
1229 case PACKET3_3D_DRAW_INDX:
1230 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1231 r = r100_cs_track_check(p->rdev, track);
1232 if (r) {
1233 return r;
1234 }
1235 break;
1236 case PACKET3_3D_DRAW_INDX_2:
1237 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1238 r = r100_cs_track_check(p->rdev, track);
1239 if (r) {
1240 return r;
1241 }
1242 break;
1243 case PACKET3_3D_CLEAR_HIZ:
1244 case PACKET3_3D_CLEAR_ZMASK:
1245 if (p->rdev->hyperz_filp != p->filp)
1246 return -EINVAL;
1247 break;
1248 case PACKET3_3D_CLEAR_CMASK:
1249 if (p->rdev->cmask_filp != p->filp)
1250 return -EINVAL;
1251 break;
1252 case PACKET3_NOP:
1253 break;
1254 default:
1255 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1256 return -EINVAL;
1257 }
1258 return 0;
1259 }
1260
1261 int r300_cs_parse(struct radeon_cs_parser *p)
1262 {
1263 struct radeon_cs_packet pkt;
1264 struct r100_cs_track *track;
1265 int r;
1266
1267 track = kzalloc(sizeof(*track), GFP_KERNEL);
1268 if (track == NULL)
1269 return -ENOMEM;
1270 r100_cs_track_clear(p->rdev, track);
1271 p->track = track;
1272 do {
1273 r = r100_cs_packet_parse(p, &pkt, p->idx);
1274 if (r) {
1275 return r;
1276 }
1277 p->idx += pkt.count + 2;
1278 switch (pkt.type) {
1279 case PACKET_TYPE0:
1280 r = r100_cs_parse_packet0(p, &pkt,
1281 p->rdev->config.r300.reg_safe_bm,
1282 p->rdev->config.r300.reg_safe_bm_size,
1283 &r300_packet0_check);
1284 break;
1285 case PACKET_TYPE2:
1286 break;
1287 case PACKET_TYPE3:
1288 r = r300_packet3_check(p, &pkt);
1289 break;
1290 default:
1291 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1292 return -EINVAL;
1293 }
1294 if (r) {
1295 return r;
1296 }
1297 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1298 return 0;
1299 }
1300
1301 void r300_set_reg_safe(struct radeon_device *rdev)
1302 {
1303 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1304 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1305 }
1306
1307 void r300_mc_program(struct radeon_device *rdev)
1308 {
1309 struct r100_mc_save save;
1310 int r;
1311
1312 r = r100_debugfs_mc_info_init(rdev);
1313 if (r) {
1314 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1315 }
1316
1317 /* Stops all mc clients */
1318 r100_mc_stop(rdev, &save);
1319 if (rdev->flags & RADEON_IS_AGP) {
1320 WREG32(R_00014C_MC_AGP_LOCATION,
1321 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1322 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1323 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1324 WREG32(R_00015C_AGP_BASE_2,
1325 upper_32_bits(rdev->mc.agp_base) & 0xff);
1326 } else {
1327 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1328 WREG32(R_000170_AGP_BASE, 0);
1329 WREG32(R_00015C_AGP_BASE_2, 0);
1330 }
1331 /* Wait for mc idle */
1332 if (r300_mc_wait_for_idle(rdev))
1333 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1334 /* Program MC, should be a 32bits limited address space */
1335 WREG32(R_000148_MC_FB_LOCATION,
1336 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1337 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1338 r100_mc_resume(rdev, &save);
1339 }
1340
1341 void r300_clock_startup(struct radeon_device *rdev)
1342 {
1343 u32 tmp;
1344
1345 if (radeon_dynclks != -1 && radeon_dynclks)
1346 radeon_legacy_set_clock_gating(rdev, 1);
1347 /* We need to force on some of the block */
1348 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1349 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1350 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1351 tmp |= S_00000D_FORCE_VAP(1);
1352 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1353 }
1354
1355 static int r300_startup(struct radeon_device *rdev)
1356 {
1357 int r;
1358
1359 /* set common regs */
1360 r100_set_common_regs(rdev);
1361 /* program mc */
1362 r300_mc_program(rdev);
1363 /* Resume clock */
1364 r300_clock_startup(rdev);
1365 /* Initialize GPU configuration (# pipes, ...) */
1366 r300_gpu_init(rdev);
1367 /* Initialize GART (initialize after TTM so we can allocate
1368 * memory through TTM but finalize after TTM) */
1369 if (rdev->flags & RADEON_IS_PCIE) {
1370 r = rv370_pcie_gart_enable(rdev);
1371 if (r)
1372 return r;
1373 }
1374
1375 if (rdev->family == CHIP_R300 ||
1376 rdev->family == CHIP_R350 ||
1377 rdev->family == CHIP_RV350)
1378 r100_enable_bm(rdev);
1379
1380 if (rdev->flags & RADEON_IS_PCI) {
1381 r = r100_pci_gart_enable(rdev);
1382 if (r)
1383 return r;
1384 }
1385
1386 /* allocate wb buffer */
1387 r = radeon_wb_init(rdev);
1388 if (r)
1389 return r;
1390
1391 /* Enable IRQ */
1392 r100_irq_set(rdev);
1393 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1394 /* 1M ring buffer */
1395 r = r100_cp_init(rdev, 1024 * 1024);
1396 if (r) {
1397 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1398 return r;
1399 }
1400 r = r100_ib_init(rdev);
1401 if (r) {
1402 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
1403 return r;
1404 }
1405 return 0;
1406 }
1407
1408 int r300_resume(struct radeon_device *rdev)
1409 {
1410 /* Make sur GART are not working */
1411 if (rdev->flags & RADEON_IS_PCIE)
1412 rv370_pcie_gart_disable(rdev);
1413 if (rdev->flags & RADEON_IS_PCI)
1414 r100_pci_gart_disable(rdev);
1415 /* Resume clock before doing reset */
1416 r300_clock_startup(rdev);
1417 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1418 if (radeon_asic_reset(rdev)) {
1419 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1420 RREG32(R_000E40_RBBM_STATUS),
1421 RREG32(R_0007C0_CP_STAT));
1422 }
1423 /* post */
1424 radeon_combios_asic_init(rdev->ddev);
1425 /* Resume clock after posting */
1426 r300_clock_startup(rdev);
1427 /* Initialize surface registers */
1428 radeon_surface_init(rdev);
1429 return r300_startup(rdev);
1430 }
1431
1432 int r300_suspend(struct radeon_device *rdev)
1433 {
1434 r100_cp_disable(rdev);
1435 radeon_wb_disable(rdev);
1436 r100_irq_disable(rdev);
1437 if (rdev->flags & RADEON_IS_PCIE)
1438 rv370_pcie_gart_disable(rdev);
1439 if (rdev->flags & RADEON_IS_PCI)
1440 r100_pci_gart_disable(rdev);
1441 return 0;
1442 }
1443
1444 void r300_fini(struct radeon_device *rdev)
1445 {
1446 r100_cp_fini(rdev);
1447 radeon_wb_fini(rdev);
1448 r100_ib_fini(rdev);
1449 radeon_gem_fini(rdev);
1450 if (rdev->flags & RADEON_IS_PCIE)
1451 rv370_pcie_gart_fini(rdev);
1452 if (rdev->flags & RADEON_IS_PCI)
1453 r100_pci_gart_fini(rdev);
1454 radeon_agp_fini(rdev);
1455 radeon_irq_kms_fini(rdev);
1456 radeon_fence_driver_fini(rdev);
1457 radeon_bo_fini(rdev);
1458 radeon_atombios_fini(rdev);
1459 kfree(rdev->bios);
1460 rdev->bios = NULL;
1461 }
1462
1463 int r300_init(struct radeon_device *rdev)
1464 {
1465 int r;
1466
1467 /* Disable VGA */
1468 r100_vga_render_disable(rdev);
1469 /* Initialize scratch registers */
1470 radeon_scratch_init(rdev);
1471 /* Initialize surface registers */
1472 radeon_surface_init(rdev);
1473 /* TODO: disable VGA need to use VGA request */
1474 /* restore some register to sane defaults */
1475 r100_restore_sanity(rdev);
1476 /* BIOS*/
1477 if (!radeon_get_bios(rdev)) {
1478 if (ASIC_IS_AVIVO(rdev))
1479 return -EINVAL;
1480 }
1481 if (rdev->is_atom_bios) {
1482 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1483 return -EINVAL;
1484 } else {
1485 r = radeon_combios_init(rdev);
1486 if (r)
1487 return r;
1488 }
1489 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1490 if (radeon_asic_reset(rdev)) {
1491 dev_warn(rdev->dev,
1492 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1493 RREG32(R_000E40_RBBM_STATUS),
1494 RREG32(R_0007C0_CP_STAT));
1495 }
1496 /* check if cards are posted or not */
1497 if (radeon_boot_test_post_card(rdev) == false)
1498 return -EINVAL;
1499 /* Set asic errata */
1500 r300_errata(rdev);
1501 /* Initialize clocks */
1502 radeon_get_clock_info(rdev->ddev);
1503 /* initialize AGP */
1504 if (rdev->flags & RADEON_IS_AGP) {
1505 r = radeon_agp_init(rdev);
1506 if (r) {
1507 radeon_agp_disable(rdev);
1508 }
1509 }
1510 /* initialize memory controller */
1511 r300_mc_init(rdev);
1512 /* Fence driver */
1513 r = radeon_fence_driver_init(rdev);
1514 if (r)
1515 return r;
1516 r = radeon_irq_kms_init(rdev);
1517 if (r)
1518 return r;
1519 /* Memory manager */
1520 r = radeon_bo_init(rdev);
1521 if (r)
1522 return r;
1523 if (rdev->flags & RADEON_IS_PCIE) {
1524 r = rv370_pcie_gart_init(rdev);
1525 if (r)
1526 return r;
1527 }
1528 if (rdev->flags & RADEON_IS_PCI) {
1529 r = r100_pci_gart_init(rdev);
1530 if (r)
1531 return r;
1532 }
1533 r300_set_reg_safe(rdev);
1534 rdev->accel_working = true;
1535 r = r300_startup(rdev);
1536 if (r) {
1537 /* Somethings want wront with the accel init stop accel */
1538 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1539 r100_cp_fini(rdev);
1540 radeon_wb_fini(rdev);
1541 r100_ib_fini(rdev);
1542 radeon_irq_kms_fini(rdev);
1543 if (rdev->flags & RADEON_IS_PCIE)
1544 rv370_pcie_gart_fini(rdev);
1545 if (rdev->flags & RADEON_IS_PCI)
1546 r100_pci_gart_fini(rdev);
1547 radeon_agp_fini(rdev);
1548 rdev->accel_working = false;
1549 }
1550 return 0;
1551 }
Linux kernel - Deliverables
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