2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_reg.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
37 #include "r300_reg_safe.h"
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
42 * rv370,rv380 PCIE GART
44 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
46 void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
51 /* Workaround HW bug do flush 2 times */
52 for (i
= 0; i
< 2; i
++) {
53 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
54 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
| RADEON_PCIE_TX_GART_INVALIDATE_TLB
);
55 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
56 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
61 int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
63 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
65 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
68 addr
= (lower_32_bits(addr
) >> 8) |
69 ((upper_32_bits(addr
) & 0xff) << 24) |
71 /* on x86 we want this to be CPU endian, on powerpc
72 * on powerpc without HW swappers, it'll get swapped on way
73 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
74 writel(addr
, ((void __iomem
*)ptr
) + (i
* 4));
78 int rv370_pcie_gart_init(struct radeon_device
*rdev
)
82 if (rdev
->gart
.table
.vram
.robj
) {
83 WARN(1, "RV370 PCIE GART already initialized.\n");
86 /* Initialize common gart structure */
87 r
= radeon_gart_init(rdev
);
90 r
= rv370_debugfs_pcie_gart_info_init(rdev
);
92 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
93 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
94 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
95 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
96 return radeon_gart_table_vram_alloc(rdev
);
99 int rv370_pcie_gart_enable(struct radeon_device
*rdev
)
105 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
106 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
109 r
= radeon_gart_table_vram_pin(rdev
);
112 /* discard memory request outside of configured range */
113 tmp
= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
114 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
115 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
, rdev
->mc
.gtt_location
);
116 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- RADEON_GPU_PAGE_SIZE
;
117 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
, tmp
);
118 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
, 0);
119 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
, 0);
120 table_addr
= rdev
->gart
.table_addr
;
121 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE
, table_addr
);
122 /* FIXME: setup default page */
123 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
, rdev
->mc
.vram_location
);
124 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI
, 0);
126 WREG32_PCIE(0x18, 0);
127 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
128 tmp
|= RADEON_PCIE_TX_GART_EN
;
129 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
131 rv370_pcie_gart_tlb_flush(rdev
);
132 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
133 (unsigned)(rdev
->mc
.gtt_size
>> 20), table_addr
);
134 rdev
->gart
.ready
= true;
138 void rv370_pcie_gart_disable(struct radeon_device
*rdev
)
143 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
144 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
& ~RADEON_PCIE_TX_GART_EN
);
146 if (rdev
->gart
.table
.vram
.robj
) {
147 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
148 if (likely(r
== 0)) {
149 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
150 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
151 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
156 void rv370_pcie_gart_fini(struct radeon_device
*rdev
)
158 rv370_pcie_gart_disable(rdev
);
159 radeon_gart_table_vram_free(rdev
);
160 radeon_gart_fini(rdev
);
163 void r300_fence_ring_emit(struct radeon_device
*rdev
,
164 struct radeon_fence
*fence
)
166 /* Who ever call radeon_fence_emit should call ring_lock and ask
167 * for enough space (today caller are ib schedule and buffer move) */
168 /* Write SC register so SC & US assert idle */
169 radeon_ring_write(rdev
, PACKET0(0x43E0, 0));
170 radeon_ring_write(rdev
, 0);
171 radeon_ring_write(rdev
, PACKET0(0x43E4, 0));
172 radeon_ring_write(rdev
, 0);
174 radeon_ring_write(rdev
, PACKET0(0x4E4C, 0));
175 radeon_ring_write(rdev
, (2 << 0));
176 radeon_ring_write(rdev
, PACKET0(0x4F18, 0));
177 radeon_ring_write(rdev
, (1 << 0));
178 /* Wait until IDLE & CLEAN */
179 radeon_ring_write(rdev
, PACKET0(0x1720, 0));
180 radeon_ring_write(rdev
, (1 << 17) | (1 << 16) | (1 << 9));
181 /* Emit fence sequence & fire IRQ */
182 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
183 radeon_ring_write(rdev
, fence
->seq
);
184 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
185 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
188 int r300_copy_dma(struct radeon_device
*rdev
,
192 struct radeon_fence
*fence
)
199 /* radeon pitch is /64 */
200 size
= num_pages
<< PAGE_SHIFT
;
201 num_loops
= DIV_ROUND_UP(size
, 0x1FFFFF);
202 r
= radeon_ring_lock(rdev
, num_loops
* 4 + 64);
204 DRM_ERROR("radeon: moving bo (%d).\n", r
);
207 /* Must wait for 2D idle & clean before DMA or hangs might happen */
208 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0 ));
209 radeon_ring_write(rdev
, (1 << 16));
210 for (i
= 0; i
< num_loops
; i
++) {
212 if (cur_size
> 0x1FFFFF) {
216 radeon_ring_write(rdev
, PACKET0(0x720, 2));
217 radeon_ring_write(rdev
, src_offset
);
218 radeon_ring_write(rdev
, dst_offset
);
219 radeon_ring_write(rdev
, cur_size
| (1 << 31) | (1 << 30));
220 src_offset
+= cur_size
;
221 dst_offset
+= cur_size
;
223 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
224 radeon_ring_write(rdev
, RADEON_WAIT_DMA_GUI_IDLE
);
226 r
= radeon_fence_emit(rdev
, fence
);
228 radeon_ring_unlock_commit(rdev
);
232 void r300_ring_start(struct radeon_device
*rdev
)
234 unsigned gb_tile_config
;
237 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
238 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
239 switch(rdev
->num_gb_pipes
) {
241 gb_tile_config
|= R300_PIPE_COUNT_R300
;
244 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
247 gb_tile_config
|= R300_PIPE_COUNT_R420
;
251 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
255 r
= radeon_ring_lock(rdev
, 64);
259 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
260 radeon_ring_write(rdev
,
261 RADEON_ISYNC_ANY2D_IDLE3D
|
262 RADEON_ISYNC_ANY3D_IDLE2D
|
263 RADEON_ISYNC_WAIT_IDLEGUI
|
264 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
265 radeon_ring_write(rdev
, PACKET0(R300_GB_TILE_CONFIG
, 0));
266 radeon_ring_write(rdev
, gb_tile_config
);
267 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
268 radeon_ring_write(rdev
,
269 RADEON_WAIT_2D_IDLECLEAN
|
270 RADEON_WAIT_3D_IDLECLEAN
);
271 radeon_ring_write(rdev
, PACKET0(0x170C, 0));
272 radeon_ring_write(rdev
, 1 << 31);
273 radeon_ring_write(rdev
, PACKET0(R300_GB_SELECT
, 0));
274 radeon_ring_write(rdev
, 0);
275 radeon_ring_write(rdev
, PACKET0(R300_GB_ENABLE
, 0));
276 radeon_ring_write(rdev
, 0);
277 radeon_ring_write(rdev
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
278 radeon_ring_write(rdev
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
279 radeon_ring_write(rdev
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
280 radeon_ring_write(rdev
, R300_ZC_FLUSH
| R300_ZC_FREE
);
281 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
282 radeon_ring_write(rdev
,
283 RADEON_WAIT_2D_IDLECLEAN
|
284 RADEON_WAIT_3D_IDLECLEAN
);
285 radeon_ring_write(rdev
, PACKET0(R300_GB_AA_CONFIG
, 0));
286 radeon_ring_write(rdev
, 0);
287 radeon_ring_write(rdev
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
288 radeon_ring_write(rdev
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
289 radeon_ring_write(rdev
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
290 radeon_ring_write(rdev
, R300_ZC_FLUSH
| R300_ZC_FREE
);
291 radeon_ring_write(rdev
, PACKET0(R300_GB_MSPOS0
, 0));
292 radeon_ring_write(rdev
,
293 ((6 << R300_MS_X0_SHIFT
) |
294 (6 << R300_MS_Y0_SHIFT
) |
295 (6 << R300_MS_X1_SHIFT
) |
296 (6 << R300_MS_Y1_SHIFT
) |
297 (6 << R300_MS_X2_SHIFT
) |
298 (6 << R300_MS_Y2_SHIFT
) |
299 (6 << R300_MSBD0_Y_SHIFT
) |
300 (6 << R300_MSBD0_X_SHIFT
)));
301 radeon_ring_write(rdev
, PACKET0(R300_GB_MSPOS1
, 0));
302 radeon_ring_write(rdev
,
303 ((6 << R300_MS_X3_SHIFT
) |
304 (6 << R300_MS_Y3_SHIFT
) |
305 (6 << R300_MS_X4_SHIFT
) |
306 (6 << R300_MS_Y4_SHIFT
) |
307 (6 << R300_MS_X5_SHIFT
) |
308 (6 << R300_MS_Y5_SHIFT
) |
309 (6 << R300_MSBD1_SHIFT
)));
310 radeon_ring_write(rdev
, PACKET0(R300_GA_ENHANCE
, 0));
311 radeon_ring_write(rdev
, R300_GA_DEADLOCK_CNTL
| R300_GA_FASTSYNC_CNTL
);
312 radeon_ring_write(rdev
, PACKET0(R300_GA_POLY_MODE
, 0));
313 radeon_ring_write(rdev
,
314 R300_FRONT_PTYPE_TRIANGE
| R300_BACK_PTYPE_TRIANGE
);
315 radeon_ring_write(rdev
, PACKET0(R300_GA_ROUND_MODE
, 0));
316 radeon_ring_write(rdev
,
317 R300_GEOMETRY_ROUND_NEAREST
|
318 R300_COLOR_ROUND_NEAREST
);
319 radeon_ring_unlock_commit(rdev
);
322 void r300_errata(struct radeon_device
*rdev
)
324 rdev
->pll_errata
= 0;
326 if (rdev
->family
== CHIP_R300
&&
327 (RREG32(RADEON_CONFIG_CNTL
) & RADEON_CFG_ATI_REV_ID_MASK
) == RADEON_CFG_ATI_REV_A11
) {
328 rdev
->pll_errata
|= CHIP_ERRATA_R300_CG
;
332 int r300_mc_wait_for_idle(struct radeon_device
*rdev
)
337 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
339 tmp
= RREG32(0x0150);
340 if (tmp
& (1 << 4)) {
348 void r300_gpu_init(struct radeon_device
*rdev
)
350 uint32_t gb_tile_config
, tmp
;
352 r100_hdp_reset(rdev
);
353 /* FIXME: rv380 one pipes ? */
354 if ((rdev
->family
== CHIP_R300
) || (rdev
->family
== CHIP_R350
)) {
356 rdev
->num_gb_pipes
= 2;
358 /* rv350,rv370,rv380 */
359 rdev
->num_gb_pipes
= 1;
361 rdev
->num_z_pipes
= 1;
362 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
363 switch (rdev
->num_gb_pipes
) {
365 gb_tile_config
|= R300_PIPE_COUNT_R300
;
368 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
371 gb_tile_config
|= R300_PIPE_COUNT_R420
;
375 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
378 WREG32(R300_GB_TILE_CONFIG
, gb_tile_config
);
380 if (r100_gui_wait_for_idle(rdev
)) {
381 printk(KERN_WARNING
"Failed to wait GUI idle while "
382 "programming pipes. Bad things might happen.\n");
385 tmp
= RREG32(0x170C);
386 WREG32(0x170C, tmp
| (1 << 31));
388 WREG32(R300_RB2D_DSTCACHE_MODE
,
389 R300_DC_AUTOFLUSH_ENABLE
|
390 R300_DC_DC_DISABLE_IGNORE_PE
);
392 if (r100_gui_wait_for_idle(rdev
)) {
393 printk(KERN_WARNING
"Failed to wait GUI idle while "
394 "programming pipes. Bad things might happen.\n");
396 if (r300_mc_wait_for_idle(rdev
)) {
397 printk(KERN_WARNING
"Failed to wait MC idle while "
398 "programming pipes. Bad things might happen.\n");
400 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
401 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
404 int r300_ga_reset(struct radeon_device
*rdev
)
410 reinit_cp
= rdev
->cp
.ready
;
411 rdev
->cp
.ready
= false;
412 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
413 WREG32(RADEON_CP_CSQ_MODE
, 0);
414 WREG32(RADEON_CP_CSQ_CNTL
, 0);
415 WREG32(RADEON_RBBM_SOFT_RESET
, 0x32005);
416 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
418 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
419 /* Wait to prevent race in RBBM_STATUS */
421 tmp
= RREG32(RADEON_RBBM_STATUS
);
422 if (tmp
& ((1 << 20) | (1 << 26))) {
423 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp
);
424 /* GA still busy soft reset it */
425 WREG32(0x429C, 0x200);
426 WREG32(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
431 /* Wait to prevent race in RBBM_STATUS */
433 tmp
= RREG32(RADEON_RBBM_STATUS
);
434 if (!(tmp
& ((1 << 20) | (1 << 26)))) {
438 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
439 tmp
= RREG32(RADEON_RBBM_STATUS
);
440 if (!(tmp
& ((1 << 20) | (1 << 26)))) {
441 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
444 return r100_cp_init(rdev
, rdev
->cp
.ring_size
);
450 tmp
= RREG32(RADEON_RBBM_STATUS
);
451 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp
);
455 int r300_gpu_reset(struct radeon_device
*rdev
)
459 /* reset order likely matter */
460 status
= RREG32(RADEON_RBBM_STATUS
);
462 r100_hdp_reset(rdev
);
464 if (status
& ((1 << 17) | (1 << 18) | (1 << 27))) {
465 r100_rb2d_reset(rdev
);
468 if (status
& ((1 << 20) | (1 << 26))) {
472 status
= RREG32(RADEON_RBBM_STATUS
);
473 if (status
& (1 << 16)) {
476 /* Check if GPU is idle */
477 status
= RREG32(RADEON_RBBM_STATUS
);
478 if (status
& (1 << 31)) {
479 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status
);
482 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status
);
488 * r300,r350,rv350,rv380 VRAM info
490 void r300_vram_info(struct radeon_device
*rdev
)
494 /* DDR for all card after R300 & IGP */
495 rdev
->mc
.vram_is_ddr
= true;
496 tmp
= RREG32(RADEON_MEM_CNTL
);
497 if (tmp
& R300_MEM_NUM_CHANNELS_MASK
) {
498 rdev
->mc
.vram_width
= 128;
500 rdev
->mc
.vram_width
= 64;
503 r100_vram_init_sizes(rdev
);
506 void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
508 uint32_t link_width_cntl
, mask
;
510 if (rdev
->flags
& RADEON_IS_IGP
)
513 if (!(rdev
->flags
& RADEON_IS_PCIE
))
516 /* FIXME wait for idle */
520 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
523 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
526 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
529 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
532 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
535 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
539 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
543 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
545 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
546 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
549 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
550 RADEON_PCIE_LC_RECONFIG_NOW
|
551 RADEON_PCIE_LC_RECONFIG_LATER
|
552 RADEON_PCIE_LC_SHORT_RECONFIG_EN
);
553 link_width_cntl
|= mask
;
554 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
555 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
556 RADEON_PCIE_LC_RECONFIG_NOW
));
558 /* wait for lane set to complete */
559 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
560 while (link_width_cntl
== 0xffffffff)
561 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
565 #if defined(CONFIG_DEBUG_FS)
566 static int rv370_debugfs_pcie_gart_info(struct seq_file
*m
, void *data
)
568 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
569 struct drm_device
*dev
= node
->minor
->dev
;
570 struct radeon_device
*rdev
= dev
->dev_private
;
573 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
574 seq_printf(m
, "PCIE_TX_GART_CNTL 0x%08x\n", tmp
);
575 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_BASE
);
576 seq_printf(m
, "PCIE_TX_GART_BASE 0x%08x\n", tmp
);
577 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
);
578 seq_printf(m
, "PCIE_TX_GART_START_LO 0x%08x\n", tmp
);
579 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
);
580 seq_printf(m
, "PCIE_TX_GART_START_HI 0x%08x\n", tmp
);
581 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
);
582 seq_printf(m
, "PCIE_TX_GART_END_LO 0x%08x\n", tmp
);
583 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
);
584 seq_printf(m
, "PCIE_TX_GART_END_HI 0x%08x\n", tmp
);
585 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR
);
586 seq_printf(m
, "PCIE_TX_GART_ERROR 0x%08x\n", tmp
);
590 static struct drm_info_list rv370_pcie_gart_info_list
[] = {
591 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info
, 0, NULL
},
595 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
597 #if defined(CONFIG_DEBUG_FS)
598 return radeon_debugfs_add_files(rdev
, rv370_pcie_gart_info_list
, 1);
604 static int r300_packet0_check(struct radeon_cs_parser
*p
,
605 struct radeon_cs_packet
*pkt
,
606 unsigned idx
, unsigned reg
)
608 struct radeon_cs_reloc
*reloc
;
609 struct r100_cs_track
*track
;
610 volatile uint32_t *ib
;
611 uint32_t tmp
, tile_flags
= 0;
617 track
= (struct r100_cs_track
*)p
->track
;
618 idx_value
= radeon_get_ib_value(p
, idx
);
621 case AVIVO_D1MODE_VLINE_START_END
:
622 case RADEON_CRTC_GUI_TRIG_VLINE
:
623 r
= r100_cs_packet_parse_vline(p
);
625 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
627 r100_cs_dump_packet(p
, pkt
);
631 case RADEON_DST_PITCH_OFFSET
:
632 case RADEON_SRC_PITCH_OFFSET
:
633 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
637 case R300_RB3D_COLOROFFSET0
:
638 case R300_RB3D_COLOROFFSET1
:
639 case R300_RB3D_COLOROFFSET2
:
640 case R300_RB3D_COLOROFFSET3
:
641 i
= (reg
- R300_RB3D_COLOROFFSET0
) >> 2;
642 r
= r100_cs_packet_next_reloc(p
, &reloc
);
644 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
646 r100_cs_dump_packet(p
, pkt
);
649 track
->cb
[i
].robj
= reloc
->robj
;
650 track
->cb
[i
].offset
= idx_value
;
651 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
653 case R300_ZB_DEPTHOFFSET
:
654 r
= r100_cs_packet_next_reloc(p
, &reloc
);
656 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
658 r100_cs_dump_packet(p
, pkt
);
661 track
->zb
.robj
= reloc
->robj
;
662 track
->zb
.offset
= idx_value
;
663 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
665 case R300_TX_OFFSET_0
:
666 case R300_TX_OFFSET_0
+4:
667 case R300_TX_OFFSET_0
+8:
668 case R300_TX_OFFSET_0
+12:
669 case R300_TX_OFFSET_0
+16:
670 case R300_TX_OFFSET_0
+20:
671 case R300_TX_OFFSET_0
+24:
672 case R300_TX_OFFSET_0
+28:
673 case R300_TX_OFFSET_0
+32:
674 case R300_TX_OFFSET_0
+36:
675 case R300_TX_OFFSET_0
+40:
676 case R300_TX_OFFSET_0
+44:
677 case R300_TX_OFFSET_0
+48:
678 case R300_TX_OFFSET_0
+52:
679 case R300_TX_OFFSET_0
+56:
680 case R300_TX_OFFSET_0
+60:
681 i
= (reg
- R300_TX_OFFSET_0
) >> 2;
682 r
= r100_cs_packet_next_reloc(p
, &reloc
);
684 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
686 r100_cs_dump_packet(p
, pkt
);
689 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
690 track
->textures
[i
].robj
= reloc
->robj
;
692 /* Tracked registers */
695 track
->vap_vf_cntl
= idx_value
;
699 track
->vtx_size
= idx_value
& 0x7F;
702 /* VAP_VF_MAX_VTX_INDX */
703 track
->max_indx
= idx_value
& 0x00FFFFFFUL
;
707 track
->maxy
= ((idx_value
>> 13) & 0x1FFF) + 1;
708 if (p
->rdev
->family
< CHIP_RV515
) {
714 track
->num_cb
= ((idx_value
>> 5) & 0x3) + 1;
720 /* RB3D_COLORPITCH0 */
721 /* RB3D_COLORPITCH1 */
722 /* RB3D_COLORPITCH2 */
723 /* RB3D_COLORPITCH3 */
724 r
= r100_cs_packet_next_reloc(p
, &reloc
);
726 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
728 r100_cs_dump_packet(p
, pkt
);
732 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
733 tile_flags
|= R300_COLOR_TILE_ENABLE
;
734 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
735 tile_flags
|= R300_COLOR_MICROTILE_ENABLE
;
737 tmp
= idx_value
& ~(0x7 << 16);
741 i
= (reg
- 0x4E38) >> 2;
742 track
->cb
[i
].pitch
= idx_value
& 0x3FFE;
743 switch (((idx_value
>> 21) & 0xF)) {
747 track
->cb
[i
].cpp
= 1;
753 track
->cb
[i
].cpp
= 2;
756 track
->cb
[i
].cpp
= 4;
759 track
->cb
[i
].cpp
= 8;
762 track
->cb
[i
].cpp
= 16;
765 DRM_ERROR("Invalid color buffer format (%d) !\n",
766 ((idx_value
>> 21) & 0xF));
773 track
->z_enabled
= true;
775 track
->z_enabled
= false;
780 switch ((idx_value
& 0xF)) {
789 DRM_ERROR("Invalid z buffer format (%d) !\n",
796 r
= r100_cs_packet_next_reloc(p
, &reloc
);
798 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
800 r100_cs_dump_packet(p
, pkt
);
804 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
805 tile_flags
|= R300_DEPTHMACROTILE_ENABLE
;
806 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
807 tile_flags
|= R300_DEPTHMICROTILE_TILED
;;
809 tmp
= idx_value
& ~(0x7 << 16);
813 track
->zb
.pitch
= idx_value
& 0x3FFC;
816 for (i
= 0; i
< 16; i
++) {
819 enabled
= !!(idx_value
& (1 << i
));
820 track
->textures
[i
].enabled
= enabled
;
839 /* TX_FORMAT1_[0-15] */
840 i
= (reg
- 0x44C0) >> 2;
841 tmp
= (idx_value
>> 25) & 0x3;
842 track
->textures
[i
].tex_coord_type
= tmp
;
843 switch ((idx_value
& 0x1F)) {
844 case R300_TX_FORMAT_X8
:
845 case R300_TX_FORMAT_Y4X4
:
846 case R300_TX_FORMAT_Z3Y3X2
:
847 track
->textures
[i
].cpp
= 1;
849 case R300_TX_FORMAT_X16
:
850 case R300_TX_FORMAT_Y8X8
:
851 case R300_TX_FORMAT_Z5Y6X5
:
852 case R300_TX_FORMAT_Z6Y5X5
:
853 case R300_TX_FORMAT_W4Z4Y4X4
:
854 case R300_TX_FORMAT_W1Z5Y5X5
:
855 case R300_TX_FORMAT_DXT1
:
856 case R300_TX_FORMAT_D3DMFT_CxV8U8
:
857 case R300_TX_FORMAT_B8G8_B8G8
:
858 case R300_TX_FORMAT_G8R8_G8B8
:
859 track
->textures
[i
].cpp
= 2;
861 case R300_TX_FORMAT_Y16X16
:
862 case R300_TX_FORMAT_Z11Y11X10
:
863 case R300_TX_FORMAT_Z10Y11X11
:
864 case R300_TX_FORMAT_W8Z8Y8X8
:
865 case R300_TX_FORMAT_W2Z10Y10X10
:
867 case R300_TX_FORMAT_FL_I32
:
869 case R300_TX_FORMAT_DXT3
:
870 case R300_TX_FORMAT_DXT5
:
871 track
->textures
[i
].cpp
= 4;
873 case R300_TX_FORMAT_W16Z16Y16X16
:
874 case R300_TX_FORMAT_FL_R16G16B16A16
:
875 case R300_TX_FORMAT_FL_I32A32
:
876 track
->textures
[i
].cpp
= 8;
878 case R300_TX_FORMAT_FL_R32G32B32A32
:
879 track
->textures
[i
].cpp
= 16;
882 DRM_ERROR("Invalid texture format %u\n",
904 /* TX_FILTER0_[0-15] */
905 i
= (reg
- 0x4400) >> 2;
906 tmp
= idx_value
& 0x7;
907 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
908 track
->textures
[i
].roundup_w
= false;
910 tmp
= (idx_value
>> 3) & 0x7;
911 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
912 track
->textures
[i
].roundup_h
= false;
931 /* TX_FORMAT2_[0-15] */
932 i
= (reg
- 0x4500) >> 2;
933 tmp
= idx_value
& 0x3FFF;
934 track
->textures
[i
].pitch
= tmp
+ 1;
935 if (p
->rdev
->family
>= CHIP_RV515
) {
936 tmp
= ((idx_value
>> 15) & 1) << 11;
937 track
->textures
[i
].width_11
= tmp
;
938 tmp
= ((idx_value
>> 16) & 1) << 11;
939 track
->textures
[i
].height_11
= tmp
;
958 /* TX_FORMAT0_[0-15] */
959 i
= (reg
- 0x4480) >> 2;
960 tmp
= idx_value
& 0x7FF;
961 track
->textures
[i
].width
= tmp
+ 1;
962 tmp
= (idx_value
>> 11) & 0x7FF;
963 track
->textures
[i
].height
= tmp
+ 1;
964 tmp
= (idx_value
>> 26) & 0xF;
965 track
->textures
[i
].num_levels
= tmp
;
966 tmp
= idx_value
& (1 << 31);
967 track
->textures
[i
].use_pitch
= !!tmp
;
968 tmp
= (idx_value
>> 22) & 0xF;
969 track
->textures
[i
].txdepth
= tmp
;
971 case R300_ZB_ZPASS_ADDR
:
972 r
= r100_cs_packet_next_reloc(p
, &reloc
);
974 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
976 r100_cs_dump_packet(p
, pkt
);
979 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
982 /* valid register only on RV530 */
983 if (p
->rdev
->family
== CHIP_RV530
)
985 /* fallthrough do not move */
987 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
994 static int r300_packet3_check(struct radeon_cs_parser
*p
,
995 struct radeon_cs_packet
*pkt
)
997 struct radeon_cs_reloc
*reloc
;
998 struct r100_cs_track
*track
;
999 volatile uint32_t *ib
;
1005 track
= (struct r100_cs_track
*)p
->track
;
1006 switch(pkt
->opcode
) {
1007 case PACKET3_3D_LOAD_VBPNTR
:
1008 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1012 case PACKET3_INDX_BUFFER
:
1013 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1015 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1016 r100_cs_dump_packet(p
, pkt
);
1019 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+ 1) + ((u32
)reloc
->lobj
.gpu_offset
);
1020 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1026 case PACKET3_3D_DRAW_IMMD
:
1027 /* Number of dwords is vtx_size * (num_vertices - 1)
1028 * PRIM_WALK must be equal to 3 vertex data in embedded
1030 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1031 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1034 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1035 track
->immd_dwords
= pkt
->count
- 1;
1036 r
= r100_cs_track_check(p
->rdev
, track
);
1041 case PACKET3_3D_DRAW_IMMD_2
:
1042 /* Number of dwords is vtx_size * (num_vertices - 1)
1043 * PRIM_WALK must be equal to 3 vertex data in embedded
1045 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1046 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1049 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1050 track
->immd_dwords
= pkt
->count
;
1051 r
= r100_cs_track_check(p
->rdev
, track
);
1056 case PACKET3_3D_DRAW_VBUF
:
1057 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1058 r
= r100_cs_track_check(p
->rdev
, track
);
1063 case PACKET3_3D_DRAW_VBUF_2
:
1064 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1065 r
= r100_cs_track_check(p
->rdev
, track
);
1070 case PACKET3_3D_DRAW_INDX
:
1071 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1072 r
= r100_cs_track_check(p
->rdev
, track
);
1077 case PACKET3_3D_DRAW_INDX_2
:
1078 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1079 r
= r100_cs_track_check(p
->rdev
, track
);
1087 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1093 int r300_cs_parse(struct radeon_cs_parser
*p
)
1095 struct radeon_cs_packet pkt
;
1096 struct r100_cs_track
*track
;
1099 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1100 r100_cs_track_clear(p
->rdev
, track
);
1103 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1107 p
->idx
+= pkt
.count
+ 2;
1110 r
= r100_cs_parse_packet0(p
, &pkt
,
1111 p
->rdev
->config
.r300
.reg_safe_bm
,
1112 p
->rdev
->config
.r300
.reg_safe_bm_size
,
1113 &r300_packet0_check
);
1118 r
= r300_packet3_check(p
, &pkt
);
1121 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
1127 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1131 void r300_set_reg_safe(struct radeon_device
*rdev
)
1133 rdev
->config
.r300
.reg_safe_bm
= r300_reg_safe_bm
;
1134 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(r300_reg_safe_bm
);
1137 void r300_mc_program(struct radeon_device
*rdev
)
1139 struct r100_mc_save save
;
1142 r
= r100_debugfs_mc_info_init(rdev
);
1144 dev_err(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
1147 /* Stops all mc clients */
1148 r100_mc_stop(rdev
, &save
);
1149 if (rdev
->flags
& RADEON_IS_AGP
) {
1150 WREG32(R_00014C_MC_AGP_LOCATION
,
1151 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
1152 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
1153 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
1154 WREG32(R_00015C_AGP_BASE_2
,
1155 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
1157 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
1158 WREG32(R_000170_AGP_BASE
, 0);
1159 WREG32(R_00015C_AGP_BASE_2
, 0);
1161 /* Wait for mc idle */
1162 if (r300_mc_wait_for_idle(rdev
))
1163 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1164 /* Program MC, should be a 32bits limited address space */
1165 WREG32(R_000148_MC_FB_LOCATION
,
1166 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
1167 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
1168 r100_mc_resume(rdev
, &save
);
1171 void r300_clock_startup(struct radeon_device
*rdev
)
1175 if (radeon_dynclks
!= -1 && radeon_dynclks
)
1176 radeon_legacy_set_clock_gating(rdev
, 1);
1177 /* We need to force on some of the block */
1178 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
1179 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1180 if ((rdev
->family
== CHIP_RV350
) || (rdev
->family
== CHIP_RV380
))
1181 tmp
|= S_00000D_FORCE_VAP(1);
1182 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
1185 static int r300_startup(struct radeon_device
*rdev
)
1189 r300_mc_program(rdev
);
1191 r300_clock_startup(rdev
);
1192 /* Initialize GPU configuration (# pipes, ...) */
1193 r300_gpu_init(rdev
);
1194 /* Initialize GART (initialize after TTM so we can allocate
1195 * memory through TTM but finalize after TTM) */
1196 if (rdev
->flags
& RADEON_IS_PCIE
) {
1197 r
= rv370_pcie_gart_enable(rdev
);
1202 if (rdev
->family
== CHIP_R300
||
1203 rdev
->family
== CHIP_R350
||
1204 rdev
->family
== CHIP_RV350
)
1205 r100_enable_bm(rdev
);
1207 if (rdev
->flags
& RADEON_IS_PCI
) {
1208 r
= r100_pci_gart_enable(rdev
);
1214 /* 1M ring buffer */
1215 r
= r100_cp_init(rdev
, 1024 * 1024);
1217 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
1220 r
= r100_wb_init(rdev
);
1222 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
1223 r
= r100_ib_init(rdev
);
1225 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
1231 int r300_resume(struct radeon_device
*rdev
)
1233 /* Make sur GART are not working */
1234 if (rdev
->flags
& RADEON_IS_PCIE
)
1235 rv370_pcie_gart_disable(rdev
);
1236 if (rdev
->flags
& RADEON_IS_PCI
)
1237 r100_pci_gart_disable(rdev
);
1238 /* Resume clock before doing reset */
1239 r300_clock_startup(rdev
);
1240 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1241 if (radeon_gpu_reset(rdev
)) {
1242 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1243 RREG32(R_000E40_RBBM_STATUS
),
1244 RREG32(R_0007C0_CP_STAT
));
1247 radeon_combios_asic_init(rdev
->ddev
);
1248 /* Resume clock after posting */
1249 r300_clock_startup(rdev
);
1250 return r300_startup(rdev
);
1253 int r300_suspend(struct radeon_device
*rdev
)
1255 r100_cp_disable(rdev
);
1256 r100_wb_disable(rdev
);
1257 r100_irq_disable(rdev
);
1258 if (rdev
->flags
& RADEON_IS_PCIE
)
1259 rv370_pcie_gart_disable(rdev
);
1260 if (rdev
->flags
& RADEON_IS_PCI
)
1261 r100_pci_gart_disable(rdev
);
1265 void r300_fini(struct radeon_device
*rdev
)
1271 radeon_gem_fini(rdev
);
1272 if (rdev
->flags
& RADEON_IS_PCIE
)
1273 rv370_pcie_gart_fini(rdev
);
1274 if (rdev
->flags
& RADEON_IS_PCI
)
1275 r100_pci_gart_fini(rdev
);
1276 radeon_irq_kms_fini(rdev
);
1277 radeon_fence_driver_fini(rdev
);
1278 radeon_bo_fini(rdev
);
1279 radeon_atombios_fini(rdev
);
1284 int r300_init(struct radeon_device
*rdev
)
1289 r100_vga_render_disable(rdev
);
1290 /* Initialize scratch registers */
1291 radeon_scratch_init(rdev
);
1292 /* Initialize surface registers */
1293 radeon_surface_init(rdev
);
1294 /* TODO: disable VGA need to use VGA request */
1296 if (!radeon_get_bios(rdev
)) {
1297 if (ASIC_IS_AVIVO(rdev
))
1300 if (rdev
->is_atom_bios
) {
1301 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
1304 r
= radeon_combios_init(rdev
);
1308 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1309 if (radeon_gpu_reset(rdev
)) {
1311 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1312 RREG32(R_000E40_RBBM_STATUS
),
1313 RREG32(R_0007C0_CP_STAT
));
1315 /* check if cards are posted or not */
1316 if (radeon_boot_test_post_card(rdev
) == false)
1318 /* Set asic errata */
1320 /* Initialize clocks */
1321 radeon_get_clock_info(rdev
->ddev
);
1322 /* Get vram informations */
1323 r300_vram_info(rdev
);
1324 /* Initialize memory controller (also test AGP) */
1325 r
= r420_mc_init(rdev
);
1329 r
= radeon_fence_driver_init(rdev
);
1332 r
= radeon_irq_kms_init(rdev
);
1335 /* Memory manager */
1336 r
= radeon_bo_init(rdev
);
1339 if (rdev
->flags
& RADEON_IS_PCIE
) {
1340 r
= rv370_pcie_gart_init(rdev
);
1344 if (rdev
->flags
& RADEON_IS_PCI
) {
1345 r
= r100_pci_gart_init(rdev
);
1349 r300_set_reg_safe(rdev
);
1350 rdev
->accel_working
= true;
1351 r
= r300_startup(rdev
);
1353 /* Somethings want wront with the accel init stop accel */
1354 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
1359 if (rdev
->flags
& RADEON_IS_PCIE
)
1360 rv370_pcie_gart_fini(rdev
);
1361 if (rdev
->flags
& RADEON_IS_PCI
)
1362 r100_pci_gart_fini(rdev
);
1363 radeon_irq_kms_fini(rdev
);
1364 rdev
->accel_working
= false;