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drm/radeon/kms: implement reading active PCIE lanes on R600+
[deliverable/linux.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
35 #include "r300d.h"
36 #include "rv350d.h"
37 #include "r300_reg_safe.h"
38
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40 *
41 * GPU Errata:
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
47 */
48
49 /*
50 * rv370,rv380 PCIE GART
51 */
52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
53
54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
55 {
56 uint32_t tmp;
57 int i;
58
59 /* Workaround HW bug do flush 2 times */
60 for (i = 0; i < 2; i++) {
61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
65 }
66 mb();
67 }
68
69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
70 {
71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
72
73 if (i < 0 || i > rdev->gart.num_gpu_pages) {
74 return -EINVAL;
75 }
76 addr = (lower_32_bits(addr) >> 8) |
77 ((upper_32_bits(addr) & 0xff) << 24) |
78 0xc;
79 /* on x86 we want this to be CPU endian, on powerpc
80 * on powerpc without HW swappers, it'll get swapped on way
81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 writel(addr, ((void __iomem *)ptr) + (i * 4));
83 return 0;
84 }
85
86 int rv370_pcie_gart_init(struct radeon_device *rdev)
87 {
88 int r;
89
90 if (rdev->gart.table.vram.robj) {
91 WARN(1, "RV370 PCIE GART already initialized.\n");
92 return 0;
93 }
94 /* Initialize common gart structure */
95 r = radeon_gart_init(rdev);
96 if (r)
97 return r;
98 r = rv370_debugfs_pcie_gart_info_init(rdev);
99 if (r)
100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 return radeon_gart_table_vram_alloc(rdev);
105 }
106
107 int rv370_pcie_gart_enable(struct radeon_device *rdev)
108 {
109 uint32_t table_addr;
110 uint32_t tmp;
111 int r;
112
113 if (rdev->gart.table.vram.robj == NULL) {
114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
115 return -EINVAL;
116 }
117 r = radeon_gart_table_vram_pin(rdev);
118 if (r)
119 return r;
120 radeon_gart_restore(rdev);
121 /* discard memory request outside of configured range */
122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129 table_addr = rdev->gart.table_addr;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131 /* FIXME: setup default page */
132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134 /* Clear error */
135 WREG32_PCIE(0x18, 0);
136 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
137 tmp |= RADEON_PCIE_TX_GART_EN;
138 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
140 rv370_pcie_gart_tlb_flush(rdev);
141 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
142 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
143 rdev->gart.ready = true;
144 return 0;
145 }
146
147 void rv370_pcie_gart_disable(struct radeon_device *rdev)
148 {
149 u32 tmp;
150 int r;
151
152 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
153 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
154 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
155 if (rdev->gart.table.vram.robj) {
156 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
157 if (likely(r == 0)) {
158 radeon_bo_kunmap(rdev->gart.table.vram.robj);
159 radeon_bo_unpin(rdev->gart.table.vram.robj);
160 radeon_bo_unreserve(rdev->gart.table.vram.robj);
161 }
162 }
163 }
164
165 void rv370_pcie_gart_fini(struct radeon_device *rdev)
166 {
167 rv370_pcie_gart_disable(rdev);
168 radeon_gart_table_vram_free(rdev);
169 radeon_gart_fini(rdev);
170 }
171
172 void r300_fence_ring_emit(struct radeon_device *rdev,
173 struct radeon_fence *fence)
174 {
175 /* Who ever call radeon_fence_emit should call ring_lock and ask
176 * for enough space (today caller are ib schedule and buffer move) */
177 /* Write SC register so SC & US assert idle */
178 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
179 radeon_ring_write(rdev, 0);
180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
181 radeon_ring_write(rdev, 0);
182 /* Flush 3D cache */
183 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
184 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_ZC_FLUSH);
187 /* Wait until IDLE & CLEAN */
188 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
189 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
190 RADEON_WAIT_2D_IDLECLEAN |
191 RADEON_WAIT_DMA_GUI_IDLE));
192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
194 RADEON_HDP_READ_BUFFER_INVALIDATE);
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
197 /* Emit fence sequence & fire IRQ */
198 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
199 radeon_ring_write(rdev, fence->seq);
200 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
201 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
202 }
203
204 void r300_ring_start(struct radeon_device *rdev)
205 {
206 unsigned gb_tile_config;
207 int r;
208
209 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
210 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
211 switch(rdev->num_gb_pipes) {
212 case 2:
213 gb_tile_config |= R300_PIPE_COUNT_R300;
214 break;
215 case 3:
216 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
217 break;
218 case 4:
219 gb_tile_config |= R300_PIPE_COUNT_R420;
220 break;
221 case 1:
222 default:
223 gb_tile_config |= R300_PIPE_COUNT_RV350;
224 break;
225 }
226
227 r = radeon_ring_lock(rdev, 64);
228 if (r) {
229 return;
230 }
231 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
232 radeon_ring_write(rdev,
233 RADEON_ISYNC_ANY2D_IDLE3D |
234 RADEON_ISYNC_ANY3D_IDLE2D |
235 RADEON_ISYNC_WAIT_IDLEGUI |
236 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
237 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
238 radeon_ring_write(rdev, gb_tile_config);
239 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
240 radeon_ring_write(rdev,
241 RADEON_WAIT_2D_IDLECLEAN |
242 RADEON_WAIT_3D_IDLECLEAN);
243 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
244 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
245 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
246 radeon_ring_write(rdev, 0);
247 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
250 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
253 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
254 radeon_ring_write(rdev,
255 RADEON_WAIT_2D_IDLECLEAN |
256 RADEON_WAIT_3D_IDLECLEAN);
257 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
258 radeon_ring_write(rdev, 0);
259 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
260 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
264 radeon_ring_write(rdev,
265 ((6 << R300_MS_X0_SHIFT) |
266 (6 << R300_MS_Y0_SHIFT) |
267 (6 << R300_MS_X1_SHIFT) |
268 (6 << R300_MS_Y1_SHIFT) |
269 (6 << R300_MS_X2_SHIFT) |
270 (6 << R300_MS_Y2_SHIFT) |
271 (6 << R300_MSBD0_Y_SHIFT) |
272 (6 << R300_MSBD0_X_SHIFT)));
273 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
274 radeon_ring_write(rdev,
275 ((6 << R300_MS_X3_SHIFT) |
276 (6 << R300_MS_Y3_SHIFT) |
277 (6 << R300_MS_X4_SHIFT) |
278 (6 << R300_MS_Y4_SHIFT) |
279 (6 << R300_MS_X5_SHIFT) |
280 (6 << R300_MS_Y5_SHIFT) |
281 (6 << R300_MSBD1_SHIFT)));
282 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
283 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
284 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
285 radeon_ring_write(rdev,
286 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
287 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
288 radeon_ring_write(rdev,
289 R300_GEOMETRY_ROUND_NEAREST |
290 R300_COLOR_ROUND_NEAREST);
291 radeon_ring_unlock_commit(rdev);
292 }
293
294 void r300_errata(struct radeon_device *rdev)
295 {
296 rdev->pll_errata = 0;
297
298 if (rdev->family == CHIP_R300 &&
299 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
300 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
301 }
302 }
303
304 int r300_mc_wait_for_idle(struct radeon_device *rdev)
305 {
306 unsigned i;
307 uint32_t tmp;
308
309 for (i = 0; i < rdev->usec_timeout; i++) {
310 /* read MC_STATUS */
311 tmp = RREG32(RADEON_MC_STATUS);
312 if (tmp & R300_MC_IDLE) {
313 return 0;
314 }
315 DRM_UDELAY(1);
316 }
317 return -1;
318 }
319
320 void r300_gpu_init(struct radeon_device *rdev)
321 {
322 uint32_t gb_tile_config, tmp;
323
324 r100_hdp_reset(rdev);
325 /* FIXME: rv380 one pipes ? */
326 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
327 /* r300,r350 */
328 rdev->num_gb_pipes = 2;
329 } else {
330 /* rv350,rv370,rv380 */
331 rdev->num_gb_pipes = 1;
332 }
333 rdev->num_z_pipes = 1;
334 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
335 switch (rdev->num_gb_pipes) {
336 case 2:
337 gb_tile_config |= R300_PIPE_COUNT_R300;
338 break;
339 case 3:
340 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
341 break;
342 case 4:
343 gb_tile_config |= R300_PIPE_COUNT_R420;
344 break;
345 default:
346 case 1:
347 gb_tile_config |= R300_PIPE_COUNT_RV350;
348 break;
349 }
350 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
351
352 if (r100_gui_wait_for_idle(rdev)) {
353 printk(KERN_WARNING "Failed to wait GUI idle while "
354 "programming pipes. Bad things might happen.\n");
355 }
356
357 tmp = RREG32(R300_DST_PIPE_CONFIG);
358 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
359
360 WREG32(R300_RB2D_DSTCACHE_MODE,
361 R300_DC_AUTOFLUSH_ENABLE |
362 R300_DC_DC_DISABLE_IGNORE_PE);
363
364 if (r100_gui_wait_for_idle(rdev)) {
365 printk(KERN_WARNING "Failed to wait GUI idle while "
366 "programming pipes. Bad things might happen.\n");
367 }
368 if (r300_mc_wait_for_idle(rdev)) {
369 printk(KERN_WARNING "Failed to wait MC idle while "
370 "programming pipes. Bad things might happen.\n");
371 }
372 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
373 rdev->num_gb_pipes, rdev->num_z_pipes);
374 }
375
376 int r300_ga_reset(struct radeon_device *rdev)
377 {
378 uint32_t tmp;
379 bool reinit_cp;
380 int i;
381
382 reinit_cp = rdev->cp.ready;
383 rdev->cp.ready = false;
384 for (i = 0; i < rdev->usec_timeout; i++) {
385 WREG32(RADEON_CP_CSQ_MODE, 0);
386 WREG32(RADEON_CP_CSQ_CNTL, 0);
387 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
388 (void)RREG32(RADEON_RBBM_SOFT_RESET);
389 udelay(200);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0);
391 /* Wait to prevent race in RBBM_STATUS */
392 mdelay(1);
393 tmp = RREG32(RADEON_RBBM_STATUS);
394 if (tmp & ((1 << 20) | (1 << 26))) {
395 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
396 /* GA still busy soft reset it */
397 WREG32(0x429C, 0x200);
398 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
399 WREG32(R300_RE_SCISSORS_TL, 0);
400 WREG32(R300_RE_SCISSORS_BR, 0);
401 WREG32(0x24AC, 0);
402 }
403 /* Wait to prevent race in RBBM_STATUS */
404 mdelay(1);
405 tmp = RREG32(RADEON_RBBM_STATUS);
406 if (!(tmp & ((1 << 20) | (1 << 26)))) {
407 break;
408 }
409 }
410 for (i = 0; i < rdev->usec_timeout; i++) {
411 tmp = RREG32(RADEON_RBBM_STATUS);
412 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
414 tmp);
415 if (reinit_cp) {
416 return r100_cp_init(rdev, rdev->cp.ring_size);
417 }
418 return 0;
419 }
420 DRM_UDELAY(1);
421 }
422 tmp = RREG32(RADEON_RBBM_STATUS);
423 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
424 return -1;
425 }
426
427 int r300_gpu_reset(struct radeon_device *rdev)
428 {
429 uint32_t status;
430
431 /* reset order likely matter */
432 status = RREG32(RADEON_RBBM_STATUS);
433 /* reset HDP */
434 r100_hdp_reset(rdev);
435 /* reset rb2d */
436 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
437 r100_rb2d_reset(rdev);
438 }
439 /* reset GA */
440 if (status & ((1 << 20) | (1 << 26))) {
441 r300_ga_reset(rdev);
442 }
443 /* reset CP */
444 status = RREG32(RADEON_RBBM_STATUS);
445 if (status & (1 << 16)) {
446 r100_cp_reset(rdev);
447 }
448 /* Check if GPU is idle */
449 status = RREG32(RADEON_RBBM_STATUS);
450 if (status & RADEON_RBBM_ACTIVE) {
451 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
452 return -1;
453 }
454 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
455 return 0;
456 }
457
458
459 /*
460 * r300,r350,rv350,rv380 VRAM info
461 */
462 void r300_mc_init(struct radeon_device *rdev)
463 {
464 u64 base;
465 u32 tmp;
466
467 /* DDR for all card after R300 & IGP */
468 rdev->mc.vram_is_ddr = true;
469 tmp = RREG32(RADEON_MEM_CNTL);
470 tmp &= R300_MEM_NUM_CHANNELS_MASK;
471 switch (tmp) {
472 case 0: rdev->mc.vram_width = 64; break;
473 case 1: rdev->mc.vram_width = 128; break;
474 case 2: rdev->mc.vram_width = 256; break;
475 default: rdev->mc.vram_width = 128; break;
476 }
477 r100_vram_init_sizes(rdev);
478 base = rdev->mc.aper_base;
479 if (rdev->flags & RADEON_IS_IGP)
480 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
481 radeon_vram_location(rdev, &rdev->mc, base);
482 if (!(rdev->flags & RADEON_IS_AGP))
483 radeon_gtt_location(rdev, &rdev->mc);
484 }
485
486 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
487 {
488 uint32_t link_width_cntl, mask;
489
490 if (rdev->flags & RADEON_IS_IGP)
491 return;
492
493 if (!(rdev->flags & RADEON_IS_PCIE))
494 return;
495
496 /* FIXME wait for idle */
497
498 switch (lanes) {
499 case 0:
500 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
501 break;
502 case 1:
503 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
504 break;
505 case 2:
506 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
507 break;
508 case 4:
509 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
510 break;
511 case 8:
512 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
513 break;
514 case 12:
515 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
516 break;
517 case 16:
518 default:
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
520 break;
521 }
522
523 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
524
525 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
526 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
527 return;
528
529 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
530 RADEON_PCIE_LC_RECONFIG_NOW |
531 RADEON_PCIE_LC_RECONFIG_LATER |
532 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
533 link_width_cntl |= mask;
534 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
535 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
536 RADEON_PCIE_LC_RECONFIG_NOW));
537
538 /* wait for lane set to complete */
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
540 while (link_width_cntl == 0xffffffff)
541 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
542
543 }
544
545 int rv370_get_pcie_lanes(struct radeon_device *rdev)
546 {
547 u32 link_width_cntl;
548
549 if (rdev->flags & RADEON_IS_IGP)
550 return 0;
551
552 if (!(rdev->flags & RADEON_IS_PCIE))
553 return 0;
554
555 /* FIXME wait for idle */
556
557 if (rdev->family < CHIP_R600)
558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
559 else
560 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
561
562 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
563 case RADEON_PCIE_LC_LINK_WIDTH_X0:
564 return 0;
565 case RADEON_PCIE_LC_LINK_WIDTH_X1:
566 return 1;
567 case RADEON_PCIE_LC_LINK_WIDTH_X2:
568 return 2;
569 case RADEON_PCIE_LC_LINK_WIDTH_X4:
570 return 4;
571 case RADEON_PCIE_LC_LINK_WIDTH_X8:
572 return 8;
573 case RADEON_PCIE_LC_LINK_WIDTH_X16:
574 default:
575 return 16;
576 }
577 }
578
579 #if defined(CONFIG_DEBUG_FS)
580 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
581 {
582 struct drm_info_node *node = (struct drm_info_node *) m->private;
583 struct drm_device *dev = node->minor->dev;
584 struct radeon_device *rdev = dev->dev_private;
585 uint32_t tmp;
586
587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
588 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
590 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
592 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
594 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
596 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
598 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
600 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
601 return 0;
602 }
603
604 static struct drm_info_list rv370_pcie_gart_info_list[] = {
605 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
606 };
607 #endif
608
609 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
610 {
611 #if defined(CONFIG_DEBUG_FS)
612 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
613 #else
614 return 0;
615 #endif
616 }
617
618 static int r300_packet0_check(struct radeon_cs_parser *p,
619 struct radeon_cs_packet *pkt,
620 unsigned idx, unsigned reg)
621 {
622 struct radeon_cs_reloc *reloc;
623 struct r100_cs_track *track;
624 volatile uint32_t *ib;
625 uint32_t tmp, tile_flags = 0;
626 unsigned i;
627 int r;
628 u32 idx_value;
629
630 ib = p->ib->ptr;
631 track = (struct r100_cs_track *)p->track;
632 idx_value = radeon_get_ib_value(p, idx);
633
634 switch(reg) {
635 case AVIVO_D1MODE_VLINE_START_END:
636 case RADEON_CRTC_GUI_TRIG_VLINE:
637 r = r100_cs_packet_parse_vline(p);
638 if (r) {
639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
640 idx, reg);
641 r100_cs_dump_packet(p, pkt);
642 return r;
643 }
644 break;
645 case RADEON_DST_PITCH_OFFSET:
646 case RADEON_SRC_PITCH_OFFSET:
647 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
648 if (r)
649 return r;
650 break;
651 case R300_RB3D_COLOROFFSET0:
652 case R300_RB3D_COLOROFFSET1:
653 case R300_RB3D_COLOROFFSET2:
654 case R300_RB3D_COLOROFFSET3:
655 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
656 r = r100_cs_packet_next_reloc(p, &reloc);
657 if (r) {
658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
659 idx, reg);
660 r100_cs_dump_packet(p, pkt);
661 return r;
662 }
663 track->cb[i].robj = reloc->robj;
664 track->cb[i].offset = idx_value;
665 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
666 break;
667 case R300_ZB_DEPTHOFFSET:
668 r = r100_cs_packet_next_reloc(p, &reloc);
669 if (r) {
670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
671 idx, reg);
672 r100_cs_dump_packet(p, pkt);
673 return r;
674 }
675 track->zb.robj = reloc->robj;
676 track->zb.offset = idx_value;
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
678 break;
679 case R300_TX_OFFSET_0:
680 case R300_TX_OFFSET_0+4:
681 case R300_TX_OFFSET_0+8:
682 case R300_TX_OFFSET_0+12:
683 case R300_TX_OFFSET_0+16:
684 case R300_TX_OFFSET_0+20:
685 case R300_TX_OFFSET_0+24:
686 case R300_TX_OFFSET_0+28:
687 case R300_TX_OFFSET_0+32:
688 case R300_TX_OFFSET_0+36:
689 case R300_TX_OFFSET_0+40:
690 case R300_TX_OFFSET_0+44:
691 case R300_TX_OFFSET_0+48:
692 case R300_TX_OFFSET_0+52:
693 case R300_TX_OFFSET_0+56:
694 case R300_TX_OFFSET_0+60:
695 i = (reg - R300_TX_OFFSET_0) >> 2;
696 r = r100_cs_packet_next_reloc(p, &reloc);
697 if (r) {
698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
699 idx, reg);
700 r100_cs_dump_packet(p, pkt);
701 return r;
702 }
703
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
705 tile_flags |= R300_TXO_MACRO_TILE;
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
707 tile_flags |= R300_TXO_MICRO_TILE;
708
709 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
710 tmp |= tile_flags;
711 ib[idx] = tmp;
712 track->textures[i].robj = reloc->robj;
713 break;
714 /* Tracked registers */
715 case 0x2084:
716 /* VAP_VF_CNTL */
717 track->vap_vf_cntl = idx_value;
718 break;
719 case 0x20B4:
720 /* VAP_VTX_SIZE */
721 track->vtx_size = idx_value & 0x7F;
722 break;
723 case 0x2134:
724 /* VAP_VF_MAX_VTX_INDX */
725 track->max_indx = idx_value & 0x00FFFFFFUL;
726 break;
727 case 0x43E4:
728 /* SC_SCISSOR1 */
729 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
730 if (p->rdev->family < CHIP_RV515) {
731 track->maxy -= 1440;
732 }
733 break;
734 case 0x4E00:
735 /* RB3D_CCTL */
736 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
737 break;
738 case 0x4E38:
739 case 0x4E3C:
740 case 0x4E40:
741 case 0x4E44:
742 /* RB3D_COLORPITCH0 */
743 /* RB3D_COLORPITCH1 */
744 /* RB3D_COLORPITCH2 */
745 /* RB3D_COLORPITCH3 */
746 r = r100_cs_packet_next_reloc(p, &reloc);
747 if (r) {
748 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
749 idx, reg);
750 r100_cs_dump_packet(p, pkt);
751 return r;
752 }
753
754 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
755 tile_flags |= R300_COLOR_TILE_ENABLE;
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
757 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
758
759 tmp = idx_value & ~(0x7 << 16);
760 tmp |= tile_flags;
761 ib[idx] = tmp;
762
763 i = (reg - 0x4E38) >> 2;
764 track->cb[i].pitch = idx_value & 0x3FFE;
765 switch (((idx_value >> 21) & 0xF)) {
766 case 9:
767 case 11:
768 case 12:
769 track->cb[i].cpp = 1;
770 break;
771 case 3:
772 case 4:
773 case 13:
774 case 15:
775 track->cb[i].cpp = 2;
776 break;
777 case 6:
778 track->cb[i].cpp = 4;
779 break;
780 case 10:
781 track->cb[i].cpp = 8;
782 break;
783 case 7:
784 track->cb[i].cpp = 16;
785 break;
786 default:
787 DRM_ERROR("Invalid color buffer format (%d) !\n",
788 ((idx_value >> 21) & 0xF));
789 return -EINVAL;
790 }
791 break;
792 case 0x4F00:
793 /* ZB_CNTL */
794 if (idx_value & 2) {
795 track->z_enabled = true;
796 } else {
797 track->z_enabled = false;
798 }
799 break;
800 case 0x4F10:
801 /* ZB_FORMAT */
802 switch ((idx_value & 0xF)) {
803 case 0:
804 case 1:
805 track->zb.cpp = 2;
806 break;
807 case 2:
808 track->zb.cpp = 4;
809 break;
810 default:
811 DRM_ERROR("Invalid z buffer format (%d) !\n",
812 (idx_value & 0xF));
813 return -EINVAL;
814 }
815 break;
816 case 0x4F24:
817 /* ZB_DEPTHPITCH */
818 r = r100_cs_packet_next_reloc(p, &reloc);
819 if (r) {
820 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
821 idx, reg);
822 r100_cs_dump_packet(p, pkt);
823 return r;
824 }
825
826 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
827 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
828 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
829 tile_flags |= R300_DEPTHMICROTILE_TILED;;
830
831 tmp = idx_value & ~(0x7 << 16);
832 tmp |= tile_flags;
833 ib[idx] = tmp;
834
835 track->zb.pitch = idx_value & 0x3FFC;
836 break;
837 case 0x4104:
838 for (i = 0; i < 16; i++) {
839 bool enabled;
840
841 enabled = !!(idx_value & (1 << i));
842 track->textures[i].enabled = enabled;
843 }
844 break;
845 case 0x44C0:
846 case 0x44C4:
847 case 0x44C8:
848 case 0x44CC:
849 case 0x44D0:
850 case 0x44D4:
851 case 0x44D8:
852 case 0x44DC:
853 case 0x44E0:
854 case 0x44E4:
855 case 0x44E8:
856 case 0x44EC:
857 case 0x44F0:
858 case 0x44F4:
859 case 0x44F8:
860 case 0x44FC:
861 /* TX_FORMAT1_[0-15] */
862 i = (reg - 0x44C0) >> 2;
863 tmp = (idx_value >> 25) & 0x3;
864 track->textures[i].tex_coord_type = tmp;
865 switch ((idx_value & 0x1F)) {
866 case R300_TX_FORMAT_X8:
867 case R300_TX_FORMAT_Y4X4:
868 case R300_TX_FORMAT_Z3Y3X2:
869 track->textures[i].cpp = 1;
870 break;
871 case R300_TX_FORMAT_X16:
872 case R300_TX_FORMAT_Y8X8:
873 case R300_TX_FORMAT_Z5Y6X5:
874 case R300_TX_FORMAT_Z6Y5X5:
875 case R300_TX_FORMAT_W4Z4Y4X4:
876 case R300_TX_FORMAT_W1Z5Y5X5:
877 case R300_TX_FORMAT_D3DMFT_CxV8U8:
878 case R300_TX_FORMAT_B8G8_B8G8:
879 case R300_TX_FORMAT_G8R8_G8B8:
880 track->textures[i].cpp = 2;
881 break;
882 case R300_TX_FORMAT_Y16X16:
883 case R300_TX_FORMAT_Z11Y11X10:
884 case R300_TX_FORMAT_Z10Y11X11:
885 case R300_TX_FORMAT_W8Z8Y8X8:
886 case R300_TX_FORMAT_W2Z10Y10X10:
887 case 0x17:
888 case R300_TX_FORMAT_FL_I32:
889 case 0x1e:
890 track->textures[i].cpp = 4;
891 break;
892 case R300_TX_FORMAT_W16Z16Y16X16:
893 case R300_TX_FORMAT_FL_R16G16B16A16:
894 case R300_TX_FORMAT_FL_I32A32:
895 track->textures[i].cpp = 8;
896 break;
897 case R300_TX_FORMAT_FL_R32G32B32A32:
898 track->textures[i].cpp = 16;
899 break;
900 case R300_TX_FORMAT_DXT1:
901 track->textures[i].cpp = 1;
902 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
903 break;
904 case R300_TX_FORMAT_ATI2N:
905 if (p->rdev->family < CHIP_R420) {
906 DRM_ERROR("Invalid texture format %u\n",
907 (idx_value & 0x1F));
908 return -EINVAL;
909 }
910 /* The same rules apply as for DXT3/5. */
911 /* Pass through. */
912 case R300_TX_FORMAT_DXT3:
913 case R300_TX_FORMAT_DXT5:
914 track->textures[i].cpp = 1;
915 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
916 break;
917 default:
918 DRM_ERROR("Invalid texture format %u\n",
919 (idx_value & 0x1F));
920 return -EINVAL;
921 break;
922 }
923 break;
924 case 0x4400:
925 case 0x4404:
926 case 0x4408:
927 case 0x440C:
928 case 0x4410:
929 case 0x4414:
930 case 0x4418:
931 case 0x441C:
932 case 0x4420:
933 case 0x4424:
934 case 0x4428:
935 case 0x442C:
936 case 0x4430:
937 case 0x4434:
938 case 0x4438:
939 case 0x443C:
940 /* TX_FILTER0_[0-15] */
941 i = (reg - 0x4400) >> 2;
942 tmp = idx_value & 0x7;
943 if (tmp == 2 || tmp == 4 || tmp == 6) {
944 track->textures[i].roundup_w = false;
945 }
946 tmp = (idx_value >> 3) & 0x7;
947 if (tmp == 2 || tmp == 4 || tmp == 6) {
948 track->textures[i].roundup_h = false;
949 }
950 break;
951 case 0x4500:
952 case 0x4504:
953 case 0x4508:
954 case 0x450C:
955 case 0x4510:
956 case 0x4514:
957 case 0x4518:
958 case 0x451C:
959 case 0x4520:
960 case 0x4524:
961 case 0x4528:
962 case 0x452C:
963 case 0x4530:
964 case 0x4534:
965 case 0x4538:
966 case 0x453C:
967 /* TX_FORMAT2_[0-15] */
968 i = (reg - 0x4500) >> 2;
969 tmp = idx_value & 0x3FFF;
970 track->textures[i].pitch = tmp + 1;
971 if (p->rdev->family >= CHIP_RV515) {
972 tmp = ((idx_value >> 15) & 1) << 11;
973 track->textures[i].width_11 = tmp;
974 tmp = ((idx_value >> 16) & 1) << 11;
975 track->textures[i].height_11 = tmp;
976
977 /* ATI1N */
978 if (idx_value & (1 << 14)) {
979 /* The same rules apply as for DXT1. */
980 track->textures[i].compress_format =
981 R100_TRACK_COMP_DXT1;
982 }
983 } else if (idx_value & (1 << 14)) {
984 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
985 return -EINVAL;
986 }
987 break;
988 case 0x4480:
989 case 0x4484:
990 case 0x4488:
991 case 0x448C:
992 case 0x4490:
993 case 0x4494:
994 case 0x4498:
995 case 0x449C:
996 case 0x44A0:
997 case 0x44A4:
998 case 0x44A8:
999 case 0x44AC:
1000 case 0x44B0:
1001 case 0x44B4:
1002 case 0x44B8:
1003 case 0x44BC:
1004 /* TX_FORMAT0_[0-15] */
1005 i = (reg - 0x4480) >> 2;
1006 tmp = idx_value & 0x7FF;
1007 track->textures[i].width = tmp + 1;
1008 tmp = (idx_value >> 11) & 0x7FF;
1009 track->textures[i].height = tmp + 1;
1010 tmp = (idx_value >> 26) & 0xF;
1011 track->textures[i].num_levels = tmp;
1012 tmp = idx_value & (1 << 31);
1013 track->textures[i].use_pitch = !!tmp;
1014 tmp = (idx_value >> 22) & 0xF;
1015 track->textures[i].txdepth = tmp;
1016 break;
1017 case R300_ZB_ZPASS_ADDR:
1018 r = r100_cs_packet_next_reloc(p, &reloc);
1019 if (r) {
1020 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1021 idx, reg);
1022 r100_cs_dump_packet(p, pkt);
1023 return r;
1024 }
1025 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1026 break;
1027 case 0x4e0c:
1028 /* RB3D_COLOR_CHANNEL_MASK */
1029 track->color_channel_mask = idx_value;
1030 break;
1031 case 0x4d1c:
1032 /* ZB_BW_CNTL */
1033 track->fastfill = !!(idx_value & (1 << 2));
1034 break;
1035 case 0x4e04:
1036 /* RB3D_BLENDCNTL */
1037 track->blend_read_enable = !!(idx_value & (1 << 2));
1038 break;
1039 case 0x4be8:
1040 /* valid register only on RV530 */
1041 if (p->rdev->family == CHIP_RV530)
1042 break;
1043 /* fallthrough do not move */
1044 default:
1045 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1046 reg, idx);
1047 return -EINVAL;
1048 }
1049 return 0;
1050 }
1051
1052 static int r300_packet3_check(struct radeon_cs_parser *p,
1053 struct radeon_cs_packet *pkt)
1054 {
1055 struct radeon_cs_reloc *reloc;
1056 struct r100_cs_track *track;
1057 volatile uint32_t *ib;
1058 unsigned idx;
1059 int r;
1060
1061 ib = p->ib->ptr;
1062 idx = pkt->idx + 1;
1063 track = (struct r100_cs_track *)p->track;
1064 switch(pkt->opcode) {
1065 case PACKET3_3D_LOAD_VBPNTR:
1066 r = r100_packet3_load_vbpntr(p, pkt, idx);
1067 if (r)
1068 return r;
1069 break;
1070 case PACKET3_INDX_BUFFER:
1071 r = r100_cs_packet_next_reloc(p, &reloc);
1072 if (r) {
1073 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1074 r100_cs_dump_packet(p, pkt);
1075 return r;
1076 }
1077 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1078 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1079 if (r) {
1080 return r;
1081 }
1082 break;
1083 /* Draw packet */
1084 case PACKET3_3D_DRAW_IMMD:
1085 /* Number of dwords is vtx_size * (num_vertices - 1)
1086 * PRIM_WALK must be equal to 3 vertex data in embedded
1087 * in cmd stream */
1088 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1089 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1090 return -EINVAL;
1091 }
1092 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1093 track->immd_dwords = pkt->count - 1;
1094 r = r100_cs_track_check(p->rdev, track);
1095 if (r) {
1096 return r;
1097 }
1098 break;
1099 case PACKET3_3D_DRAW_IMMD_2:
1100 /* Number of dwords is vtx_size * (num_vertices - 1)
1101 * PRIM_WALK must be equal to 3 vertex data in embedded
1102 * in cmd stream */
1103 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1104 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1105 return -EINVAL;
1106 }
1107 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1108 track->immd_dwords = pkt->count;
1109 r = r100_cs_track_check(p->rdev, track);
1110 if (r) {
1111 return r;
1112 }
1113 break;
1114 case PACKET3_3D_DRAW_VBUF:
1115 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1116 r = r100_cs_track_check(p->rdev, track);
1117 if (r) {
1118 return r;
1119 }
1120 break;
1121 case PACKET3_3D_DRAW_VBUF_2:
1122 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1123 r = r100_cs_track_check(p->rdev, track);
1124 if (r) {
1125 return r;
1126 }
1127 break;
1128 case PACKET3_3D_DRAW_INDX:
1129 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1130 r = r100_cs_track_check(p->rdev, track);
1131 if (r) {
1132 return r;
1133 }
1134 break;
1135 case PACKET3_3D_DRAW_INDX_2:
1136 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1137 r = r100_cs_track_check(p->rdev, track);
1138 if (r) {
1139 return r;
1140 }
1141 break;
1142 case PACKET3_NOP:
1143 break;
1144 default:
1145 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1146 return -EINVAL;
1147 }
1148 return 0;
1149 }
1150
1151 int r300_cs_parse(struct radeon_cs_parser *p)
1152 {
1153 struct radeon_cs_packet pkt;
1154 struct r100_cs_track *track;
1155 int r;
1156
1157 track = kzalloc(sizeof(*track), GFP_KERNEL);
1158 r100_cs_track_clear(p->rdev, track);
1159 p->track = track;
1160 do {
1161 r = r100_cs_packet_parse(p, &pkt, p->idx);
1162 if (r) {
1163 return r;
1164 }
1165 p->idx += pkt.count + 2;
1166 switch (pkt.type) {
1167 case PACKET_TYPE0:
1168 r = r100_cs_parse_packet0(p, &pkt,
1169 p->rdev->config.r300.reg_safe_bm,
1170 p->rdev->config.r300.reg_safe_bm_size,
1171 &r300_packet0_check);
1172 break;
1173 case PACKET_TYPE2:
1174 break;
1175 case PACKET_TYPE3:
1176 r = r300_packet3_check(p, &pkt);
1177 break;
1178 default:
1179 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1180 return -EINVAL;
1181 }
1182 if (r) {
1183 return r;
1184 }
1185 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1186 return 0;
1187 }
1188
1189 void r300_set_reg_safe(struct radeon_device *rdev)
1190 {
1191 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1192 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1193 }
1194
1195 void r300_mc_program(struct radeon_device *rdev)
1196 {
1197 struct r100_mc_save save;
1198 int r;
1199
1200 r = r100_debugfs_mc_info_init(rdev);
1201 if (r) {
1202 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1203 }
1204
1205 /* Stops all mc clients */
1206 r100_mc_stop(rdev, &save);
1207 if (rdev->flags & RADEON_IS_AGP) {
1208 WREG32(R_00014C_MC_AGP_LOCATION,
1209 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1210 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1211 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1212 WREG32(R_00015C_AGP_BASE_2,
1213 upper_32_bits(rdev->mc.agp_base) & 0xff);
1214 } else {
1215 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1216 WREG32(R_000170_AGP_BASE, 0);
1217 WREG32(R_00015C_AGP_BASE_2, 0);
1218 }
1219 /* Wait for mc idle */
1220 if (r300_mc_wait_for_idle(rdev))
1221 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1222 /* Program MC, should be a 32bits limited address space */
1223 WREG32(R_000148_MC_FB_LOCATION,
1224 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1225 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1226 r100_mc_resume(rdev, &save);
1227 }
1228
1229 void r300_clock_startup(struct radeon_device *rdev)
1230 {
1231 u32 tmp;
1232
1233 if (radeon_dynclks != -1 && radeon_dynclks)
1234 radeon_legacy_set_clock_gating(rdev, 1);
1235 /* We need to force on some of the block */
1236 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1237 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1238 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1239 tmp |= S_00000D_FORCE_VAP(1);
1240 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1241 }
1242
1243 static int r300_startup(struct radeon_device *rdev)
1244 {
1245 int r;
1246
1247 /* set common regs */
1248 r100_set_common_regs(rdev);
1249 /* program mc */
1250 r300_mc_program(rdev);
1251 /* Resume clock */
1252 r300_clock_startup(rdev);
1253 /* Initialize GPU configuration (# pipes, ...) */
1254 r300_gpu_init(rdev);
1255 /* Initialize GART (initialize after TTM so we can allocate
1256 * memory through TTM but finalize after TTM) */
1257 if (rdev->flags & RADEON_IS_PCIE) {
1258 r = rv370_pcie_gart_enable(rdev);
1259 if (r)
1260 return r;
1261 }
1262
1263 if (rdev->family == CHIP_R300 ||
1264 rdev->family == CHIP_R350 ||
1265 rdev->family == CHIP_RV350)
1266 r100_enable_bm(rdev);
1267
1268 if (rdev->flags & RADEON_IS_PCI) {
1269 r = r100_pci_gart_enable(rdev);
1270 if (r)
1271 return r;
1272 }
1273 /* Enable IRQ */
1274 r100_irq_set(rdev);
1275 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1276 /* 1M ring buffer */
1277 r = r100_cp_init(rdev, 1024 * 1024);
1278 if (r) {
1279 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1280 return r;
1281 }
1282 r = r100_wb_init(rdev);
1283 if (r)
1284 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1285 r = r100_ib_init(rdev);
1286 if (r) {
1287 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1288 return r;
1289 }
1290 return 0;
1291 }
1292
1293 int r300_resume(struct radeon_device *rdev)
1294 {
1295 /* Make sur GART are not working */
1296 if (rdev->flags & RADEON_IS_PCIE)
1297 rv370_pcie_gart_disable(rdev);
1298 if (rdev->flags & RADEON_IS_PCI)
1299 r100_pci_gart_disable(rdev);
1300 /* Resume clock before doing reset */
1301 r300_clock_startup(rdev);
1302 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1303 if (radeon_gpu_reset(rdev)) {
1304 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1305 RREG32(R_000E40_RBBM_STATUS),
1306 RREG32(R_0007C0_CP_STAT));
1307 }
1308 /* post */
1309 radeon_combios_asic_init(rdev->ddev);
1310 /* Resume clock after posting */
1311 r300_clock_startup(rdev);
1312 /* Initialize surface registers */
1313 radeon_surface_init(rdev);
1314 return r300_startup(rdev);
1315 }
1316
1317 int r300_suspend(struct radeon_device *rdev)
1318 {
1319 r100_cp_disable(rdev);
1320 r100_wb_disable(rdev);
1321 r100_irq_disable(rdev);
1322 if (rdev->flags & RADEON_IS_PCIE)
1323 rv370_pcie_gart_disable(rdev);
1324 if (rdev->flags & RADEON_IS_PCI)
1325 r100_pci_gart_disable(rdev);
1326 return 0;
1327 }
1328
1329 void r300_fini(struct radeon_device *rdev)
1330 {
1331 r100_cp_fini(rdev);
1332 r100_wb_fini(rdev);
1333 r100_ib_fini(rdev);
1334 radeon_gem_fini(rdev);
1335 if (rdev->flags & RADEON_IS_PCIE)
1336 rv370_pcie_gart_fini(rdev);
1337 if (rdev->flags & RADEON_IS_PCI)
1338 r100_pci_gart_fini(rdev);
1339 radeon_agp_fini(rdev);
1340 radeon_irq_kms_fini(rdev);
1341 radeon_fence_driver_fini(rdev);
1342 radeon_bo_fini(rdev);
1343 radeon_atombios_fini(rdev);
1344 kfree(rdev->bios);
1345 rdev->bios = NULL;
1346 }
1347
1348 int r300_init(struct radeon_device *rdev)
1349 {
1350 int r;
1351
1352 /* Disable VGA */
1353 r100_vga_render_disable(rdev);
1354 /* Initialize scratch registers */
1355 radeon_scratch_init(rdev);
1356 /* Initialize surface registers */
1357 radeon_surface_init(rdev);
1358 /* TODO: disable VGA need to use VGA request */
1359 /* BIOS*/
1360 if (!radeon_get_bios(rdev)) {
1361 if (ASIC_IS_AVIVO(rdev))
1362 return -EINVAL;
1363 }
1364 if (rdev->is_atom_bios) {
1365 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1366 return -EINVAL;
1367 } else {
1368 r = radeon_combios_init(rdev);
1369 if (r)
1370 return r;
1371 }
1372 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1373 if (radeon_gpu_reset(rdev)) {
1374 dev_warn(rdev->dev,
1375 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1376 RREG32(R_000E40_RBBM_STATUS),
1377 RREG32(R_0007C0_CP_STAT));
1378 }
1379 /* check if cards are posted or not */
1380 if (radeon_boot_test_post_card(rdev) == false)
1381 return -EINVAL;
1382 /* Set asic errata */
1383 r300_errata(rdev);
1384 /* Initialize clocks */
1385 radeon_get_clock_info(rdev->ddev);
1386 /* Initialize power management */
1387 radeon_pm_init(rdev);
1388 /* initialize AGP */
1389 if (rdev->flags & RADEON_IS_AGP) {
1390 r = radeon_agp_init(rdev);
1391 if (r) {
1392 radeon_agp_disable(rdev);
1393 }
1394 }
1395 /* initialize memory controller */
1396 r300_mc_init(rdev);
1397 /* Fence driver */
1398 r = radeon_fence_driver_init(rdev);
1399 if (r)
1400 return r;
1401 r = radeon_irq_kms_init(rdev);
1402 if (r)
1403 return r;
1404 /* Memory manager */
1405 r = radeon_bo_init(rdev);
1406 if (r)
1407 return r;
1408 if (rdev->flags & RADEON_IS_PCIE) {
1409 r = rv370_pcie_gart_init(rdev);
1410 if (r)
1411 return r;
1412 }
1413 if (rdev->flags & RADEON_IS_PCI) {
1414 r = r100_pci_gart_init(rdev);
1415 if (r)
1416 return r;
1417 }
1418 r300_set_reg_safe(rdev);
1419 rdev->accel_working = true;
1420 r = r300_startup(rdev);
1421 if (r) {
1422 /* Somethings want wront with the accel init stop accel */
1423 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1424 r100_cp_fini(rdev);
1425 r100_wb_fini(rdev);
1426 r100_ib_fini(rdev);
1427 radeon_irq_kms_fini(rdev);
1428 if (rdev->flags & RADEON_IS_PCIE)
1429 rv370_pcie_gart_fini(rdev);
1430 if (rdev->flags & RADEON_IS_PCI)
1431 r100_pci_gart_fini(rdev);
1432 radeon_agp_fini(rdev);
1433 rdev->accel_working = false;
1434 }
1435 return 0;
1436 }
Linux kernel - Deliverables
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