drm/radeon/kms/dp: disable training pattern on the sink at the end of link training
[deliverable/linux.git] / drivers / gpu / drm / radeon / r300d.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __R300D_H__
29 #define __R300D_H__
30
31 #define CP_PACKET0 0x00000000
32 #define PACKET0_BASE_INDEX_SHIFT 0
33 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
34 #define PACKET0_COUNT_SHIFT 16
35 #define PACKET0_COUNT_MASK (0x3fff << 16)
36 #define CP_PACKET1 0x40000000
37 #define CP_PACKET2 0x80000000
38 #define PACKET2_PAD_SHIFT 0
39 #define PACKET2_PAD_MASK (0x3fffffff << 0)
40 #define CP_PACKET3 0xC0000000
41 #define PACKET3_IT_OPCODE_SHIFT 8
42 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
43 #define PACKET3_COUNT_SHIFT 16
44 #define PACKET3_COUNT_MASK (0x3fff << 16)
45 /* PACKET3 op code */
46 #define PACKET3_NOP 0x10
47 #define PACKET3_3D_DRAW_VBUF 0x28
48 #define PACKET3_3D_DRAW_IMMD 0x29
49 #define PACKET3_3D_DRAW_INDX 0x2A
50 #define PACKET3_3D_LOAD_VBPNTR 0x2F
51 #define PACKET3_INDX_BUFFER 0x33
52 #define PACKET3_3D_DRAW_VBUF_2 0x34
53 #define PACKET3_3D_DRAW_IMMD_2 0x35
54 #define PACKET3_3D_DRAW_INDX_2 0x36
55 #define PACKET3_BITBLT_MULTI 0x9B
56
57 #define PACKET0(reg, n) (CP_PACKET0 | \
58 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
59 REG_SET(PACKET0_COUNT, (n)))
60 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
61 #define PACKET3(op, n) (CP_PACKET3 | \
62 REG_SET(PACKET3_IT_OPCODE, (op)) | \
63 REG_SET(PACKET3_COUNT, (n)))
64
65 #define PACKET_TYPE0 0
66 #define PACKET_TYPE1 1
67 #define PACKET_TYPE2 2
68 #define PACKET_TYPE3 3
69
70 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
71 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
72 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
73 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
74 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
75
76 /* Registers */
77 #define R_000148_MC_FB_LOCATION 0x000148
78 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
79 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
80 #define C_000148_MC_FB_START 0xFFFF0000
81 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
82 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
83 #define C_000148_MC_FB_TOP 0x0000FFFF
84 #define R_00014C_MC_AGP_LOCATION 0x00014C
85 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
86 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
87 #define C_00014C_MC_AGP_START 0xFFFF0000
88 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
89 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
90 #define C_00014C_MC_AGP_TOP 0x0000FFFF
91 #define R_00015C_AGP_BASE_2 0x00015C
92 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
93 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
94 #define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
95 #define R_000170_AGP_BASE 0x000170
96 #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
97 #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
98 #define C_000170_AGP_BASE_ADDR 0x00000000
99 #define R_0007C0_CP_STAT 0x0007C0
100 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
101 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
102 #define C_0007C0_MRU_BUSY 0xFFFFFFFE
103 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
104 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
105 #define C_0007C0_MWU_BUSY 0xFFFFFFFD
106 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
107 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
108 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
109 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
110 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
111 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
112 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
113 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
114 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
115 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
116 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
117 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
118 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
119 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
120 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
121 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
122 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
123 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
124 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
125 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
126 #define C_0007C0_CSI_BUSY 0xFFFFDFFF
127 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
128 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
129 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
130 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
131 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
132 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
133 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
134 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
135 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
136 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
137 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
138 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
139 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
140 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
141 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
142 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
143 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
144 #define C_0007C0_CP_BUSY 0x7FFFFFFF
145 #define R_000E40_RBBM_STATUS 0x000E40
146 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
147 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
148 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
149 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
150 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
151 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
152 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
153 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
154 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
155 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
156 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
157 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
158 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
159 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
160 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
161 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
162 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
163 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
164 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
165 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
166 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
167 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
168 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
169 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
170 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
171 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
172 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
173 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
174 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
175 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
176 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
177 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
178 #define C_000E40_E2_BUSY 0xFFFDFFFF
179 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
180 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
181 #define C_000E40_RB2D_BUSY 0xFFFBFFFF
182 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
183 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
184 #define C_000E40_RB3D_BUSY 0xFFF7FFFF
185 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
186 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
187 #define C_000E40_VAP_BUSY 0xFFEFFFFF
188 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
189 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
190 #define C_000E40_RE_BUSY 0xFFDFFFFF
191 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
192 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
193 #define C_000E40_TAM_BUSY 0xFFBFFFFF
194 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
195 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
196 #define C_000E40_TDM_BUSY 0xFF7FFFFF
197 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
198 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
199 #define C_000E40_PB_BUSY 0xFEFFFFFF
200 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
201 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
202 #define C_000E40_TIM_BUSY 0xFDFFFFFF
203 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
204 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
205 #define C_000E40_GA_BUSY 0xFBFFFFFF
206 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
207 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
208 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF
209 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
210 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
211 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
212
213
214 #define R_00000D_SCLK_CNTL 0x00000D
215 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
216 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
217 #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
218 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
219 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
220 #define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
221 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
222 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
223 #define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
224 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
225 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
226 #define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
227 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
228 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
229 #define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
230 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
231 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
232 #define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
233 #define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
234 #define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
235 #define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
236 #define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
237 #define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
238 #define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
239 #define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
240 #define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
241 #define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
242 #define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
243 #define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
244 #define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
245 #define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
246 #define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
247 #define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
248 #define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
249 #define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
250 #define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
251 #define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
252 #define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
253 #define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
254 #define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
255 #define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
256 #define C_00000D_FORCE_DISP2 0xFFFF7FFF
257 #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
258 #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
259 #define C_00000D_FORCE_CP 0xFFFEFFFF
260 #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
261 #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
262 #define C_00000D_FORCE_HDP 0xFFFDFFFF
263 #define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
264 #define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
265 #define C_00000D_FORCE_DISP1 0xFFFBFFFF
266 #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
267 #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
268 #define C_00000D_FORCE_TOP 0xFFF7FFFF
269 #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
270 #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
271 #define C_00000D_FORCE_E2 0xFFEFFFFF
272 #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
273 #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
274 #define C_00000D_FORCE_SE 0xFFDFFFFF
275 #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
276 #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
277 #define C_00000D_FORCE_IDCT 0xFFBFFFFF
278 #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
279 #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
280 #define C_00000D_FORCE_VIP 0xFF7FFFFF
281 #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
282 #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
283 #define C_00000D_FORCE_RE 0xFEFFFFFF
284 #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
285 #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
286 #define C_00000D_FORCE_PB 0xFDFFFFFF
287 #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
288 #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
289 #define C_00000D_FORCE_TAM 0xFBFFFFFF
290 #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
291 #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
292 #define C_00000D_FORCE_TDM 0xF7FFFFFF
293 #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
294 #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
295 #define C_00000D_FORCE_RB 0xEFFFFFFF
296 #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
297 #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
298 #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
299 #define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
300 #define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
301 #define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
302 #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
303 #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
304 #define C_00000D_FORCE_OV0 0x7FFFFFFF
305
306 #endif
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