drivers/gpu/drm/radeon/r300d.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __R300D_H__
  29 #define __R300D_H__
  30
  31 #define CP_PACKET0                      0x00000000
  32 #define         PACKET0_BASE_INDEX_SHIFT        0
  33 #define         PACKET0_BASE_INDEX_MASK         (0x1ffff << 0)
  34 #define         PACKET0_COUNT_SHIFT             16
  35 #define         PACKET0_COUNT_MASK              (0x3fff << 16)
  36 #define CP_PACKET1                      0x40000000
  37 #define CP_PACKET2                      0x80000000
  38 #define         PACKET2_PAD_SHIFT               0
  39 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
  40 #define CP_PACKET3                      0xC0000000
  41 #define         PACKET3_IT_OPCODE_SHIFT         8
  42 #define         PACKET3_IT_OPCODE_MASK          (0xff << 8)
  43 #define         PACKET3_COUNT_SHIFT             16
  44 #define         PACKET3_COUNT_MASK              (0x3fff << 16)
  45 /* PACKET3 op code */
  46 #define         PACKET3_NOP                     0x10
  47 #define         PACKET3_3D_DRAW_VBUF            0x28
  48 #define         PACKET3_3D_DRAW_IMMD            0x29
  49 #define         PACKET3_3D_DRAW_INDX            0x2A
  50 #define         PACKET3_3D_LOAD_VBPNTR          0x2F
  51 #define         PACKET3_INDX_BUFFER             0x33
  52 #define         PACKET3_3D_DRAW_VBUF_2          0x34
  53 #define         PACKET3_3D_DRAW_IMMD_2          0x35
  54 #define         PACKET3_3D_DRAW_INDX_2          0x36
  55 #define         PACKET3_BITBLT_MULTI            0x9B
  56
  57 #define PACKET0(reg, n) (CP_PACKET0 |                                   \
  58                          REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |      \
  59                          REG_SET(PACKET0_COUNT, (n)))
  60 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  61 #define PACKET3(op, n)  (CP_PACKET3 |                                   \
  62                          REG_SET(PACKET3_IT_OPCODE, (op)) |             \
  63                          REG_SET(PACKET3_COUNT, (n)))
  64
  65 #define PACKET_TYPE0    0
  66 #define PACKET_TYPE1    1
  67 #define PACKET_TYPE2    2
  68 #define PACKET_TYPE3    3
  69
  70 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
  71 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
  72 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
  73 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
  74 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
  75
  76 /* Registers */
  77 #define R_000148_MC_FB_LOCATION                      0x000148
  78 #define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
  79 #define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
  80 #define   C_000148_MC_FB_START                         0xFFFF0000
  81 #define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
  82 #define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
  83 #define   C_000148_MC_FB_TOP                           0x0000FFFF
  84 #define R_00014C_MC_AGP_LOCATION                     0x00014C
  85 #define   S_00014C_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
  86 #define   G_00014C_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
  87 #define   C_00014C_MC_AGP_START                        0xFFFF0000
  88 #define   S_00014C_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
  89 #define   G_00014C_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
  90 #define   C_00014C_MC_AGP_TOP                          0x0000FFFF
  91 #define R_00015C_AGP_BASE_2                          0x00015C
  92 #define   S_00015C_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
  93 #define   G_00015C_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
  94 #define   C_00015C_AGP_BASE_ADDR_2                     0xFFFFFFF0
  95 #define R_000170_AGP_BASE                            0x000170
  96 #define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
  97 #define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
  98 #define   C_000170_AGP_BASE_ADDR                       0x00000000
  99
 100
 101 #endif