2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
35 int r420_mc_init(struct radeon_device
*rdev
)
39 /* Setup GPU memory space */
40 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
41 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
42 if (rdev
->flags
& RADEON_IS_AGP
) {
43 r
= radeon_agp_init(rdev
);
45 printk(KERN_WARNING
"[drm] Disabling AGP\n");
46 rdev
->flags
&= ~RADEON_IS_AGP
;
47 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
49 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
52 r
= radeon_mc_setup(rdev
);
59 void r420_pipes_init(struct radeon_device
*rdev
)
62 unsigned gb_pipe_select
;
65 /* GA_ENHANCE workaround TCL deadlock issue */
66 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
67 /* add idle wait as per freedesktop.org bug 24041 */
68 if (r100_gui_wait_for_idle(rdev
)) {
69 printk(KERN_WARNING
"Failed to wait GUI idle while "
70 "programming pipes. Bad things might happen.\n");
72 /* get max number of pipes */
73 gb_pipe_select
= RREG32(0x402C);
74 num_pipes
= ((gb_pipe_select
>> 12) & 3) + 1;
75 rdev
->num_gb_pipes
= num_pipes
;
94 WREG32(0x42C8, (1 << num_pipes
) - 1);
95 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
96 tmp
|= (1 << 4) | (1 << 0);
98 if (r100_gui_wait_for_idle(rdev
)) {
99 printk(KERN_WARNING
"Failed to wait GUI idle while "
100 "programming pipes. Bad things might happen.\n");
103 tmp
= RREG32(0x170C);
104 WREG32(0x170C, tmp
| (1 << 31));
106 WREG32(R300_RB2D_DSTCACHE_MODE
,
107 RREG32(R300_RB2D_DSTCACHE_MODE
) |
108 R300_DC_AUTOFLUSH_ENABLE
|
109 R300_DC_DC_DISABLE_IGNORE_PE
);
111 if (r100_gui_wait_for_idle(rdev
)) {
112 printk(KERN_WARNING
"Failed to wait GUI idle while "
113 "programming pipes. Bad things might happen.\n");
116 if (rdev
->family
== CHIP_RV530
) {
117 tmp
= RREG32(RV530_GB_PIPE_SELECT2
);
119 rdev
->num_z_pipes
= 2;
121 rdev
->num_z_pipes
= 1;
123 rdev
->num_z_pipes
= 1;
125 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
126 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
129 u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
)
133 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
));
134 r
= RREG32(R_0001FC_MC_IND_DATA
);
138 void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
140 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
) |
141 S_0001F8_MC_IND_WR_EN(1));
142 WREG32(R_0001FC_MC_IND_DATA
, v
);
145 static void r420_debugfs(struct radeon_device
*rdev
)
147 if (r100_debugfs_rbbm_init(rdev
)) {
148 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
150 if (r420_debugfs_pipes_info_init(rdev
)) {
151 DRM_ERROR("Failed to register debugfs file for pipes !\n");
155 static void r420_clock_resume(struct radeon_device
*rdev
)
159 if (radeon_dynclks
!= -1 && radeon_dynclks
)
160 radeon_atom_set_clock_gating(rdev
, 1);
161 sclk_cntl
= RREG32_PLL(R_00000D_SCLK_CNTL
);
162 sclk_cntl
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
163 if (rdev
->family
== CHIP_R420
)
164 sclk_cntl
|= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
165 WREG32_PLL(R_00000D_SCLK_CNTL
, sclk_cntl
);
168 static int r420_startup(struct radeon_device
*rdev
)
172 r300_mc_program(rdev
);
174 r420_clock_resume(rdev
);
175 /* Initialize GART (initialize after TTM so we can allocate
176 * memory through TTM but finalize after TTM) */
177 if (rdev
->flags
& RADEON_IS_PCIE
) {
178 r
= rv370_pcie_gart_enable(rdev
);
182 if (rdev
->flags
& RADEON_IS_PCI
) {
183 r
= r100_pci_gart_enable(rdev
);
187 r420_pipes_init(rdev
);
191 r
= r100_cp_init(rdev
, 1024 * 1024);
193 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
196 r
= r100_wb_init(rdev
);
198 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
200 r
= r100_ib_init(rdev
);
202 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
208 int r420_resume(struct radeon_device
*rdev
)
210 /* Make sur GART are not working */
211 if (rdev
->flags
& RADEON_IS_PCIE
)
212 rv370_pcie_gart_disable(rdev
);
213 if (rdev
->flags
& RADEON_IS_PCI
)
214 r100_pci_gart_disable(rdev
);
215 /* Resume clock before doing reset */
216 r420_clock_resume(rdev
);
217 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
218 if (radeon_gpu_reset(rdev
)) {
219 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
220 RREG32(R_000E40_RBBM_STATUS
),
221 RREG32(R_0007C0_CP_STAT
));
223 /* check if cards are posted or not */
224 if (rdev
->is_atom_bios
) {
225 atom_asic_init(rdev
->mode_info
.atom_context
);
227 radeon_combios_asic_init(rdev
->ddev
);
229 /* Resume clock after posting */
230 r420_clock_resume(rdev
);
232 return r420_startup(rdev
);
235 int r420_suspend(struct radeon_device
*rdev
)
237 r100_cp_disable(rdev
);
238 r100_wb_disable(rdev
);
239 r100_irq_disable(rdev
);
240 if (rdev
->flags
& RADEON_IS_PCIE
)
241 rv370_pcie_gart_disable(rdev
);
242 if (rdev
->flags
& RADEON_IS_PCI
)
243 r100_pci_gart_disable(rdev
);
247 void r420_fini(struct radeon_device
*rdev
)
252 radeon_gem_fini(rdev
);
253 if (rdev
->flags
& RADEON_IS_PCIE
)
254 rv370_pcie_gart_fini(rdev
);
255 if (rdev
->flags
& RADEON_IS_PCI
)
256 r100_pci_gart_fini(rdev
);
257 radeon_agp_fini(rdev
);
258 radeon_irq_kms_fini(rdev
);
259 radeon_fence_driver_fini(rdev
);
260 radeon_bo_fini(rdev
);
261 if (rdev
->is_atom_bios
) {
262 radeon_atombios_fini(rdev
);
264 radeon_combios_fini(rdev
);
270 int r420_init(struct radeon_device
*rdev
)
274 /* Initialize scratch registers */
275 radeon_scratch_init(rdev
);
276 /* Initialize surface registers */
277 radeon_surface_init(rdev
);
278 /* TODO: disable VGA need to use VGA request */
280 if (!radeon_get_bios(rdev
)) {
281 if (ASIC_IS_AVIVO(rdev
))
284 if (rdev
->is_atom_bios
) {
285 r
= radeon_atombios_init(rdev
);
290 r
= radeon_combios_init(rdev
);
295 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
296 if (radeon_gpu_reset(rdev
)) {
298 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
299 RREG32(R_000E40_RBBM_STATUS
),
300 RREG32(R_0007C0_CP_STAT
));
302 /* check if cards are posted or not */
303 if (radeon_boot_test_post_card(rdev
) == false)
306 /* Initialize clocks */
307 radeon_get_clock_info(rdev
->ddev
);
308 /* Initialize power management */
309 radeon_pm_init(rdev
);
310 /* Get vram informations */
311 r300_vram_info(rdev
);
312 /* Initialize memory controller (also test AGP) */
313 r
= r420_mc_init(rdev
);
319 r
= radeon_fence_driver_init(rdev
);
323 r
= radeon_irq_kms_init(rdev
);
328 r
= radeon_bo_init(rdev
);
332 if (rdev
->family
== CHIP_R420
)
333 r100_enable_bm(rdev
);
335 if (rdev
->flags
& RADEON_IS_PCIE
) {
336 r
= rv370_pcie_gart_init(rdev
);
340 if (rdev
->flags
& RADEON_IS_PCI
) {
341 r
= r100_pci_gart_init(rdev
);
345 r300_set_reg_safe(rdev
);
346 rdev
->accel_working
= true;
347 r
= r420_startup(rdev
);
349 /* Somethings want wront with the accel init stop accel */
350 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
355 if (rdev
->flags
& RADEON_IS_PCIE
)
356 rv370_pcie_gart_fini(rdev
);
357 if (rdev
->flags
& RADEON_IS_PCI
)
358 r100_pci_gart_fini(rdev
);
359 radeon_agp_fini(rdev
);
360 radeon_irq_kms_fini(rdev
);
361 rdev
->accel_working
= false;
369 #if defined(CONFIG_DEBUG_FS)
370 static int r420_debugfs_pipes_info(struct seq_file
*m
, void *data
)
372 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
373 struct drm_device
*dev
= node
->minor
->dev
;
374 struct radeon_device
*rdev
= dev
->dev_private
;
377 tmp
= RREG32(R400_GB_PIPE_SELECT
);
378 seq_printf(m
, "GB_PIPE_SELECT 0x%08x\n", tmp
);
379 tmp
= RREG32(R300_GB_TILE_CONFIG
);
380 seq_printf(m
, "GB_TILE_CONFIG 0x%08x\n", tmp
);
381 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
382 seq_printf(m
, "DST_PIPE_CONFIG 0x%08x\n", tmp
);
386 static struct drm_info_list r420_pipes_info_list
[] = {
387 {"r420_pipes_info", r420_debugfs_pipes_info
, 0, NULL
},
391 int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
)
393 #if defined(CONFIG_DEBUG_FS)
394 return radeon_debugfs_add_files(rdev
, r420_pipes_info_list
, 1);