drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32 #include "atom.h"
  33 #include "r100d.h"
  34 #include "r420d.h"
  35
  36 int r420_mc_init(struct radeon_device *rdev)
  37 {
  38         int r;
  39
  40         /* Setup GPU memory space */
  41         rdev->mc.vram_location = 0xFFFFFFFFUL;
  42         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  43         if (rdev->flags & RADEON_IS_AGP) {
  44                 r = radeon_agp_init(rdev);
  45                 if (r) {
  46                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  47                         rdev->flags &= ~RADEON_IS_AGP;
  48                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  49                 } else {
  50                         rdev->mc.gtt_location = rdev->mc.agp_base;
  51                 }
  52         }
  53         r = radeon_mc_setup(rdev);
  54         if (r) {
  55                 return r;
  56         }
  57         return 0;
  58 }
  59
  60 void r420_pipes_init(struct radeon_device *rdev)
  61 {
  62         unsigned tmp;
  63         unsigned gb_pipe_select;
  64         unsigned num_pipes;
  65
  66         /* GA_ENHANCE workaround TCL deadlock issue */
  67         WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
  68         /* add idle wait as per freedesktop.org bug 24041 */
  69         if (r100_gui_wait_for_idle(rdev)) {
  70                 printk(KERN_WARNING "Failed to wait GUI idle while "
  71                        "programming pipes. Bad things might happen.\n");
  72         }
  73         /* get max number of pipes */
  74         gb_pipe_select = RREG32(0x402C);
  75         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  76         rdev->num_gb_pipes = num_pipes;
  77         tmp = 0;
  78         switch (num_pipes) {
  79         default:
  80                 /* force to 1 pipe */
  81                 num_pipes = 1;
  82         case 1:
  83                 tmp = (0 << 1);
  84                 break;
  85         case 2:
  86                 tmp = (3 << 1);
  87                 break;
  88         case 3:
  89                 tmp = (6 << 1);
  90                 break;
  91         case 4:
  92                 tmp = (7 << 1);
  93                 break;
  94         }
  95         WREG32(0x42C8, (1 << num_pipes) - 1);
  96         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  97         tmp |= (1 << 4) | (1 << 0);
  98         WREG32(0x4018, tmp);
  99         if (r100_gui_wait_for_idle(rdev)) {
 100                 printk(KERN_WARNING "Failed to wait GUI idle while "
 101                        "programming pipes. Bad things might happen.\n");
 102         }
 103
 104         tmp = RREG32(0x170C);
 105         WREG32(0x170C, tmp | (1 << 31));
 106
 107         WREG32(R300_RB2D_DSTCACHE_MODE,
 108                RREG32(R300_RB2D_DSTCACHE_MODE) |
 109                R300_DC_AUTOFLUSH_ENABLE |
 110                R300_DC_DC_DISABLE_IGNORE_PE);
 111
 112         if (r100_gui_wait_for_idle(rdev)) {
 113                 printk(KERN_WARNING "Failed to wait GUI idle while "
 114                        "programming pipes. Bad things might happen.\n");
 115         }
 116
 117         if (rdev->family == CHIP_RV530) {
 118                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 119                 if ((tmp & 3) == 3)
 120                         rdev->num_z_pipes = 2;
 121                 else
 122                         rdev->num_z_pipes = 1;
 123         } else
 124                 rdev->num_z_pipes = 1;
 125
 126         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 127                  rdev->num_gb_pipes, rdev->num_z_pipes);
 128 }
 129
 130 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 131 {
 132         u32 r;
 133
 134         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 135         r = RREG32(R_0001FC_MC_IND_DATA);
 136         return r;
 137 }
 138
 139 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 140 {
 141         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 142                 S_0001F8_MC_IND_WR_EN(1));
 143         WREG32(R_0001FC_MC_IND_DATA, v);
 144 }
 145
 146 static void r420_debugfs(struct radeon_device *rdev)
 147 {
 148         if (r100_debugfs_rbbm_init(rdev)) {
 149                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 150         }
 151         if (r420_debugfs_pipes_info_init(rdev)) {
 152                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 153         }
 154 }
 155
 156 static void r420_clock_resume(struct radeon_device *rdev)
 157 {
 158         u32 sclk_cntl;
 159
 160         if (radeon_dynclks != -1 && radeon_dynclks)
 161                 radeon_atom_set_clock_gating(rdev, 1);
 162         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 163         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 164         if (rdev->family == CHIP_R420)
 165                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 166         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 167 }
 168
 169 static void r420_cp_errata_init(struct radeon_device *rdev)
 170 {
 171         /* RV410 and R420 can lock up if CP DMA to host memory happens
 172          * while the 2D engine is busy.
 173          *
 174          * The proper workaround is to queue a RESYNC at the beginning
 175          * of the CP init, apparently.
 176          */
 177         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 178         radeon_ring_lock(rdev, 8);
 179         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 180         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 181         radeon_ring_write(rdev, 0xDEADBEEF);
 182         radeon_ring_unlock_commit(rdev);
 183 }
 184
 185 static void r420_cp_errata_fini(struct radeon_device *rdev)
 186 {
 187         /* Catch the RESYNC we dispatched all the way back,
 188          * at the very beginning of the CP init.
 189          */
 190         radeon_ring_lock(rdev, 8);
 191         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 192         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 193         radeon_ring_unlock_commit(rdev);
 194         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 195 }
 196
 197 static int r420_startup(struct radeon_device *rdev)
 198 {
 199         int r;
 200
 201         /* set common regs */
 202         r100_set_common_regs(rdev);
 203         /* program mc */
 204         r300_mc_program(rdev);
 205         /* Resume clock */
 206         r420_clock_resume(rdev);
 207         /* Initialize GART (initialize after TTM so we can allocate
 208          * memory through TTM but finalize after TTM) */
 209         if (rdev->flags & RADEON_IS_PCIE) {
 210                 r = rv370_pcie_gart_enable(rdev);
 211                 if (r)
 212                         return r;
 213         }
 214         if (rdev->flags & RADEON_IS_PCI) {
 215                 r = r100_pci_gart_enable(rdev);
 216                 if (r)
 217                         return r;
 218         }
 219         r420_pipes_init(rdev);
 220         /* Enable IRQ */
 221         r100_irq_set(rdev);
 222         /* 1M ring buffer */
 223         r = r100_cp_init(rdev, 1024 * 1024);
 224         if (r) {
 225                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 226                 return r;
 227         }
 228         r420_cp_errata_init(rdev);
 229         r = r100_wb_init(rdev);
 230         if (r) {
 231                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 232         }
 233         r = r100_ib_init(rdev);
 234         if (r) {
 235                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 236                 return r;
 237         }
 238         return 0;
 239 }
 240
 241 int r420_resume(struct radeon_device *rdev)
 242 {
 243         /* Make sur GART are not working */
 244         if (rdev->flags & RADEON_IS_PCIE)
 245                 rv370_pcie_gart_disable(rdev);
 246         if (rdev->flags & RADEON_IS_PCI)
 247                 r100_pci_gart_disable(rdev);
 248         /* Resume clock before doing reset */
 249         r420_clock_resume(rdev);
 250         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 251         if (radeon_gpu_reset(rdev)) {
 252                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 253                         RREG32(R_000E40_RBBM_STATUS),
 254                         RREG32(R_0007C0_CP_STAT));
 255         }
 256         /* check if cards are posted or not */
 257         if (rdev->is_atom_bios) {
 258                 atom_asic_init(rdev->mode_info.atom_context);
 259         } else {
 260                 radeon_combios_asic_init(rdev->ddev);
 261         }
 262         /* Resume clock after posting */
 263         r420_clock_resume(rdev);
 264         /* Initialize surface registers */
 265         radeon_surface_init(rdev);
 266         return r420_startup(rdev);
 267 }
 268
 269 int r420_suspend(struct radeon_device *rdev)
 270 {
 271         r420_cp_errata_fini(rdev);
 272         r100_cp_disable(rdev);
 273         r100_wb_disable(rdev);
 274         r100_irq_disable(rdev);
 275         if (rdev->flags & RADEON_IS_PCIE)
 276                 rv370_pcie_gart_disable(rdev);
 277         if (rdev->flags & RADEON_IS_PCI)
 278                 r100_pci_gart_disable(rdev);
 279         return 0;
 280 }
 281
 282 void r420_fini(struct radeon_device *rdev)
 283 {
 284         r100_cp_fini(rdev);
 285         r100_wb_fini(rdev);
 286         r100_ib_fini(rdev);
 287         radeon_gem_fini(rdev);
 288         if (rdev->flags & RADEON_IS_PCIE)
 289                 rv370_pcie_gart_fini(rdev);
 290         if (rdev->flags & RADEON_IS_PCI)
 291                 r100_pci_gart_fini(rdev);
 292         radeon_agp_fini(rdev);
 293         radeon_irq_kms_fini(rdev);
 294         radeon_fence_driver_fini(rdev);
 295         radeon_bo_fini(rdev);
 296         if (rdev->is_atom_bios) {
 297                 radeon_atombios_fini(rdev);
 298         } else {
 299                 radeon_combios_fini(rdev);
 300         }
 301         kfree(rdev->bios);
 302         rdev->bios = NULL;
 303 }
 304
 305 int r420_init(struct radeon_device *rdev)
 306 {
 307         int r;
 308
 309         /* Initialize scratch registers */
 310         radeon_scratch_init(rdev);
 311         /* Initialize surface registers */
 312         radeon_surface_init(rdev);
 313         /* TODO: disable VGA need to use VGA request */
 314         /* BIOS*/
 315         if (!radeon_get_bios(rdev)) {
 316                 if (ASIC_IS_AVIVO(rdev))
 317                         return -EINVAL;
 318         }
 319         if (rdev->is_atom_bios) {
 320                 r = radeon_atombios_init(rdev);
 321                 if (r) {
 322                         return r;
 323                 }
 324         } else {
 325                 r = radeon_combios_init(rdev);
 326                 if (r) {
 327                         return r;
 328                 }
 329         }
 330         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 331         if (radeon_gpu_reset(rdev)) {
 332                 dev_warn(rdev->dev,
 333                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 334                         RREG32(R_000E40_RBBM_STATUS),
 335                         RREG32(R_0007C0_CP_STAT));
 336         }
 337         /* check if cards are posted or not */
 338         if (radeon_boot_test_post_card(rdev) == false)
 339                 return -EINVAL;
 340
 341         /* Initialize clocks */
 342         radeon_get_clock_info(rdev->ddev);
 343         /* Initialize power management */
 344         radeon_pm_init(rdev);
 345         /* Get vram informations */
 346         r300_vram_info(rdev);
 347         /* Initialize memory controller (also test AGP) */
 348         r = r420_mc_init(rdev);
 349         if (r) {
 350                 return r;
 351         }
 352         r420_debugfs(rdev);
 353         /* Fence driver */
 354         r = radeon_fence_driver_init(rdev);
 355         if (r) {
 356                 return r;
 357         }
 358         r = radeon_irq_kms_init(rdev);
 359         if (r) {
 360                 return r;
 361         }
 362         /* Memory manager */
 363         r = radeon_bo_init(rdev);
 364         if (r) {
 365                 return r;
 366         }
 367         if (rdev->family == CHIP_R420)
 368                 r100_enable_bm(rdev);
 369
 370         if (rdev->flags & RADEON_IS_PCIE) {
 371                 r = rv370_pcie_gart_init(rdev);
 372                 if (r)
 373                         return r;
 374         }
 375         if (rdev->flags & RADEON_IS_PCI) {
 376                 r = r100_pci_gart_init(rdev);
 377                 if (r)
 378                         return r;
 379         }
 380         r300_set_reg_safe(rdev);
 381         rdev->accel_working = true;
 382         r = r420_startup(rdev);
 383         if (r) {
 384                 /* Somethings want wront with the accel init stop accel */
 385                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 386                 r420_suspend(rdev);
 387                 r100_cp_fini(rdev);
 388                 r100_wb_fini(rdev);
 389                 r100_ib_fini(rdev);
 390                 if (rdev->flags & RADEON_IS_PCIE)
 391                         rv370_pcie_gart_fini(rdev);
 392                 if (rdev->flags & RADEON_IS_PCI)
 393                         r100_pci_gart_fini(rdev);
 394                 radeon_agp_fini(rdev);
 395                 radeon_irq_kms_fini(rdev);
 396                 rdev->accel_working = false;
 397         }
 398         return 0;
 399 }
 400
 401 /*
 402  * Debugfs info
 403  */
 404 #if defined(CONFIG_DEBUG_FS)
 405 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 406 {
 407         struct drm_info_node *node = (struct drm_info_node *) m->private;
 408         struct drm_device *dev = node->minor->dev;
 409         struct radeon_device *rdev = dev->dev_private;
 410         uint32_t tmp;
 411
 412         tmp = RREG32(R400_GB_PIPE_SELECT);
 413         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 414         tmp = RREG32(R300_GB_TILE_CONFIG);
 415         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 416         tmp = RREG32(R300_DST_PIPE_CONFIG);
 417         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 418         return 0;
 419 }
 420
 421 static struct drm_info_list r420_pipes_info_list[] = {
 422         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 423 };
 424 #endif
 425
 426 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 427 {
 428 #if defined(CONFIG_DEBUG_FS)
 429         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 430 #else
 431         return 0;
 432 #endif
 433 }