drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "radeon_reg.h"
  31 #include "radeon.h"
  32
  33 /* r420,r423,rv410 depends on : */
  34 void r100_pci_gart_disable(struct radeon_device *rdev);
  35 void r100_hdp_reset(struct radeon_device *rdev);
  36 void r100_mc_setup(struct radeon_device *rdev);
  37 int r100_gui_wait_for_idle(struct radeon_device *rdev);
  38 void r100_mc_disable_clients(struct radeon_device *rdev);
  39 void r300_vram_info(struct radeon_device *rdev);
  40 int r300_mc_wait_for_idle(struct radeon_device *rdev);
  41 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  42 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  43
  44 /* This files gather functions specifics to :
  45  * r420,r423,rv410
  46  *
  47  * Some of these functions might be used by newer ASICs.
  48  */
  49 void r420_gpu_init(struct radeon_device *rdev);
  50 int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  51
  52
  53 /*
  54  * MC
  55  */
  56 int r420_mc_init(struct radeon_device *rdev)
  57 {
  58         int r;
  59
  60         if (r100_debugfs_rbbm_init(rdev)) {
  61                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  62         }
  63         if (r420_debugfs_pipes_info_init(rdev)) {
  64                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  65         }
  66
  67         r420_gpu_init(rdev);
  68         r100_pci_gart_disable(rdev);
  69         if (rdev->flags & RADEON_IS_PCIE) {
  70                 rv370_pcie_gart_disable(rdev);
  71         }
  72
  73         /* Setup GPU memory space */
  74         rdev->mc.vram_location = 0xFFFFFFFFUL;
  75         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  76         if (rdev->flags & RADEON_IS_AGP) {
  77                 r = radeon_agp_init(rdev);
  78                 if (r) {
  79                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  80                         rdev->flags &= ~RADEON_IS_AGP;
  81                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  82                 } else {
  83                         rdev->mc.gtt_location = rdev->mc.agp_base;
  84                 }
  85         }
  86         r = radeon_mc_setup(rdev);
  87         if (r) {
  88                 return r;
  89         }
  90
  91         /* Program GPU memory space */
  92         r100_mc_disable_clients(rdev);
  93         if (r300_mc_wait_for_idle(rdev)) {
  94                 printk(KERN_WARNING "Failed to wait MC idle while "
  95                        "programming pipes. Bad things might happen.\n");
  96         }
  97         r100_mc_setup(rdev);
  98         return 0;
  99 }
 100
 101 void r420_mc_fini(struct radeon_device *rdev)
 102 {
 103         rv370_pcie_gart_disable(rdev);
 104         radeon_gart_table_vram_free(rdev);
 105         radeon_gart_fini(rdev);
 106 }
 107
 108
 109 /*
 110  * Global GPU functions
 111  */
 112 void r420_errata(struct radeon_device *rdev)
 113 {
 114         rdev->pll_errata = 0;
 115 }
 116
 117 void r420_pipes_init(struct radeon_device *rdev)
 118 {
 119         unsigned tmp;
 120         unsigned gb_pipe_select;
 121         unsigned num_pipes;
 122
 123         /* GA_ENHANCE workaround TCL deadlock issue */
 124         WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
 125         /* get max number of pipes */
 126         gb_pipe_select = RREG32(0x402C);
 127         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
 128         rdev->num_gb_pipes = num_pipes;
 129         tmp = 0;
 130         switch (num_pipes) {
 131         default:
 132                 /* force to 1 pipe */
 133                 num_pipes = 1;
 134         case 1:
 135                 tmp = (0 << 1);
 136                 break;
 137         case 2:
 138                 tmp = (3 << 1);
 139                 break;
 140         case 3:
 141                 tmp = (6 << 1);
 142                 break;
 143         case 4:
 144                 tmp = (7 << 1);
 145                 break;
 146         }
 147         WREG32(0x42C8, (1 << num_pipes) - 1);
 148         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 149         tmp |= (1 << 4) | (1 << 0);
 150         WREG32(0x4018, tmp);
 151         if (r100_gui_wait_for_idle(rdev)) {
 152                 printk(KERN_WARNING "Failed to wait GUI idle while "
 153                        "programming pipes. Bad things might happen.\n");
 154         }
 155
 156         tmp = RREG32(0x170C);
 157         WREG32(0x170C, tmp | (1 << 31));
 158
 159         WREG32(R300_RB2D_DSTCACHE_MODE,
 160                RREG32(R300_RB2D_DSTCACHE_MODE) |
 161                R300_DC_AUTOFLUSH_ENABLE |
 162                R300_DC_DC_DISABLE_IGNORE_PE);
 163
 164         if (r100_gui_wait_for_idle(rdev)) {
 165                 printk(KERN_WARNING "Failed to wait GUI idle while "
 166                        "programming pipes. Bad things might happen.\n");
 167         }
 168         DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
 169 }
 170
 171 void r420_gpu_init(struct radeon_device *rdev)
 172 {
 173         r100_hdp_reset(rdev);
 174         r420_pipes_init(rdev);
 175         if (r300_mc_wait_for_idle(rdev)) {
 176                 printk(KERN_WARNING "Failed to wait MC idle while "
 177                        "programming pipes. Bad things might happen.\n");
 178         }
 179 }
 180
 181
 182 /*
 183  * r420,r423,rv410 VRAM info
 184  */
 185 void r420_vram_info(struct radeon_device *rdev)
 186 {
 187         r300_vram_info(rdev);
 188 }
 189
 190
 191 /*
 192  * Debugfs info
 193  */
 194 #if defined(CONFIG_DEBUG_FS)
 195 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 196 {
 197         struct drm_info_node *node = (struct drm_info_node *) m->private;
 198         struct drm_device *dev = node->minor->dev;
 199         struct radeon_device *rdev = dev->dev_private;
 200         uint32_t tmp;
 201
 202         tmp = RREG32(R400_GB_PIPE_SELECT);
 203         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 204         tmp = RREG32(R300_GB_TILE_CONFIG);
 205         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 206         tmp = RREG32(R300_DST_PIPE_CONFIG);
 207         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 208         return 0;
 209 }
 210
 211 static struct drm_info_list r420_pipes_info_list[] = {
 212         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 213 };
 214 #endif
 215
 216 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 217 {
 218 #if defined(CONFIG_DEBUG_FS)
 219         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 220 #else
 221         return 0;
 222 #endif
 223 }