2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
35 int r420_mc_init(struct radeon_device
*rdev
)
39 /* Setup GPU memory space */
40 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
41 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
42 if (rdev
->flags
& RADEON_IS_AGP
) {
43 r
= radeon_agp_init(rdev
);
45 printk(KERN_WARNING
"[drm] Disabling AGP\n");
46 rdev
->flags
&= ~RADEON_IS_AGP
;
47 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
49 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
52 r
= radeon_mc_setup(rdev
);
59 void r420_pipes_init(struct radeon_device
*rdev
)
62 unsigned gb_pipe_select
;
65 /* GA_ENHANCE workaround TCL deadlock issue */
66 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
67 /* get max number of pipes */
68 gb_pipe_select
= RREG32(0x402C);
69 num_pipes
= ((gb_pipe_select
>> 12) & 3) + 1;
70 rdev
->num_gb_pipes
= num_pipes
;
89 WREG32(0x42C8, (1 << num_pipes
) - 1);
90 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
91 tmp
|= (1 << 4) | (1 << 0);
93 if (r100_gui_wait_for_idle(rdev
)) {
94 printk(KERN_WARNING
"Failed to wait GUI idle while "
95 "programming pipes. Bad things might happen.\n");
99 WREG32(0x170C, tmp
| (1 << 31));
101 WREG32(R300_RB2D_DSTCACHE_MODE
,
102 RREG32(R300_RB2D_DSTCACHE_MODE
) |
103 R300_DC_AUTOFLUSH_ENABLE
|
104 R300_DC_DC_DISABLE_IGNORE_PE
);
106 if (r100_gui_wait_for_idle(rdev
)) {
107 printk(KERN_WARNING
"Failed to wait GUI idle while "
108 "programming pipes. Bad things might happen.\n");
111 if (rdev
->family
== CHIP_RV530
) {
112 tmp
= RREG32(RV530_GB_PIPE_SELECT2
);
114 rdev
->num_z_pipes
= 2;
116 rdev
->num_z_pipes
= 1;
118 rdev
->num_z_pipes
= 1;
120 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
121 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
124 u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
)
128 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
));
129 r
= RREG32(R_0001FC_MC_IND_DATA
);
133 void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
135 WREG32(R_0001F8_MC_IND_INDEX
, S_0001F8_MC_IND_ADDR(reg
) |
136 S_0001F8_MC_IND_WR_EN(1));
137 WREG32(R_0001FC_MC_IND_DATA
, v
);
140 static void r420_debugfs(struct radeon_device
*rdev
)
142 if (r100_debugfs_rbbm_init(rdev
)) {
143 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
145 if (r420_debugfs_pipes_info_init(rdev
)) {
146 DRM_ERROR("Failed to register debugfs file for pipes !\n");
150 static void r420_clock_resume(struct radeon_device
*rdev
)
153 sclk_cntl
= RREG32_PLL(R_00000D_SCLK_CNTL
);
154 sclk_cntl
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
155 if (rdev
->family
== CHIP_R420
)
156 sclk_cntl
|= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
157 WREG32_PLL(R_00000D_SCLK_CNTL
, sclk_cntl
);
160 int r420_resume(struct radeon_device
*rdev
)
164 /* Make sur GART are not working */
165 if (rdev
->flags
& RADEON_IS_PCIE
)
166 rv370_pcie_gart_disable(rdev
);
167 if (rdev
->flags
& RADEON_IS_PCI
)
168 r100_pci_gart_disable(rdev
);
169 /* Resume clock before doing reset */
170 r420_clock_resume(rdev
);
171 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
172 if (radeon_gpu_reset(rdev
)) {
173 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
174 RREG32(R_000E40_RBBM_STATUS
),
175 RREG32(R_0007C0_CP_STAT
));
177 /* check if cards are posted or not */
178 if (rdev
->is_atom_bios
) {
179 atom_asic_init(rdev
->mode_info
.atom_context
);
181 radeon_combios_asic_init(rdev
->ddev
);
183 /* Resume clock after posting */
184 r420_clock_resume(rdev
);
185 r300_mc_program(rdev
);
186 /* Initialize GART (initialize after TTM so we can allocate
187 * memory through TTM but finalize after TTM) */
188 if (rdev
->flags
& RADEON_IS_PCIE
) {
189 r
= rv370_pcie_gart_enable(rdev
);
193 if (rdev
->flags
& RADEON_IS_PCI
) {
194 r
= r100_pci_gart_enable(rdev
);
198 r420_pipes_init(rdev
);
200 rdev
->irq
.sw_int
= true;
203 r
= r100_cp_init(rdev
, 1024 * 1024);
205 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
208 r
= r100_wb_init(rdev
);
210 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
212 r
= r100_ib_init(rdev
);
214 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
220 int r420_suspend(struct radeon_device
*rdev
)
222 r100_cp_disable(rdev
);
223 r100_wb_disable(rdev
);
224 r100_irq_disable(rdev
);
225 if (rdev
->flags
& RADEON_IS_PCIE
)
226 rv370_pcie_gart_disable(rdev
);
227 if (rdev
->flags
& RADEON_IS_PCI
)
228 r100_pci_gart_disable(rdev
);
232 void r420_fini(struct radeon_device
*rdev
)
237 radeon_gem_fini(rdev
);
238 if (rdev
->flags
& RADEON_IS_PCIE
)
239 rv370_pcie_gart_fini(rdev
);
240 if (rdev
->flags
& RADEON_IS_PCI
)
241 r100_pci_gart_fini(rdev
);
242 radeon_agp_fini(rdev
);
243 radeon_irq_kms_fini(rdev
);
244 radeon_fence_driver_fini(rdev
);
245 radeon_object_fini(rdev
);
246 if (rdev
->is_atom_bios
) {
247 radeon_atombios_fini(rdev
);
249 radeon_combios_fini(rdev
);
255 int r420_init(struct radeon_device
*rdev
)
259 rdev
->new_init_path
= true;
260 /* Initialize scratch registers */
261 radeon_scratch_init(rdev
);
262 /* Initialize surface registers */
263 radeon_surface_init(rdev
);
264 /* TODO: disable VGA need to use VGA request */
266 if (!radeon_get_bios(rdev
)) {
267 if (ASIC_IS_AVIVO(rdev
))
270 if (rdev
->is_atom_bios
) {
271 r
= radeon_atombios_init(rdev
);
276 r
= radeon_combios_init(rdev
);
281 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
282 if (radeon_gpu_reset(rdev
)) {
284 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
285 RREG32(R_000E40_RBBM_STATUS
),
286 RREG32(R_0007C0_CP_STAT
));
288 /* check if cards are posted or not */
289 if (!radeon_card_posted(rdev
) && rdev
->bios
) {
290 DRM_INFO("GPU not posted. posting now...\n");
291 if (rdev
->is_atom_bios
) {
292 atom_asic_init(rdev
->mode_info
.atom_context
);
294 radeon_combios_asic_init(rdev
->ddev
);
297 /* Initialize clocks */
298 radeon_get_clock_info(rdev
->ddev
);
299 /* Get vram informations */
300 r300_vram_info(rdev
);
301 /* Initialize memory controller (also test AGP) */
302 r
= r420_mc_init(rdev
);
308 r
= radeon_fence_driver_init(rdev
);
312 r
= radeon_irq_kms_init(rdev
);
317 r
= radeon_object_init(rdev
);
321 if (rdev
->flags
& RADEON_IS_PCIE
) {
322 r
= rv370_pcie_gart_init(rdev
);
326 if (rdev
->flags
& RADEON_IS_PCI
) {
327 r
= r100_pci_gart_init(rdev
);
331 r300_set_reg_safe(rdev
);
332 rdev
->accel_working
= true;
333 r
= r420_resume(rdev
);
335 /* Somethings want wront with the accel init stop accel */
336 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
341 if (rdev
->flags
& RADEON_IS_PCIE
)
342 rv370_pcie_gart_fini(rdev
);
343 if (rdev
->flags
& RADEON_IS_PCI
)
344 r100_pci_gart_fini(rdev
);
345 radeon_agp_fini(rdev
);
346 radeon_irq_kms_fini(rdev
);
347 rdev
->accel_working
= false;
355 #if defined(CONFIG_DEBUG_FS)
356 static int r420_debugfs_pipes_info(struct seq_file
*m
, void *data
)
358 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
359 struct drm_device
*dev
= node
->minor
->dev
;
360 struct radeon_device
*rdev
= dev
->dev_private
;
363 tmp
= RREG32(R400_GB_PIPE_SELECT
);
364 seq_printf(m
, "GB_PIPE_SELECT 0x%08x\n", tmp
);
365 tmp
= RREG32(R300_GB_TILE_CONFIG
);
366 seq_printf(m
, "GB_TILE_CONFIG 0x%08x\n", tmp
);
367 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
368 seq_printf(m
, "DST_PIPE_CONFIG 0x%08x\n", tmp
);
372 static struct drm_info_list r420_pipes_info_list
[] = {
373 {"r420_pipes_info", r420_debugfs_pipes_info
, 0, NULL
},
377 int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
)
379 #if defined(CONFIG_DEBUG_FS)
380 return radeon_debugfs_add_files(rdev
, r420_pipes_info_list
, 1);