2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_mode.h"
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
74 void r600_gpu_init(struct radeon_device
*rdev
);
75 void r600_fini(struct radeon_device
*rdev
);
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
80 bool connected
= false;
82 if (ASIC_IS_DCE3(rdev
)) {
85 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
89 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
93 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
97 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
102 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
106 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
133 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
134 enum radeon_hpd_id hpd
)
137 bool connected
= r600_hpd_sense(rdev
, hpd
);
139 if (ASIC_IS_DCE3(rdev
)) {
142 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
144 tmp
&= ~DC_HPDx_INT_POLARITY
;
146 tmp
|= DC_HPDx_INT_POLARITY
;
147 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
150 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
152 tmp
&= ~DC_HPDx_INT_POLARITY
;
154 tmp
|= DC_HPDx_INT_POLARITY
;
155 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
158 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
160 tmp
&= ~DC_HPDx_INT_POLARITY
;
162 tmp
|= DC_HPDx_INT_POLARITY
;
163 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
166 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
168 tmp
&= ~DC_HPDx_INT_POLARITY
;
170 tmp
|= DC_HPDx_INT_POLARITY
;
171 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
174 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
176 tmp
&= ~DC_HPDx_INT_POLARITY
;
178 tmp
|= DC_HPDx_INT_POLARITY
;
179 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
183 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
185 tmp
&= ~DC_HPDx_INT_POLARITY
;
187 tmp
|= DC_HPDx_INT_POLARITY
;
188 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
196 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
198 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
200 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
204 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
206 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
208 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
212 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
214 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
216 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
225 void r600_hpd_init(struct radeon_device
*rdev
)
227 struct drm_device
*dev
= rdev
->ddev
;
228 struct drm_connector
*connector
;
230 if (ASIC_IS_DCE3(rdev
)) {
231 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev
))
235 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
236 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
237 switch (radeon_connector
->hpd
.hpd
) {
239 WREG32(DC_HPD1_CONTROL
, tmp
);
240 rdev
->irq
.hpd
[0] = true;
243 WREG32(DC_HPD2_CONTROL
, tmp
);
244 rdev
->irq
.hpd
[1] = true;
247 WREG32(DC_HPD3_CONTROL
, tmp
);
248 rdev
->irq
.hpd
[2] = true;
251 WREG32(DC_HPD4_CONTROL
, tmp
);
252 rdev
->irq
.hpd
[3] = true;
256 WREG32(DC_HPD5_CONTROL
, tmp
);
257 rdev
->irq
.hpd
[4] = true;
260 WREG32(DC_HPD6_CONTROL
, tmp
);
261 rdev
->irq
.hpd
[5] = true;
268 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
269 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
270 switch (radeon_connector
->hpd
.hpd
) {
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
273 rdev
->irq
.hpd
[0] = true;
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
277 rdev
->irq
.hpd
[1] = true;
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
281 rdev
->irq
.hpd
[2] = true;
291 void r600_hpd_fini(struct radeon_device
*rdev
)
293 struct drm_device
*dev
= rdev
->ddev
;
294 struct drm_connector
*connector
;
296 if (ASIC_IS_DCE3(rdev
)) {
297 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
298 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
299 switch (radeon_connector
->hpd
.hpd
) {
301 WREG32(DC_HPD1_CONTROL
, 0);
302 rdev
->irq
.hpd
[0] = false;
305 WREG32(DC_HPD2_CONTROL
, 0);
306 rdev
->irq
.hpd
[1] = false;
309 WREG32(DC_HPD3_CONTROL
, 0);
310 rdev
->irq
.hpd
[2] = false;
313 WREG32(DC_HPD4_CONTROL
, 0);
314 rdev
->irq
.hpd
[3] = false;
318 WREG32(DC_HPD5_CONTROL
, 0);
319 rdev
->irq
.hpd
[4] = false;
322 WREG32(DC_HPD6_CONTROL
, 0);
323 rdev
->irq
.hpd
[5] = false;
330 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
331 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
332 switch (radeon_connector
->hpd
.hpd
) {
334 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
335 rdev
->irq
.hpd
[0] = false;
338 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
339 rdev
->irq
.hpd
[1] = false;
342 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
343 rdev
->irq
.hpd
[2] = false;
355 int r600_gart_clear_page(struct radeon_device
*rdev
, int i
)
357 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
360 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
)
363 writeq(pte
, ((void __iomem
*)ptr
) + (i
* 8));
367 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
372 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
373 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
374 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
375 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
377 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
378 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
380 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
390 int r600_pcie_gart_init(struct radeon_device
*rdev
)
394 if (rdev
->gart
.table
.vram
.robj
) {
395 WARN(1, "R600 PCIE GART already initialized.\n");
398 /* Initialize common gart structure */
399 r
= radeon_gart_init(rdev
);
402 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
403 return radeon_gart_table_vram_alloc(rdev
);
406 int r600_pcie_gart_enable(struct radeon_device
*rdev
)
411 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
412 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
415 r
= radeon_gart_table_vram_pin(rdev
);
420 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
421 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
422 EFFECTIVE_L2_QUEUE_SIZE(7));
423 WREG32(VM_L2_CNTL2
, 0);
424 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
425 /* Setup TLB control */
426 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
427 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
428 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
429 ENABLE_WAIT_L2_QUERY
;
430 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
431 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
432 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
433 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
434 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
435 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
436 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
437 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
438 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
439 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
440 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
441 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
442 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
443 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
444 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
445 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
446 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
447 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
448 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
449 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
450 (u32
)(rdev
->dummy_page
.addr
>> 12));
451 for (i
= 1; i
< 7; i
++)
452 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
454 r600_pcie_gart_tlb_flush(rdev
);
455 rdev
->gart
.ready
= true;
459 void r600_pcie_gart_disable(struct radeon_device
*rdev
)
464 /* Disable all tables */
465 for (i
= 0; i
< 7; i
++)
466 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
468 /* Disable L2 cache */
469 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
470 EFFECTIVE_L2_QUEUE_SIZE(7));
471 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
472 /* Setup L1 TLB control */
473 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
474 ENABLE_WAIT_L2_QUERY
;
475 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
476 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
477 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
478 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
479 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
480 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
481 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
482 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
483 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
484 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
485 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
486 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
487 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
488 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
489 if (rdev
->gart
.table
.vram
.robj
) {
490 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
491 if (likely(r
== 0)) {
492 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
493 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
494 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
499 void r600_pcie_gart_fini(struct radeon_device
*rdev
)
501 r600_pcie_gart_disable(rdev
);
502 radeon_gart_table_vram_free(rdev
);
503 radeon_gart_fini(rdev
);
506 void r600_agp_enable(struct radeon_device
*rdev
)
512 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
513 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
514 EFFECTIVE_L2_QUEUE_SIZE(7));
515 WREG32(VM_L2_CNTL2
, 0);
516 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
517 /* Setup TLB control */
518 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
519 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
520 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
521 ENABLE_WAIT_L2_QUERY
;
522 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
523 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
524 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
525 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
526 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
527 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
528 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
529 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
530 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
531 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
532 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
533 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
534 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
535 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
536 for (i
= 0; i
< 7; i
++)
537 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
540 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
545 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
547 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
555 static void r600_mc_program(struct radeon_device
*rdev
)
557 struct rv515_mc_save save
;
562 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
563 WREG32((0x2c14 + j
), 0x00000000);
564 WREG32((0x2c18 + j
), 0x00000000);
565 WREG32((0x2c1c + j
), 0x00000000);
566 WREG32((0x2c20 + j
), 0x00000000);
567 WREG32((0x2c24 + j
), 0x00000000);
569 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
571 rv515_mc_stop(rdev
, &save
);
572 if (r600_mc_wait_for_idle(rdev
)) {
573 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
575 /* Lockout access through VGA aperture (doesn't exist before R600) */
576 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
577 /* Update configuration */
578 if (rdev
->flags
& RADEON_IS_AGP
) {
579 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
580 /* VRAM before AGP */
581 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
582 rdev
->mc
.vram_start
>> 12);
583 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
584 rdev
->mc
.gtt_end
>> 12);
587 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
588 rdev
->mc
.gtt_start
>> 12);
589 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
590 rdev
->mc
.vram_end
>> 12);
593 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
594 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
596 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
597 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
598 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
599 WREG32(MC_VM_FB_LOCATION
, tmp
);
600 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
601 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
602 WREG32(HDP_NONSURFACE_SIZE
, rdev
->mc
.mc_vram_size
| 0x3FF);
603 if (rdev
->flags
& RADEON_IS_AGP
) {
604 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
605 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
606 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
608 WREG32(MC_VM_AGP_BASE
, 0);
609 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
610 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
612 if (r600_mc_wait_for_idle(rdev
)) {
613 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
615 rv515_mc_resume(rdev
, &save
);
616 /* we need to own VRAM, so turn off the VGA renderer here
617 * to stop it overwriting our objects */
618 rv515_vga_render_disable(rdev
);
621 int r600_mc_init(struct radeon_device
*rdev
)
625 int chansize
, numchan
;
628 /* Get VRAM informations */
629 rdev
->mc
.vram_is_ddr
= true;
630 tmp
= RREG32(RAMCFG
);
631 if (tmp
& CHANSIZE_OVERRIDE
) {
633 } else if (tmp
& CHANSIZE_MASK
) {
639 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
654 rdev
->mc
.vram_width
= numchan
* chansize
;
655 /* Could aper size report 0 ? */
656 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
657 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
658 /* Setup GPU memory space */
659 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
660 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
662 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
)
663 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
665 if (rdev
->mc
.real_vram_size
> rdev
->mc
.aper_size
)
666 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
668 if (rdev
->flags
& RADEON_IS_AGP
) {
669 r
= radeon_agp_init(rdev
);
672 /* gtt_size is setup by radeon_agp_init */
673 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
674 tmp
= 0xFFFFFFFFUL
- rdev
->mc
.agp_base
- rdev
->mc
.gtt_size
;
675 /* Try to put vram before or after AGP because we
676 * we want SYSTEM_APERTURE to cover both VRAM and
677 * AGP so that GPU can catch out of VRAM/AGP access
679 if (rdev
->mc
.gtt_location
> rdev
->mc
.mc_vram_size
) {
680 /* Enought place before */
681 rdev
->mc
.vram_location
= rdev
->mc
.gtt_location
-
682 rdev
->mc
.mc_vram_size
;
683 } else if (tmp
> rdev
->mc
.mc_vram_size
) {
684 /* Enought place after */
685 rdev
->mc
.vram_location
= rdev
->mc
.gtt_location
+
688 /* Try to setup VRAM then AGP might not
689 * not work on some card
691 rdev
->mc
.vram_location
= 0x00000000UL
;
692 rdev
->mc
.gtt_location
= rdev
->mc
.mc_vram_size
;
695 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
696 rdev
->mc
.vram_location
= (RREG32(MC_VM_FB_LOCATION
) &
698 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
;
699 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.gtt_size
) {
700 /* Enough place after vram */
701 rdev
->mc
.gtt_location
= tmp
;
702 } else if (rdev
->mc
.vram_location
>= rdev
->mc
.gtt_size
) {
703 /* Enough place before vram */
704 rdev
->mc
.gtt_location
= 0;
706 /* Not enough place after or before shrink
709 if (rdev
->mc
.vram_location
> (0xFFFFFFFFUL
- tmp
)) {
710 rdev
->mc
.gtt_location
= 0;
711 rdev
->mc
.gtt_size
= rdev
->mc
.vram_location
;
713 rdev
->mc
.gtt_location
= tmp
;
714 rdev
->mc
.gtt_size
= 0xFFFFFFFFUL
- tmp
;
717 rdev
->mc
.gtt_location
= rdev
->mc
.mc_vram_size
;
719 rdev
->mc
.vram_start
= rdev
->mc
.vram_location
;
720 rdev
->mc
.vram_end
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1;
721 rdev
->mc
.gtt_start
= rdev
->mc
.gtt_location
;
722 rdev
->mc
.gtt_end
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
723 /* FIXME: we should enforce default clock in case GPU is not in
726 a
.full
= rfixed_const(100);
727 rdev
->pm
.sclk
.full
= rfixed_const(rdev
->clock
.default_sclk
);
728 rdev
->pm
.sclk
.full
= rfixed_div(rdev
->pm
.sclk
, a
);
732 /* We doesn't check that the GPU really needs a reset we simply do the
733 * reset, it's up to the caller to determine if the GPU needs one. We
734 * might add an helper function to check that.
736 int r600_gpu_soft_reset(struct radeon_device
*rdev
)
738 struct rv515_mc_save save
;
739 u32 grbm_busy_mask
= S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
740 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
741 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
742 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
743 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
744 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
745 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
746 S_008010_GUI_ACTIVE(1);
747 u32 grbm2_busy_mask
= S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
748 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
749 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
750 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
751 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
752 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
753 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
754 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
758 dev_info(rdev
->dev
, "GPU softreset \n");
759 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
760 RREG32(R_008010_GRBM_STATUS
));
761 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
762 RREG32(R_008014_GRBM_STATUS2
));
763 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
764 RREG32(R_000E50_SRBM_STATUS
));
765 rv515_mc_stop(rdev
, &save
);
766 if (r600_mc_wait_for_idle(rdev
)) {
767 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
769 /* Disable CP parsing/prefetching */
770 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(0xff));
771 /* Check if any of the rendering block is busy and reset it */
772 if ((RREG32(R_008010_GRBM_STATUS
) & grbm_busy_mask
) ||
773 (RREG32(R_008014_GRBM_STATUS2
) & grbm2_busy_mask
)) {
774 tmp
= S_008020_SOFT_RESET_CR(1) |
775 S_008020_SOFT_RESET_DB(1) |
776 S_008020_SOFT_RESET_CB(1) |
777 S_008020_SOFT_RESET_PA(1) |
778 S_008020_SOFT_RESET_SC(1) |
779 S_008020_SOFT_RESET_SMX(1) |
780 S_008020_SOFT_RESET_SPI(1) |
781 S_008020_SOFT_RESET_SX(1) |
782 S_008020_SOFT_RESET_SH(1) |
783 S_008020_SOFT_RESET_TC(1) |
784 S_008020_SOFT_RESET_TA(1) |
785 S_008020_SOFT_RESET_VC(1) |
786 S_008020_SOFT_RESET_VGT(1);
787 dev_info(rdev
->dev
, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
788 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
789 (void)RREG32(R_008020_GRBM_SOFT_RESET
);
791 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
792 (void)RREG32(R_008020_GRBM_SOFT_RESET
);
794 /* Reset CP (we always reset CP) */
795 tmp
= S_008020_SOFT_RESET_CP(1);
796 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
797 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
798 (void)RREG32(R_008020_GRBM_SOFT_RESET
);
800 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
801 (void)RREG32(R_008020_GRBM_SOFT_RESET
);
802 /* Reset others GPU block if necessary */
803 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
804 srbm_reset
|= S_000E60_SOFT_RESET_RLC(1);
805 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS
)))
806 srbm_reset
|= S_000E60_SOFT_RESET_GRBM(1);
807 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS
)))
808 srbm_reset
|= S_000E60_SOFT_RESET_IH(1);
809 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
810 srbm_reset
|= S_000E60_SOFT_RESET_VMC(1);
811 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
812 srbm_reset
|= S_000E60_SOFT_RESET_MC(1);
813 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
814 srbm_reset
|= S_000E60_SOFT_RESET_MC(1);
815 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
816 srbm_reset
|= S_000E60_SOFT_RESET_MC(1);
817 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
818 srbm_reset
|= S_000E60_SOFT_RESET_MC(1);
819 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
820 srbm_reset
|= S_000E60_SOFT_RESET_MC(1);
821 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
822 srbm_reset
|= S_000E60_SOFT_RESET_RLC(1);
823 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
824 srbm_reset
|= S_000E60_SOFT_RESET_SEM(1);
825 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS
)))
826 srbm_reset
|= S_000E60_SOFT_RESET_BIF(1);
827 dev_info(rdev
->dev
, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset
);
828 WREG32(R_000E60_SRBM_SOFT_RESET
, srbm_reset
);
829 (void)RREG32(R_000E60_SRBM_SOFT_RESET
);
831 WREG32(R_000E60_SRBM_SOFT_RESET
, 0);
832 (void)RREG32(R_000E60_SRBM_SOFT_RESET
);
833 WREG32(R_000E60_SRBM_SOFT_RESET
, srbm_reset
);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET
);
836 WREG32(R_000E60_SRBM_SOFT_RESET
, 0);
837 (void)RREG32(R_000E60_SRBM_SOFT_RESET
);
838 /* Wait a little for things to settle down */
840 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
841 RREG32(R_008010_GRBM_STATUS
));
842 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
843 RREG32(R_008014_GRBM_STATUS2
));
844 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
845 RREG32(R_000E50_SRBM_STATUS
));
846 /* After reset we need to reinit the asic as GPU often endup in an
849 atom_asic_init(rdev
->mode_info
.atom_context
);
850 rv515_mc_resume(rdev
, &save
);
854 int r600_gpu_reset(struct radeon_device
*rdev
)
856 return r600_gpu_soft_reset(rdev
);
859 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
861 u32 backend_disable_mask
)
864 u32 enabled_backends_mask
;
865 u32 enabled_backends_count
;
867 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
871 if (num_tile_pipes
> R6XX_MAX_PIPES
)
872 num_tile_pipes
= R6XX_MAX_PIPES
;
873 if (num_tile_pipes
< 1)
875 if (num_backends
> R6XX_MAX_BACKENDS
)
876 num_backends
= R6XX_MAX_BACKENDS
;
877 if (num_backends
< 1)
880 enabled_backends_mask
= 0;
881 enabled_backends_count
= 0;
882 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
883 if (((backend_disable_mask
>> i
) & 1) == 0) {
884 enabled_backends_mask
|= (1 << i
);
885 ++enabled_backends_count
;
887 if (enabled_backends_count
== num_backends
)
891 if (enabled_backends_count
== 0) {
892 enabled_backends_mask
= 1;
893 enabled_backends_count
= 1;
896 if (enabled_backends_count
!= num_backends
)
897 num_backends
= enabled_backends_count
;
899 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
900 switch (num_tile_pipes
) {
956 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
957 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
958 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
960 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
962 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
968 int r600_count_pipe_bits(uint32_t val
)
972 for (i
= 0; i
< 32; i
++) {
979 void r600_gpu_init(struct radeon_device
*rdev
)
986 u32 sq_gpr_resource_mgmt_1
= 0;
987 u32 sq_gpr_resource_mgmt_2
= 0;
988 u32 sq_thread_resource_mgmt
= 0;
989 u32 sq_stack_resource_mgmt_1
= 0;
990 u32 sq_stack_resource_mgmt_2
= 0;
992 /* FIXME: implement */
993 switch (rdev
->family
) {
995 rdev
->config
.r600
.max_pipes
= 4;
996 rdev
->config
.r600
.max_tile_pipes
= 8;
997 rdev
->config
.r600
.max_simds
= 4;
998 rdev
->config
.r600
.max_backends
= 4;
999 rdev
->config
.r600
.max_gprs
= 256;
1000 rdev
->config
.r600
.max_threads
= 192;
1001 rdev
->config
.r600
.max_stack_entries
= 256;
1002 rdev
->config
.r600
.max_hw_contexts
= 8;
1003 rdev
->config
.r600
.max_gs_threads
= 16;
1004 rdev
->config
.r600
.sx_max_export_size
= 128;
1005 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1006 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1007 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1011 rdev
->config
.r600
.max_pipes
= 2;
1012 rdev
->config
.r600
.max_tile_pipes
= 2;
1013 rdev
->config
.r600
.max_simds
= 3;
1014 rdev
->config
.r600
.max_backends
= 1;
1015 rdev
->config
.r600
.max_gprs
= 128;
1016 rdev
->config
.r600
.max_threads
= 192;
1017 rdev
->config
.r600
.max_stack_entries
= 128;
1018 rdev
->config
.r600
.max_hw_contexts
= 8;
1019 rdev
->config
.r600
.max_gs_threads
= 4;
1020 rdev
->config
.r600
.sx_max_export_size
= 128;
1021 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1022 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1023 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1029 rdev
->config
.r600
.max_pipes
= 1;
1030 rdev
->config
.r600
.max_tile_pipes
= 1;
1031 rdev
->config
.r600
.max_simds
= 2;
1032 rdev
->config
.r600
.max_backends
= 1;
1033 rdev
->config
.r600
.max_gprs
= 128;
1034 rdev
->config
.r600
.max_threads
= 192;
1035 rdev
->config
.r600
.max_stack_entries
= 128;
1036 rdev
->config
.r600
.max_hw_contexts
= 4;
1037 rdev
->config
.r600
.max_gs_threads
= 4;
1038 rdev
->config
.r600
.sx_max_export_size
= 128;
1039 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1040 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1041 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1044 rdev
->config
.r600
.max_pipes
= 4;
1045 rdev
->config
.r600
.max_tile_pipes
= 4;
1046 rdev
->config
.r600
.max_simds
= 4;
1047 rdev
->config
.r600
.max_backends
= 4;
1048 rdev
->config
.r600
.max_gprs
= 192;
1049 rdev
->config
.r600
.max_threads
= 192;
1050 rdev
->config
.r600
.max_stack_entries
= 256;
1051 rdev
->config
.r600
.max_hw_contexts
= 8;
1052 rdev
->config
.r600
.max_gs_threads
= 16;
1053 rdev
->config
.r600
.sx_max_export_size
= 128;
1054 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1055 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1056 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1062 /* Initialize HDP */
1063 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1064 WREG32((0x2c14 + j
), 0x00000000);
1065 WREG32((0x2c18 + j
), 0x00000000);
1066 WREG32((0x2c1c + j
), 0x00000000);
1067 WREG32((0x2c20 + j
), 0x00000000);
1068 WREG32((0x2c24 + j
), 0x00000000);
1071 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1075 ramcfg
= RREG32(RAMCFG
);
1076 switch (rdev
->config
.r600
.max_tile_pipes
) {
1078 tiling_config
|= PIPE_TILING(0);
1081 tiling_config
|= PIPE_TILING(1);
1084 tiling_config
|= PIPE_TILING(2);
1087 tiling_config
|= PIPE_TILING(3);
1092 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1093 tiling_config
|= GROUP_SIZE(0);
1094 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1096 tiling_config
|= ROW_TILING(3);
1097 tiling_config
|= SAMPLE_SPLIT(3);
1099 tiling_config
|= ROW_TILING(tmp
);
1100 tiling_config
|= SAMPLE_SPLIT(tmp
);
1102 tiling_config
|= BANK_SWAPS(1);
1103 tmp
= r600_get_tile_pipe_to_backend_map(rdev
->config
.r600
.max_tile_pipes
,
1104 rdev
->config
.r600
.max_backends
,
1105 (0xff << rdev
->config
.r600
.max_backends
) & 0xff);
1106 tiling_config
|= BACKEND_MAP(tmp
);
1107 WREG32(GB_TILING_CONFIG
, tiling_config
);
1108 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1109 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1111 tmp
= BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< rdev
->config
.r600
.max_backends
) & R6XX_MAX_BACKENDS_MASK
);
1112 WREG32(CC_RB_BACKEND_DISABLE
, tmp
);
1115 tmp
= INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< rdev
->config
.r600
.max_pipes
) & R6XX_MAX_PIPES_MASK
);
1116 tmp
|= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< rdev
->config
.r600
.max_simds
) & R6XX_MAX_SIMDS_MASK
);
1117 WREG32(CC_GC_SHADER_PIPE_CONFIG
, tmp
);
1118 WREG32(GC_USER_SHADER_PIPE_CONFIG
, tmp
);
1120 tmp
= R6XX_MAX_BACKENDS
- r600_count_pipe_bits(tmp
& INACTIVE_QD_PIPES_MASK
);
1121 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1122 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1124 /* Setup some CP states */
1125 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1126 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1128 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1129 SYNC_WALKER
| SYNC_ALIGNER
));
1130 /* Setup various GPU states */
1131 if (rdev
->family
== CHIP_RV670
)
1132 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1134 tmp
= RREG32(SX_DEBUG_1
);
1135 tmp
|= SMX_EVENT_RELEASE
;
1136 if ((rdev
->family
> CHIP_R600
))
1137 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1138 WREG32(SX_DEBUG_1
, tmp
);
1140 if (((rdev
->family
) == CHIP_R600
) ||
1141 ((rdev
->family
) == CHIP_RV630
) ||
1142 ((rdev
->family
) == CHIP_RV610
) ||
1143 ((rdev
->family
) == CHIP_RV620
) ||
1144 ((rdev
->family
) == CHIP_RS780
) ||
1145 ((rdev
->family
) == CHIP_RS880
)) {
1146 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1148 WREG32(DB_DEBUG
, 0);
1150 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1151 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1153 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1154 WREG32(VGT_NUM_INSTANCES
, 0);
1156 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1157 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1159 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1160 if (((rdev
->family
) == CHIP_RV610
) ||
1161 ((rdev
->family
) == CHIP_RV620
) ||
1162 ((rdev
->family
) == CHIP_RS780
) ||
1163 ((rdev
->family
) == CHIP_RS880
)) {
1164 tmp
= (CACHE_FIFO_SIZE(0xa) |
1165 FETCH_FIFO_HIWATER(0xa) |
1166 DONE_FIFO_HIWATER(0xe0) |
1167 ALU_UPDATE_FIFO_HIWATER(0x8));
1168 } else if (((rdev
->family
) == CHIP_R600
) ||
1169 ((rdev
->family
) == CHIP_RV630
)) {
1170 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1171 tmp
|= DONE_FIFO_HIWATER(0x4);
1173 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1175 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1176 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1178 sq_config
= RREG32(SQ_CONFIG
);
1179 sq_config
&= ~(PS_PRIO(3) |
1183 sq_config
|= (DX9_CONSTS
|
1190 if ((rdev
->family
) == CHIP_R600
) {
1191 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1193 NUM_CLAUSE_TEMP_GPRS(4));
1194 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1196 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1197 NUM_VS_THREADS(48) |
1200 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1201 NUM_VS_STACK_ENTRIES(128));
1202 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1203 NUM_ES_STACK_ENTRIES(0));
1204 } else if (((rdev
->family
) == CHIP_RV610
) ||
1205 ((rdev
->family
) == CHIP_RV620
) ||
1206 ((rdev
->family
) == CHIP_RS780
) ||
1207 ((rdev
->family
) == CHIP_RS880
)) {
1208 /* no vertex cache */
1209 sq_config
&= ~VC_ENABLE
;
1211 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1213 NUM_CLAUSE_TEMP_GPRS(2));
1214 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1216 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1217 NUM_VS_THREADS(78) |
1219 NUM_ES_THREADS(31));
1220 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1221 NUM_VS_STACK_ENTRIES(40));
1222 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1223 NUM_ES_STACK_ENTRIES(16));
1224 } else if (((rdev
->family
) == CHIP_RV630
) ||
1225 ((rdev
->family
) == CHIP_RV635
)) {
1226 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1228 NUM_CLAUSE_TEMP_GPRS(2));
1229 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1231 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1232 NUM_VS_THREADS(78) |
1234 NUM_ES_THREADS(31));
1235 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1236 NUM_VS_STACK_ENTRIES(40));
1237 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1238 NUM_ES_STACK_ENTRIES(16));
1239 } else if ((rdev
->family
) == CHIP_RV670
) {
1240 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1242 NUM_CLAUSE_TEMP_GPRS(2));
1243 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1245 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1246 NUM_VS_THREADS(78) |
1248 NUM_ES_THREADS(31));
1249 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1250 NUM_VS_STACK_ENTRIES(64));
1251 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1252 NUM_ES_STACK_ENTRIES(64));
1255 WREG32(SQ_CONFIG
, sq_config
);
1256 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1257 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1258 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1259 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1260 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1262 if (((rdev
->family
) == CHIP_RV610
) ||
1263 ((rdev
->family
) == CHIP_RV620
) ||
1264 ((rdev
->family
) == CHIP_RS780
) ||
1265 ((rdev
->family
) == CHIP_RS880
)) {
1266 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
1268 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
1271 /* More default values. 2D/3D driver should adjust as needed */
1272 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
1273 S1_X(0x4) | S1_Y(0xc)));
1274 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
1275 S1_X(0x2) | S1_Y(0x2) |
1276 S2_X(0xa) | S2_Y(0x6) |
1277 S3_X(0x6) | S3_Y(0xa)));
1278 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
1279 S1_X(0x4) | S1_Y(0xc) |
1280 S2_X(0x1) | S2_Y(0x6) |
1281 S3_X(0xa) | S3_Y(0xe)));
1282 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
1283 S5_X(0x0) | S5_Y(0x0) |
1284 S6_X(0xb) | S6_Y(0x4) |
1285 S7_X(0x7) | S7_Y(0x8)));
1287 WREG32(VGT_STRMOUT_EN
, 0);
1288 tmp
= rdev
->config
.r600
.max_pipes
* 16;
1289 switch (rdev
->family
) {
1305 WREG32(VGT_ES_PER_GS
, 128);
1306 WREG32(VGT_GS_PER_ES
, tmp
);
1307 WREG32(VGT_GS_PER_VS
, 2);
1308 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1310 /* more default values. 2D/3D driver should adjust as needed */
1311 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1312 WREG32(VGT_STRMOUT_EN
, 0);
1314 WREG32(PA_SC_MODE_CNTL
, 0);
1315 WREG32(PA_SC_AA_CONFIG
, 0);
1316 WREG32(PA_SC_LINE_STIPPLE
, 0);
1317 WREG32(SPI_INPUT_Z
, 0);
1318 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
1319 WREG32(CB_COLOR7_FRAG
, 0);
1321 /* Clear render buffer base addresses */
1322 WREG32(CB_COLOR0_BASE
, 0);
1323 WREG32(CB_COLOR1_BASE
, 0);
1324 WREG32(CB_COLOR2_BASE
, 0);
1325 WREG32(CB_COLOR3_BASE
, 0);
1326 WREG32(CB_COLOR4_BASE
, 0);
1327 WREG32(CB_COLOR5_BASE
, 0);
1328 WREG32(CB_COLOR6_BASE
, 0);
1329 WREG32(CB_COLOR7_BASE
, 0);
1330 WREG32(CB_COLOR7_FRAG
, 0);
1332 switch (rdev
->family
) {
1337 tmp
= TC_L2_SIZE(8);
1341 tmp
= TC_L2_SIZE(4);
1344 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
1347 tmp
= TC_L2_SIZE(0);
1350 WREG32(TC_CNTL
, tmp
);
1352 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
1353 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
1355 tmp
= RREG32(ARB_POP
);
1356 tmp
|= ENABLE_TC128
;
1357 WREG32(ARB_POP
, tmp
);
1359 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1360 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
1362 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
1367 * Indirect registers accessor
1369 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
1373 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1374 (void)RREG32(PCIE_PORT_INDEX
);
1375 r
= RREG32(PCIE_PORT_DATA
);
1379 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
1381 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1382 (void)RREG32(PCIE_PORT_INDEX
);
1383 WREG32(PCIE_PORT_DATA
, (v
));
1384 (void)RREG32(PCIE_PORT_DATA
);
1387 void r600_hdp_flush(struct radeon_device
*rdev
)
1389 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
1395 void r600_cp_stop(struct radeon_device
*rdev
)
1397 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1400 int r600_init_microcode(struct radeon_device
*rdev
)
1402 struct platform_device
*pdev
;
1403 const char *chip_name
;
1404 const char *rlc_chip_name
;
1405 size_t pfp_req_size
, me_req_size
, rlc_req_size
;
1411 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
1414 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
1418 switch (rdev
->family
) {
1421 rlc_chip_name
= "R600";
1424 chip_name
= "RV610";
1425 rlc_chip_name
= "R600";
1428 chip_name
= "RV630";
1429 rlc_chip_name
= "R600";
1432 chip_name
= "RV620";
1433 rlc_chip_name
= "R600";
1436 chip_name
= "RV635";
1437 rlc_chip_name
= "R600";
1440 chip_name
= "RV670";
1441 rlc_chip_name
= "R600";
1445 chip_name
= "RS780";
1446 rlc_chip_name
= "R600";
1449 chip_name
= "RV770";
1450 rlc_chip_name
= "R700";
1454 chip_name
= "RV730";
1455 rlc_chip_name
= "R700";
1458 chip_name
= "RV710";
1459 rlc_chip_name
= "R700";
1464 if (rdev
->family
>= CHIP_RV770
) {
1465 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
1466 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
1467 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
1469 pfp_req_size
= PFP_UCODE_SIZE
* 4;
1470 me_req_size
= PM4_UCODE_SIZE
* 12;
1471 rlc_req_size
= RLC_UCODE_SIZE
* 4;
1474 DRM_INFO("Loading %s Microcode\n", chip_name
);
1476 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
1477 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
1480 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
1482 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1483 rdev
->pfp_fw
->size
, fw_name
);
1488 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
1489 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
1492 if (rdev
->me_fw
->size
!= me_req_size
) {
1494 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1495 rdev
->me_fw
->size
, fw_name
);
1499 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
1500 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
1503 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
1505 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1506 rdev
->rlc_fw
->size
, fw_name
);
1511 platform_device_unregister(pdev
);
1516 "r600_cp: Failed to load firmware \"%s\"\n",
1518 release_firmware(rdev
->pfp_fw
);
1519 rdev
->pfp_fw
= NULL
;
1520 release_firmware(rdev
->me_fw
);
1522 release_firmware(rdev
->rlc_fw
);
1523 rdev
->rlc_fw
= NULL
;
1528 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
1530 const __be32
*fw_data
;
1533 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1538 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
1541 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
1542 RREG32(GRBM_SOFT_RESET
);
1544 WREG32(GRBM_SOFT_RESET
, 0);
1546 WREG32(CP_ME_RAM_WADDR
, 0);
1548 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1549 WREG32(CP_ME_RAM_WADDR
, 0);
1550 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
1551 WREG32(CP_ME_RAM_DATA
,
1552 be32_to_cpup(fw_data
++));
1554 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1555 WREG32(CP_PFP_UCODE_ADDR
, 0);
1556 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
1557 WREG32(CP_PFP_UCODE_DATA
,
1558 be32_to_cpup(fw_data
++));
1560 WREG32(CP_PFP_UCODE_ADDR
, 0);
1561 WREG32(CP_ME_RAM_WADDR
, 0);
1562 WREG32(CP_ME_RAM_RADDR
, 0);
1566 int r600_cp_start(struct radeon_device
*rdev
)
1571 r
= radeon_ring_lock(rdev
, 7);
1573 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1576 radeon_ring_write(rdev
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1577 radeon_ring_write(rdev
, 0x1);
1578 if (rdev
->family
< CHIP_RV770
) {
1579 radeon_ring_write(rdev
, 0x3);
1580 radeon_ring_write(rdev
, rdev
->config
.r600
.max_hw_contexts
- 1);
1582 radeon_ring_write(rdev
, 0x0);
1583 radeon_ring_write(rdev
, rdev
->config
.rv770
.max_hw_contexts
- 1);
1585 radeon_ring_write(rdev
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1586 radeon_ring_write(rdev
, 0);
1587 radeon_ring_write(rdev
, 0);
1588 radeon_ring_unlock_commit(rdev
);
1591 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
1595 int r600_cp_resume(struct radeon_device
*rdev
)
1602 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
1603 RREG32(GRBM_SOFT_RESET
);
1605 WREG32(GRBM_SOFT_RESET
, 0);
1607 /* Set ring buffer size */
1608 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
1609 tmp
= RB_NO_UPDATE
| (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
1611 tmp
|= BUF_SWAP_32BIT
;
1613 WREG32(CP_RB_CNTL
, tmp
);
1614 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
1616 /* Set the write pointer delay */
1617 WREG32(CP_RB_WPTR_DELAY
, 0);
1619 /* Initialize the ring buffer's read and write pointers */
1620 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
1621 WREG32(CP_RB_RPTR_WR
, 0);
1622 WREG32(CP_RB_WPTR
, 0);
1623 WREG32(CP_RB_RPTR_ADDR
, rdev
->cp
.gpu_addr
& 0xFFFFFFFF);
1624 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->cp
.gpu_addr
));
1626 WREG32(CP_RB_CNTL
, tmp
);
1628 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
1629 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
1631 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
1632 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
1634 r600_cp_start(rdev
);
1635 rdev
->cp
.ready
= true;
1636 r
= radeon_ring_test(rdev
);
1638 rdev
->cp
.ready
= false;
1644 void r600_cp_commit(struct radeon_device
*rdev
)
1646 WREG32(CP_RB_WPTR
, rdev
->cp
.wptr
);
1647 (void)RREG32(CP_RB_WPTR
);
1650 void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
1654 /* Align ring size */
1655 rb_bufsz
= drm_order(ring_size
/ 8);
1656 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
1657 rdev
->cp
.ring_size
= ring_size
;
1658 rdev
->cp
.align_mask
= 16 - 1;
1663 * GPU scratch registers helpers function.
1665 void r600_scratch_init(struct radeon_device
*rdev
)
1669 rdev
->scratch
.num_reg
= 7;
1670 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
1671 rdev
->scratch
.free
[i
] = true;
1672 rdev
->scratch
.reg
[i
] = SCRATCH_REG0
+ (i
* 4);
1676 int r600_ring_test(struct radeon_device
*rdev
)
1683 r
= radeon_scratch_get(rdev
, &scratch
);
1685 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
1688 WREG32(scratch
, 0xCAFEDEAD);
1689 r
= radeon_ring_lock(rdev
, 3);
1691 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1692 radeon_scratch_free(rdev
, scratch
);
1695 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1696 radeon_ring_write(rdev
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
1697 radeon_ring_write(rdev
, 0xDEADBEEF);
1698 radeon_ring_unlock_commit(rdev
);
1699 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1700 tmp
= RREG32(scratch
);
1701 if (tmp
== 0xDEADBEEF)
1705 if (i
< rdev
->usec_timeout
) {
1706 DRM_INFO("ring test succeeded in %d usecs\n", i
);
1708 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1712 radeon_scratch_free(rdev
, scratch
);
1716 void r600_wb_disable(struct radeon_device
*rdev
)
1720 WREG32(SCRATCH_UMSK
, 0);
1721 if (rdev
->wb
.wb_obj
) {
1722 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
1723 if (unlikely(r
!= 0))
1725 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
1726 radeon_bo_unpin(rdev
->wb
.wb_obj
);
1727 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
1731 void r600_wb_fini(struct radeon_device
*rdev
)
1733 r600_wb_disable(rdev
);
1734 if (rdev
->wb
.wb_obj
) {
1735 radeon_bo_unref(&rdev
->wb
.wb_obj
);
1737 rdev
->wb
.wb_obj
= NULL
;
1741 int r600_wb_enable(struct radeon_device
*rdev
)
1745 if (rdev
->wb
.wb_obj
== NULL
) {
1746 r
= radeon_bo_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
, true,
1747 RADEON_GEM_DOMAIN_GTT
, &rdev
->wb
.wb_obj
);
1749 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
1752 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
1753 if (unlikely(r
!= 0)) {
1757 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
1758 &rdev
->wb
.gpu_addr
);
1760 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
1761 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
1765 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
1766 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
1768 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
1773 WREG32(SCRATCH_ADDR
, (rdev
->wb
.gpu_addr
>> 8) & 0xFFFFFFFF);
1774 WREG32(CP_RB_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ 1024) & 0xFFFFFFFC);
1775 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ 1024) & 0xFF);
1776 WREG32(SCRATCH_UMSK
, 0xff);
1780 void r600_fence_ring_emit(struct radeon_device
*rdev
,
1781 struct radeon_fence
*fence
)
1783 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1784 /* Emit fence sequence & fire IRQ */
1785 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1786 radeon_ring_write(rdev
, ((rdev
->fence_drv
.scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
1787 radeon_ring_write(rdev
, fence
->seq
);
1788 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1789 radeon_ring_write(rdev
, PACKET0(CP_INT_STATUS
, 0));
1790 radeon_ring_write(rdev
, RB_INT_STAT
);
1793 int r600_copy_dma(struct radeon_device
*rdev
,
1794 uint64_t src_offset
,
1795 uint64_t dst_offset
,
1797 struct radeon_fence
*fence
)
1799 /* FIXME: implement */
1803 int r600_copy_blit(struct radeon_device
*rdev
,
1804 uint64_t src_offset
, uint64_t dst_offset
,
1805 unsigned num_pages
, struct radeon_fence
*fence
)
1807 r600_blit_prepare_copy(rdev
, num_pages
* RADEON_GPU_PAGE_SIZE
);
1808 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_pages
* RADEON_GPU_PAGE_SIZE
);
1809 r600_blit_done_copy(rdev
, fence
);
1813 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
1814 uint32_t tiling_flags
, uint32_t pitch
,
1815 uint32_t offset
, uint32_t obj_size
)
1817 /* FIXME: implement */
1821 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
1823 /* FIXME: implement */
1827 bool r600_card_posted(struct radeon_device
*rdev
)
1831 /* first check CRTCs */
1832 reg
= RREG32(D1CRTC_CONTROL
) |
1833 RREG32(D2CRTC_CONTROL
);
1837 /* then check MEM_SIZE, in case the crtcs are off */
1838 if (RREG32(CONFIG_MEMSIZE
))
1844 int r600_startup(struct radeon_device
*rdev
)
1848 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
1849 r
= r600_init_microcode(rdev
);
1851 DRM_ERROR("Failed to load firmware!\n");
1856 r600_mc_program(rdev
);
1857 if (rdev
->flags
& RADEON_IS_AGP
) {
1858 r600_agp_enable(rdev
);
1860 r
= r600_pcie_gart_enable(rdev
);
1864 r600_gpu_init(rdev
);
1866 if (!rdev
->r600_blit
.shader_obj
) {
1867 r
= r600_blit_init(rdev
);
1869 DRM_ERROR("radeon: failed blitter (%d).\n", r
);
1874 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1875 if (unlikely(r
!= 0))
1877 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
1878 &rdev
->r600_blit
.shader_gpu_addr
);
1879 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1881 dev_err(rdev
->dev
, "(%d) pin blit object failed\n", r
);
1886 r
= r600_irq_init(rdev
);
1888 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
1889 radeon_irq_kms_fini(rdev
);
1894 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
1897 r
= r600_cp_load_microcode(rdev
);
1900 r
= r600_cp_resume(rdev
);
1903 /* write back buffer are not vital so don't worry about failure */
1904 r600_wb_enable(rdev
);
1908 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
1912 temp
= RREG32(CONFIG_CNTL
);
1913 if (state
== false) {
1919 WREG32(CONFIG_CNTL
, temp
);
1922 int r600_resume(struct radeon_device
*rdev
)
1926 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1927 * posting will perform necessary task to bring back GPU into good
1931 atom_asic_init(rdev
->mode_info
.atom_context
);
1932 /* Initialize clocks */
1933 r
= radeon_clocks_init(rdev
);
1938 r
= r600_startup(rdev
);
1940 DRM_ERROR("r600 startup failed on resume\n");
1944 r
= r600_ib_test(rdev
);
1946 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
1952 int r600_suspend(struct radeon_device
*rdev
)
1956 /* FIXME: we should wait for ring to be empty */
1958 rdev
->cp
.ready
= false;
1959 r600_wb_disable(rdev
);
1960 r600_pcie_gart_disable(rdev
);
1961 /* unpin shaders bo */
1962 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1963 if (unlikely(r
!= 0))
1965 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
1966 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1970 /* Plan is to move initialization in that function and use
1971 * helper function so that radeon_device_init pretty much
1972 * do nothing more than calling asic specific function. This
1973 * should also allow to remove a bunch of callback function
1976 int r600_init(struct radeon_device
*rdev
)
1980 r
= radeon_dummy_page_init(rdev
);
1983 if (r600_debugfs_mc_info_init(rdev
)) {
1984 DRM_ERROR("Failed to register debugfs file for mc !\n");
1986 /* This don't do much */
1987 r
= radeon_gem_init(rdev
);
1991 if (!radeon_get_bios(rdev
)) {
1992 if (ASIC_IS_AVIVO(rdev
))
1995 /* Must be an ATOMBIOS */
1996 if (!rdev
->is_atom_bios
) {
1997 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2000 r
= radeon_atombios_init(rdev
);
2003 /* Post card if necessary */
2004 if (!r600_card_posted(rdev
)) {
2006 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2009 DRM_INFO("GPU not posted. posting now...\n");
2010 atom_asic_init(rdev
->mode_info
.atom_context
);
2012 /* Initialize scratch registers */
2013 r600_scratch_init(rdev
);
2014 /* Initialize surface registers */
2015 radeon_surface_init(rdev
);
2016 /* Initialize clocks */
2017 radeon_get_clock_info(rdev
->ddev
);
2018 r
= radeon_clocks_init(rdev
);
2021 /* Initialize power management */
2022 radeon_pm_init(rdev
);
2024 r
= radeon_fence_driver_init(rdev
);
2027 r
= r600_mc_init(rdev
);
2030 /* Memory manager */
2031 r
= radeon_bo_init(rdev
);
2035 r
= radeon_irq_kms_init(rdev
);
2039 rdev
->cp
.ring_obj
= NULL
;
2040 r600_ring_init(rdev
, 1024 * 1024);
2042 rdev
->ih
.ring_obj
= NULL
;
2043 r600_ih_ring_init(rdev
, 64 * 1024);
2045 r
= r600_pcie_gart_init(rdev
);
2049 rdev
->accel_working
= true;
2050 r
= r600_startup(rdev
);
2054 radeon_ring_fini(rdev
);
2055 r600_pcie_gart_fini(rdev
);
2056 rdev
->accel_working
= false;
2058 if (rdev
->accel_working
) {
2059 r
= radeon_ib_pool_init(rdev
);
2061 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r
);
2062 rdev
->accel_working
= false;
2064 r
= r600_ib_test(rdev
);
2066 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
2067 rdev
->accel_working
= false;
2071 r
= r600_audio_init(rdev
);
2073 return r
; /* TODO error handling */
2077 void r600_fini(struct radeon_device
*rdev
)
2079 /* Suspend operations */
2082 r600_audio_fini(rdev
);
2083 r600_blit_fini(rdev
);
2084 r600_irq_fini(rdev
);
2085 radeon_irq_kms_fini(rdev
);
2086 radeon_ring_fini(rdev
);
2088 r600_pcie_gart_fini(rdev
);
2089 radeon_gem_fini(rdev
);
2090 radeon_fence_driver_fini(rdev
);
2091 radeon_clocks_fini(rdev
);
2092 if (rdev
->flags
& RADEON_IS_AGP
)
2093 radeon_agp_fini(rdev
);
2094 radeon_bo_fini(rdev
);
2095 radeon_atombios_fini(rdev
);
2098 radeon_dummy_page_fini(rdev
);
2105 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2107 /* FIXME: implement */
2108 radeon_ring_write(rdev
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2109 radeon_ring_write(rdev
, ib
->gpu_addr
& 0xFFFFFFFC);
2110 radeon_ring_write(rdev
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
2111 radeon_ring_write(rdev
, ib
->length_dw
);
2114 int r600_ib_test(struct radeon_device
*rdev
)
2116 struct radeon_ib
*ib
;
2122 r
= radeon_scratch_get(rdev
, &scratch
);
2124 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
2127 WREG32(scratch
, 0xCAFEDEAD);
2128 r
= radeon_ib_get(rdev
, &ib
);
2130 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
2133 ib
->ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
2134 ib
->ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2135 ib
->ptr
[2] = 0xDEADBEEF;
2136 ib
->ptr
[3] = PACKET2(0);
2137 ib
->ptr
[4] = PACKET2(0);
2138 ib
->ptr
[5] = PACKET2(0);
2139 ib
->ptr
[6] = PACKET2(0);
2140 ib
->ptr
[7] = PACKET2(0);
2141 ib
->ptr
[8] = PACKET2(0);
2142 ib
->ptr
[9] = PACKET2(0);
2143 ib
->ptr
[10] = PACKET2(0);
2144 ib
->ptr
[11] = PACKET2(0);
2145 ib
->ptr
[12] = PACKET2(0);
2146 ib
->ptr
[13] = PACKET2(0);
2147 ib
->ptr
[14] = PACKET2(0);
2148 ib
->ptr
[15] = PACKET2(0);
2150 r
= radeon_ib_schedule(rdev
, ib
);
2152 radeon_scratch_free(rdev
, scratch
);
2153 radeon_ib_free(rdev
, &ib
);
2154 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
2157 r
= radeon_fence_wait(ib
->fence
, false);
2159 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
2162 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2163 tmp
= RREG32(scratch
);
2164 if (tmp
== 0xDEADBEEF)
2168 if (i
< rdev
->usec_timeout
) {
2169 DRM_INFO("ib test succeeded in %u usecs\n", i
);
2171 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2175 radeon_scratch_free(rdev
, scratch
);
2176 radeon_ib_free(rdev
, &ib
);
2183 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2184 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2185 * writing to the ring and the GPU consuming, the GPU writes to the ring
2186 * and host consumes. As the host irq handler processes interrupts, it
2187 * increments the rptr. When the rptr catches up with the wptr, all the
2188 * current interrupts have been processed.
2191 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2195 /* Align ring size */
2196 rb_bufsz
= drm_order(ring_size
/ 4);
2197 ring_size
= (1 << rb_bufsz
) * 4;
2198 rdev
->ih
.ring_size
= ring_size
;
2199 rdev
->ih
.align_mask
= 4 - 1;
2202 static int r600_ih_ring_alloc(struct radeon_device
*rdev
, unsigned ring_size
)
2206 rdev
->ih
.ring_size
= ring_size
;
2207 /* Allocate ring buffer */
2208 if (rdev
->ih
.ring_obj
== NULL
) {
2209 r
= radeon_bo_create(rdev
, NULL
, rdev
->ih
.ring_size
,
2211 RADEON_GEM_DOMAIN_GTT
,
2212 &rdev
->ih
.ring_obj
);
2214 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
2217 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2218 if (unlikely(r
!= 0))
2220 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
2221 RADEON_GEM_DOMAIN_GTT
,
2222 &rdev
->ih
.gpu_addr
);
2224 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2225 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
2228 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
2229 (void **)&rdev
->ih
.ring
);
2230 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2232 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
2236 rdev
->ih
.ptr_mask
= (rdev
->cp
.ring_size
/ 4) - 1;
2242 static void r600_ih_ring_fini(struct radeon_device
*rdev
)
2245 if (rdev
->ih
.ring_obj
) {
2246 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2247 if (likely(r
== 0)) {
2248 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
2249 radeon_bo_unpin(rdev
->ih
.ring_obj
);
2250 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2252 radeon_bo_unref(&rdev
->ih
.ring_obj
);
2253 rdev
->ih
.ring
= NULL
;
2254 rdev
->ih
.ring_obj
= NULL
;
2258 static void r600_rlc_stop(struct radeon_device
*rdev
)
2261 if (rdev
->family
>= CHIP_RV770
) {
2262 /* r7xx asics need to soft reset RLC before halting */
2263 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
2264 RREG32(SRBM_SOFT_RESET
);
2266 WREG32(SRBM_SOFT_RESET
, 0);
2267 RREG32(SRBM_SOFT_RESET
);
2270 WREG32(RLC_CNTL
, 0);
2273 static void r600_rlc_start(struct radeon_device
*rdev
)
2275 WREG32(RLC_CNTL
, RLC_ENABLE
);
2278 static int r600_rlc_init(struct radeon_device
*rdev
)
2281 const __be32
*fw_data
;
2286 r600_rlc_stop(rdev
);
2288 WREG32(RLC_HB_BASE
, 0);
2289 WREG32(RLC_HB_CNTL
, 0);
2290 WREG32(RLC_HB_RPTR
, 0);
2291 WREG32(RLC_HB_WPTR
, 0);
2292 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
2293 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
2294 WREG32(RLC_MC_CNTL
, 0);
2295 WREG32(RLC_UCODE_CNTL
, 0);
2297 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
2298 if (rdev
->family
>= CHIP_RV770
) {
2299 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
2300 WREG32(RLC_UCODE_ADDR
, i
);
2301 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2304 for (i
= 0; i
< RLC_UCODE_SIZE
; i
++) {
2305 WREG32(RLC_UCODE_ADDR
, i
);
2306 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2309 WREG32(RLC_UCODE_ADDR
, 0);
2311 r600_rlc_start(rdev
);
2316 static void r600_enable_interrupts(struct radeon_device
*rdev
)
2318 u32 ih_cntl
= RREG32(IH_CNTL
);
2319 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2321 ih_cntl
|= ENABLE_INTR
;
2322 ih_rb_cntl
|= IH_RB_ENABLE
;
2323 WREG32(IH_CNTL
, ih_cntl
);
2324 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2325 rdev
->ih
.enabled
= true;
2328 static void r600_disable_interrupts(struct radeon_device
*rdev
)
2330 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2331 u32 ih_cntl
= RREG32(IH_CNTL
);
2333 ih_rb_cntl
&= ~IH_RB_ENABLE
;
2334 ih_cntl
&= ~ENABLE_INTR
;
2335 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2336 WREG32(IH_CNTL
, ih_cntl
);
2337 /* set rptr, wptr to 0 */
2338 WREG32(IH_RB_RPTR
, 0);
2339 WREG32(IH_RB_WPTR
, 0);
2340 rdev
->ih
.enabled
= false;
2345 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
2349 WREG32(CP_INT_CNTL
, 0);
2350 WREG32(GRBM_INT_CNTL
, 0);
2351 WREG32(DxMODE_INT_MASK
, 0);
2352 if (ASIC_IS_DCE3(rdev
)) {
2353 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
2354 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
2355 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2356 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2357 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2358 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2359 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2360 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2361 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2362 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2363 if (ASIC_IS_DCE32(rdev
)) {
2364 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2365 WREG32(DC_HPD5_INT_CONTROL
, 0);
2366 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2367 WREG32(DC_HPD6_INT_CONTROL
, 0);
2370 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2371 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2372 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2373 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, 0);
2374 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2375 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, 0);
2376 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2377 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, 0);
2381 int r600_irq_init(struct radeon_device
*rdev
)
2385 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
2388 ret
= r600_ih_ring_alloc(rdev
, rdev
->ih
.ring_size
);
2393 r600_disable_interrupts(rdev
);
2396 ret
= r600_rlc_init(rdev
);
2398 r600_ih_ring_fini(rdev
);
2402 /* setup interrupt control */
2403 /* set dummy read address to ring address */
2404 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
2405 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
2406 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2407 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2409 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
2410 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2411 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
2412 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
2414 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
2415 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
2417 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
2418 IH_WPTR_OVERFLOW_CLEAR
|
2420 /* WPTR writeback, not yet */
2421 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2422 WREG32(IH_RB_WPTR_ADDR_LO
, 0);
2423 WREG32(IH_RB_WPTR_ADDR_HI
, 0);
2425 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2427 /* set rptr, wptr to 0 */
2428 WREG32(IH_RB_RPTR
, 0);
2429 WREG32(IH_RB_WPTR
, 0);
2431 /* Default settings for IH_CNTL (disabled at first) */
2432 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2433 /* RPTR_REARM only works if msi's are enabled */
2434 if (rdev
->msi_enabled
)
2435 ih_cntl
|= RPTR_REARM
;
2438 ih_cntl
|= IH_MC_SWAP(IH_MC_SWAP_32BIT
);
2440 WREG32(IH_CNTL
, ih_cntl
);
2442 /* force the active interrupt state to all disabled */
2443 r600_disable_interrupt_state(rdev
);
2446 r600_enable_interrupts(rdev
);
2451 void r600_irq_fini(struct radeon_device
*rdev
)
2453 r600_disable_interrupts(rdev
);
2454 r600_rlc_stop(rdev
);
2455 r600_ih_ring_fini(rdev
);
2458 int r600_irq_set(struct radeon_device
*rdev
)
2460 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2462 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
2464 /* don't enable anything if the ih is disabled */
2465 if (!rdev
->ih
.enabled
)
2468 if (ASIC_IS_DCE3(rdev
)) {
2469 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2470 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2471 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2472 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2473 if (ASIC_IS_DCE32(rdev
)) {
2474 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2475 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2478 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2479 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2480 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2483 if (rdev
->irq
.sw_int
) {
2484 DRM_DEBUG("r600_irq_set: sw int\n");
2485 cp_int_cntl
|= RB_INT_ENABLE
;
2487 if (rdev
->irq
.crtc_vblank_int
[0]) {
2488 DRM_DEBUG("r600_irq_set: vblank 0\n");
2489 mode_int
|= D1MODE_VBLANK_INT_MASK
;
2491 if (rdev
->irq
.crtc_vblank_int
[1]) {
2492 DRM_DEBUG("r600_irq_set: vblank 1\n");
2493 mode_int
|= D2MODE_VBLANK_INT_MASK
;
2495 if (rdev
->irq
.hpd
[0]) {
2496 DRM_DEBUG("r600_irq_set: hpd 1\n");
2497 hpd1
|= DC_HPDx_INT_EN
;
2499 if (rdev
->irq
.hpd
[1]) {
2500 DRM_DEBUG("r600_irq_set: hpd 2\n");
2501 hpd2
|= DC_HPDx_INT_EN
;
2503 if (rdev
->irq
.hpd
[2]) {
2504 DRM_DEBUG("r600_irq_set: hpd 3\n");
2505 hpd3
|= DC_HPDx_INT_EN
;
2507 if (rdev
->irq
.hpd
[3]) {
2508 DRM_DEBUG("r600_irq_set: hpd 4\n");
2509 hpd4
|= DC_HPDx_INT_EN
;
2511 if (rdev
->irq
.hpd
[4]) {
2512 DRM_DEBUG("r600_irq_set: hpd 5\n");
2513 hpd5
|= DC_HPDx_INT_EN
;
2515 if (rdev
->irq
.hpd
[5]) {
2516 DRM_DEBUG("r600_irq_set: hpd 6\n");
2517 hpd6
|= DC_HPDx_INT_EN
;
2520 WREG32(CP_INT_CNTL
, cp_int_cntl
);
2521 WREG32(DxMODE_INT_MASK
, mode_int
);
2522 if (ASIC_IS_DCE3(rdev
)) {
2523 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
2524 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
2525 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
2526 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
2527 if (ASIC_IS_DCE32(rdev
)) {
2528 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
2529 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
2532 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
2533 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
2534 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
2540 static inline void r600_irq_ack(struct radeon_device
*rdev
,
2543 u32
*disp_int_cont2
)
2547 if (ASIC_IS_DCE3(rdev
)) {
2548 *disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
2549 *disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
2550 *disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
2552 *disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
2553 *disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
2554 *disp_int_cont2
= 0;
2557 if (*disp_int
& LB_D1_VBLANK_INTERRUPT
)
2558 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
2559 if (*disp_int
& LB_D1_VLINE_INTERRUPT
)
2560 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
2561 if (*disp_int
& LB_D2_VBLANK_INTERRUPT
)
2562 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
2563 if (*disp_int
& LB_D2_VLINE_INTERRUPT
)
2564 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
2565 if (*disp_int
& DC_HPD1_INTERRUPT
) {
2566 if (ASIC_IS_DCE3(rdev
)) {
2567 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
2568 tmp
|= DC_HPDx_INT_ACK
;
2569 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2571 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
2572 tmp
|= DC_HPDx_INT_ACK
;
2573 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
2576 if (*disp_int
& DC_HPD2_INTERRUPT
) {
2577 if (ASIC_IS_DCE3(rdev
)) {
2578 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
2579 tmp
|= DC_HPDx_INT_ACK
;
2580 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2582 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
2583 tmp
|= DC_HPDx_INT_ACK
;
2584 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
2587 if (*disp_int_cont
& DC_HPD3_INTERRUPT
) {
2588 if (ASIC_IS_DCE3(rdev
)) {
2589 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
2590 tmp
|= DC_HPDx_INT_ACK
;
2591 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2593 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
2594 tmp
|= DC_HPDx_INT_ACK
;
2595 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
2598 if (*disp_int_cont
& DC_HPD4_INTERRUPT
) {
2599 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
2600 tmp
|= DC_HPDx_INT_ACK
;
2601 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2603 if (ASIC_IS_DCE32(rdev
)) {
2604 if (*disp_int_cont2
& DC_HPD5_INTERRUPT
) {
2605 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2606 tmp
|= DC_HPDx_INT_ACK
;
2607 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2609 if (*disp_int_cont2
& DC_HPD6_INTERRUPT
) {
2610 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
2611 tmp
|= DC_HPDx_INT_ACK
;
2612 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2617 void r600_irq_disable(struct radeon_device
*rdev
)
2619 u32 disp_int
, disp_int_cont
, disp_int_cont2
;
2621 r600_disable_interrupts(rdev
);
2622 /* Wait and acknowledge irq */
2624 r600_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
);
2625 r600_disable_interrupt_state(rdev
);
2628 static inline u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
2632 /* XXX use writeback */
2633 wptr
= RREG32(IH_RB_WPTR
);
2635 if (wptr
& RB_OVERFLOW
) {
2637 /* XXX deal with overflow */
2638 DRM_ERROR("IH RB overflow\n");
2639 tmp
= RREG32(IH_RB_CNTL
);
2640 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
2641 WREG32(IH_RB_CNTL
, tmp
);
2643 wptr
= wptr
& WPTR_OFFSET_MASK
;
2649 * Each IV ring entry is 128 bits:
2650 * [7:0] - interrupt source id
2652 * [59:32] - interrupt source data
2653 * [127:60] - reserved
2655 * The basic interrupt vector entries
2656 * are decoded as follows:
2657 * src_id src_data description
2662 * 19 0 FP Hot plug detection A
2663 * 19 1 FP Hot plug detection B
2664 * 19 2 DAC A auto-detection
2665 * 19 3 DAC B auto-detection
2669 * 181 - EOP Interrupt
2672 * Note, these are based on r600 and may need to be
2673 * adjusted or added to on newer asics
2676 int r600_irq_process(struct radeon_device
*rdev
)
2678 u32 wptr
= r600_get_ih_wptr(rdev
);
2679 u32 rptr
= rdev
->ih
.rptr
;
2680 u32 src_id
, src_data
;
2681 u32 last_entry
= rdev
->ih
.ring_size
- 16;
2682 u32 ring_index
, disp_int
, disp_int_cont
, disp_int_cont2
;
2683 unsigned long flags
;
2684 bool queue_hotplug
= false;
2686 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
2688 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
2691 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2694 if (rdev
->shutdown
) {
2695 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2700 /* display interrupts */
2701 r600_irq_ack(rdev
, &disp_int
, &disp_int_cont
, &disp_int_cont2
);
2703 rdev
->ih
.wptr
= wptr
;
2704 while (rptr
!= wptr
) {
2705 /* wptr/rptr are in bytes! */
2706 ring_index
= rptr
/ 4;
2707 src_id
= rdev
->ih
.ring
[ring_index
] & 0xff;
2708 src_data
= rdev
->ih
.ring
[ring_index
+ 1] & 0xfffffff;
2711 case 1: /* D1 vblank/vline */
2713 case 0: /* D1 vblank */
2714 if (disp_int
& LB_D1_VBLANK_INTERRUPT
) {
2715 drm_handle_vblank(rdev
->ddev
, 0);
2716 disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
2717 DRM_DEBUG("IH: D1 vblank\n");
2720 case 1: /* D1 vline */
2721 if (disp_int
& LB_D1_VLINE_INTERRUPT
) {
2722 disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
2723 DRM_DEBUG("IH: D1 vline\n");
2727 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2731 case 5: /* D2 vblank/vline */
2733 case 0: /* D2 vblank */
2734 if (disp_int
& LB_D2_VBLANK_INTERRUPT
) {
2735 drm_handle_vblank(rdev
->ddev
, 1);
2736 disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
2737 DRM_DEBUG("IH: D2 vblank\n");
2740 case 1: /* D1 vline */
2741 if (disp_int
& LB_D2_VLINE_INTERRUPT
) {
2742 disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
2743 DRM_DEBUG("IH: D2 vline\n");
2747 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2751 case 19: /* HPD/DAC hotplug */
2754 if (disp_int
& DC_HPD1_INTERRUPT
) {
2755 disp_int
&= ~DC_HPD1_INTERRUPT
;
2756 queue_hotplug
= true;
2757 DRM_DEBUG("IH: HPD1\n");
2761 if (disp_int
& DC_HPD2_INTERRUPT
) {
2762 disp_int
&= ~DC_HPD2_INTERRUPT
;
2763 queue_hotplug
= true;
2764 DRM_DEBUG("IH: HPD2\n");
2768 if (disp_int_cont
& DC_HPD3_INTERRUPT
) {
2769 disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
2770 queue_hotplug
= true;
2771 DRM_DEBUG("IH: HPD3\n");
2775 if (disp_int_cont
& DC_HPD4_INTERRUPT
) {
2776 disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
2777 queue_hotplug
= true;
2778 DRM_DEBUG("IH: HPD4\n");
2782 if (disp_int_cont2
& DC_HPD5_INTERRUPT
) {
2783 disp_int_cont
&= ~DC_HPD5_INTERRUPT
;
2784 queue_hotplug
= true;
2785 DRM_DEBUG("IH: HPD5\n");
2789 if (disp_int_cont2
& DC_HPD6_INTERRUPT
) {
2790 disp_int_cont
&= ~DC_HPD6_INTERRUPT
;
2791 queue_hotplug
= true;
2792 DRM_DEBUG("IH: HPD6\n");
2796 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2800 case 176: /* CP_INT in ring buffer */
2801 case 177: /* CP_INT in IB1 */
2802 case 178: /* CP_INT in IB2 */
2803 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
2804 radeon_fence_process(rdev
);
2806 case 181: /* CP EOP event */
2807 DRM_DEBUG("IH: CP EOP\n");
2810 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
2814 /* wptr/rptr are in bytes! */
2815 if (rptr
== last_entry
)
2820 /* make sure wptr hasn't changed while processing */
2821 wptr
= r600_get_ih_wptr(rdev
);
2822 if (wptr
!= rdev
->ih
.wptr
)
2825 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
2826 rdev
->ih
.rptr
= rptr
;
2827 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
2828 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
2835 #if defined(CONFIG_DEBUG_FS)
2837 static int r600_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
2839 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2840 struct drm_device
*dev
= node
->minor
->dev
;
2841 struct radeon_device
*rdev
= dev
->dev_private
;
2842 unsigned count
, i
, j
;
2844 radeon_ring_free_size(rdev
);
2845 count
= (rdev
->cp
.ring_size
/ 4) - rdev
->cp
.ring_free_dw
;
2846 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(CP_STAT
));
2847 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR
));
2848 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR
));
2849 seq_printf(m
, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev
->cp
.wptr
);
2850 seq_printf(m
, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev
->cp
.rptr
);
2851 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
2852 seq_printf(m
, "%u dwords in ring\n", count
);
2854 for (j
= 0; j
<= count
; j
++) {
2855 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
2856 i
= (i
+ 1) & rdev
->cp
.ptr_mask
;
2861 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
2863 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2864 struct drm_device
*dev
= node
->minor
->dev
;
2865 struct radeon_device
*rdev
= dev
->dev_private
;
2867 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
2868 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
2872 static struct drm_info_list r600_mc_info_list
[] = {
2873 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
2874 {"r600_ring_info", r600_debugfs_cp_ring_info
, 0, NULL
},
2878 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
2880 #if defined(CONFIG_DEBUG_FS)
2881 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));