projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/radeon: move radeon_ib_ring_tests out of chipset code
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
33 #include "drmP.h"
34 #include "radeon_drm.h"
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
38 #include "r600d.h"
39 #include "atom.h"
40 #include "avivod.h"
41
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
53
54 /* Firmware Names */
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
96
97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
98
99 /* r600,rv610,rv630,rv620,rv635,rv670 */
100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
101 void r600_gpu_init(struct radeon_device *rdev);
102 void r600_fini(struct radeon_device *rdev);
103 void r600_irq_disable(struct radeon_device *rdev);
104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
105
106 /* get temperature in millidegrees */
107 int rv6xx_get_temp(struct radeon_device *rdev)
108 {
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 ASIC_T_SHIFT;
111 int actual_temp = temp & 0xff;
112
113 if (temp & 0x100)
114 actual_temp -= 256;
115
116 return actual_temp * 1000;
117 }
118
119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
120 {
121 int i;
122
123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
125
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
129
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
132
133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
137 rdev->pm.dynpm_can_downclock = false;
138 break;
139 case DYNPM_ACTION_DOWNCLOCK:
140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
142 rdev->pm.dynpm_can_downclock = false;
143 } else {
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
147 continue;
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
151 break;
152 } else {
153 rdev->pm.requested_power_state_index = i;
154 break;
155 }
156 }
157 } else {
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
161 else
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
164 }
165 }
166 rdev->pm.requested_clock_mode_index = 0;
167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
173 }
174 break;
175 case DYNPM_ACTION_UPCLOCK:
176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
178 rdev->pm.dynpm_can_upclock = false;
179 } else {
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
183 continue;
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
187 break;
188 } else {
189 rdev->pm.requested_power_state_index = i;
190 break;
191 }
192 }
193 } else
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
196 }
197 rdev->pm.requested_clock_mode_index = 0;
198 break;
199 case DYNPM_ACTION_DEFAULT:
200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
202 rdev->pm.dynpm_can_upclock = false;
203 break;
204 case DYNPM_ACTION_NONE:
205 default:
206 DRM_ERROR("Requested mode for not defined action\n");
207 return;
208 }
209 } else {
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
218 continue;
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
222 break;
223 }
224 }
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
228 } else
229 rdev->pm.requested_power_state_index = 1;
230
231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
233 rdev->pm.requested_clock_mode_index = 0;
234 rdev->pm.dynpm_can_downclock = false;
235 break;
236 case DYNPM_ACTION_DOWNCLOCK:
237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
240 rdev->pm.dynpm_can_downclock = false;
241 } else
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
244 } else {
245 rdev->pm.requested_clock_mode_index = 0;
246 rdev->pm.dynpm_can_downclock = false;
247 }
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
254 }
255 break;
256 case DYNPM_ACTION_UPCLOCK:
257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
261 rdev->pm.dynpm_can_upclock = false;
262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
265 } else {
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
268 rdev->pm.dynpm_can_upclock = false;
269 }
270 break;
271 case DYNPM_ACTION_DEFAULT:
272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
274 rdev->pm.dynpm_can_upclock = false;
275 break;
276 case DYNPM_ACTION_NONE:
277 default:
278 DRM_ERROR("Requested mode for not defined action\n");
279 return;
280 }
281 }
282
283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 pcie_lanes);
290 }
291
292 void rs780_pm_init_profile(struct radeon_device *rdev)
293 {
294 if (rdev->pm.num_power_states == 2) {
295 /* default */
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 /* low sh */
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
305 /* mid sh */
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
310 /* high sh */
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 /* low mh */
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
320 /* mid mh */
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
325 /* high mh */
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
331 /* default */
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 /* low sh */
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
341 /* mid sh */
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
346 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 /* low mh */
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
356 /* mid mh */
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
361 /* high mh */
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
366 } else {
367 /* default */
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 /* low sh */
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
377 /* mid sh */
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
382 /* high sh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 /* low mh */
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
392 /* mid mh */
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
397 /* high mh */
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
402 }
403 }
404
405 void r600_pm_init_profile(struct radeon_device *rdev)
406 {
407 int idx;
408
409 if (rdev->family == CHIP_R600) {
410 /* XXX */
411 /* default */
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
416 /* low sh */
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
421 /* mid sh */
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
426 /* high sh */
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
431 /* low mh */
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
436 /* mid mh */
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
441 /* high mh */
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
446 } else {
447 if (rdev->pm.num_power_states < 4) {
448 /* default */
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 /* low sh */
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 /* mid sh */
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
463 /* high sh */
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 /* low mh */
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 /* low mh */
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
478 /* high mh */
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
483 } else {
484 /* default */
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 /* low sh */
490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 else
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
498 /* mid sh */
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
503 /* high sh */
504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 /* low mh */
510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 else
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
518 /* mid mh */
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
523 /* high mh */
524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
529 }
530 }
531 }
532
533 void r600_pm_misc(struct radeon_device *rdev)
534 {
535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
539
540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
543 return;
544 if (voltage->voltage != rdev->pm.current_vddc) {
545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
546 rdev->pm.current_vddc = voltage->voltage;
547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
548 }
549 }
550 }
551
552 bool r600_gui_idle(struct radeon_device *rdev)
553 {
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
555 return false;
556 else
557 return true;
558 }
559
560 /* hpd for digital panel detect/disconnect */
561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562 {
563 bool connected = false;
564
565 if (ASIC_IS_DCE3(rdev)) {
566 switch (hpd) {
567 case RADEON_HPD_1:
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
569 connected = true;
570 break;
571 case RADEON_HPD_2:
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
573 connected = true;
574 break;
575 case RADEON_HPD_3:
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_4:
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 /* DCE 3.2 */
584 case RADEON_HPD_5:
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
586 connected = true;
587 break;
588 case RADEON_HPD_6:
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 default:
593 break;
594 }
595 } else {
596 switch (hpd) {
597 case RADEON_HPD_1:
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_2:
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
603 connected = true;
604 break;
605 case RADEON_HPD_3:
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 default:
610 break;
611 }
612 }
613 return connected;
614 }
615
616 void r600_hpd_set_polarity(struct radeon_device *rdev,
617 enum radeon_hpd_id hpd)
618 {
619 u32 tmp;
620 bool connected = r600_hpd_sense(rdev, hpd);
621
622 if (ASIC_IS_DCE3(rdev)) {
623 switch (hpd) {
624 case RADEON_HPD_1:
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 if (connected)
627 tmp &= ~DC_HPDx_INT_POLARITY;
628 else
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
631 break;
632 case RADEON_HPD_2:
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_3:
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_4:
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_5:
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
663 break;
664 /* DCE 3.2 */
665 case RADEON_HPD_6:
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 if (connected)
668 tmp &= ~DC_HPDx_INT_POLARITY;
669 else
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
672 break;
673 default:
674 break;
675 }
676 } else {
677 switch (hpd) {
678 case RADEON_HPD_1:
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 else
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
685 break;
686 case RADEON_HPD_2:
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_3:
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
701 break;
702 default:
703 break;
704 }
705 }
706 }
707
708 void r600_hpd_init(struct radeon_device *rdev)
709 {
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
712 unsigned enable = 0;
713
714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
715 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
716
717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
719 /* don't try to enable hpd on eDP or LVDS avoid breaking the
720 * aux dp channel on imac and help (but not completely fix)
721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
722 */
723 continue;
724 }
725 if (ASIC_IS_DCE3(rdev)) {
726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
727 if (ASIC_IS_DCE32(rdev))
728 tmp |= DC_HPDx_EN;
729
730 switch (radeon_connector->hpd.hpd) {
731 case RADEON_HPD_1:
732 WREG32(DC_HPD1_CONTROL, tmp);
733 break;
734 case RADEON_HPD_2:
735 WREG32(DC_HPD2_CONTROL, tmp);
736 break;
737 case RADEON_HPD_3:
738 WREG32(DC_HPD3_CONTROL, tmp);
739 break;
740 case RADEON_HPD_4:
741 WREG32(DC_HPD4_CONTROL, tmp);
742 break;
743 /* DCE 3.2 */
744 case RADEON_HPD_5:
745 WREG32(DC_HPD5_CONTROL, tmp);
746 break;
747 case RADEON_HPD_6:
748 WREG32(DC_HPD6_CONTROL, tmp);
749 break;
750 default:
751 break;
752 }
753 } else {
754 switch (radeon_connector->hpd.hpd) {
755 case RADEON_HPD_1:
756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
757 break;
758 case RADEON_HPD_2:
759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
760 break;
761 case RADEON_HPD_3:
762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
763 break;
764 default:
765 break;
766 }
767 }
768 enable |= 1 << radeon_connector->hpd.hpd;
769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
770 }
771 radeon_irq_kms_enable_hpd(rdev, enable);
772 }
773
774 void r600_hpd_fini(struct radeon_device *rdev)
775 {
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
778 unsigned disable = 0;
779
780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 if (ASIC_IS_DCE3(rdev)) {
783 switch (radeon_connector->hpd.hpd) {
784 case RADEON_HPD_1:
785 WREG32(DC_HPD1_CONTROL, 0);
786 break;
787 case RADEON_HPD_2:
788 WREG32(DC_HPD2_CONTROL, 0);
789 break;
790 case RADEON_HPD_3:
791 WREG32(DC_HPD3_CONTROL, 0);
792 break;
793 case RADEON_HPD_4:
794 WREG32(DC_HPD4_CONTROL, 0);
795 break;
796 /* DCE 3.2 */
797 case RADEON_HPD_5:
798 WREG32(DC_HPD5_CONTROL, 0);
799 break;
800 case RADEON_HPD_6:
801 WREG32(DC_HPD6_CONTROL, 0);
802 break;
803 default:
804 break;
805 }
806 } else {
807 switch (radeon_connector->hpd.hpd) {
808 case RADEON_HPD_1:
809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
810 break;
811 case RADEON_HPD_2:
812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
816 break;
817 default:
818 break;
819 }
820 }
821 disable |= 1 << radeon_connector->hpd.hpd;
822 }
823 radeon_irq_kms_disable_hpd(rdev, disable);
824 }
825
826 /*
827 * R600 PCIE GART
828 */
829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
830 {
831 unsigned i;
832 u32 tmp;
833
834 /* flush hdp cache so updates hit vram */
835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
836 !(rdev->flags & RADEON_IS_AGP)) {
837 void __iomem *ptr = (void *)rdev->gart.ptr;
838 u32 tmp;
839
840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
842 * This seems to cause problems on some AGP cards. Just use the old
843 * method for them.
844 */
845 WREG32(HDP_DEBUG1, 0);
846 tmp = readl((void __iomem *)ptr);
847 } else
848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
849
850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
853 for (i = 0; i < rdev->usec_timeout; i++) {
854 /* read MC_STATUS */
855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
857 if (tmp == 2) {
858 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
859 return;
860 }
861 if (tmp) {
862 return;
863 }
864 udelay(1);
865 }
866 }
867
868 int r600_pcie_gart_init(struct radeon_device *rdev)
869 {
870 int r;
871
872 if (rdev->gart.robj) {
873 WARN(1, "R600 PCIE GART already initialized\n");
874 return 0;
875 }
876 /* Initialize common gart structure */
877 r = radeon_gart_init(rdev);
878 if (r)
879 return r;
880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
881 return radeon_gart_table_vram_alloc(rdev);
882 }
883
884 int r600_pcie_gart_enable(struct radeon_device *rdev)
885 {
886 u32 tmp;
887 int r, i;
888
889 if (rdev->gart.robj == NULL) {
890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
891 return -EINVAL;
892 }
893 r = radeon_gart_table_vram_pin(rdev);
894 if (r)
895 return r;
896 radeon_gart_restore(rdev);
897
898 /* Setup L2 cache */
899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
901 EFFECTIVE_L2_QUEUE_SIZE(7));
902 WREG32(VM_L2_CNTL2, 0);
903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
904 /* Setup TLB control */
905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
906 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
908 ENABLE_WAIT_L2_QUERY;
909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
929 (u32)(rdev->dummy_page.addr >> 12));
930 for (i = 1; i < 7; i++)
931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
932
933 r600_pcie_gart_tlb_flush(rdev);
934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
935 (unsigned)(rdev->mc.gtt_size >> 20),
936 (unsigned long long)rdev->gart.table_addr);
937 rdev->gart.ready = true;
938 return 0;
939 }
940
941 void r600_pcie_gart_disable(struct radeon_device *rdev)
942 {
943 u32 tmp;
944 int i;
945
946 /* Disable all tables */
947 for (i = 0; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
949
950 /* Disable L2 cache */
951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
952 EFFECTIVE_L2_QUEUE_SIZE(7));
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup L1 TLB control */
955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
956 ENABLE_WAIT_L2_QUERY;
957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
971 radeon_gart_table_vram_unpin(rdev);
972 }
973
974 void r600_pcie_gart_fini(struct radeon_device *rdev)
975 {
976 radeon_gart_fini(rdev);
977 r600_pcie_gart_disable(rdev);
978 radeon_gart_table_vram_free(rdev);
979 }
980
981 void r600_agp_enable(struct radeon_device *rdev)
982 {
983 u32 tmp;
984 int i;
985
986 /* Setup L2 cache */
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
989 EFFECTIVE_L2_QUEUE_SIZE(7));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
992 /* Setup TLB control */
993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
994 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
996 ENABLE_WAIT_L2_QUERY;
997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011 for (i = 0; i < 7; i++)
1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013 }
1014
1015 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016 {
1017 unsigned i;
1018 u32 tmp;
1019
1020 for (i = 0; i < rdev->usec_timeout; i++) {
1021 /* read MC_STATUS */
1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023 if (!tmp)
1024 return 0;
1025 udelay(1);
1026 }
1027 return -1;
1028 }
1029
1030 static void r600_mc_program(struct radeon_device *rdev)
1031 {
1032 struct rv515_mc_save save;
1033 u32 tmp;
1034 int i, j;
1035
1036 /* Initialize HDP */
1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038 WREG32((0x2c14 + j), 0x00000000);
1039 WREG32((0x2c18 + j), 0x00000000);
1040 WREG32((0x2c1c + j), 0x00000000);
1041 WREG32((0x2c20 + j), 0x00000000);
1042 WREG32((0x2c24 + j), 0x00000000);
1043 }
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
1046 rv515_mc_stop(rdev, &save);
1047 if (r600_mc_wait_for_idle(rdev)) {
1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049 }
1050 /* Lockout access through VGA aperture (doesn't exist before R600) */
1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052 /* Update configuration */
1053 if (rdev->flags & RADEON_IS_AGP) {
1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057 rdev->mc.vram_start >> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 rdev->mc.gtt_end >> 12);
1060 } else {
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.gtt_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.vram_end >> 12);
1066 }
1067 } else {
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070 }
1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074 WREG32(MC_VM_FB_LOCATION, tmp);
1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1078 if (rdev->flags & RADEON_IS_AGP) {
1079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082 } else {
1083 WREG32(MC_VM_AGP_BASE, 0);
1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086 }
1087 if (r600_mc_wait_for_idle(rdev)) {
1088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1089 }
1090 rv515_mc_resume(rdev, &save);
1091 /* we need to own VRAM, so turn off the VGA renderer here
1092 * to stop it overwriting our objects */
1093 rv515_vga_render_disable(rdev);
1094 }
1095
1096 /**
1097 * r600_vram_gtt_location - try to find VRAM & GTT location
1098 * @rdev: radeon device structure holding all necessary informations
1099 * @mc: memory controller structure holding memory informations
1100 *
1101 * Function will place try to place VRAM at same place as in CPU (PCI)
1102 * address space as some GPU seems to have issue when we reprogram at
1103 * different address space.
1104 *
1105 * If there is not enough space to fit the unvisible VRAM after the
1106 * aperture then we limit the VRAM size to the aperture.
1107 *
1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109 * them to be in one from GPU point of view so that we can program GPU to
1110 * catch access outside them (weird GPU policy see ??).
1111 *
1112 * This function will never fails, worst case are limiting VRAM or GTT.
1113 *
1114 * Note: GTT start, end, size should be initialized before calling this
1115 * function on AGP platform.
1116 */
1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1118 {
1119 u64 size_bf, size_af;
1120
1121 if (mc->mc_vram_size > 0xE0000000) {
1122 /* leave room for at least 512M GTT */
1123 dev_warn(rdev->dev, "limiting VRAM\n");
1124 mc->real_vram_size = 0xE0000000;
1125 mc->mc_vram_size = 0xE0000000;
1126 }
1127 if (rdev->flags & RADEON_IS_AGP) {
1128 size_bf = mc->gtt_start;
1129 size_af = 0xFFFFFFFF - mc->gtt_end;
1130 if (size_bf > size_af) {
1131 if (mc->mc_vram_size > size_bf) {
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = size_bf;
1134 mc->mc_vram_size = size_bf;
1135 }
1136 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137 } else {
1138 if (mc->mc_vram_size > size_af) {
1139 dev_warn(rdev->dev, "limiting VRAM\n");
1140 mc->real_vram_size = size_af;
1141 mc->mc_vram_size = size_af;
1142 }
1143 mc->vram_start = mc->gtt_end + 1;
1144 }
1145 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147 mc->mc_vram_size >> 20, mc->vram_start,
1148 mc->vram_end, mc->real_vram_size >> 20);
1149 } else {
1150 u64 base = 0;
1151 if (rdev->flags & RADEON_IS_IGP) {
1152 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153 base <<= 24;
1154 }
1155 radeon_vram_location(rdev, &rdev->mc, base);
1156 rdev->mc.gtt_base_align = 0;
1157 radeon_gtt_location(rdev, mc);
1158 }
1159 }
1160
1161 int r600_mc_init(struct radeon_device *rdev)
1162 {
1163 u32 tmp;
1164 int chansize, numchan;
1165
1166 /* Get VRAM informations */
1167 rdev->mc.vram_is_ddr = true;
1168 tmp = RREG32(RAMCFG);
1169 if (tmp & CHANSIZE_OVERRIDE) {
1170 chansize = 16;
1171 } else if (tmp & CHANSIZE_MASK) {
1172 chansize = 64;
1173 } else {
1174 chansize = 32;
1175 }
1176 tmp = RREG32(CHMAP);
1177 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178 case 0:
1179 default:
1180 numchan = 1;
1181 break;
1182 case 1:
1183 numchan = 2;
1184 break;
1185 case 2:
1186 numchan = 4;
1187 break;
1188 case 3:
1189 numchan = 8;
1190 break;
1191 }
1192 rdev->mc.vram_width = numchan * chansize;
1193 /* Could aper size report 0 ? */
1194 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1196 /* Setup GPU memory space */
1197 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1199 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1200 r600_vram_gtt_location(rdev, &rdev->mc);
1201
1202 if (rdev->flags & RADEON_IS_IGP) {
1203 rs690_pm_info(rdev);
1204 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1205 }
1206 radeon_update_bandwidth_info(rdev);
1207 return 0;
1208 }
1209
1210 int r600_vram_scratch_init(struct radeon_device *rdev)
1211 {
1212 int r;
1213
1214 if (rdev->vram_scratch.robj == NULL) {
1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217 NULL, &rdev->vram_scratch.robj);
1218 if (r) {
1219 return r;
1220 }
1221 }
1222
1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224 if (unlikely(r != 0))
1225 return r;
1226 r = radeon_bo_pin(rdev->vram_scratch.robj,
1227 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228 if (r) {
1229 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230 return r;
1231 }
1232 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233 (void **)&rdev->vram_scratch.ptr);
1234 if (r)
1235 radeon_bo_unpin(rdev->vram_scratch.robj);
1236 radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238 return r;
1239 }
1240
1241 void r600_vram_scratch_fini(struct radeon_device *rdev)
1242 {
1243 int r;
1244
1245 if (rdev->vram_scratch.robj == NULL) {
1246 return;
1247 }
1248 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249 if (likely(r == 0)) {
1250 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251 radeon_bo_unpin(rdev->vram_scratch.robj);
1252 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253 }
1254 radeon_bo_unref(&rdev->vram_scratch.robj);
1255 }
1256
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258 * reset, it's up to the caller to determine if the GPU needs one. We
1259 * might add an helper function to check that.
1260 */
1261 int r600_gpu_soft_reset(struct radeon_device *rdev)
1262 {
1263 struct rv515_mc_save save;
1264 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1267 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1268 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1269 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1270 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1271 S_008010_GUI_ACTIVE(1);
1272 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1273 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1274 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1275 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1276 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1277 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1278 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1279 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1280 u32 tmp;
1281
1282 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1283 return 0;
1284
1285 dev_info(rdev->dev, "GPU softreset \n");
1286 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1287 RREG32(R_008010_GRBM_STATUS));
1288 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1289 RREG32(R_008014_GRBM_STATUS2));
1290 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1291 RREG32(R_000E50_SRBM_STATUS));
1292 rv515_mc_stop(rdev, &save);
1293 if (r600_mc_wait_for_idle(rdev)) {
1294 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1295 }
1296 /* Disable CP parsing/prefetching */
1297 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1298 /* Check if any of the rendering block is busy and reset it */
1299 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1300 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1301 tmp = S_008020_SOFT_RESET_CR(1) |
1302 S_008020_SOFT_RESET_DB(1) |
1303 S_008020_SOFT_RESET_CB(1) |
1304 S_008020_SOFT_RESET_PA(1) |
1305 S_008020_SOFT_RESET_SC(1) |
1306 S_008020_SOFT_RESET_SMX(1) |
1307 S_008020_SOFT_RESET_SPI(1) |
1308 S_008020_SOFT_RESET_SX(1) |
1309 S_008020_SOFT_RESET_SH(1) |
1310 S_008020_SOFT_RESET_TC(1) |
1311 S_008020_SOFT_RESET_TA(1) |
1312 S_008020_SOFT_RESET_VC(1) |
1313 S_008020_SOFT_RESET_VGT(1);
1314 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1315 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1316 RREG32(R_008020_GRBM_SOFT_RESET);
1317 mdelay(15);
1318 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1319 }
1320 /* Reset CP (we always reset CP) */
1321 tmp = S_008020_SOFT_RESET_CP(1);
1322 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1323 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1324 RREG32(R_008020_GRBM_SOFT_RESET);
1325 mdelay(15);
1326 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1327 /* Wait a little for things to settle down */
1328 mdelay(1);
1329 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1330 RREG32(R_008010_GRBM_STATUS));
1331 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1332 RREG32(R_008014_GRBM_STATUS2));
1333 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1334 RREG32(R_000E50_SRBM_STATUS));
1335 rv515_mc_resume(rdev, &save);
1336 return 0;
1337 }
1338
1339 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1340 {
1341 u32 srbm_status;
1342 u32 grbm_status;
1343 u32 grbm_status2;
1344
1345 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1346 grbm_status = RREG32(R_008010_GRBM_STATUS);
1347 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1348 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1349 radeon_ring_lockup_update(ring);
1350 return false;
1351 }
1352 /* force CP activities */
1353 radeon_ring_force_activity(rdev, ring);
1354 return radeon_ring_test_lockup(rdev, ring);
1355 }
1356
1357 int r600_asic_reset(struct radeon_device *rdev)
1358 {
1359 return r600_gpu_soft_reset(rdev);
1360 }
1361
1362 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1363 u32 tiling_pipe_num,
1364 u32 max_rb_num,
1365 u32 total_max_rb_num,
1366 u32 disabled_rb_mask)
1367 {
1368 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1369 u32 pipe_rb_ratio, pipe_rb_remain;
1370 u32 data = 0, mask = 1 << (max_rb_num - 1);
1371 unsigned i, j;
1372
1373 /* mask out the RBs that don't exist on that asic */
1374 disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1375
1376 rendering_pipe_num = 1 << tiling_pipe_num;
1377 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1378 BUG_ON(rendering_pipe_num < req_rb_num);
1379
1380 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1381 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1382
1383 if (rdev->family <= CHIP_RV740) {
1384 /* r6xx/r7xx */
1385 rb_num_width = 2;
1386 } else {
1387 /* eg+ */
1388 rb_num_width = 4;
1389 }
1390
1391 for (i = 0; i < max_rb_num; i++) {
1392 if (!(mask & disabled_rb_mask)) {
1393 for (j = 0; j < pipe_rb_ratio; j++) {
1394 data <<= rb_num_width;
1395 data |= max_rb_num - i - 1;
1396 }
1397 if (pipe_rb_remain) {
1398 data <<= rb_num_width;
1399 data |= max_rb_num - i - 1;
1400 pipe_rb_remain--;
1401 }
1402 }
1403 mask >>= 1;
1404 }
1405
1406 return data;
1407 }
1408
1409 int r600_count_pipe_bits(uint32_t val)
1410 {
1411 int i, ret = 0;
1412
1413 for (i = 0; i < 32; i++) {
1414 ret += val & 1;
1415 val >>= 1;
1416 }
1417 return ret;
1418 }
1419
1420 void r600_gpu_init(struct radeon_device *rdev)
1421 {
1422 u32 tiling_config;
1423 u32 ramcfg;
1424 u32 cc_rb_backend_disable;
1425 u32 cc_gc_shader_pipe_config;
1426 u32 tmp;
1427 int i, j;
1428 u32 sq_config;
1429 u32 sq_gpr_resource_mgmt_1 = 0;
1430 u32 sq_gpr_resource_mgmt_2 = 0;
1431 u32 sq_thread_resource_mgmt = 0;
1432 u32 sq_stack_resource_mgmt_1 = 0;
1433 u32 sq_stack_resource_mgmt_2 = 0;
1434 u32 disabled_rb_mask;
1435
1436 rdev->config.r600.tiling_group_size = 256;
1437 switch (rdev->family) {
1438 case CHIP_R600:
1439 rdev->config.r600.max_pipes = 4;
1440 rdev->config.r600.max_tile_pipes = 8;
1441 rdev->config.r600.max_simds = 4;
1442 rdev->config.r600.max_backends = 4;
1443 rdev->config.r600.max_gprs = 256;
1444 rdev->config.r600.max_threads = 192;
1445 rdev->config.r600.max_stack_entries = 256;
1446 rdev->config.r600.max_hw_contexts = 8;
1447 rdev->config.r600.max_gs_threads = 16;
1448 rdev->config.r600.sx_max_export_size = 128;
1449 rdev->config.r600.sx_max_export_pos_size = 16;
1450 rdev->config.r600.sx_max_export_smx_size = 128;
1451 rdev->config.r600.sq_num_cf_insts = 2;
1452 break;
1453 case CHIP_RV630:
1454 case CHIP_RV635:
1455 rdev->config.r600.max_pipes = 2;
1456 rdev->config.r600.max_tile_pipes = 2;
1457 rdev->config.r600.max_simds = 3;
1458 rdev->config.r600.max_backends = 1;
1459 rdev->config.r600.max_gprs = 128;
1460 rdev->config.r600.max_threads = 192;
1461 rdev->config.r600.max_stack_entries = 128;
1462 rdev->config.r600.max_hw_contexts = 8;
1463 rdev->config.r600.max_gs_threads = 4;
1464 rdev->config.r600.sx_max_export_size = 128;
1465 rdev->config.r600.sx_max_export_pos_size = 16;
1466 rdev->config.r600.sx_max_export_smx_size = 128;
1467 rdev->config.r600.sq_num_cf_insts = 2;
1468 break;
1469 case CHIP_RV610:
1470 case CHIP_RV620:
1471 case CHIP_RS780:
1472 case CHIP_RS880:
1473 rdev->config.r600.max_pipes = 1;
1474 rdev->config.r600.max_tile_pipes = 1;
1475 rdev->config.r600.max_simds = 2;
1476 rdev->config.r600.max_backends = 1;
1477 rdev->config.r600.max_gprs = 128;
1478 rdev->config.r600.max_threads = 192;
1479 rdev->config.r600.max_stack_entries = 128;
1480 rdev->config.r600.max_hw_contexts = 4;
1481 rdev->config.r600.max_gs_threads = 4;
1482 rdev->config.r600.sx_max_export_size = 128;
1483 rdev->config.r600.sx_max_export_pos_size = 16;
1484 rdev->config.r600.sx_max_export_smx_size = 128;
1485 rdev->config.r600.sq_num_cf_insts = 1;
1486 break;
1487 case CHIP_RV670:
1488 rdev->config.r600.max_pipes = 4;
1489 rdev->config.r600.max_tile_pipes = 4;
1490 rdev->config.r600.max_simds = 4;
1491 rdev->config.r600.max_backends = 4;
1492 rdev->config.r600.max_gprs = 192;
1493 rdev->config.r600.max_threads = 192;
1494 rdev->config.r600.max_stack_entries = 256;
1495 rdev->config.r600.max_hw_contexts = 8;
1496 rdev->config.r600.max_gs_threads = 16;
1497 rdev->config.r600.sx_max_export_size = 128;
1498 rdev->config.r600.sx_max_export_pos_size = 16;
1499 rdev->config.r600.sx_max_export_smx_size = 128;
1500 rdev->config.r600.sq_num_cf_insts = 2;
1501 break;
1502 default:
1503 break;
1504 }
1505
1506 /* Initialize HDP */
1507 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1508 WREG32((0x2c14 + j), 0x00000000);
1509 WREG32((0x2c18 + j), 0x00000000);
1510 WREG32((0x2c1c + j), 0x00000000);
1511 WREG32((0x2c20 + j), 0x00000000);
1512 WREG32((0x2c24 + j), 0x00000000);
1513 }
1514
1515 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1516
1517 /* Setup tiling */
1518 tiling_config = 0;
1519 ramcfg = RREG32(RAMCFG);
1520 switch (rdev->config.r600.max_tile_pipes) {
1521 case 1:
1522 tiling_config |= PIPE_TILING(0);
1523 break;
1524 case 2:
1525 tiling_config |= PIPE_TILING(1);
1526 break;
1527 case 4:
1528 tiling_config |= PIPE_TILING(2);
1529 break;
1530 case 8:
1531 tiling_config |= PIPE_TILING(3);
1532 break;
1533 default:
1534 break;
1535 }
1536 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1537 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1538 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1539 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1540
1541 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1542 if (tmp > 3) {
1543 tiling_config |= ROW_TILING(3);
1544 tiling_config |= SAMPLE_SPLIT(3);
1545 } else {
1546 tiling_config |= ROW_TILING(tmp);
1547 tiling_config |= SAMPLE_SPLIT(tmp);
1548 }
1549 tiling_config |= BANK_SWAPS(1);
1550
1551 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1552 tmp = R6XX_MAX_BACKENDS -
1553 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1554 if (tmp < rdev->config.r600.max_backends) {
1555 rdev->config.r600.max_backends = tmp;
1556 }
1557
1558 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1559 tmp = R6XX_MAX_PIPES -
1560 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1561 if (tmp < rdev->config.r600.max_pipes) {
1562 rdev->config.r600.max_pipes = tmp;
1563 }
1564 tmp = R6XX_MAX_SIMDS -
1565 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1566 if (tmp < rdev->config.r600.max_simds) {
1567 rdev->config.r600.max_simds = tmp;
1568 }
1569
1570 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1571 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1572 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1573 R6XX_MAX_BACKENDS, disabled_rb_mask);
1574 tiling_config |= tmp << 16;
1575 rdev->config.r600.backend_map = tmp;
1576
1577 rdev->config.r600.tile_config = tiling_config;
1578 WREG32(GB_TILING_CONFIG, tiling_config);
1579 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1580 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1581
1582 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1583 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1584 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1585
1586 /* Setup some CP states */
1587 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1588 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1589
1590 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1591 SYNC_WALKER | SYNC_ALIGNER));
1592 /* Setup various GPU states */
1593 if (rdev->family == CHIP_RV670)
1594 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1595
1596 tmp = RREG32(SX_DEBUG_1);
1597 tmp |= SMX_EVENT_RELEASE;
1598 if ((rdev->family > CHIP_R600))
1599 tmp |= ENABLE_NEW_SMX_ADDRESS;
1600 WREG32(SX_DEBUG_1, tmp);
1601
1602 if (((rdev->family) == CHIP_R600) ||
1603 ((rdev->family) == CHIP_RV630) ||
1604 ((rdev->family) == CHIP_RV610) ||
1605 ((rdev->family) == CHIP_RV620) ||
1606 ((rdev->family) == CHIP_RS780) ||
1607 ((rdev->family) == CHIP_RS880)) {
1608 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1609 } else {
1610 WREG32(DB_DEBUG, 0);
1611 }
1612 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1613 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1614
1615 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1616 WREG32(VGT_NUM_INSTANCES, 0);
1617
1618 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1619 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1620
1621 tmp = RREG32(SQ_MS_FIFO_SIZES);
1622 if (((rdev->family) == CHIP_RV610) ||
1623 ((rdev->family) == CHIP_RV620) ||
1624 ((rdev->family) == CHIP_RS780) ||
1625 ((rdev->family) == CHIP_RS880)) {
1626 tmp = (CACHE_FIFO_SIZE(0xa) |
1627 FETCH_FIFO_HIWATER(0xa) |
1628 DONE_FIFO_HIWATER(0xe0) |
1629 ALU_UPDATE_FIFO_HIWATER(0x8));
1630 } else if (((rdev->family) == CHIP_R600) ||
1631 ((rdev->family) == CHIP_RV630)) {
1632 tmp &= ~DONE_FIFO_HIWATER(0xff);
1633 tmp |= DONE_FIFO_HIWATER(0x4);
1634 }
1635 WREG32(SQ_MS_FIFO_SIZES, tmp);
1636
1637 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1638 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1639 */
1640 sq_config = RREG32(SQ_CONFIG);
1641 sq_config &= ~(PS_PRIO(3) |
1642 VS_PRIO(3) |
1643 GS_PRIO(3) |
1644 ES_PRIO(3));
1645 sq_config |= (DX9_CONSTS |
1646 VC_ENABLE |
1647 PS_PRIO(0) |
1648 VS_PRIO(1) |
1649 GS_PRIO(2) |
1650 ES_PRIO(3));
1651
1652 if ((rdev->family) == CHIP_R600) {
1653 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1654 NUM_VS_GPRS(124) |
1655 NUM_CLAUSE_TEMP_GPRS(4));
1656 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1657 NUM_ES_GPRS(0));
1658 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1659 NUM_VS_THREADS(48) |
1660 NUM_GS_THREADS(4) |
1661 NUM_ES_THREADS(4));
1662 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1663 NUM_VS_STACK_ENTRIES(128));
1664 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1665 NUM_ES_STACK_ENTRIES(0));
1666 } else if (((rdev->family) == CHIP_RV610) ||
1667 ((rdev->family) == CHIP_RV620) ||
1668 ((rdev->family) == CHIP_RS780) ||
1669 ((rdev->family) == CHIP_RS880)) {
1670 /* no vertex cache */
1671 sq_config &= ~VC_ENABLE;
1672
1673 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1674 NUM_VS_GPRS(44) |
1675 NUM_CLAUSE_TEMP_GPRS(2));
1676 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1677 NUM_ES_GPRS(17));
1678 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1679 NUM_VS_THREADS(78) |
1680 NUM_GS_THREADS(4) |
1681 NUM_ES_THREADS(31));
1682 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1683 NUM_VS_STACK_ENTRIES(40));
1684 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1685 NUM_ES_STACK_ENTRIES(16));
1686 } else if (((rdev->family) == CHIP_RV630) ||
1687 ((rdev->family) == CHIP_RV635)) {
1688 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1689 NUM_VS_GPRS(44) |
1690 NUM_CLAUSE_TEMP_GPRS(2));
1691 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1692 NUM_ES_GPRS(18));
1693 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1694 NUM_VS_THREADS(78) |
1695 NUM_GS_THREADS(4) |
1696 NUM_ES_THREADS(31));
1697 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1698 NUM_VS_STACK_ENTRIES(40));
1699 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1700 NUM_ES_STACK_ENTRIES(16));
1701 } else if ((rdev->family) == CHIP_RV670) {
1702 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1703 NUM_VS_GPRS(44) |
1704 NUM_CLAUSE_TEMP_GPRS(2));
1705 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1706 NUM_ES_GPRS(17));
1707 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1708 NUM_VS_THREADS(78) |
1709 NUM_GS_THREADS(4) |
1710 NUM_ES_THREADS(31));
1711 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1712 NUM_VS_STACK_ENTRIES(64));
1713 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1714 NUM_ES_STACK_ENTRIES(64));
1715 }
1716
1717 WREG32(SQ_CONFIG, sq_config);
1718 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1719 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1720 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1721 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1722 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1723
1724 if (((rdev->family) == CHIP_RV610) ||
1725 ((rdev->family) == CHIP_RV620) ||
1726 ((rdev->family) == CHIP_RS780) ||
1727 ((rdev->family) == CHIP_RS880)) {
1728 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1729 } else {
1730 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1731 }
1732
1733 /* More default values. 2D/3D driver should adjust as needed */
1734 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1735 S1_X(0x4) | S1_Y(0xc)));
1736 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1737 S1_X(0x2) | S1_Y(0x2) |
1738 S2_X(0xa) | S2_Y(0x6) |
1739 S3_X(0x6) | S3_Y(0xa)));
1740 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1741 S1_X(0x4) | S1_Y(0xc) |
1742 S2_X(0x1) | S2_Y(0x6) |
1743 S3_X(0xa) | S3_Y(0xe)));
1744 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1745 S5_X(0x0) | S5_Y(0x0) |
1746 S6_X(0xb) | S6_Y(0x4) |
1747 S7_X(0x7) | S7_Y(0x8)));
1748
1749 WREG32(VGT_STRMOUT_EN, 0);
1750 tmp = rdev->config.r600.max_pipes * 16;
1751 switch (rdev->family) {
1752 case CHIP_RV610:
1753 case CHIP_RV620:
1754 case CHIP_RS780:
1755 case CHIP_RS880:
1756 tmp += 32;
1757 break;
1758 case CHIP_RV670:
1759 tmp += 128;
1760 break;
1761 default:
1762 break;
1763 }
1764 if (tmp > 256) {
1765 tmp = 256;
1766 }
1767 WREG32(VGT_ES_PER_GS, 128);
1768 WREG32(VGT_GS_PER_ES, tmp);
1769 WREG32(VGT_GS_PER_VS, 2);
1770 WREG32(VGT_GS_VERTEX_REUSE, 16);
1771
1772 /* more default values. 2D/3D driver should adjust as needed */
1773 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1774 WREG32(VGT_STRMOUT_EN, 0);
1775 WREG32(SX_MISC, 0);
1776 WREG32(PA_SC_MODE_CNTL, 0);
1777 WREG32(PA_SC_AA_CONFIG, 0);
1778 WREG32(PA_SC_LINE_STIPPLE, 0);
1779 WREG32(SPI_INPUT_Z, 0);
1780 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1781 WREG32(CB_COLOR7_FRAG, 0);
1782
1783 /* Clear render buffer base addresses */
1784 WREG32(CB_COLOR0_BASE, 0);
1785 WREG32(CB_COLOR1_BASE, 0);
1786 WREG32(CB_COLOR2_BASE, 0);
1787 WREG32(CB_COLOR3_BASE, 0);
1788 WREG32(CB_COLOR4_BASE, 0);
1789 WREG32(CB_COLOR5_BASE, 0);
1790 WREG32(CB_COLOR6_BASE, 0);
1791 WREG32(CB_COLOR7_BASE, 0);
1792 WREG32(CB_COLOR7_FRAG, 0);
1793
1794 switch (rdev->family) {
1795 case CHIP_RV610:
1796 case CHIP_RV620:
1797 case CHIP_RS780:
1798 case CHIP_RS880:
1799 tmp = TC_L2_SIZE(8);
1800 break;
1801 case CHIP_RV630:
1802 case CHIP_RV635:
1803 tmp = TC_L2_SIZE(4);
1804 break;
1805 case CHIP_R600:
1806 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1807 break;
1808 default:
1809 tmp = TC_L2_SIZE(0);
1810 break;
1811 }
1812 WREG32(TC_CNTL, tmp);
1813
1814 tmp = RREG32(HDP_HOST_PATH_CNTL);
1815 WREG32(HDP_HOST_PATH_CNTL, tmp);
1816
1817 tmp = RREG32(ARB_POP);
1818 tmp |= ENABLE_TC128;
1819 WREG32(ARB_POP, tmp);
1820
1821 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1822 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1823 NUM_CLIP_SEQ(3)));
1824 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1825 WREG32(VC_ENHANCE, 0);
1826 }
1827
1828
1829 /*
1830 * Indirect registers accessor
1831 */
1832 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1833 {
1834 u32 r;
1835
1836 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1837 (void)RREG32(PCIE_PORT_INDEX);
1838 r = RREG32(PCIE_PORT_DATA);
1839 return r;
1840 }
1841
1842 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1843 {
1844 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1845 (void)RREG32(PCIE_PORT_INDEX);
1846 WREG32(PCIE_PORT_DATA, (v));
1847 (void)RREG32(PCIE_PORT_DATA);
1848 }
1849
1850 /*
1851 * CP & Ring
1852 */
1853 void r600_cp_stop(struct radeon_device *rdev)
1854 {
1855 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1856 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1857 WREG32(SCRATCH_UMSK, 0);
1858 }
1859
1860 int r600_init_microcode(struct radeon_device *rdev)
1861 {
1862 struct platform_device *pdev;
1863 const char *chip_name;
1864 const char *rlc_chip_name;
1865 size_t pfp_req_size, me_req_size, rlc_req_size;
1866 char fw_name[30];
1867 int err;
1868
1869 DRM_DEBUG("\n");
1870
1871 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1872 err = IS_ERR(pdev);
1873 if (err) {
1874 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1875 return -EINVAL;
1876 }
1877
1878 switch (rdev->family) {
1879 case CHIP_R600:
1880 chip_name = "R600";
1881 rlc_chip_name = "R600";
1882 break;
1883 case CHIP_RV610:
1884 chip_name = "RV610";
1885 rlc_chip_name = "R600";
1886 break;
1887 case CHIP_RV630:
1888 chip_name = "RV630";
1889 rlc_chip_name = "R600";
1890 break;
1891 case CHIP_RV620:
1892 chip_name = "RV620";
1893 rlc_chip_name = "R600";
1894 break;
1895 case CHIP_RV635:
1896 chip_name = "RV635";
1897 rlc_chip_name = "R600";
1898 break;
1899 case CHIP_RV670:
1900 chip_name = "RV670";
1901 rlc_chip_name = "R600";
1902 break;
1903 case CHIP_RS780:
1904 case CHIP_RS880:
1905 chip_name = "RS780";
1906 rlc_chip_name = "R600";
1907 break;
1908 case CHIP_RV770:
1909 chip_name = "RV770";
1910 rlc_chip_name = "R700";
1911 break;
1912 case CHIP_RV730:
1913 case CHIP_RV740:
1914 chip_name = "RV730";
1915 rlc_chip_name = "R700";
1916 break;
1917 case CHIP_RV710:
1918 chip_name = "RV710";
1919 rlc_chip_name = "R700";
1920 break;
1921 case CHIP_CEDAR:
1922 chip_name = "CEDAR";
1923 rlc_chip_name = "CEDAR";
1924 break;
1925 case CHIP_REDWOOD:
1926 chip_name = "REDWOOD";
1927 rlc_chip_name = "REDWOOD";
1928 break;
1929 case CHIP_JUNIPER:
1930 chip_name = "JUNIPER";
1931 rlc_chip_name = "JUNIPER";
1932 break;
1933 case CHIP_CYPRESS:
1934 case CHIP_HEMLOCK:
1935 chip_name = "CYPRESS";
1936 rlc_chip_name = "CYPRESS";
1937 break;
1938 case CHIP_PALM:
1939 chip_name = "PALM";
1940 rlc_chip_name = "SUMO";
1941 break;
1942 case CHIP_SUMO:
1943 chip_name = "SUMO";
1944 rlc_chip_name = "SUMO";
1945 break;
1946 case CHIP_SUMO2:
1947 chip_name = "SUMO2";
1948 rlc_chip_name = "SUMO";
1949 break;
1950 default: BUG();
1951 }
1952
1953 if (rdev->family >= CHIP_CEDAR) {
1954 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1955 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1956 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1957 } else if (rdev->family >= CHIP_RV770) {
1958 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1959 me_req_size = R700_PM4_UCODE_SIZE * 4;
1960 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1961 } else {
1962 pfp_req_size = PFP_UCODE_SIZE * 4;
1963 me_req_size = PM4_UCODE_SIZE * 12;
1964 rlc_req_size = RLC_UCODE_SIZE * 4;
1965 }
1966
1967 DRM_INFO("Loading %s Microcode\n", chip_name);
1968
1969 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1970 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1971 if (err)
1972 goto out;
1973 if (rdev->pfp_fw->size != pfp_req_size) {
1974 printk(KERN_ERR
1975 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1976 rdev->pfp_fw->size, fw_name);
1977 err = -EINVAL;
1978 goto out;
1979 }
1980
1981 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1982 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1983 if (err)
1984 goto out;
1985 if (rdev->me_fw->size != me_req_size) {
1986 printk(KERN_ERR
1987 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1988 rdev->me_fw->size, fw_name);
1989 err = -EINVAL;
1990 }
1991
1992 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1993 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1994 if (err)
1995 goto out;
1996 if (rdev->rlc_fw->size != rlc_req_size) {
1997 printk(KERN_ERR
1998 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1999 rdev->rlc_fw->size, fw_name);
2000 err = -EINVAL;
2001 }
2002
2003 out:
2004 platform_device_unregister(pdev);
2005
2006 if (err) {
2007 if (err != -EINVAL)
2008 printk(KERN_ERR
2009 "r600_cp: Failed to load firmware \"%s\"\n",
2010 fw_name);
2011 release_firmware(rdev->pfp_fw);
2012 rdev->pfp_fw = NULL;
2013 release_firmware(rdev->me_fw);
2014 rdev->me_fw = NULL;
2015 release_firmware(rdev->rlc_fw);
2016 rdev->rlc_fw = NULL;
2017 }
2018 return err;
2019 }
2020
2021 static int r600_cp_load_microcode(struct radeon_device *rdev)
2022 {
2023 const __be32 *fw_data;
2024 int i;
2025
2026 if (!rdev->me_fw || !rdev->pfp_fw)
2027 return -EINVAL;
2028
2029 r600_cp_stop(rdev);
2030
2031 WREG32(CP_RB_CNTL,
2032 #ifdef __BIG_ENDIAN
2033 BUF_SWAP_32BIT |
2034 #endif
2035 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2036
2037 /* Reset cp */
2038 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2039 RREG32(GRBM_SOFT_RESET);
2040 mdelay(15);
2041 WREG32(GRBM_SOFT_RESET, 0);
2042
2043 WREG32(CP_ME_RAM_WADDR, 0);
2044
2045 fw_data = (const __be32 *)rdev->me_fw->data;
2046 WREG32(CP_ME_RAM_WADDR, 0);
2047 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2048 WREG32(CP_ME_RAM_DATA,
2049 be32_to_cpup(fw_data++));
2050
2051 fw_data = (const __be32 *)rdev->pfp_fw->data;
2052 WREG32(CP_PFP_UCODE_ADDR, 0);
2053 for (i = 0; i < PFP_UCODE_SIZE; i++)
2054 WREG32(CP_PFP_UCODE_DATA,
2055 be32_to_cpup(fw_data++));
2056
2057 WREG32(CP_PFP_UCODE_ADDR, 0);
2058 WREG32(CP_ME_RAM_WADDR, 0);
2059 WREG32(CP_ME_RAM_RADDR, 0);
2060 return 0;
2061 }
2062
2063 int r600_cp_start(struct radeon_device *rdev)
2064 {
2065 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2066 int r;
2067 uint32_t cp_me;
2068
2069 r = radeon_ring_lock(rdev, ring, 7);
2070 if (r) {
2071 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2072 return r;
2073 }
2074 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2075 radeon_ring_write(ring, 0x1);
2076 if (rdev->family >= CHIP_RV770) {
2077 radeon_ring_write(ring, 0x0);
2078 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2079 } else {
2080 radeon_ring_write(ring, 0x3);
2081 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2082 }
2083 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2084 radeon_ring_write(ring, 0);
2085 radeon_ring_write(ring, 0);
2086 radeon_ring_unlock_commit(rdev, ring);
2087
2088 cp_me = 0xff;
2089 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2090 return 0;
2091 }
2092
2093 int r600_cp_resume(struct radeon_device *rdev)
2094 {
2095 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2096 u32 tmp;
2097 u32 rb_bufsz;
2098 int r;
2099
2100 /* Reset cp */
2101 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2102 RREG32(GRBM_SOFT_RESET);
2103 mdelay(15);
2104 WREG32(GRBM_SOFT_RESET, 0);
2105
2106 /* Set ring buffer size */
2107 rb_bufsz = drm_order(ring->ring_size / 8);
2108 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2109 #ifdef __BIG_ENDIAN
2110 tmp |= BUF_SWAP_32BIT;
2111 #endif
2112 WREG32(CP_RB_CNTL, tmp);
2113 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2114
2115 /* Set the write pointer delay */
2116 WREG32(CP_RB_WPTR_DELAY, 0);
2117
2118 /* Initialize the ring buffer's read and write pointers */
2119 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2120 WREG32(CP_RB_RPTR_WR, 0);
2121 ring->wptr = 0;
2122 WREG32(CP_RB_WPTR, ring->wptr);
2123
2124 /* set the wb address whether it's enabled or not */
2125 WREG32(CP_RB_RPTR_ADDR,
2126 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2127 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2128 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2129
2130 if (rdev->wb.enabled)
2131 WREG32(SCRATCH_UMSK, 0xff);
2132 else {
2133 tmp |= RB_NO_UPDATE;
2134 WREG32(SCRATCH_UMSK, 0);
2135 }
2136
2137 mdelay(1);
2138 WREG32(CP_RB_CNTL, tmp);
2139
2140 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2141 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2142
2143 ring->rptr = RREG32(CP_RB_RPTR);
2144
2145 r600_cp_start(rdev);
2146 ring->ready = true;
2147 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2148 if (r) {
2149 ring->ready = false;
2150 return r;
2151 }
2152 return 0;
2153 }
2154
2155 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2156 {
2157 u32 rb_bufsz;
2158
2159 /* Align ring size */
2160 rb_bufsz = drm_order(ring_size / 8);
2161 ring_size = (1 << (rb_bufsz + 1)) * 4;
2162 ring->ring_size = ring_size;
2163 ring->align_mask = 16 - 1;
2164 }
2165
2166 void r600_cp_fini(struct radeon_device *rdev)
2167 {
2168 r600_cp_stop(rdev);
2169 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2170 }
2171
2172
2173 /*
2174 * GPU scratch registers helpers function.
2175 */
2176 void r600_scratch_init(struct radeon_device *rdev)
2177 {
2178 int i;
2179
2180 rdev->scratch.num_reg = 7;
2181 rdev->scratch.reg_base = SCRATCH_REG0;
2182 for (i = 0; i < rdev->scratch.num_reg; i++) {
2183 rdev->scratch.free[i] = true;
2184 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2185 }
2186 }
2187
2188 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2189 {
2190 uint32_t scratch;
2191 uint32_t tmp = 0;
2192 unsigned i, ridx = radeon_ring_index(rdev, ring);
2193 int r;
2194
2195 r = radeon_scratch_get(rdev, &scratch);
2196 if (r) {
2197 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2198 return r;
2199 }
2200 WREG32(scratch, 0xCAFEDEAD);
2201 r = radeon_ring_lock(rdev, ring, 3);
2202 if (r) {
2203 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
2204 radeon_scratch_free(rdev, scratch);
2205 return r;
2206 }
2207 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2208 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2209 radeon_ring_write(ring, 0xDEADBEEF);
2210 radeon_ring_unlock_commit(rdev, ring);
2211 for (i = 0; i < rdev->usec_timeout; i++) {
2212 tmp = RREG32(scratch);
2213 if (tmp == 0xDEADBEEF)
2214 break;
2215 DRM_UDELAY(1);
2216 }
2217 if (i < rdev->usec_timeout) {
2218 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
2219 } else {
2220 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2221 ridx, scratch, tmp);
2222 r = -EINVAL;
2223 }
2224 radeon_scratch_free(rdev, scratch);
2225 return r;
2226 }
2227
2228 void r600_fence_ring_emit(struct radeon_device *rdev,
2229 struct radeon_fence *fence)
2230 {
2231 struct radeon_ring *ring = &rdev->ring[fence->ring];
2232
2233 if (rdev->wb.use_event) {
2234 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2235 /* flush read cache over gart */
2236 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2237 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2238 PACKET3_VC_ACTION_ENA |
2239 PACKET3_SH_ACTION_ENA);
2240 radeon_ring_write(ring, 0xFFFFFFFF);
2241 radeon_ring_write(ring, 0);
2242 radeon_ring_write(ring, 10); /* poll interval */
2243 /* EVENT_WRITE_EOP - flush caches, send int */
2244 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2245 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2246 radeon_ring_write(ring, addr & 0xffffffff);
2247 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2248 radeon_ring_write(ring, fence->seq);
2249 radeon_ring_write(ring, 0);
2250 } else {
2251 /* flush read cache over gart */
2252 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2253 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2254 PACKET3_VC_ACTION_ENA |
2255 PACKET3_SH_ACTION_ENA);
2256 radeon_ring_write(ring, 0xFFFFFFFF);
2257 radeon_ring_write(ring, 0);
2258 radeon_ring_write(ring, 10); /* poll interval */
2259 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2260 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2261 /* wait for 3D idle clean */
2262 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2263 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2264 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2265 /* Emit fence sequence & fire IRQ */
2266 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2267 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2268 radeon_ring_write(ring, fence->seq);
2269 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2270 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2271 radeon_ring_write(ring, RB_INT_STAT);
2272 }
2273 }
2274
2275 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2276 struct radeon_ring *ring,
2277 struct radeon_semaphore *semaphore,
2278 bool emit_wait)
2279 {
2280 uint64_t addr = semaphore->gpu_addr;
2281 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2282
2283 if (rdev->family < CHIP_CAYMAN)
2284 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2285
2286 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2287 radeon_ring_write(ring, addr & 0xffffffff);
2288 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2289 }
2290
2291 int r600_copy_blit(struct radeon_device *rdev,
2292 uint64_t src_offset,
2293 uint64_t dst_offset,
2294 unsigned num_gpu_pages,
2295 struct radeon_fence **fence)
2296 {
2297 struct radeon_semaphore *sem = NULL;
2298 struct radeon_sa_bo *vb = NULL;
2299 int r;
2300
2301 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2302 if (r) {
2303 return r;
2304 }
2305 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2306 r600_blit_done_copy(rdev, fence, vb, sem);
2307 return 0;
2308 }
2309
2310 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2311 uint32_t tiling_flags, uint32_t pitch,
2312 uint32_t offset, uint32_t obj_size)
2313 {
2314 /* FIXME: implement */
2315 return 0;
2316 }
2317
2318 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2319 {
2320 /* FIXME: implement */
2321 }
2322
2323 int r600_startup(struct radeon_device *rdev)
2324 {
2325 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2326 int r;
2327
2328 /* enable pcie gen2 link */
2329 r600_pcie_gen2_enable(rdev);
2330
2331 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2332 r = r600_init_microcode(rdev);
2333 if (r) {
2334 DRM_ERROR("Failed to load firmware!\n");
2335 return r;
2336 }
2337 }
2338
2339 r = r600_vram_scratch_init(rdev);
2340 if (r)
2341 return r;
2342
2343 r600_mc_program(rdev);
2344 if (rdev->flags & RADEON_IS_AGP) {
2345 r600_agp_enable(rdev);
2346 } else {
2347 r = r600_pcie_gart_enable(rdev);
2348 if (r)
2349 return r;
2350 }
2351 r600_gpu_init(rdev);
2352 r = r600_blit_init(rdev);
2353 if (r) {
2354 r600_blit_fini(rdev);
2355 rdev->asic->copy.copy = NULL;
2356 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2357 }
2358
2359 /* allocate wb buffer */
2360 r = radeon_wb_init(rdev);
2361 if (r)
2362 return r;
2363
2364 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2365 if (r) {
2366 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2367 return r;
2368 }
2369
2370 /* Enable IRQ */
2371 r = r600_irq_init(rdev);
2372 if (r) {
2373 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2374 radeon_irq_kms_fini(rdev);
2375 return r;
2376 }
2377 r600_irq_set(rdev);
2378
2379 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2380 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2381 0, 0xfffff, RADEON_CP_PACKET2);
2382
2383 if (r)
2384 return r;
2385 r = r600_cp_load_microcode(rdev);
2386 if (r)
2387 return r;
2388 r = r600_cp_resume(rdev);
2389 if (r)
2390 return r;
2391
2392 r = radeon_ib_pool_init(rdev);
2393 if (r) {
2394 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2395 return r;
2396 }
2397
2398 r = r600_audio_init(rdev);
2399 if (r) {
2400 DRM_ERROR("radeon: audio init failed\n");
2401 return r;
2402 }
2403
2404 return 0;
2405 }
2406
2407 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2408 {
2409 uint32_t temp;
2410
2411 temp = RREG32(CONFIG_CNTL);
2412 if (state == false) {
2413 temp &= ~(1<<0);
2414 temp |= (1<<1);
2415 } else {
2416 temp &= ~(1<<1);
2417 }
2418 WREG32(CONFIG_CNTL, temp);
2419 }
2420
2421 int r600_resume(struct radeon_device *rdev)
2422 {
2423 int r;
2424
2425 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2426 * posting will perform necessary task to bring back GPU into good
2427 * shape.
2428 */
2429 /* post card */
2430 atom_asic_init(rdev->mode_info.atom_context);
2431
2432 rdev->accel_working = true;
2433 r = r600_startup(rdev);
2434 if (r) {
2435 DRM_ERROR("r600 startup failed on resume\n");
2436 rdev->accel_working = false;
2437 return r;
2438 }
2439
2440 return r;
2441 }
2442
2443 int r600_suspend(struct radeon_device *rdev)
2444 {
2445 r600_audio_fini(rdev);
2446 r600_cp_stop(rdev);
2447 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2448 r600_irq_suspend(rdev);
2449 radeon_wb_disable(rdev);
2450 r600_pcie_gart_disable(rdev);
2451
2452 return 0;
2453 }
2454
2455 /* Plan is to move initialization in that function and use
2456 * helper function so that radeon_device_init pretty much
2457 * do nothing more than calling asic specific function. This
2458 * should also allow to remove a bunch of callback function
2459 * like vram_info.
2460 */
2461 int r600_init(struct radeon_device *rdev)
2462 {
2463 int r;
2464
2465 if (r600_debugfs_mc_info_init(rdev)) {
2466 DRM_ERROR("Failed to register debugfs file for mc !\n");
2467 }
2468 /* Read BIOS */
2469 if (!radeon_get_bios(rdev)) {
2470 if (ASIC_IS_AVIVO(rdev))
2471 return -EINVAL;
2472 }
2473 /* Must be an ATOMBIOS */
2474 if (!rdev->is_atom_bios) {
2475 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2476 return -EINVAL;
2477 }
2478 r = radeon_atombios_init(rdev);
2479 if (r)
2480 return r;
2481 /* Post card if necessary */
2482 if (!radeon_card_posted(rdev)) {
2483 if (!rdev->bios) {
2484 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2485 return -EINVAL;
2486 }
2487 DRM_INFO("GPU not posted. posting now...\n");
2488 atom_asic_init(rdev->mode_info.atom_context);
2489 }
2490 /* Initialize scratch registers */
2491 r600_scratch_init(rdev);
2492 /* Initialize surface registers */
2493 radeon_surface_init(rdev);
2494 /* Initialize clocks */
2495 radeon_get_clock_info(rdev->ddev);
2496 /* Fence driver */
2497 r = radeon_fence_driver_init(rdev);
2498 if (r)
2499 return r;
2500 if (rdev->flags & RADEON_IS_AGP) {
2501 r = radeon_agp_init(rdev);
2502 if (r)
2503 radeon_agp_disable(rdev);
2504 }
2505 r = r600_mc_init(rdev);
2506 if (r)
2507 return r;
2508 /* Memory manager */
2509 r = radeon_bo_init(rdev);
2510 if (r)
2511 return r;
2512
2513 r = radeon_irq_kms_init(rdev);
2514 if (r)
2515 return r;
2516
2517 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2518 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2519
2520 rdev->ih.ring_obj = NULL;
2521 r600_ih_ring_init(rdev, 64 * 1024);
2522
2523 r = r600_pcie_gart_init(rdev);
2524 if (r)
2525 return r;
2526
2527 rdev->accel_working = true;
2528 r = r600_startup(rdev);
2529 if (r) {
2530 dev_err(rdev->dev, "disabling GPU acceleration\n");
2531 r600_cp_fini(rdev);
2532 r600_irq_fini(rdev);
2533 radeon_wb_fini(rdev);
2534 radeon_ib_pool_fini(rdev);
2535 radeon_irq_kms_fini(rdev);
2536 r600_pcie_gart_fini(rdev);
2537 rdev->accel_working = false;
2538 }
2539
2540 return 0;
2541 }
2542
2543 void r600_fini(struct radeon_device *rdev)
2544 {
2545 r600_audio_fini(rdev);
2546 r600_blit_fini(rdev);
2547 r600_cp_fini(rdev);
2548 r600_irq_fini(rdev);
2549 radeon_wb_fini(rdev);
2550 radeon_ib_pool_fini(rdev);
2551 radeon_irq_kms_fini(rdev);
2552 r600_pcie_gart_fini(rdev);
2553 r600_vram_scratch_fini(rdev);
2554 radeon_agp_fini(rdev);
2555 radeon_gem_fini(rdev);
2556 radeon_fence_driver_fini(rdev);
2557 radeon_bo_fini(rdev);
2558 radeon_atombios_fini(rdev);
2559 kfree(rdev->bios);
2560 rdev->bios = NULL;
2561 }
2562
2563
2564 /*
2565 * CS stuff
2566 */
2567 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2568 {
2569 struct radeon_ring *ring = &rdev->ring[ib->ring];
2570
2571 /* FIXME: implement */
2572 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2573 radeon_ring_write(ring,
2574 #ifdef __BIG_ENDIAN
2575 (2 << 0) |
2576 #endif
2577 (ib->gpu_addr & 0xFFFFFFFC));
2578 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2579 radeon_ring_write(ring, ib->length_dw);
2580 }
2581
2582 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2583 {
2584 struct radeon_ib ib;
2585 uint32_t scratch;
2586 uint32_t tmp = 0;
2587 unsigned i;
2588 int r;
2589 int ring_index = radeon_ring_index(rdev, ring);
2590
2591 r = radeon_scratch_get(rdev, &scratch);
2592 if (r) {
2593 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2594 return r;
2595 }
2596 WREG32(scratch, 0xCAFEDEAD);
2597 r = radeon_ib_get(rdev, ring_index, &ib, 256);
2598 if (r) {
2599 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2600 return r;
2601 }
2602 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2603 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2604 ib.ptr[2] = 0xDEADBEEF;
2605 ib.length_dw = 3;
2606 r = radeon_ib_schedule(rdev, &ib);
2607 if (r) {
2608 radeon_scratch_free(rdev, scratch);
2609 radeon_ib_free(rdev, &ib);
2610 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2611 return r;
2612 }
2613 r = radeon_fence_wait(ib.fence, false);
2614 if (r) {
2615 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2616 return r;
2617 }
2618 for (i = 0; i < rdev->usec_timeout; i++) {
2619 tmp = RREG32(scratch);
2620 if (tmp == 0xDEADBEEF)
2621 break;
2622 DRM_UDELAY(1);
2623 }
2624 if (i < rdev->usec_timeout) {
2625 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
2626 } else {
2627 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2628 scratch, tmp);
2629 r = -EINVAL;
2630 }
2631 radeon_scratch_free(rdev, scratch);
2632 radeon_ib_free(rdev, &ib);
2633 return r;
2634 }
2635
2636 /*
2637 * Interrupts
2638 *
2639 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2640 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2641 * writing to the ring and the GPU consuming, the GPU writes to the ring
2642 * and host consumes. As the host irq handler processes interrupts, it
2643 * increments the rptr. When the rptr catches up with the wptr, all the
2644 * current interrupts have been processed.
2645 */
2646
2647 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2648 {
2649 u32 rb_bufsz;
2650
2651 /* Align ring size */
2652 rb_bufsz = drm_order(ring_size / 4);
2653 ring_size = (1 << rb_bufsz) * 4;
2654 rdev->ih.ring_size = ring_size;
2655 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2656 rdev->ih.rptr = 0;
2657 }
2658
2659 int r600_ih_ring_alloc(struct radeon_device *rdev)
2660 {
2661 int r;
2662
2663 /* Allocate ring buffer */
2664 if (rdev->ih.ring_obj == NULL) {
2665 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2666 PAGE_SIZE, true,
2667 RADEON_GEM_DOMAIN_GTT,
2668 NULL, &rdev->ih.ring_obj);
2669 if (r) {
2670 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2671 return r;
2672 }
2673 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2674 if (unlikely(r != 0))
2675 return r;
2676 r = radeon_bo_pin(rdev->ih.ring_obj,
2677 RADEON_GEM_DOMAIN_GTT,
2678 &rdev->ih.gpu_addr);
2679 if (r) {
2680 radeon_bo_unreserve(rdev->ih.ring_obj);
2681 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2682 return r;
2683 }
2684 r = radeon_bo_kmap(rdev->ih.ring_obj,
2685 (void **)&rdev->ih.ring);
2686 radeon_bo_unreserve(rdev->ih.ring_obj);
2687 if (r) {
2688 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2689 return r;
2690 }
2691 }
2692 return 0;
2693 }
2694
2695 void r600_ih_ring_fini(struct radeon_device *rdev)
2696 {
2697 int r;
2698 if (rdev->ih.ring_obj) {
2699 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2700 if (likely(r == 0)) {
2701 radeon_bo_kunmap(rdev->ih.ring_obj);
2702 radeon_bo_unpin(rdev->ih.ring_obj);
2703 radeon_bo_unreserve(rdev->ih.ring_obj);
2704 }
2705 radeon_bo_unref(&rdev->ih.ring_obj);
2706 rdev->ih.ring = NULL;
2707 rdev->ih.ring_obj = NULL;
2708 }
2709 }
2710
2711 void r600_rlc_stop(struct radeon_device *rdev)
2712 {
2713
2714 if ((rdev->family >= CHIP_RV770) &&
2715 (rdev->family <= CHIP_RV740)) {
2716 /* r7xx asics need to soft reset RLC before halting */
2717 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2718 RREG32(SRBM_SOFT_RESET);
2719 mdelay(15);
2720 WREG32(SRBM_SOFT_RESET, 0);
2721 RREG32(SRBM_SOFT_RESET);
2722 }
2723
2724 WREG32(RLC_CNTL, 0);
2725 }
2726
2727 static void r600_rlc_start(struct radeon_device *rdev)
2728 {
2729 WREG32(RLC_CNTL, RLC_ENABLE);
2730 }
2731
2732 static int r600_rlc_init(struct radeon_device *rdev)
2733 {
2734 u32 i;
2735 const __be32 *fw_data;
2736
2737 if (!rdev->rlc_fw)
2738 return -EINVAL;
2739
2740 r600_rlc_stop(rdev);
2741
2742 WREG32(RLC_HB_CNTL, 0);
2743
2744 if (rdev->family == CHIP_ARUBA) {
2745 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2746 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2747 }
2748 if (rdev->family <= CHIP_CAYMAN) {
2749 WREG32(RLC_HB_BASE, 0);
2750 WREG32(RLC_HB_RPTR, 0);
2751 WREG32(RLC_HB_WPTR, 0);
2752 }
2753 if (rdev->family <= CHIP_CAICOS) {
2754 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2755 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2756 }
2757 WREG32(RLC_MC_CNTL, 0);
2758 WREG32(RLC_UCODE_CNTL, 0);
2759
2760 fw_data = (const __be32 *)rdev->rlc_fw->data;
2761 if (rdev->family >= CHIP_ARUBA) {
2762 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
2763 WREG32(RLC_UCODE_ADDR, i);
2764 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2765 }
2766 } else if (rdev->family >= CHIP_CAYMAN) {
2767 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2768 WREG32(RLC_UCODE_ADDR, i);
2769 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2770 }
2771 } else if (rdev->family >= CHIP_CEDAR) {
2772 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2773 WREG32(RLC_UCODE_ADDR, i);
2774 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2775 }
2776 } else if (rdev->family >= CHIP_RV770) {
2777 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2778 WREG32(RLC_UCODE_ADDR, i);
2779 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2780 }
2781 } else {
2782 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2783 WREG32(RLC_UCODE_ADDR, i);
2784 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2785 }
2786 }
2787 WREG32(RLC_UCODE_ADDR, 0);
2788
2789 r600_rlc_start(rdev);
2790
2791 return 0;
2792 }
2793
2794 static void r600_enable_interrupts(struct radeon_device *rdev)
2795 {
2796 u32 ih_cntl = RREG32(IH_CNTL);
2797 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2798
2799 ih_cntl |= ENABLE_INTR;
2800 ih_rb_cntl |= IH_RB_ENABLE;
2801 WREG32(IH_CNTL, ih_cntl);
2802 WREG32(IH_RB_CNTL, ih_rb_cntl);
2803 rdev->ih.enabled = true;
2804 }
2805
2806 void r600_disable_interrupts(struct radeon_device *rdev)
2807 {
2808 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2809 u32 ih_cntl = RREG32(IH_CNTL);
2810
2811 ih_rb_cntl &= ~IH_RB_ENABLE;
2812 ih_cntl &= ~ENABLE_INTR;
2813 WREG32(IH_RB_CNTL, ih_rb_cntl);
2814 WREG32(IH_CNTL, ih_cntl);
2815 /* set rptr, wptr to 0 */
2816 WREG32(IH_RB_RPTR, 0);
2817 WREG32(IH_RB_WPTR, 0);
2818 rdev->ih.enabled = false;
2819 rdev->ih.rptr = 0;
2820 }
2821
2822 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2823 {
2824 u32 tmp;
2825
2826 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2827 WREG32(GRBM_INT_CNTL, 0);
2828 WREG32(DxMODE_INT_MASK, 0);
2829 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2830 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2831 if (ASIC_IS_DCE3(rdev)) {
2832 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2833 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2834 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2835 WREG32(DC_HPD1_INT_CONTROL, tmp);
2836 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2837 WREG32(DC_HPD2_INT_CONTROL, tmp);
2838 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2839 WREG32(DC_HPD3_INT_CONTROL, tmp);
2840 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2841 WREG32(DC_HPD4_INT_CONTROL, tmp);
2842 if (ASIC_IS_DCE32(rdev)) {
2843 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2844 WREG32(DC_HPD5_INT_CONTROL, tmp);
2845 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2846 WREG32(DC_HPD6_INT_CONTROL, tmp);
2847 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2848 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
2849 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2850 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
2851 } else {
2852 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2853 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2854 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2855 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
2856 }
2857 } else {
2858 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2859 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2860 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2861 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2862 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2863 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2864 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2865 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2866 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2867 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2868 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2869 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
2870 }
2871 }
2872
2873 int r600_irq_init(struct radeon_device *rdev)
2874 {
2875 int ret = 0;
2876 int rb_bufsz;
2877 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2878
2879 /* allocate ring */
2880 ret = r600_ih_ring_alloc(rdev);
2881 if (ret)
2882 return ret;
2883
2884 /* disable irqs */
2885 r600_disable_interrupts(rdev);
2886
2887 /* init rlc */
2888 ret = r600_rlc_init(rdev);
2889 if (ret) {
2890 r600_ih_ring_fini(rdev);
2891 return ret;
2892 }
2893
2894 /* setup interrupt control */
2895 /* set dummy read address to ring address */
2896 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2897 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2898 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2899 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2900 */
2901 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2902 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2903 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2904 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2905
2906 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2907 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2908
2909 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2910 IH_WPTR_OVERFLOW_CLEAR |
2911 (rb_bufsz << 1));
2912
2913 if (rdev->wb.enabled)
2914 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2915
2916 /* set the writeback address whether it's enabled or not */
2917 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2918 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2919
2920 WREG32(IH_RB_CNTL, ih_rb_cntl);
2921
2922 /* set rptr, wptr to 0 */
2923 WREG32(IH_RB_RPTR, 0);
2924 WREG32(IH_RB_WPTR, 0);
2925
2926 /* Default settings for IH_CNTL (disabled at first) */
2927 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2928 /* RPTR_REARM only works if msi's are enabled */
2929 if (rdev->msi_enabled)
2930 ih_cntl |= RPTR_REARM;
2931 WREG32(IH_CNTL, ih_cntl);
2932
2933 /* force the active interrupt state to all disabled */
2934 if (rdev->family >= CHIP_CEDAR)
2935 evergreen_disable_interrupt_state(rdev);
2936 else
2937 r600_disable_interrupt_state(rdev);
2938
2939 /* at this point everything should be setup correctly to enable master */
2940 pci_set_master(rdev->pdev);
2941
2942 /* enable irqs */
2943 r600_enable_interrupts(rdev);
2944
2945 return ret;
2946 }
2947
2948 void r600_irq_suspend(struct radeon_device *rdev)
2949 {
2950 r600_irq_disable(rdev);
2951 r600_rlc_stop(rdev);
2952 }
2953
2954 void r600_irq_fini(struct radeon_device *rdev)
2955 {
2956 r600_irq_suspend(rdev);
2957 r600_ih_ring_fini(rdev);
2958 }
2959
2960 int r600_irq_set(struct radeon_device *rdev)
2961 {
2962 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2963 u32 mode_int = 0;
2964 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2965 u32 grbm_int_cntl = 0;
2966 u32 hdmi0, hdmi1;
2967 u32 d1grph = 0, d2grph = 0;
2968
2969 if (!rdev->irq.installed) {
2970 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2971 return -EINVAL;
2972 }
2973 /* don't enable anything if the ih is disabled */
2974 if (!rdev->ih.enabled) {
2975 r600_disable_interrupts(rdev);
2976 /* force the active interrupt state to all disabled */
2977 r600_disable_interrupt_state(rdev);
2978 return 0;
2979 }
2980
2981 if (ASIC_IS_DCE3(rdev)) {
2982 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2983 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2984 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2985 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2986 if (ASIC_IS_DCE32(rdev)) {
2987 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2988 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2989 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2990 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2991 } else {
2992 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2993 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2994 }
2995 } else {
2996 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2997 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2998 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2999 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3000 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3001 }
3002
3003 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3004 DRM_DEBUG("r600_irq_set: sw int\n");
3005 cp_int_cntl |= RB_INT_ENABLE;
3006 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3007 }
3008 if (rdev->irq.crtc_vblank_int[0] ||
3009 atomic_read(&rdev->irq.pflip[0])) {
3010 DRM_DEBUG("r600_irq_set: vblank 0\n");
3011 mode_int |= D1MODE_VBLANK_INT_MASK;
3012 }
3013 if (rdev->irq.crtc_vblank_int[1] ||
3014 atomic_read(&rdev->irq.pflip[1])) {
3015 DRM_DEBUG("r600_irq_set: vblank 1\n");
3016 mode_int |= D2MODE_VBLANK_INT_MASK;
3017 }
3018 if (rdev->irq.hpd[0]) {
3019 DRM_DEBUG("r600_irq_set: hpd 1\n");
3020 hpd1 |= DC_HPDx_INT_EN;
3021 }
3022 if (rdev->irq.hpd[1]) {
3023 DRM_DEBUG("r600_irq_set: hpd 2\n");
3024 hpd2 |= DC_HPDx_INT_EN;
3025 }
3026 if (rdev->irq.hpd[2]) {
3027 DRM_DEBUG("r600_irq_set: hpd 3\n");
3028 hpd3 |= DC_HPDx_INT_EN;
3029 }
3030 if (rdev->irq.hpd[3]) {
3031 DRM_DEBUG("r600_irq_set: hpd 4\n");
3032 hpd4 |= DC_HPDx_INT_EN;
3033 }
3034 if (rdev->irq.hpd[4]) {
3035 DRM_DEBUG("r600_irq_set: hpd 5\n");
3036 hpd5 |= DC_HPDx_INT_EN;
3037 }
3038 if (rdev->irq.hpd[5]) {
3039 DRM_DEBUG("r600_irq_set: hpd 6\n");
3040 hpd6 |= DC_HPDx_INT_EN;
3041 }
3042 if (rdev->irq.afmt[0]) {
3043 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3044 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3045 }
3046 if (rdev->irq.afmt[1]) {
3047 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3048 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3049 }
3050 if (rdev->irq.gui_idle) {
3051 DRM_DEBUG("gui idle\n");
3052 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3053 }
3054
3055 WREG32(CP_INT_CNTL, cp_int_cntl);
3056 WREG32(DxMODE_INT_MASK, mode_int);
3057 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3058 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3059 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3060 if (ASIC_IS_DCE3(rdev)) {
3061 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3062 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3063 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3064 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3065 if (ASIC_IS_DCE32(rdev)) {
3066 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3067 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3068 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3069 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3070 } else {
3071 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3072 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3073 }
3074 } else {
3075 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3076 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3077 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3078 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3079 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3080 }
3081
3082 return 0;
3083 }
3084
3085 static void r600_irq_ack(struct radeon_device *rdev)
3086 {
3087 u32 tmp;
3088
3089 if (ASIC_IS_DCE3(rdev)) {
3090 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3091 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3092 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3093 if (ASIC_IS_DCE32(rdev)) {
3094 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3095 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3096 } else {
3097 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3098 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3099 }
3100 } else {
3101 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3102 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3103 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3104 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3105 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3106 }
3107 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3108 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3109
3110 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3111 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3112 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3113 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3114 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3115 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3116 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3117 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3118 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3119 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3120 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3121 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3122 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3123 if (ASIC_IS_DCE3(rdev)) {
3124 tmp = RREG32(DC_HPD1_INT_CONTROL);
3125 tmp |= DC_HPDx_INT_ACK;
3126 WREG32(DC_HPD1_INT_CONTROL, tmp);
3127 } else {
3128 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3129 tmp |= DC_HPDx_INT_ACK;
3130 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3131 }
3132 }
3133 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3134 if (ASIC_IS_DCE3(rdev)) {
3135 tmp = RREG32(DC_HPD2_INT_CONTROL);
3136 tmp |= DC_HPDx_INT_ACK;
3137 WREG32(DC_HPD2_INT_CONTROL, tmp);
3138 } else {
3139 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3140 tmp |= DC_HPDx_INT_ACK;
3141 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3142 }
3143 }
3144 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3145 if (ASIC_IS_DCE3(rdev)) {
3146 tmp = RREG32(DC_HPD3_INT_CONTROL);
3147 tmp |= DC_HPDx_INT_ACK;
3148 WREG32(DC_HPD3_INT_CONTROL, tmp);
3149 } else {
3150 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3151 tmp |= DC_HPDx_INT_ACK;
3152 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3153 }
3154 }
3155 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3156 tmp = RREG32(DC_HPD4_INT_CONTROL);
3157 tmp |= DC_HPDx_INT_ACK;
3158 WREG32(DC_HPD4_INT_CONTROL, tmp);
3159 }
3160 if (ASIC_IS_DCE32(rdev)) {
3161 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3162 tmp = RREG32(DC_HPD5_INT_CONTROL);
3163 tmp |= DC_HPDx_INT_ACK;
3164 WREG32(DC_HPD5_INT_CONTROL, tmp);
3165 }
3166 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3167 tmp = RREG32(DC_HPD5_INT_CONTROL);
3168 tmp |= DC_HPDx_INT_ACK;
3169 WREG32(DC_HPD6_INT_CONTROL, tmp);
3170 }
3171 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3172 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3173 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3174 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3175 }
3176 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3177 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3178 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3179 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3180 }
3181 } else {
3182 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3183 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3184 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3185 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3186 }
3187 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3188 if (ASIC_IS_DCE3(rdev)) {
3189 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3190 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3191 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3192 } else {
3193 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3194 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3195 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3196 }
3197 }
3198 }
3199 }
3200
3201 void r600_irq_disable(struct radeon_device *rdev)
3202 {
3203 r600_disable_interrupts(rdev);
3204 /* Wait and acknowledge irq */
3205 mdelay(1);
3206 r600_irq_ack(rdev);
3207 r600_disable_interrupt_state(rdev);
3208 }
3209
3210 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3211 {
3212 u32 wptr, tmp;
3213
3214 if (rdev->wb.enabled)
3215 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3216 else
3217 wptr = RREG32(IH_RB_WPTR);
3218
3219 if (wptr & RB_OVERFLOW) {
3220 /* When a ring buffer overflow happen start parsing interrupt
3221 * from the last not overwritten vector (wptr + 16). Hopefully
3222 * this should allow us to catchup.
3223 */
3224 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3225 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3226 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3227 tmp = RREG32(IH_RB_CNTL);
3228 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3229 WREG32(IH_RB_CNTL, tmp);
3230 }
3231 return (wptr & rdev->ih.ptr_mask);
3232 }
3233
3234 /* r600 IV Ring
3235 * Each IV ring entry is 128 bits:
3236 * [7:0] - interrupt source id
3237 * [31:8] - reserved
3238 * [59:32] - interrupt source data
3239 * [127:60] - reserved
3240 *
3241 * The basic interrupt vector entries
3242 * are decoded as follows:
3243 * src_id src_data description
3244 * 1 0 D1 Vblank
3245 * 1 1 D1 Vline
3246 * 5 0 D2 Vblank
3247 * 5 1 D2 Vline
3248 * 19 0 FP Hot plug detection A
3249 * 19 1 FP Hot plug detection B
3250 * 19 2 DAC A auto-detection
3251 * 19 3 DAC B auto-detection
3252 * 21 4 HDMI block A
3253 * 21 5 HDMI block B
3254 * 176 - CP_INT RB
3255 * 177 - CP_INT IB1
3256 * 178 - CP_INT IB2
3257 * 181 - EOP Interrupt
3258 * 233 - GUI Idle
3259 *
3260 * Note, these are based on r600 and may need to be
3261 * adjusted or added to on newer asics
3262 */
3263
3264 int r600_irq_process(struct radeon_device *rdev)
3265 {
3266 u32 wptr;
3267 u32 rptr;
3268 u32 src_id, src_data;
3269 u32 ring_index;
3270 bool queue_hotplug = false;
3271 bool queue_hdmi = false;
3272
3273 if (!rdev->ih.enabled || rdev->shutdown)
3274 return IRQ_NONE;
3275
3276 /* No MSIs, need a dummy read to flush PCI DMAs */
3277 if (!rdev->msi_enabled)
3278 RREG32(IH_RB_WPTR);
3279
3280 wptr = r600_get_ih_wptr(rdev);
3281
3282 restart_ih:
3283 /* is somebody else already processing irqs? */
3284 if (atomic_xchg(&rdev->ih.lock, 1))
3285 return IRQ_NONE;
3286
3287 rptr = rdev->ih.rptr;
3288 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3289
3290 /* Order reading of wptr vs. reading of IH ring data */
3291 rmb();
3292
3293 /* display interrupts */
3294 r600_irq_ack(rdev);
3295
3296 while (rptr != wptr) {
3297 /* wptr/rptr are in bytes! */
3298 ring_index = rptr / 4;
3299 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3300 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3301
3302 switch (src_id) {
3303 case 1: /* D1 vblank/vline */
3304 switch (src_data) {
3305 case 0: /* D1 vblank */
3306 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3307 if (rdev->irq.crtc_vblank_int[0]) {
3308 drm_handle_vblank(rdev->ddev, 0);
3309 rdev->pm.vblank_sync = true;
3310 wake_up(&rdev->irq.vblank_queue);
3311 }
3312 if (atomic_read(&rdev->irq.pflip[0]))
3313 radeon_crtc_handle_flip(rdev, 0);
3314 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3315 DRM_DEBUG("IH: D1 vblank\n");
3316 }
3317 break;
3318 case 1: /* D1 vline */
3319 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3320 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3321 DRM_DEBUG("IH: D1 vline\n");
3322 }
3323 break;
3324 default:
3325 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3326 break;
3327 }
3328 break;
3329 case 5: /* D2 vblank/vline */
3330 switch (src_data) {
3331 case 0: /* D2 vblank */
3332 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3333 if (rdev->irq.crtc_vblank_int[1]) {
3334 drm_handle_vblank(rdev->ddev, 1);
3335 rdev->pm.vblank_sync = true;
3336 wake_up(&rdev->irq.vblank_queue);
3337 }
3338 if (atomic_read(&rdev->irq.pflip[1]))
3339 radeon_crtc_handle_flip(rdev, 1);
3340 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3341 DRM_DEBUG("IH: D2 vblank\n");
3342 }
3343 break;
3344 case 1: /* D1 vline */
3345 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3346 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3347 DRM_DEBUG("IH: D2 vline\n");
3348 }
3349 break;
3350 default:
3351 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3352 break;
3353 }
3354 break;
3355 case 19: /* HPD/DAC hotplug */
3356 switch (src_data) {
3357 case 0:
3358 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3359 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3360 queue_hotplug = true;
3361 DRM_DEBUG("IH: HPD1\n");
3362 }
3363 break;
3364 case 1:
3365 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3366 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3367 queue_hotplug = true;
3368 DRM_DEBUG("IH: HPD2\n");
3369 }
3370 break;
3371 case 4:
3372 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3373 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3374 queue_hotplug = true;
3375 DRM_DEBUG("IH: HPD3\n");
3376 }
3377 break;
3378 case 5:
3379 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3380 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3381 queue_hotplug = true;
3382 DRM_DEBUG("IH: HPD4\n");
3383 }
3384 break;
3385 case 10:
3386 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3387 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3388 queue_hotplug = true;
3389 DRM_DEBUG("IH: HPD5\n");
3390 }
3391 break;
3392 case 12:
3393 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3394 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3395 queue_hotplug = true;
3396 DRM_DEBUG("IH: HPD6\n");
3397 }
3398 break;
3399 default:
3400 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3401 break;
3402 }
3403 break;
3404 case 21: /* hdmi */
3405 switch (src_data) {
3406 case 4:
3407 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3408 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3409 queue_hdmi = true;
3410 DRM_DEBUG("IH: HDMI0\n");
3411 }
3412 break;
3413 case 5:
3414 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3415 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3416 queue_hdmi = true;
3417 DRM_DEBUG("IH: HDMI1\n");
3418 }
3419 break;
3420 default:
3421 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3422 break;
3423 }
3424 break;
3425 case 176: /* CP_INT in ring buffer */
3426 case 177: /* CP_INT in IB1 */
3427 case 178: /* CP_INT in IB2 */
3428 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3429 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3430 break;
3431 case 181: /* CP EOP event */
3432 DRM_DEBUG("IH: CP EOP\n");
3433 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3434 break;
3435 case 233: /* GUI IDLE */
3436 DRM_DEBUG("IH: GUI idle\n");
3437 wake_up(&rdev->irq.idle_queue);
3438 break;
3439 default:
3440 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3441 break;
3442 }
3443
3444 /* wptr/rptr are in bytes! */
3445 rptr += 16;
3446 rptr &= rdev->ih.ptr_mask;
3447 }
3448 if (queue_hotplug)
3449 schedule_work(&rdev->hotplug_work);
3450 if (queue_hdmi)
3451 schedule_work(&rdev->audio_work);
3452 rdev->ih.rptr = rptr;
3453 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3454 atomic_set(&rdev->ih.lock, 0);
3455
3456 /* make sure wptr hasn't changed while processing */
3457 wptr = r600_get_ih_wptr(rdev);
3458 if (wptr != rptr)
3459 goto restart_ih;
3460
3461 return IRQ_HANDLED;
3462 }
3463
3464 /*
3465 * Debugfs info
3466 */
3467 #if defined(CONFIG_DEBUG_FS)
3468
3469 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3470 {
3471 struct drm_info_node *node = (struct drm_info_node *) m->private;
3472 struct drm_device *dev = node->minor->dev;
3473 struct radeon_device *rdev = dev->dev_private;
3474
3475 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3476 DREG32_SYS(m, rdev, VM_L2_STATUS);
3477 return 0;
3478 }
3479
3480 static struct drm_info_list r600_mc_info_list[] = {
3481 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3482 };
3483 #endif
3484
3485 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3486 {
3487 #if defined(CONFIG_DEBUG_FS)
3488 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3489 #else
3490 return 0;
3491 #endif
3492 }
3493
3494 /**
3495 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3496 * rdev: radeon device structure
3497 * bo: buffer object struct which userspace is waiting for idle
3498 *
3499 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3500 * through ring buffer, this leads to corruption in rendering, see
3501 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3502 * directly perform HDP flush by writing register through MMIO.
3503 */
3504 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3505 {
3506 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3507 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3508 * This seems to cause problems on some AGP cards. Just use the old
3509 * method for them.
3510 */
3511 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3512 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3513 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3514 u32 tmp;
3515
3516 WREG32(HDP_DEBUG1, 0);
3517 tmp = readl((void __iomem *)ptr);
3518 } else
3519 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3520 }
3521
3522 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3523 {
3524 u32 link_width_cntl, mask, target_reg;
3525
3526 if (rdev->flags & RADEON_IS_IGP)
3527 return;
3528
3529 if (!(rdev->flags & RADEON_IS_PCIE))
3530 return;
3531
3532 /* x2 cards have a special sequence */
3533 if (ASIC_IS_X2(rdev))
3534 return;
3535
3536 /* FIXME wait for idle */
3537
3538 switch (lanes) {
3539 case 0:
3540 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3541 break;
3542 case 1:
3543 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3544 break;
3545 case 2:
3546 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3547 break;
3548 case 4:
3549 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3550 break;
3551 case 8:
3552 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3553 break;
3554 case 12:
3555 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3556 break;
3557 case 16:
3558 default:
3559 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3560 break;
3561 }
3562
3563 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3564
3565 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3566 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3567 return;
3568
3569 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3570 return;
3571
3572 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3573 RADEON_PCIE_LC_RECONFIG_NOW |
3574 R600_PCIE_LC_RENEGOTIATE_EN |
3575 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3576 link_width_cntl |= mask;
3577
3578 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3579
3580 /* some northbridges can renegotiate the link rather than requiring
3581 * a complete re-config.
3582 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3583 */
3584 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3585 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3586 else
3587 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3588
3589 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3590 RADEON_PCIE_LC_RECONFIG_NOW));
3591
3592 if (rdev->family >= CHIP_RV770)
3593 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3594 else
3595 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3596
3597 /* wait for lane set to complete */
3598 link_width_cntl = RREG32(target_reg);
3599 while (link_width_cntl == 0xffffffff)
3600 link_width_cntl = RREG32(target_reg);
3601
3602 }
3603
3604 int r600_get_pcie_lanes(struct radeon_device *rdev)
3605 {
3606 u32 link_width_cntl;
3607
3608 if (rdev->flags & RADEON_IS_IGP)
3609 return 0;
3610
3611 if (!(rdev->flags & RADEON_IS_PCIE))
3612 return 0;
3613
3614 /* x2 cards have a special sequence */
3615 if (ASIC_IS_X2(rdev))
3616 return 0;
3617
3618 /* FIXME wait for idle */
3619
3620 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3621
3622 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3623 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3624 return 0;
3625 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3626 return 1;
3627 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3628 return 2;
3629 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3630 return 4;
3631 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3632 return 8;
3633 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3634 default:
3635 return 16;
3636 }
3637 }
3638
3639 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3640 {
3641 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3642 u16 link_cntl2;
3643
3644 if (radeon_pcie_gen2 == 0)
3645 return;
3646
3647 if (rdev->flags & RADEON_IS_IGP)
3648 return;
3649
3650 if (!(rdev->flags & RADEON_IS_PCIE))
3651 return;
3652
3653 /* x2 cards have a special sequence */
3654 if (ASIC_IS_X2(rdev))
3655 return;
3656
3657 /* only RV6xx+ chips are supported */
3658 if (rdev->family <= CHIP_R600)
3659 return;
3660
3661 /* 55 nm r6xx asics */
3662 if ((rdev->family == CHIP_RV670) ||
3663 (rdev->family == CHIP_RV620) ||
3664 (rdev->family == CHIP_RV635)) {
3665 /* advertise upconfig capability */
3666 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3667 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3668 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3669 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3670 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3671 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3672 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3673 LC_RECONFIG_ARC_MISSING_ESCAPE);
3674 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3675 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3676 } else {
3677 link_width_cntl |= LC_UPCONFIGURE_DIS;
3678 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3679 }
3680 }
3681
3682 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3683 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3684 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3685
3686 /* 55 nm r6xx asics */
3687 if ((rdev->family == CHIP_RV670) ||
3688 (rdev->family == CHIP_RV620) ||
3689 (rdev->family == CHIP_RV635)) {
3690 WREG32(MM_CFGREGS_CNTL, 0x8);
3691 link_cntl2 = RREG32(0x4088);
3692 WREG32(MM_CFGREGS_CNTL, 0);
3693 /* not supported yet */
3694 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3695 return;
3696 }
3697
3698 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3699 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3700 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3701 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3702 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3703 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3704
3705 tmp = RREG32(0x541c);
3706 WREG32(0x541c, tmp | 0x8);
3707 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3708 link_cntl2 = RREG16(0x4088);
3709 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3710 link_cntl2 |= 0x2;
3711 WREG16(0x4088, link_cntl2);
3712 WREG32(MM_CFGREGS_CNTL, 0);
3713
3714 if ((rdev->family == CHIP_RV670) ||
3715 (rdev->family == CHIP_RV620) ||
3716 (rdev->family == CHIP_RV635)) {
3717 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3718 training_cntl &= ~LC_POINT_7_PLUS_EN;
3719 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3720 } else {
3721 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3722 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3723 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3724 }
3725
3726 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3727 speed_cntl |= LC_GEN2_EN_STRAP;
3728 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3729
3730 } else {
3731 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3732 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3733 if (1)
3734 link_width_cntl |= LC_UPCONFIGURE_DIS;
3735 else
3736 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3737 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3738 }
3739 }
Linux kernel - Deliverables
This page took 0.113247 seconds and 5 git commands to generate.