2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
34 #include <drm/radeon_drm.h>
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
97 static const u32 crtc_offsets
[2] =
100 AVIVO_D2CRTC_H_TOTAL
- AVIVO_D1CRTC_H_TOTAL
103 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
105 /* r600,rv610,rv630,rv620,rv635,rv670 */
106 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
107 static void r600_gpu_init(struct radeon_device
*rdev
);
108 void r600_fini(struct radeon_device
*rdev
);
109 void r600_irq_disable(struct radeon_device
*rdev
);
110 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
);
113 * r600_get_xclk - get the xclk
115 * @rdev: radeon_device pointer
117 * Returns the reference clock used by the gfx engine
118 * (r6xx, IGPs, APUs).
120 u32
r600_get_xclk(struct radeon_device
*rdev
)
122 return rdev
->clock
.spll
.reference_freq
;
125 /* get temperature in millidegrees */
126 int rv6xx_get_temp(struct radeon_device
*rdev
)
128 u32 temp
= (RREG32(CG_THERMAL_STATUS
) & ASIC_T_MASK
) >>
130 int actual_temp
= temp
& 0xff;
135 return actual_temp
* 1000;
138 void r600_pm_get_dynpm_state(struct radeon_device
*rdev
)
142 rdev
->pm
.dynpm_can_upclock
= true;
143 rdev
->pm
.dynpm_can_downclock
= true;
145 /* power state array is low to high, default is first */
146 if ((rdev
->flags
& RADEON_IS_IGP
) || (rdev
->family
== CHIP_R600
)) {
147 int min_power_state_index
= 0;
149 if (rdev
->pm
.num_power_states
> 2)
150 min_power_state_index
= 1;
152 switch (rdev
->pm
.dynpm_planned_action
) {
153 case DYNPM_ACTION_MINIMUM
:
154 rdev
->pm
.requested_power_state_index
= min_power_state_index
;
155 rdev
->pm
.requested_clock_mode_index
= 0;
156 rdev
->pm
.dynpm_can_downclock
= false;
158 case DYNPM_ACTION_DOWNCLOCK
:
159 if (rdev
->pm
.current_power_state_index
== min_power_state_index
) {
160 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
161 rdev
->pm
.dynpm_can_downclock
= false;
163 if (rdev
->pm
.active_crtc_count
> 1) {
164 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
165 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
167 else if (i
>= rdev
->pm
.current_power_state_index
) {
168 rdev
->pm
.requested_power_state_index
=
169 rdev
->pm
.current_power_state_index
;
172 rdev
->pm
.requested_power_state_index
= i
;
177 if (rdev
->pm
.current_power_state_index
== 0)
178 rdev
->pm
.requested_power_state_index
=
179 rdev
->pm
.num_power_states
- 1;
181 rdev
->pm
.requested_power_state_index
=
182 rdev
->pm
.current_power_state_index
- 1;
185 rdev
->pm
.requested_clock_mode_index
= 0;
186 /* don't use the power state if crtcs are active and no display flag is set */
187 if ((rdev
->pm
.active_crtc_count
> 0) &&
188 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
189 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
190 RADEON_PM_MODE_NO_DISPLAY
)) {
191 rdev
->pm
.requested_power_state_index
++;
194 case DYNPM_ACTION_UPCLOCK
:
195 if (rdev
->pm
.current_power_state_index
== (rdev
->pm
.num_power_states
- 1)) {
196 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
197 rdev
->pm
.dynpm_can_upclock
= false;
199 if (rdev
->pm
.active_crtc_count
> 1) {
200 for (i
= (rdev
->pm
.num_power_states
- 1); i
>= 0; i
--) {
201 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
203 else if (i
<= rdev
->pm
.current_power_state_index
) {
204 rdev
->pm
.requested_power_state_index
=
205 rdev
->pm
.current_power_state_index
;
208 rdev
->pm
.requested_power_state_index
= i
;
213 rdev
->pm
.requested_power_state_index
=
214 rdev
->pm
.current_power_state_index
+ 1;
216 rdev
->pm
.requested_clock_mode_index
= 0;
218 case DYNPM_ACTION_DEFAULT
:
219 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
220 rdev
->pm
.requested_clock_mode_index
= 0;
221 rdev
->pm
.dynpm_can_upclock
= false;
223 case DYNPM_ACTION_NONE
:
225 DRM_ERROR("Requested mode for not defined action\n");
229 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
230 /* for now just select the first power state and switch between clock modes */
231 /* power state array is low to high, default is first (0) */
232 if (rdev
->pm
.active_crtc_count
> 1) {
233 rdev
->pm
.requested_power_state_index
= -1;
234 /* start at 1 as we don't want the default mode */
235 for (i
= 1; i
< rdev
->pm
.num_power_states
; i
++) {
236 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
238 else if ((rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_PERFORMANCE
) ||
239 (rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_BATTERY
)) {
240 rdev
->pm
.requested_power_state_index
= i
;
244 /* if nothing selected, grab the default state. */
245 if (rdev
->pm
.requested_power_state_index
== -1)
246 rdev
->pm
.requested_power_state_index
= 0;
248 rdev
->pm
.requested_power_state_index
= 1;
250 switch (rdev
->pm
.dynpm_planned_action
) {
251 case DYNPM_ACTION_MINIMUM
:
252 rdev
->pm
.requested_clock_mode_index
= 0;
253 rdev
->pm
.dynpm_can_downclock
= false;
255 case DYNPM_ACTION_DOWNCLOCK
:
256 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
257 if (rdev
->pm
.current_clock_mode_index
== 0) {
258 rdev
->pm
.requested_clock_mode_index
= 0;
259 rdev
->pm
.dynpm_can_downclock
= false;
261 rdev
->pm
.requested_clock_mode_index
=
262 rdev
->pm
.current_clock_mode_index
- 1;
264 rdev
->pm
.requested_clock_mode_index
= 0;
265 rdev
->pm
.dynpm_can_downclock
= false;
267 /* don't use the power state if crtcs are active and no display flag is set */
268 if ((rdev
->pm
.active_crtc_count
> 0) &&
269 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
270 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
271 RADEON_PM_MODE_NO_DISPLAY
)) {
272 rdev
->pm
.requested_clock_mode_index
++;
275 case DYNPM_ACTION_UPCLOCK
:
276 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
277 if (rdev
->pm
.current_clock_mode_index
==
278 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1)) {
279 rdev
->pm
.requested_clock_mode_index
= rdev
->pm
.current_clock_mode_index
;
280 rdev
->pm
.dynpm_can_upclock
= false;
282 rdev
->pm
.requested_clock_mode_index
=
283 rdev
->pm
.current_clock_mode_index
+ 1;
285 rdev
->pm
.requested_clock_mode_index
=
286 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1;
287 rdev
->pm
.dynpm_can_upclock
= false;
290 case DYNPM_ACTION_DEFAULT
:
291 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
292 rdev
->pm
.requested_clock_mode_index
= 0;
293 rdev
->pm
.dynpm_can_upclock
= false;
295 case DYNPM_ACTION_NONE
:
297 DRM_ERROR("Requested mode for not defined action\n");
302 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
303 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
304 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
,
305 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
306 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
,
307 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
311 void rs780_pm_init_profile(struct radeon_device
*rdev
)
313 if (rdev
->pm
.num_power_states
== 2) {
315 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
316 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
317 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
318 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
320 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 0;
321 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 0;
322 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
323 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
325 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 0;
326 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 0;
327 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
328 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
330 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 0;
331 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
332 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
333 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
335 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 0;
336 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
337 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
338 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
340 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 0;
341 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
342 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
343 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
345 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 0;
346 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 1;
347 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
348 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
349 } else if (rdev
->pm
.num_power_states
== 3) {
351 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
352 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
353 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
354 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
356 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
357 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
358 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
359 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
361 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
362 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
363 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
364 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
366 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
367 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 2;
368 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
369 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
371 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 1;
372 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 1;
373 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
374 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
376 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 1;
377 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 1;
378 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
379 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
381 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 1;
382 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
383 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
384 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
387 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
388 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
389 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
390 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
392 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 2;
393 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 2;
394 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
395 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
397 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 2;
398 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 2;
399 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
400 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
402 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 2;
403 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 3;
404 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
405 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
407 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
408 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
409 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
410 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
412 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
413 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
414 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
415 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
417 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
418 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 3;
419 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
420 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
424 void r600_pm_init_profile(struct radeon_device
*rdev
)
428 if (rdev
->family
== CHIP_R600
) {
431 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
432 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
433 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
434 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
436 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
437 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
438 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
439 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
441 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
442 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
443 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
444 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
446 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
447 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
448 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
449 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
451 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
452 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
453 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
454 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
456 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
457 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
458 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
459 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
461 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
462 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
463 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
464 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
466 if (rdev
->pm
.num_power_states
< 4) {
468 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
469 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
470 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
471 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
473 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
474 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
475 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
476 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
478 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
479 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
480 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
481 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
483 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
484 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
485 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
486 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
488 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
489 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 2;
490 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
491 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
493 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
494 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 2;
495 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
496 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
498 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
499 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
500 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
501 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
504 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
505 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
506 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
507 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
509 if (rdev
->flags
& RADEON_IS_MOBILITY
)
510 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
512 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
513 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
514 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
515 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
516 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
518 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
519 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
520 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
521 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
523 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
524 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
525 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
526 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
527 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
529 if (rdev
->flags
& RADEON_IS_MOBILITY
)
530 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
532 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
533 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
534 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
535 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
536 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
538 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
539 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
540 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
541 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
543 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
544 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
545 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
546 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
547 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
552 void r600_pm_misc(struct radeon_device
*rdev
)
554 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
555 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
556 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
557 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
559 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
560 /* 0xff01 is a flag rather then an actual voltage */
561 if (voltage
->voltage
== 0xff01)
563 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
564 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
565 rdev
->pm
.current_vddc
= voltage
->voltage
;
566 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage
->voltage
);
571 bool r600_gui_idle(struct radeon_device
*rdev
)
573 if (RREG32(GRBM_STATUS
) & GUI_ACTIVE
)
579 /* hpd for digital panel detect/disconnect */
580 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
582 bool connected
= false;
584 if (ASIC_IS_DCE3(rdev
)) {
587 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
591 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
595 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
599 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
604 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
608 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
617 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
621 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
625 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
635 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
636 enum radeon_hpd_id hpd
)
639 bool connected
= r600_hpd_sense(rdev
, hpd
);
641 if (ASIC_IS_DCE3(rdev
)) {
644 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
646 tmp
&= ~DC_HPDx_INT_POLARITY
;
648 tmp
|= DC_HPDx_INT_POLARITY
;
649 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
652 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
654 tmp
&= ~DC_HPDx_INT_POLARITY
;
656 tmp
|= DC_HPDx_INT_POLARITY
;
657 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
660 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
662 tmp
&= ~DC_HPDx_INT_POLARITY
;
664 tmp
|= DC_HPDx_INT_POLARITY
;
665 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
668 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
670 tmp
&= ~DC_HPDx_INT_POLARITY
;
672 tmp
|= DC_HPDx_INT_POLARITY
;
673 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
676 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
678 tmp
&= ~DC_HPDx_INT_POLARITY
;
680 tmp
|= DC_HPDx_INT_POLARITY
;
681 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
685 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
687 tmp
&= ~DC_HPDx_INT_POLARITY
;
689 tmp
|= DC_HPDx_INT_POLARITY
;
690 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
698 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
700 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
702 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
703 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
706 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
708 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
710 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
711 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
714 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
716 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
718 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
719 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
727 void r600_hpd_init(struct radeon_device
*rdev
)
729 struct drm_device
*dev
= rdev
->ddev
;
730 struct drm_connector
*connector
;
733 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
734 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
736 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
737 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
738 /* don't try to enable hpd on eDP or LVDS avoid breaking the
739 * aux dp channel on imac and help (but not completely fix)
740 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
744 if (ASIC_IS_DCE3(rdev
)) {
745 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
746 if (ASIC_IS_DCE32(rdev
))
749 switch (radeon_connector
->hpd
.hpd
) {
751 WREG32(DC_HPD1_CONTROL
, tmp
);
754 WREG32(DC_HPD2_CONTROL
, tmp
);
757 WREG32(DC_HPD3_CONTROL
, tmp
);
760 WREG32(DC_HPD4_CONTROL
, tmp
);
764 WREG32(DC_HPD5_CONTROL
, tmp
);
767 WREG32(DC_HPD6_CONTROL
, tmp
);
773 switch (radeon_connector
->hpd
.hpd
) {
775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
778 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
781 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
787 enable
|= 1 << radeon_connector
->hpd
.hpd
;
788 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
790 radeon_irq_kms_enable_hpd(rdev
, enable
);
793 void r600_hpd_fini(struct radeon_device
*rdev
)
795 struct drm_device
*dev
= rdev
->ddev
;
796 struct drm_connector
*connector
;
797 unsigned disable
= 0;
799 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
800 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
801 if (ASIC_IS_DCE3(rdev
)) {
802 switch (radeon_connector
->hpd
.hpd
) {
804 WREG32(DC_HPD1_CONTROL
, 0);
807 WREG32(DC_HPD2_CONTROL
, 0);
810 WREG32(DC_HPD3_CONTROL
, 0);
813 WREG32(DC_HPD4_CONTROL
, 0);
817 WREG32(DC_HPD5_CONTROL
, 0);
820 WREG32(DC_HPD6_CONTROL
, 0);
826 switch (radeon_connector
->hpd
.hpd
) {
828 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
831 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
834 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
840 disable
|= 1 << radeon_connector
->hpd
.hpd
;
842 radeon_irq_kms_disable_hpd(rdev
, disable
);
848 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
853 /* flush hdp cache so updates hit vram */
854 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
855 !(rdev
->flags
& RADEON_IS_AGP
)) {
856 void __iomem
*ptr
= (void *)rdev
->gart
.ptr
;
859 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
860 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
861 * This seems to cause problems on some AGP cards. Just use the old
864 WREG32(HDP_DEBUG1
, 0);
865 tmp
= readl((void __iomem
*)ptr
);
867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
872 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
874 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
875 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
877 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
887 int r600_pcie_gart_init(struct radeon_device
*rdev
)
891 if (rdev
->gart
.robj
) {
892 WARN(1, "R600 PCIE GART already initialized\n");
895 /* Initialize common gart structure */
896 r
= radeon_gart_init(rdev
);
899 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
900 return radeon_gart_table_vram_alloc(rdev
);
903 static int r600_pcie_gart_enable(struct radeon_device
*rdev
)
908 if (rdev
->gart
.robj
== NULL
) {
909 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
912 r
= radeon_gart_table_vram_pin(rdev
);
915 radeon_gart_restore(rdev
);
918 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
920 EFFECTIVE_L2_QUEUE_SIZE(7));
921 WREG32(VM_L2_CNTL2
, 0);
922 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
923 /* Setup TLB control */
924 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
925 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
927 ENABLE_WAIT_L2_QUERY
;
928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
945 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
948 (u32
)(rdev
->dummy_page
.addr
>> 12));
949 for (i
= 1; i
< 7; i
++)
950 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
952 r600_pcie_gart_tlb_flush(rdev
);
953 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
954 (unsigned)(rdev
->mc
.gtt_size
>> 20),
955 (unsigned long long)rdev
->gart
.table_addr
);
956 rdev
->gart
.ready
= true;
960 static void r600_pcie_gart_disable(struct radeon_device
*rdev
)
965 /* Disable all tables */
966 for (i
= 0; i
< 7; i
++)
967 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
969 /* Disable L2 cache */
970 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
971 EFFECTIVE_L2_QUEUE_SIZE(7));
972 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
973 /* Setup L1 TLB control */
974 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
975 ENABLE_WAIT_L2_QUERY
;
976 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
977 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
978 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
979 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
980 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
981 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
982 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
983 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
984 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
985 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
986 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
987 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
988 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
989 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
990 radeon_gart_table_vram_unpin(rdev
);
993 static void r600_pcie_gart_fini(struct radeon_device
*rdev
)
995 radeon_gart_fini(rdev
);
996 r600_pcie_gart_disable(rdev
);
997 radeon_gart_table_vram_free(rdev
);
1000 static void r600_agp_enable(struct radeon_device
*rdev
)
1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1008 EFFECTIVE_L2_QUEUE_SIZE(7));
1009 WREG32(VM_L2_CNTL2
, 0);
1010 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1011 /* Setup TLB control */
1012 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1014 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1015 ENABLE_WAIT_L2_QUERY
;
1016 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1020 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1021 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1022 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1023 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1024 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1025 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1030 for (i
= 0; i
< 7; i
++)
1031 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1034 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
1039 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1040 /* read MC_STATUS */
1041 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
1049 static void r600_mc_program(struct radeon_device
*rdev
)
1051 struct rv515_mc_save save
;
1055 /* Initialize HDP */
1056 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1057 WREG32((0x2c14 + j
), 0x00000000);
1058 WREG32((0x2c18 + j
), 0x00000000);
1059 WREG32((0x2c1c + j
), 0x00000000);
1060 WREG32((0x2c20 + j
), 0x00000000);
1061 WREG32((0x2c24 + j
), 0x00000000);
1063 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1065 rv515_mc_stop(rdev
, &save
);
1066 if (r600_mc_wait_for_idle(rdev
)) {
1067 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1069 /* Lockout access through VGA aperture (doesn't exist before R600) */
1070 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1071 /* Update configuration */
1072 if (rdev
->flags
& RADEON_IS_AGP
) {
1073 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1074 /* VRAM before AGP */
1075 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1076 rdev
->mc
.vram_start
>> 12);
1077 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1078 rdev
->mc
.gtt_end
>> 12);
1080 /* VRAM after AGP */
1081 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1082 rdev
->mc
.gtt_start
>> 12);
1083 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1084 rdev
->mc
.vram_end
>> 12);
1087 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
1088 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
1090 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1091 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1092 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1093 WREG32(MC_VM_FB_LOCATION
, tmp
);
1094 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1095 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1096 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1097 if (rdev
->flags
& RADEON_IS_AGP
) {
1098 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
1099 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
1100 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1102 WREG32(MC_VM_AGP_BASE
, 0);
1103 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1104 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1106 if (r600_mc_wait_for_idle(rdev
)) {
1107 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1109 rv515_mc_resume(rdev
, &save
);
1110 /* we need to own VRAM, so turn off the VGA renderer here
1111 * to stop it overwriting our objects */
1112 rv515_vga_render_disable(rdev
);
1116 * r600_vram_gtt_location - try to find VRAM & GTT location
1117 * @rdev: radeon device structure holding all necessary informations
1118 * @mc: memory controller structure holding memory informations
1120 * Function will place try to place VRAM at same place as in CPU (PCI)
1121 * address space as some GPU seems to have issue when we reprogram at
1122 * different address space.
1124 * If there is not enough space to fit the unvisible VRAM after the
1125 * aperture then we limit the VRAM size to the aperture.
1127 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1128 * them to be in one from GPU point of view so that we can program GPU to
1129 * catch access outside them (weird GPU policy see ??).
1131 * This function will never fails, worst case are limiting VRAM or GTT.
1133 * Note: GTT start, end, size should be initialized before calling this
1134 * function on AGP platform.
1136 static void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
1138 u64 size_bf
, size_af
;
1140 if (mc
->mc_vram_size
> 0xE0000000) {
1141 /* leave room for at least 512M GTT */
1142 dev_warn(rdev
->dev
, "limiting VRAM\n");
1143 mc
->real_vram_size
= 0xE0000000;
1144 mc
->mc_vram_size
= 0xE0000000;
1146 if (rdev
->flags
& RADEON_IS_AGP
) {
1147 size_bf
= mc
->gtt_start
;
1148 size_af
= mc
->mc_mask
- mc
->gtt_end
;
1149 if (size_bf
> size_af
) {
1150 if (mc
->mc_vram_size
> size_bf
) {
1151 dev_warn(rdev
->dev
, "limiting VRAM\n");
1152 mc
->real_vram_size
= size_bf
;
1153 mc
->mc_vram_size
= size_bf
;
1155 mc
->vram_start
= mc
->gtt_start
- mc
->mc_vram_size
;
1157 if (mc
->mc_vram_size
> size_af
) {
1158 dev_warn(rdev
->dev
, "limiting VRAM\n");
1159 mc
->real_vram_size
= size_af
;
1160 mc
->mc_vram_size
= size_af
;
1162 mc
->vram_start
= mc
->gtt_end
+ 1;
1164 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
1165 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1166 mc
->mc_vram_size
>> 20, mc
->vram_start
,
1167 mc
->vram_end
, mc
->real_vram_size
>> 20);
1170 if (rdev
->flags
& RADEON_IS_IGP
) {
1171 base
= RREG32(MC_VM_FB_LOCATION
) & 0xFFFF;
1174 radeon_vram_location(rdev
, &rdev
->mc
, base
);
1175 rdev
->mc
.gtt_base_align
= 0;
1176 radeon_gtt_location(rdev
, mc
);
1180 static int r600_mc_init(struct radeon_device
*rdev
)
1183 int chansize
, numchan
;
1185 /* Get VRAM informations */
1186 rdev
->mc
.vram_is_ddr
= true;
1187 tmp
= RREG32(RAMCFG
);
1188 if (tmp
& CHANSIZE_OVERRIDE
) {
1190 } else if (tmp
& CHANSIZE_MASK
) {
1195 tmp
= RREG32(CHMAP
);
1196 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1211 rdev
->mc
.vram_width
= numchan
* chansize
;
1212 /* Could aper size report 0 ? */
1213 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1214 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1215 /* Setup GPU memory space */
1216 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
1217 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
1218 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1219 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1221 if (rdev
->flags
& RADEON_IS_IGP
) {
1222 rs690_pm_info(rdev
);
1223 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
1225 radeon_update_bandwidth_info(rdev
);
1229 int r600_vram_scratch_init(struct radeon_device
*rdev
)
1233 if (rdev
->vram_scratch
.robj
== NULL
) {
1234 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
,
1235 PAGE_SIZE
, true, RADEON_GEM_DOMAIN_VRAM
,
1236 NULL
, &rdev
->vram_scratch
.robj
);
1242 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1243 if (unlikely(r
!= 0))
1245 r
= radeon_bo_pin(rdev
->vram_scratch
.robj
,
1246 RADEON_GEM_DOMAIN_VRAM
, &rdev
->vram_scratch
.gpu_addr
);
1248 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1251 r
= radeon_bo_kmap(rdev
->vram_scratch
.robj
,
1252 (void **)&rdev
->vram_scratch
.ptr
);
1254 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1255 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1260 void r600_vram_scratch_fini(struct radeon_device
*rdev
)
1264 if (rdev
->vram_scratch
.robj
== NULL
) {
1267 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1268 if (likely(r
== 0)) {
1269 radeon_bo_kunmap(rdev
->vram_scratch
.robj
);
1270 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1271 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1273 radeon_bo_unref(&rdev
->vram_scratch
.robj
);
1276 void r600_set_bios_scratch_engine_hung(struct radeon_device
*rdev
, bool hung
)
1278 u32 tmp
= RREG32(R600_BIOS_3_SCRATCH
);
1281 tmp
|= ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
1283 tmp
&= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
1285 WREG32(R600_BIOS_3_SCRATCH
, tmp
);
1288 static void r600_print_gpu_status_regs(struct radeon_device
*rdev
)
1290 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS = 0x%08X\n",
1291 RREG32(R_008010_GRBM_STATUS
));
1292 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1293 RREG32(R_008014_GRBM_STATUS2
));
1294 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS = 0x%08X\n",
1295 RREG32(R_000E50_SRBM_STATUS
));
1296 dev_info(rdev
->dev
, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1297 RREG32(CP_STALLED_STAT1
));
1298 dev_info(rdev
->dev
, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1299 RREG32(CP_STALLED_STAT2
));
1300 dev_info(rdev
->dev
, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1301 RREG32(CP_BUSY_STAT
));
1302 dev_info(rdev
->dev
, " R_008680_CP_STAT = 0x%08X\n",
1304 dev_info(rdev
->dev
, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1305 RREG32(DMA_STATUS_REG
));
1308 static bool r600_is_display_hung(struct radeon_device
*rdev
)
1314 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1315 if (RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]) & AVIVO_CRTC_EN
) {
1316 crtc_status
[i
] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
1317 crtc_hung
|= (1 << i
);
1321 for (j
= 0; j
< 10; j
++) {
1322 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1323 if (crtc_hung
& (1 << i
)) {
1324 tmp
= RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
1325 if (tmp
!= crtc_status
[i
])
1326 crtc_hung
&= ~(1 << i
);
1337 static u32
r600_gpu_check_soft_reset(struct radeon_device
*rdev
)
1343 tmp
= RREG32(R_008010_GRBM_STATUS
);
1344 if (rdev
->family
>= CHIP_RV770
) {
1345 if (G_008010_PA_BUSY(tmp
) | G_008010_SC_BUSY(tmp
) |
1346 G_008010_SH_BUSY(tmp
) | G_008010_SX_BUSY(tmp
) |
1347 G_008010_TA_BUSY(tmp
) | G_008010_VGT_BUSY(tmp
) |
1348 G_008010_DB03_BUSY(tmp
) | G_008010_CB03_BUSY(tmp
) |
1349 G_008010_SPI03_BUSY(tmp
) | G_008010_VGT_BUSY_NO_DMA(tmp
))
1350 reset_mask
|= RADEON_RESET_GFX
;
1352 if (G_008010_PA_BUSY(tmp
) | G_008010_SC_BUSY(tmp
) |
1353 G_008010_SH_BUSY(tmp
) | G_008010_SX_BUSY(tmp
) |
1354 G_008010_TA03_BUSY(tmp
) | G_008010_VGT_BUSY(tmp
) |
1355 G_008010_DB03_BUSY(tmp
) | G_008010_CB03_BUSY(tmp
) |
1356 G_008010_SPI03_BUSY(tmp
) | G_008010_VGT_BUSY_NO_DMA(tmp
))
1357 reset_mask
|= RADEON_RESET_GFX
;
1360 if (G_008010_CF_RQ_PENDING(tmp
) | G_008010_PF_RQ_PENDING(tmp
) |
1361 G_008010_CP_BUSY(tmp
) | G_008010_CP_COHERENCY_BUSY(tmp
))
1362 reset_mask
|= RADEON_RESET_CP
;
1364 if (G_008010_GRBM_EE_BUSY(tmp
))
1365 reset_mask
|= RADEON_RESET_GRBM
| RADEON_RESET_GFX
| RADEON_RESET_CP
;
1367 /* DMA_STATUS_REG */
1368 tmp
= RREG32(DMA_STATUS_REG
);
1369 if (!(tmp
& DMA_IDLE
))
1370 reset_mask
|= RADEON_RESET_DMA
;
1373 tmp
= RREG32(R_000E50_SRBM_STATUS
);
1374 if (G_000E50_RLC_RQ_PENDING(tmp
) | G_000E50_RLC_BUSY(tmp
))
1375 reset_mask
|= RADEON_RESET_RLC
;
1377 if (G_000E50_IH_BUSY(tmp
))
1378 reset_mask
|= RADEON_RESET_IH
;
1380 if (G_000E50_SEM_BUSY(tmp
))
1381 reset_mask
|= RADEON_RESET_SEM
;
1383 if (G_000E50_GRBM_RQ_PENDING(tmp
))
1384 reset_mask
|= RADEON_RESET_GRBM
;
1386 if (G_000E50_VMC_BUSY(tmp
))
1387 reset_mask
|= RADEON_RESET_VMC
;
1389 if (G_000E50_MCB_BUSY(tmp
) | G_000E50_MCDZ_BUSY(tmp
) |
1390 G_000E50_MCDY_BUSY(tmp
) | G_000E50_MCDX_BUSY(tmp
) |
1391 G_000E50_MCDW_BUSY(tmp
))
1392 reset_mask
|= RADEON_RESET_MC
;
1394 if (r600_is_display_hung(rdev
))
1395 reset_mask
|= RADEON_RESET_DISPLAY
;
1397 /* Skip MC reset as it's mostly likely not hung, just busy */
1398 if (reset_mask
& RADEON_RESET_MC
) {
1399 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
1400 reset_mask
&= ~RADEON_RESET_MC
;
1406 static void r600_gpu_soft_reset(struct radeon_device
*rdev
, u32 reset_mask
)
1408 struct rv515_mc_save save
;
1409 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
1412 if (reset_mask
== 0)
1415 dev_info(rdev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
1417 r600_print_gpu_status_regs(rdev
);
1419 /* Disable CP parsing/prefetching */
1420 if (rdev
->family
>= CHIP_RV770
)
1421 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1423 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1425 /* disable the RLC */
1426 WREG32(RLC_CNTL
, 0);
1428 if (reset_mask
& RADEON_RESET_DMA
) {
1430 tmp
= RREG32(DMA_RB_CNTL
);
1431 tmp
&= ~DMA_RB_ENABLE
;
1432 WREG32(DMA_RB_CNTL
, tmp
);
1437 rv515_mc_stop(rdev
, &save
);
1438 if (r600_mc_wait_for_idle(rdev
)) {
1439 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1442 if (reset_mask
& (RADEON_RESET_GFX
| RADEON_RESET_COMPUTE
)) {
1443 if (rdev
->family
>= CHIP_RV770
)
1444 grbm_soft_reset
|= S_008020_SOFT_RESET_DB(1) |
1445 S_008020_SOFT_RESET_CB(1) |
1446 S_008020_SOFT_RESET_PA(1) |
1447 S_008020_SOFT_RESET_SC(1) |
1448 S_008020_SOFT_RESET_SPI(1) |
1449 S_008020_SOFT_RESET_SX(1) |
1450 S_008020_SOFT_RESET_SH(1) |
1451 S_008020_SOFT_RESET_TC(1) |
1452 S_008020_SOFT_RESET_TA(1) |
1453 S_008020_SOFT_RESET_VC(1) |
1454 S_008020_SOFT_RESET_VGT(1);
1456 grbm_soft_reset
|= S_008020_SOFT_RESET_CR(1) |
1457 S_008020_SOFT_RESET_DB(1) |
1458 S_008020_SOFT_RESET_CB(1) |
1459 S_008020_SOFT_RESET_PA(1) |
1460 S_008020_SOFT_RESET_SC(1) |
1461 S_008020_SOFT_RESET_SMX(1) |
1462 S_008020_SOFT_RESET_SPI(1) |
1463 S_008020_SOFT_RESET_SX(1) |
1464 S_008020_SOFT_RESET_SH(1) |
1465 S_008020_SOFT_RESET_TC(1) |
1466 S_008020_SOFT_RESET_TA(1) |
1467 S_008020_SOFT_RESET_VC(1) |
1468 S_008020_SOFT_RESET_VGT(1);
1471 if (reset_mask
& RADEON_RESET_CP
) {
1472 grbm_soft_reset
|= S_008020_SOFT_RESET_CP(1) |
1473 S_008020_SOFT_RESET_VGT(1);
1475 srbm_soft_reset
|= S_000E60_SOFT_RESET_GRBM(1);
1478 if (reset_mask
& RADEON_RESET_DMA
) {
1479 if (rdev
->family
>= CHIP_RV770
)
1480 srbm_soft_reset
|= RV770_SOFT_RESET_DMA
;
1482 srbm_soft_reset
|= SOFT_RESET_DMA
;
1485 if (reset_mask
& RADEON_RESET_RLC
)
1486 srbm_soft_reset
|= S_000E60_SOFT_RESET_RLC(1);
1488 if (reset_mask
& RADEON_RESET_SEM
)
1489 srbm_soft_reset
|= S_000E60_SOFT_RESET_SEM(1);
1491 if (reset_mask
& RADEON_RESET_IH
)
1492 srbm_soft_reset
|= S_000E60_SOFT_RESET_IH(1);
1494 if (reset_mask
& RADEON_RESET_GRBM
)
1495 srbm_soft_reset
|= S_000E60_SOFT_RESET_GRBM(1);
1497 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
1498 if (reset_mask
& RADEON_RESET_MC
)
1499 srbm_soft_reset
|= S_000E60_SOFT_RESET_MC(1);
1502 if (reset_mask
& RADEON_RESET_VMC
)
1503 srbm_soft_reset
|= S_000E60_SOFT_RESET_VMC(1);
1505 if (grbm_soft_reset
) {
1506 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1507 tmp
|= grbm_soft_reset
;
1508 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1509 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1510 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1514 tmp
&= ~grbm_soft_reset
;
1515 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1516 tmp
= RREG32(R_008020_GRBM_SOFT_RESET
);
1519 if (srbm_soft_reset
) {
1520 tmp
= RREG32(SRBM_SOFT_RESET
);
1521 tmp
|= srbm_soft_reset
;
1522 dev_info(rdev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1523 WREG32(SRBM_SOFT_RESET
, tmp
);
1524 tmp
= RREG32(SRBM_SOFT_RESET
);
1528 tmp
&= ~srbm_soft_reset
;
1529 WREG32(SRBM_SOFT_RESET
, tmp
);
1530 tmp
= RREG32(SRBM_SOFT_RESET
);
1533 /* Wait a little for things to settle down */
1536 rv515_mc_resume(rdev
, &save
);
1539 r600_print_gpu_status_regs(rdev
);
1542 int r600_asic_reset(struct radeon_device
*rdev
)
1546 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1549 r600_set_bios_scratch_engine_hung(rdev
, true);
1551 r600_gpu_soft_reset(rdev
, reset_mask
);
1553 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1556 r600_set_bios_scratch_engine_hung(rdev
, false);
1562 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1564 * @rdev: radeon_device pointer
1565 * @ring: radeon_ring structure holding ring information
1567 * Check if the GFX engine is locked up.
1568 * Returns true if the engine appears to be locked up, false if not.
1570 bool r600_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1572 u32 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1574 if (!(reset_mask
& (RADEON_RESET_GFX
|
1575 RADEON_RESET_COMPUTE
|
1576 RADEON_RESET_CP
))) {
1577 radeon_ring_lockup_update(ring
);
1580 /* force CP activities */
1581 radeon_ring_force_activity(rdev
, ring
);
1582 return radeon_ring_test_lockup(rdev
, ring
);
1586 * r600_dma_is_lockup - Check if the DMA engine is locked up
1588 * @rdev: radeon_device pointer
1589 * @ring: radeon_ring structure holding ring information
1591 * Check if the async DMA engine is locked up.
1592 * Returns true if the engine appears to be locked up, false if not.
1594 bool r600_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1596 u32 reset_mask
= r600_gpu_check_soft_reset(rdev
);
1598 if (!(reset_mask
& RADEON_RESET_DMA
)) {
1599 radeon_ring_lockup_update(ring
);
1602 /* force ring activities */
1603 radeon_ring_force_activity(rdev
, ring
);
1604 return radeon_ring_test_lockup(rdev
, ring
);
1607 u32
r6xx_remap_render_backend(struct radeon_device
*rdev
,
1608 u32 tiling_pipe_num
,
1610 u32 total_max_rb_num
,
1611 u32 disabled_rb_mask
)
1613 u32 rendering_pipe_num
, rb_num_width
, req_rb_num
;
1614 u32 pipe_rb_ratio
, pipe_rb_remain
, tmp
;
1615 u32 data
= 0, mask
= 1 << (max_rb_num
- 1);
1618 /* mask out the RBs that don't exist on that asic */
1619 tmp
= disabled_rb_mask
| ((0xff << max_rb_num
) & 0xff);
1620 /* make sure at least one RB is available */
1621 if ((tmp
& 0xff) != 0xff)
1622 disabled_rb_mask
= tmp
;
1624 rendering_pipe_num
= 1 << tiling_pipe_num
;
1625 req_rb_num
= total_max_rb_num
- r600_count_pipe_bits(disabled_rb_mask
);
1626 BUG_ON(rendering_pipe_num
< req_rb_num
);
1628 pipe_rb_ratio
= rendering_pipe_num
/ req_rb_num
;
1629 pipe_rb_remain
= rendering_pipe_num
- pipe_rb_ratio
* req_rb_num
;
1631 if (rdev
->family
<= CHIP_RV740
) {
1639 for (i
= 0; i
< max_rb_num
; i
++) {
1640 if (!(mask
& disabled_rb_mask
)) {
1641 for (j
= 0; j
< pipe_rb_ratio
; j
++) {
1642 data
<<= rb_num_width
;
1643 data
|= max_rb_num
- i
- 1;
1645 if (pipe_rb_remain
) {
1646 data
<<= rb_num_width
;
1647 data
|= max_rb_num
- i
- 1;
1657 int r600_count_pipe_bits(uint32_t val
)
1659 return hweight32(val
);
1662 static void r600_gpu_init(struct radeon_device
*rdev
)
1666 u32 cc_rb_backend_disable
;
1667 u32 cc_gc_shader_pipe_config
;
1671 u32 sq_gpr_resource_mgmt_1
= 0;
1672 u32 sq_gpr_resource_mgmt_2
= 0;
1673 u32 sq_thread_resource_mgmt
= 0;
1674 u32 sq_stack_resource_mgmt_1
= 0;
1675 u32 sq_stack_resource_mgmt_2
= 0;
1676 u32 disabled_rb_mask
;
1678 rdev
->config
.r600
.tiling_group_size
= 256;
1679 switch (rdev
->family
) {
1681 rdev
->config
.r600
.max_pipes
= 4;
1682 rdev
->config
.r600
.max_tile_pipes
= 8;
1683 rdev
->config
.r600
.max_simds
= 4;
1684 rdev
->config
.r600
.max_backends
= 4;
1685 rdev
->config
.r600
.max_gprs
= 256;
1686 rdev
->config
.r600
.max_threads
= 192;
1687 rdev
->config
.r600
.max_stack_entries
= 256;
1688 rdev
->config
.r600
.max_hw_contexts
= 8;
1689 rdev
->config
.r600
.max_gs_threads
= 16;
1690 rdev
->config
.r600
.sx_max_export_size
= 128;
1691 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1692 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1693 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1697 rdev
->config
.r600
.max_pipes
= 2;
1698 rdev
->config
.r600
.max_tile_pipes
= 2;
1699 rdev
->config
.r600
.max_simds
= 3;
1700 rdev
->config
.r600
.max_backends
= 1;
1701 rdev
->config
.r600
.max_gprs
= 128;
1702 rdev
->config
.r600
.max_threads
= 192;
1703 rdev
->config
.r600
.max_stack_entries
= 128;
1704 rdev
->config
.r600
.max_hw_contexts
= 8;
1705 rdev
->config
.r600
.max_gs_threads
= 4;
1706 rdev
->config
.r600
.sx_max_export_size
= 128;
1707 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1708 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1709 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1715 rdev
->config
.r600
.max_pipes
= 1;
1716 rdev
->config
.r600
.max_tile_pipes
= 1;
1717 rdev
->config
.r600
.max_simds
= 2;
1718 rdev
->config
.r600
.max_backends
= 1;
1719 rdev
->config
.r600
.max_gprs
= 128;
1720 rdev
->config
.r600
.max_threads
= 192;
1721 rdev
->config
.r600
.max_stack_entries
= 128;
1722 rdev
->config
.r600
.max_hw_contexts
= 4;
1723 rdev
->config
.r600
.max_gs_threads
= 4;
1724 rdev
->config
.r600
.sx_max_export_size
= 128;
1725 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1726 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1727 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1730 rdev
->config
.r600
.max_pipes
= 4;
1731 rdev
->config
.r600
.max_tile_pipes
= 4;
1732 rdev
->config
.r600
.max_simds
= 4;
1733 rdev
->config
.r600
.max_backends
= 4;
1734 rdev
->config
.r600
.max_gprs
= 192;
1735 rdev
->config
.r600
.max_threads
= 192;
1736 rdev
->config
.r600
.max_stack_entries
= 256;
1737 rdev
->config
.r600
.max_hw_contexts
= 8;
1738 rdev
->config
.r600
.max_gs_threads
= 16;
1739 rdev
->config
.r600
.sx_max_export_size
= 128;
1740 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1741 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1742 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1748 /* Initialize HDP */
1749 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1750 WREG32((0x2c14 + j
), 0x00000000);
1751 WREG32((0x2c18 + j
), 0x00000000);
1752 WREG32((0x2c1c + j
), 0x00000000);
1753 WREG32((0x2c20 + j
), 0x00000000);
1754 WREG32((0x2c24 + j
), 0x00000000);
1757 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1761 ramcfg
= RREG32(RAMCFG
);
1762 switch (rdev
->config
.r600
.max_tile_pipes
) {
1764 tiling_config
|= PIPE_TILING(0);
1767 tiling_config
|= PIPE_TILING(1);
1770 tiling_config
|= PIPE_TILING(2);
1773 tiling_config
|= PIPE_TILING(3);
1778 rdev
->config
.r600
.tiling_npipes
= rdev
->config
.r600
.max_tile_pipes
;
1779 rdev
->config
.r600
.tiling_nbanks
= 4 << ((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1780 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1781 tiling_config
|= GROUP_SIZE((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1783 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1785 tiling_config
|= ROW_TILING(3);
1786 tiling_config
|= SAMPLE_SPLIT(3);
1788 tiling_config
|= ROW_TILING(tmp
);
1789 tiling_config
|= SAMPLE_SPLIT(tmp
);
1791 tiling_config
|= BANK_SWAPS(1);
1793 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1794 tmp
= R6XX_MAX_BACKENDS
-
1795 r600_count_pipe_bits((cc_rb_backend_disable
>> 16) & R6XX_MAX_BACKENDS_MASK
);
1796 if (tmp
< rdev
->config
.r600
.max_backends
) {
1797 rdev
->config
.r600
.max_backends
= tmp
;
1800 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0x00ffff00;
1801 tmp
= R6XX_MAX_PIPES
-
1802 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 8) & R6XX_MAX_PIPES_MASK
);
1803 if (tmp
< rdev
->config
.r600
.max_pipes
) {
1804 rdev
->config
.r600
.max_pipes
= tmp
;
1806 tmp
= R6XX_MAX_SIMDS
-
1807 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 16) & R6XX_MAX_SIMDS_MASK
);
1808 if (tmp
< rdev
->config
.r600
.max_simds
) {
1809 rdev
->config
.r600
.max_simds
= tmp
;
1812 disabled_rb_mask
= (RREG32(CC_RB_BACKEND_DISABLE
) >> 16) & R6XX_MAX_BACKENDS_MASK
;
1813 tmp
= (tiling_config
& PIPE_TILING__MASK
) >> PIPE_TILING__SHIFT
;
1814 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.r600
.max_backends
,
1815 R6XX_MAX_BACKENDS
, disabled_rb_mask
);
1816 tiling_config
|= tmp
<< 16;
1817 rdev
->config
.r600
.backend_map
= tmp
;
1819 rdev
->config
.r600
.tile_config
= tiling_config
;
1820 WREG32(GB_TILING_CONFIG
, tiling_config
);
1821 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1822 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1823 WREG32(DMA_TILING_CONFIG
, tiling_config
& 0xffff);
1825 tmp
= R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
1826 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1827 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1829 /* Setup some CP states */
1830 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1831 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1833 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1834 SYNC_WALKER
| SYNC_ALIGNER
));
1835 /* Setup various GPU states */
1836 if (rdev
->family
== CHIP_RV670
)
1837 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1839 tmp
= RREG32(SX_DEBUG_1
);
1840 tmp
|= SMX_EVENT_RELEASE
;
1841 if ((rdev
->family
> CHIP_R600
))
1842 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1843 WREG32(SX_DEBUG_1
, tmp
);
1845 if (((rdev
->family
) == CHIP_R600
) ||
1846 ((rdev
->family
) == CHIP_RV630
) ||
1847 ((rdev
->family
) == CHIP_RV610
) ||
1848 ((rdev
->family
) == CHIP_RV620
) ||
1849 ((rdev
->family
) == CHIP_RS780
) ||
1850 ((rdev
->family
) == CHIP_RS880
)) {
1851 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1853 WREG32(DB_DEBUG
, 0);
1855 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1856 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1858 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1859 WREG32(VGT_NUM_INSTANCES
, 0);
1861 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1862 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1864 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1865 if (((rdev
->family
) == CHIP_RV610
) ||
1866 ((rdev
->family
) == CHIP_RV620
) ||
1867 ((rdev
->family
) == CHIP_RS780
) ||
1868 ((rdev
->family
) == CHIP_RS880
)) {
1869 tmp
= (CACHE_FIFO_SIZE(0xa) |
1870 FETCH_FIFO_HIWATER(0xa) |
1871 DONE_FIFO_HIWATER(0xe0) |
1872 ALU_UPDATE_FIFO_HIWATER(0x8));
1873 } else if (((rdev
->family
) == CHIP_R600
) ||
1874 ((rdev
->family
) == CHIP_RV630
)) {
1875 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1876 tmp
|= DONE_FIFO_HIWATER(0x4);
1878 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1880 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1881 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1883 sq_config
= RREG32(SQ_CONFIG
);
1884 sq_config
&= ~(PS_PRIO(3) |
1888 sq_config
|= (DX9_CONSTS
|
1895 if ((rdev
->family
) == CHIP_R600
) {
1896 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1898 NUM_CLAUSE_TEMP_GPRS(4));
1899 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1901 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1902 NUM_VS_THREADS(48) |
1905 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1906 NUM_VS_STACK_ENTRIES(128));
1907 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1908 NUM_ES_STACK_ENTRIES(0));
1909 } else if (((rdev
->family
) == CHIP_RV610
) ||
1910 ((rdev
->family
) == CHIP_RV620
) ||
1911 ((rdev
->family
) == CHIP_RS780
) ||
1912 ((rdev
->family
) == CHIP_RS880
)) {
1913 /* no vertex cache */
1914 sq_config
&= ~VC_ENABLE
;
1916 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1918 NUM_CLAUSE_TEMP_GPRS(2));
1919 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1921 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1922 NUM_VS_THREADS(78) |
1924 NUM_ES_THREADS(31));
1925 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1926 NUM_VS_STACK_ENTRIES(40));
1927 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1928 NUM_ES_STACK_ENTRIES(16));
1929 } else if (((rdev
->family
) == CHIP_RV630
) ||
1930 ((rdev
->family
) == CHIP_RV635
)) {
1931 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1933 NUM_CLAUSE_TEMP_GPRS(2));
1934 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1936 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1937 NUM_VS_THREADS(78) |
1939 NUM_ES_THREADS(31));
1940 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1941 NUM_VS_STACK_ENTRIES(40));
1942 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1943 NUM_ES_STACK_ENTRIES(16));
1944 } else if ((rdev
->family
) == CHIP_RV670
) {
1945 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1947 NUM_CLAUSE_TEMP_GPRS(2));
1948 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1950 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1951 NUM_VS_THREADS(78) |
1953 NUM_ES_THREADS(31));
1954 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1955 NUM_VS_STACK_ENTRIES(64));
1956 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1957 NUM_ES_STACK_ENTRIES(64));
1960 WREG32(SQ_CONFIG
, sq_config
);
1961 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1962 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1963 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1964 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1965 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1967 if (((rdev
->family
) == CHIP_RV610
) ||
1968 ((rdev
->family
) == CHIP_RV620
) ||
1969 ((rdev
->family
) == CHIP_RS780
) ||
1970 ((rdev
->family
) == CHIP_RS880
)) {
1971 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
1973 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
1976 /* More default values. 2D/3D driver should adjust as needed */
1977 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
1978 S1_X(0x4) | S1_Y(0xc)));
1979 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
1980 S1_X(0x2) | S1_Y(0x2) |
1981 S2_X(0xa) | S2_Y(0x6) |
1982 S3_X(0x6) | S3_Y(0xa)));
1983 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
1984 S1_X(0x4) | S1_Y(0xc) |
1985 S2_X(0x1) | S2_Y(0x6) |
1986 S3_X(0xa) | S3_Y(0xe)));
1987 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
1988 S5_X(0x0) | S5_Y(0x0) |
1989 S6_X(0xb) | S6_Y(0x4) |
1990 S7_X(0x7) | S7_Y(0x8)));
1992 WREG32(VGT_STRMOUT_EN
, 0);
1993 tmp
= rdev
->config
.r600
.max_pipes
* 16;
1994 switch (rdev
->family
) {
2010 WREG32(VGT_ES_PER_GS
, 128);
2011 WREG32(VGT_GS_PER_ES
, tmp
);
2012 WREG32(VGT_GS_PER_VS
, 2);
2013 WREG32(VGT_GS_VERTEX_REUSE
, 16);
2015 /* more default values. 2D/3D driver should adjust as needed */
2016 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
2017 WREG32(VGT_STRMOUT_EN
, 0);
2019 WREG32(PA_SC_MODE_CNTL
, 0);
2020 WREG32(PA_SC_AA_CONFIG
, 0);
2021 WREG32(PA_SC_LINE_STIPPLE
, 0);
2022 WREG32(SPI_INPUT_Z
, 0);
2023 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
2024 WREG32(CB_COLOR7_FRAG
, 0);
2026 /* Clear render buffer base addresses */
2027 WREG32(CB_COLOR0_BASE
, 0);
2028 WREG32(CB_COLOR1_BASE
, 0);
2029 WREG32(CB_COLOR2_BASE
, 0);
2030 WREG32(CB_COLOR3_BASE
, 0);
2031 WREG32(CB_COLOR4_BASE
, 0);
2032 WREG32(CB_COLOR5_BASE
, 0);
2033 WREG32(CB_COLOR6_BASE
, 0);
2034 WREG32(CB_COLOR7_BASE
, 0);
2035 WREG32(CB_COLOR7_FRAG
, 0);
2037 switch (rdev
->family
) {
2042 tmp
= TC_L2_SIZE(8);
2046 tmp
= TC_L2_SIZE(4);
2049 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
2052 tmp
= TC_L2_SIZE(0);
2055 WREG32(TC_CNTL
, tmp
);
2057 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
2058 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
2060 tmp
= RREG32(ARB_POP
);
2061 tmp
|= ENABLE_TC128
;
2062 WREG32(ARB_POP
, tmp
);
2064 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
2065 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
2067 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
2068 WREG32(VC_ENHANCE
, 0);
2073 * Indirect registers accessor
2075 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
2079 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
2080 (void)RREG32(PCIE_PORT_INDEX
);
2081 r
= RREG32(PCIE_PORT_DATA
);
2085 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2087 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
2088 (void)RREG32(PCIE_PORT_INDEX
);
2089 WREG32(PCIE_PORT_DATA
, (v
));
2090 (void)RREG32(PCIE_PORT_DATA
);
2096 void r600_cp_stop(struct radeon_device
*rdev
)
2098 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
2099 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
2100 WREG32(SCRATCH_UMSK
, 0);
2101 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
2104 int r600_init_microcode(struct radeon_device
*rdev
)
2106 struct platform_device
*pdev
;
2107 const char *chip_name
;
2108 const char *rlc_chip_name
;
2109 size_t pfp_req_size
, me_req_size
, rlc_req_size
;
2115 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
2118 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
2122 switch (rdev
->family
) {
2125 rlc_chip_name
= "R600";
2128 chip_name
= "RV610";
2129 rlc_chip_name
= "R600";
2132 chip_name
= "RV630";
2133 rlc_chip_name
= "R600";
2136 chip_name
= "RV620";
2137 rlc_chip_name
= "R600";
2140 chip_name
= "RV635";
2141 rlc_chip_name
= "R600";
2144 chip_name
= "RV670";
2145 rlc_chip_name
= "R600";
2149 chip_name
= "RS780";
2150 rlc_chip_name
= "R600";
2153 chip_name
= "RV770";
2154 rlc_chip_name
= "R700";
2158 chip_name
= "RV730";
2159 rlc_chip_name
= "R700";
2162 chip_name
= "RV710";
2163 rlc_chip_name
= "R700";
2166 chip_name
= "CEDAR";
2167 rlc_chip_name
= "CEDAR";
2170 chip_name
= "REDWOOD";
2171 rlc_chip_name
= "REDWOOD";
2174 chip_name
= "JUNIPER";
2175 rlc_chip_name
= "JUNIPER";
2179 chip_name
= "CYPRESS";
2180 rlc_chip_name
= "CYPRESS";
2184 rlc_chip_name
= "SUMO";
2188 rlc_chip_name
= "SUMO";
2191 chip_name
= "SUMO2";
2192 rlc_chip_name
= "SUMO";
2197 if (rdev
->family
>= CHIP_CEDAR
) {
2198 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
2199 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
2200 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
2201 } else if (rdev
->family
>= CHIP_RV770
) {
2202 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
2203 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
2204 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
2206 pfp_req_size
= PFP_UCODE_SIZE
* 4;
2207 me_req_size
= PM4_UCODE_SIZE
* 12;
2208 rlc_req_size
= RLC_UCODE_SIZE
* 4;
2211 DRM_INFO("Loading %s Microcode\n", chip_name
);
2213 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
2214 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
2217 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
2219 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2220 rdev
->pfp_fw
->size
, fw_name
);
2225 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
2226 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
2229 if (rdev
->me_fw
->size
!= me_req_size
) {
2231 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2232 rdev
->me_fw
->size
, fw_name
);
2236 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
2237 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
2240 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
2242 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2243 rdev
->rlc_fw
->size
, fw_name
);
2248 platform_device_unregister(pdev
);
2253 "r600_cp: Failed to load firmware \"%s\"\n",
2255 release_firmware(rdev
->pfp_fw
);
2256 rdev
->pfp_fw
= NULL
;
2257 release_firmware(rdev
->me_fw
);
2259 release_firmware(rdev
->rlc_fw
);
2260 rdev
->rlc_fw
= NULL
;
2265 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
2267 const __be32
*fw_data
;
2270 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
2279 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
2282 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2283 RREG32(GRBM_SOFT_RESET
);
2285 WREG32(GRBM_SOFT_RESET
, 0);
2287 WREG32(CP_ME_RAM_WADDR
, 0);
2289 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
2290 WREG32(CP_ME_RAM_WADDR
, 0);
2291 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
2292 WREG32(CP_ME_RAM_DATA
,
2293 be32_to_cpup(fw_data
++));
2295 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
2296 WREG32(CP_PFP_UCODE_ADDR
, 0);
2297 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
2298 WREG32(CP_PFP_UCODE_DATA
,
2299 be32_to_cpup(fw_data
++));
2301 WREG32(CP_PFP_UCODE_ADDR
, 0);
2302 WREG32(CP_ME_RAM_WADDR
, 0);
2303 WREG32(CP_ME_RAM_RADDR
, 0);
2307 int r600_cp_start(struct radeon_device
*rdev
)
2309 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2313 r
= radeon_ring_lock(rdev
, ring
, 7);
2315 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2318 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
2319 radeon_ring_write(ring
, 0x1);
2320 if (rdev
->family
>= CHIP_RV770
) {
2321 radeon_ring_write(ring
, 0x0);
2322 radeon_ring_write(ring
, rdev
->config
.rv770
.max_hw_contexts
- 1);
2324 radeon_ring_write(ring
, 0x3);
2325 radeon_ring_write(ring
, rdev
->config
.r600
.max_hw_contexts
- 1);
2327 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2328 radeon_ring_write(ring
, 0);
2329 radeon_ring_write(ring
, 0);
2330 radeon_ring_unlock_commit(rdev
, ring
);
2333 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
2337 int r600_cp_resume(struct radeon_device
*rdev
)
2339 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2345 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2346 RREG32(GRBM_SOFT_RESET
);
2348 WREG32(GRBM_SOFT_RESET
, 0);
2350 /* Set ring buffer size */
2351 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2352 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2354 tmp
|= BUF_SWAP_32BIT
;
2356 WREG32(CP_RB_CNTL
, tmp
);
2357 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
2359 /* Set the write pointer delay */
2360 WREG32(CP_RB_WPTR_DELAY
, 0);
2362 /* Initialize the ring buffer's read and write pointers */
2363 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2364 WREG32(CP_RB_RPTR_WR
, 0);
2366 WREG32(CP_RB_WPTR
, ring
->wptr
);
2368 /* set the wb address whether it's enabled or not */
2369 WREG32(CP_RB_RPTR_ADDR
,
2370 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
2371 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2372 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2374 if (rdev
->wb
.enabled
)
2375 WREG32(SCRATCH_UMSK
, 0xff);
2377 tmp
|= RB_NO_UPDATE
;
2378 WREG32(SCRATCH_UMSK
, 0);
2382 WREG32(CP_RB_CNTL
, tmp
);
2384 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
2385 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
2387 ring
->rptr
= RREG32(CP_RB_RPTR
);
2389 r600_cp_start(rdev
);
2391 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
2393 ring
->ready
= false;
2399 void r600_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
)
2404 /* Align ring size */
2405 rb_bufsz
= drm_order(ring_size
/ 8);
2406 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
2407 ring
->ring_size
= ring_size
;
2408 ring
->align_mask
= 16 - 1;
2410 if (radeon_ring_supports_scratch_reg(rdev
, ring
)) {
2411 r
= radeon_scratch_get(rdev
, &ring
->rptr_save_reg
);
2413 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r
);
2414 ring
->rptr_save_reg
= 0;
2419 void r600_cp_fini(struct radeon_device
*rdev
)
2421 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2423 radeon_ring_fini(rdev
, ring
);
2424 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
2429 * Starting with R600, the GPU has an asynchronous
2430 * DMA engine. The programming model is very similar
2431 * to the 3D engine (ring buffer, IBs, etc.), but the
2432 * DMA controller has it's own packet format that is
2433 * different form the PM4 format used by the 3D engine.
2434 * It supports copying data, writing embedded data,
2435 * solid fills, and a number of other things. It also
2436 * has support for tiling/detiling of buffers.
2439 * r600_dma_stop - stop the async dma engine
2441 * @rdev: radeon_device pointer
2443 * Stop the async dma engine (r6xx-evergreen).
2445 void r600_dma_stop(struct radeon_device
*rdev
)
2447 u32 rb_cntl
= RREG32(DMA_RB_CNTL
);
2449 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
2451 rb_cntl
&= ~DMA_RB_ENABLE
;
2452 WREG32(DMA_RB_CNTL
, rb_cntl
);
2454 rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ready
= false;
2458 * r600_dma_resume - setup and start the async dma engine
2460 * @rdev: radeon_device pointer
2462 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2463 * Returns 0 for success, error for failure.
2465 int r600_dma_resume(struct radeon_device
*rdev
)
2467 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2468 u32 rb_cntl
, dma_cntl
, ib_cntl
;
2473 if (rdev
->family
>= CHIP_RV770
)
2474 WREG32(SRBM_SOFT_RESET
, RV770_SOFT_RESET_DMA
);
2476 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_DMA
);
2477 RREG32(SRBM_SOFT_RESET
);
2479 WREG32(SRBM_SOFT_RESET
, 0);
2481 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL
, 0);
2482 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL
, 0);
2484 /* Set ring buffer size in dwords */
2485 rb_bufsz
= drm_order(ring
->ring_size
/ 4);
2486 rb_cntl
= rb_bufsz
<< 1;
2488 rb_cntl
|= DMA_RB_SWAP_ENABLE
| DMA_RPTR_WRITEBACK_SWAP_ENABLE
;
2490 WREG32(DMA_RB_CNTL
, rb_cntl
);
2492 /* Initialize the ring buffer's read and write pointers */
2493 WREG32(DMA_RB_RPTR
, 0);
2494 WREG32(DMA_RB_WPTR
, 0);
2496 /* set the wb address whether it's enabled or not */
2497 WREG32(DMA_RB_RPTR_ADDR_HI
,
2498 upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_DMA_RPTR_OFFSET
) & 0xFF);
2499 WREG32(DMA_RB_RPTR_ADDR_LO
,
2500 ((rdev
->wb
.gpu_addr
+ R600_WB_DMA_RPTR_OFFSET
) & 0xFFFFFFFC));
2502 if (rdev
->wb
.enabled
)
2503 rb_cntl
|= DMA_RPTR_WRITEBACK_ENABLE
;
2505 WREG32(DMA_RB_BASE
, ring
->gpu_addr
>> 8);
2507 /* enable DMA IBs */
2508 ib_cntl
= DMA_IB_ENABLE
;
2510 ib_cntl
|= DMA_IB_SWAP_ENABLE
;
2512 WREG32(DMA_IB_CNTL
, ib_cntl
);
2514 dma_cntl
= RREG32(DMA_CNTL
);
2515 dma_cntl
&= ~CTXEMPTY_INT_ENABLE
;
2516 WREG32(DMA_CNTL
, dma_cntl
);
2518 if (rdev
->family
>= CHIP_RV770
)
2519 WREG32(DMA_MODE
, 1);
2522 WREG32(DMA_RB_WPTR
, ring
->wptr
<< 2);
2524 ring
->rptr
= RREG32(DMA_RB_RPTR
) >> 2;
2526 WREG32(DMA_RB_CNTL
, rb_cntl
| DMA_RB_ENABLE
);
2530 r
= radeon_ring_test(rdev
, R600_RING_TYPE_DMA_INDEX
, ring
);
2532 ring
->ready
= false;
2536 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);
2542 * r600_dma_fini - tear down the async dma engine
2544 * @rdev: radeon_device pointer
2546 * Stop the async dma engine and free the ring (r6xx-evergreen).
2548 void r600_dma_fini(struct radeon_device
*rdev
)
2550 r600_dma_stop(rdev
);
2551 radeon_ring_fini(rdev
, &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
]);
2557 int r600_uvd_rbc_start(struct radeon_device
*rdev
)
2559 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2561 uint32_t rb_bufsz
, tmp
;
2564 rptr_addr
= rdev
->wb
.gpu_addr
+ R600_WB_UVD_RPTR_OFFSET
;
2566 if (upper_32_bits(rptr_addr
) != upper_32_bits(ring
->gpu_addr
)) {
2567 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2571 /* force RBC into idle state */
2572 WREG32(UVD_RBC_RB_CNTL
, 0x11010101);
2574 /* Set the write pointer delay */
2575 WREG32(UVD_RBC_RB_WPTR_CNTL
, 0);
2577 /* set the wb address */
2578 WREG32(UVD_RBC_RB_RPTR_ADDR
, rptr_addr
>> 2);
2580 /* programm the 4GB memory segment for rptr and ring buffer */
2581 WREG32(UVD_LMI_EXT40_ADDR
, upper_32_bits(rptr_addr
) |
2582 (0x7 << 16) | (0x1 << 31));
2584 /* Initialize the ring buffer's read and write pointers */
2585 WREG32(UVD_RBC_RB_RPTR
, 0x0);
2587 ring
->wptr
= ring
->rptr
= RREG32(UVD_RBC_RB_RPTR
);
2588 WREG32(UVD_RBC_RB_WPTR
, ring
->wptr
);
2590 /* set the ring address */
2591 WREG32(UVD_RBC_RB_BASE
, ring
->gpu_addr
);
2593 /* Set ring buffer size */
2594 rb_bufsz
= drm_order(ring
->ring_size
);
2595 rb_bufsz
= (0x1 << 8) | rb_bufsz
;
2596 WREG32(UVD_RBC_RB_CNTL
, rb_bufsz
);
2599 r
= radeon_ring_test(rdev
, R600_RING_TYPE_UVD_INDEX
, ring
);
2601 ring
->ready
= false;
2605 r
= radeon_ring_lock(rdev
, ring
, 10);
2607 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r
);
2611 tmp
= PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
, 0);
2612 radeon_ring_write(ring
, tmp
);
2613 radeon_ring_write(ring
, 0xFFFFF);
2615 tmp
= PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
, 0);
2616 radeon_ring_write(ring
, tmp
);
2617 radeon_ring_write(ring
, 0xFFFFF);
2619 tmp
= PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
, 0);
2620 radeon_ring_write(ring
, tmp
);
2621 radeon_ring_write(ring
, 0xFFFFF);
2623 /* Clear timeout status bits */
2624 radeon_ring_write(ring
, PACKET0(UVD_SEMA_TIMEOUT_STATUS
, 0));
2625 radeon_ring_write(ring
, 0x8);
2627 radeon_ring_write(ring
, PACKET0(UVD_SEMA_CNTL
, 0));
2628 radeon_ring_write(ring
, 3);
2630 radeon_ring_unlock_commit(rdev
, ring
);
2635 void r600_uvd_rbc_stop(struct radeon_device
*rdev
)
2637 struct radeon_ring
*ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2639 /* force RBC into idle state */
2640 WREG32(UVD_RBC_RB_CNTL
, 0x11010101);
2641 ring
->ready
= false;
2644 int r600_uvd_init(struct radeon_device
*rdev
)
2648 /* raise clocks while booting up the VCPU */
2649 radeon_set_uvd_clocks(rdev
, 53300, 40000);
2651 /* disable clock gating */
2652 WREG32(UVD_CGC_GATE
, 0);
2654 /* disable interupt */
2655 WREG32_P(UVD_MASTINT_EN
, 0, ~(1 << 1));
2657 /* put LMI, VCPU, RBC etc... into reset */
2658 WREG32(UVD_SOFT_RESET
, LMI_SOFT_RESET
| VCPU_SOFT_RESET
|
2659 LBSI_SOFT_RESET
| RBC_SOFT_RESET
| CSM_SOFT_RESET
|
2660 CXW_SOFT_RESET
| TAP_SOFT_RESET
| LMI_UMC_SOFT_RESET
);
2663 /* take UVD block out of reset */
2664 WREG32_P(SRBM_SOFT_RESET
, 0, ~SOFT_RESET_UVD
);
2667 /* initialize UVD memory controller */
2668 WREG32(UVD_LMI_CTRL
, 0x40 | (1 << 8) | (1 << 13) |
2669 (1 << 21) | (1 << 9) | (1 << 20));
2671 /* disable byte swapping */
2672 WREG32(UVD_LMI_SWAP_CNTL
, 0);
2673 WREG32(UVD_MP_SWAP_CNTL
, 0);
2675 WREG32(UVD_MPC_SET_MUXA0
, 0x40c2040);
2676 WREG32(UVD_MPC_SET_MUXA1
, 0x0);
2677 WREG32(UVD_MPC_SET_MUXB0
, 0x40c2040);
2678 WREG32(UVD_MPC_SET_MUXB1
, 0x0);
2679 WREG32(UVD_MPC_SET_ALU
, 0);
2680 WREG32(UVD_MPC_SET_MUX
, 0x88);
2683 WREG32_P(UVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
2684 WREG32_P(UVD_RB_ARB_CTRL
, 1 << 3, ~(1 << 3));
2686 /* take all subblocks out of reset, except VCPU */
2687 WREG32(UVD_SOFT_RESET
, VCPU_SOFT_RESET
);
2690 /* enable VCPU clock */
2691 WREG32(UVD_VCPU_CNTL
, 1 << 9);
2694 WREG32_P(UVD_LMI_CTRL2
, 0, ~(1 << 8));
2696 /* boot up the VCPU */
2697 WREG32(UVD_SOFT_RESET
, 0);
2700 WREG32_P(UVD_RB_ARB_CTRL
, 0, ~(1 << 3));
2702 for (i
= 0; i
< 10; ++i
) {
2704 for (j
= 0; j
< 100; ++j
) {
2705 status
= RREG32(UVD_STATUS
);
2714 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2715 WREG32_P(UVD_SOFT_RESET
, VCPU_SOFT_RESET
, ~VCPU_SOFT_RESET
);
2717 WREG32_P(UVD_SOFT_RESET
, 0, ~VCPU_SOFT_RESET
);
2723 DRM_ERROR("UVD not responding, giving up!!!\n");
2724 radeon_set_uvd_clocks(rdev
, 0, 0);
2728 /* enable interupt */
2729 WREG32_P(UVD_MASTINT_EN
, 3<<1, ~(3 << 1));
2731 r
= r600_uvd_rbc_start(rdev
);
2733 DRM_INFO("UVD initialized successfully.\n");
2735 /* lower clocks again */
2736 radeon_set_uvd_clocks(rdev
, 0, 0);
2742 * GPU scratch registers helpers function.
2744 void r600_scratch_init(struct radeon_device
*rdev
)
2748 rdev
->scratch
.num_reg
= 7;
2749 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
2750 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
2751 rdev
->scratch
.free
[i
] = true;
2752 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
2756 int r600_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2763 r
= radeon_scratch_get(rdev
, &scratch
);
2765 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2768 WREG32(scratch
, 0xCAFEDEAD);
2769 r
= radeon_ring_lock(rdev
, ring
, 3);
2771 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring
->idx
, r
);
2772 radeon_scratch_free(rdev
, scratch
);
2775 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2776 radeon_ring_write(ring
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2777 radeon_ring_write(ring
, 0xDEADBEEF);
2778 radeon_ring_unlock_commit(rdev
, ring
);
2779 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2780 tmp
= RREG32(scratch
);
2781 if (tmp
== 0xDEADBEEF)
2785 if (i
< rdev
->usec_timeout
) {
2786 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2788 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2789 ring
->idx
, scratch
, tmp
);
2792 radeon_scratch_free(rdev
, scratch
);
2797 * r600_dma_ring_test - simple async dma engine test
2799 * @rdev: radeon_device pointer
2800 * @ring: radeon_ring structure holding ring information
2802 * Test the DMA engine by writing using it to write an
2803 * value to memory. (r6xx-SI).
2804 * Returns 0 for success, error for failure.
2806 int r600_dma_ring_test(struct radeon_device
*rdev
,
2807 struct radeon_ring
*ring
)
2811 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
2815 DRM_ERROR("invalid vram scratch pointer\n");
2822 r
= radeon_ring_lock(rdev
, ring
, 4);
2824 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
2827 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1));
2828 radeon_ring_write(ring
, rdev
->vram_scratch
.gpu_addr
& 0xfffffffc);
2829 radeon_ring_write(ring
, upper_32_bits(rdev
->vram_scratch
.gpu_addr
) & 0xff);
2830 radeon_ring_write(ring
, 0xDEADBEEF);
2831 radeon_ring_unlock_commit(rdev
, ring
);
2833 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2835 if (tmp
== 0xDEADBEEF)
2840 if (i
< rdev
->usec_timeout
) {
2841 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2843 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2850 int r600_uvd_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2856 WREG32(UVD_CONTEXT_ID
, 0xCAFEDEAD);
2857 r
= radeon_ring_lock(rdev
, ring
, 3);
2859 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2863 radeon_ring_write(ring
, PACKET0(UVD_CONTEXT_ID
, 0));
2864 radeon_ring_write(ring
, 0xDEADBEEF);
2865 radeon_ring_unlock_commit(rdev
, ring
);
2866 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2867 tmp
= RREG32(UVD_CONTEXT_ID
);
2868 if (tmp
== 0xDEADBEEF)
2873 if (i
< rdev
->usec_timeout
) {
2874 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2877 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2885 * CP fences/semaphores
2888 void r600_fence_ring_emit(struct radeon_device
*rdev
,
2889 struct radeon_fence
*fence
)
2891 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
2893 if (rdev
->wb
.use_event
) {
2894 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
2895 /* flush read cache over gart */
2896 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
2897 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
2898 PACKET3_VC_ACTION_ENA
|
2899 PACKET3_SH_ACTION_ENA
);
2900 radeon_ring_write(ring
, 0xFFFFFFFF);
2901 radeon_ring_write(ring
, 0);
2902 radeon_ring_write(ring
, 10); /* poll interval */
2903 /* EVENT_WRITE_EOP - flush caches, send int */
2904 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2905 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
2906 radeon_ring_write(ring
, addr
& 0xffffffff);
2907 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2908 radeon_ring_write(ring
, fence
->seq
);
2909 radeon_ring_write(ring
, 0);
2911 /* flush read cache over gart */
2912 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
2913 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
2914 PACKET3_VC_ACTION_ENA
|
2915 PACKET3_SH_ACTION_ENA
);
2916 radeon_ring_write(ring
, 0xFFFFFFFF);
2917 radeon_ring_write(ring
, 0);
2918 radeon_ring_write(ring
, 10); /* poll interval */
2919 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2920 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
2921 /* wait for 3D idle clean */
2922 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2923 radeon_ring_write(ring
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2924 radeon_ring_write(ring
, WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
2925 /* Emit fence sequence & fire IRQ */
2926 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2927 radeon_ring_write(ring
, ((rdev
->fence_drv
[fence
->ring
].scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2928 radeon_ring_write(ring
, fence
->seq
);
2929 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2930 radeon_ring_write(ring
, PACKET0(CP_INT_STATUS
, 0));
2931 radeon_ring_write(ring
, RB_INT_STAT
);
2935 void r600_uvd_fence_emit(struct radeon_device
*rdev
,
2936 struct radeon_fence
*fence
)
2938 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
2939 uint32_t addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
2941 radeon_ring_write(ring
, PACKET0(UVD_CONTEXT_ID
, 0));
2942 radeon_ring_write(ring
, fence
->seq
);
2943 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
2944 radeon_ring_write(ring
, addr
& 0xffffffff);
2945 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
2946 radeon_ring_write(ring
, upper_32_bits(addr
) & 0xff);
2947 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
2948 radeon_ring_write(ring
, 0);
2950 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA0
, 0));
2951 radeon_ring_write(ring
, 0);
2952 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_DATA1
, 0));
2953 radeon_ring_write(ring
, 0);
2954 radeon_ring_write(ring
, PACKET0(UVD_GPCOM_VCPU_CMD
, 0));
2955 radeon_ring_write(ring
, 2);
2959 void r600_semaphore_ring_emit(struct radeon_device
*rdev
,
2960 struct radeon_ring
*ring
,
2961 struct radeon_semaphore
*semaphore
,
2964 uint64_t addr
= semaphore
->gpu_addr
;
2965 unsigned sel
= emit_wait
? PACKET3_SEM_SEL_WAIT
: PACKET3_SEM_SEL_SIGNAL
;
2967 if (rdev
->family
< CHIP_CAYMAN
)
2968 sel
|= PACKET3_SEM_WAIT_ON_SIGNAL
;
2970 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_SEMAPHORE
, 1));
2971 radeon_ring_write(ring
, addr
& 0xffffffff);
2972 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | sel
);
2976 * DMA fences/semaphores
2980 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2982 * @rdev: radeon_device pointer
2983 * @fence: radeon fence object
2985 * Add a DMA fence packet to the ring to write
2986 * the fence seq number and DMA trap packet to generate
2987 * an interrupt if needed (r6xx-r7xx).
2989 void r600_dma_fence_ring_emit(struct radeon_device
*rdev
,
2990 struct radeon_fence
*fence
)
2992 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
2993 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
2995 /* write the fence */
2996 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_FENCE
, 0, 0, 0));
2997 radeon_ring_write(ring
, addr
& 0xfffffffc);
2998 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff));
2999 radeon_ring_write(ring
, lower_32_bits(fence
->seq
));
3000 /* generate an interrupt */
3001 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_TRAP
, 0, 0, 0));
3005 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
3007 * @rdev: radeon_device pointer
3008 * @ring: radeon_ring structure holding ring information
3009 * @semaphore: radeon semaphore object
3010 * @emit_wait: wait or signal semaphore
3012 * Add a DMA semaphore packet to the ring wait on or signal
3013 * other rings (r6xx-SI).
3015 void r600_dma_semaphore_ring_emit(struct radeon_device
*rdev
,
3016 struct radeon_ring
*ring
,
3017 struct radeon_semaphore
*semaphore
,
3020 u64 addr
= semaphore
->gpu_addr
;
3021 u32 s
= emit_wait
? 0 : 1;
3023 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SEMAPHORE
, 0, s
, 0));
3024 radeon_ring_write(ring
, addr
& 0xfffffffc);
3025 radeon_ring_write(ring
, upper_32_bits(addr
) & 0xff);
3028 void r600_uvd_semaphore_emit(struct radeon_device
*rdev
,
3029 struct radeon_ring
*ring
,
3030 struct radeon_semaphore
*semaphore
,
3033 uint64_t addr
= semaphore
->gpu_addr
;
3035 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_LOW
, 0));
3036 radeon_ring_write(ring
, (addr
>> 3) & 0x000FFFFF);
3038 radeon_ring_write(ring
, PACKET0(UVD_SEMA_ADDR_HIGH
, 0));
3039 radeon_ring_write(ring
, (addr
>> 23) & 0x000FFFFF);
3041 radeon_ring_write(ring
, PACKET0(UVD_SEMA_CMD
, 0));
3042 radeon_ring_write(ring
, emit_wait
? 1 : 0);
3045 int r600_copy_blit(struct radeon_device
*rdev
,
3046 uint64_t src_offset
,
3047 uint64_t dst_offset
,
3048 unsigned num_gpu_pages
,
3049 struct radeon_fence
**fence
)
3051 struct radeon_semaphore
*sem
= NULL
;
3052 struct radeon_sa_bo
*vb
= NULL
;
3055 r
= r600_blit_prepare_copy(rdev
, num_gpu_pages
, fence
, &vb
, &sem
);
3059 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_gpu_pages
, vb
);
3060 r600_blit_done_copy(rdev
, fence
, vb
, sem
);
3065 * r600_copy_dma - copy pages using the DMA engine
3067 * @rdev: radeon_device pointer
3068 * @src_offset: src GPU address
3069 * @dst_offset: dst GPU address
3070 * @num_gpu_pages: number of GPU pages to xfer
3071 * @fence: radeon fence object
3073 * Copy GPU paging using the DMA engine (r6xx).
3074 * Used by the radeon ttm implementation to move pages if
3075 * registered as the asic copy callback.
3077 int r600_copy_dma(struct radeon_device
*rdev
,
3078 uint64_t src_offset
, uint64_t dst_offset
,
3079 unsigned num_gpu_pages
,
3080 struct radeon_fence
**fence
)
3082 struct radeon_semaphore
*sem
= NULL
;
3083 int ring_index
= rdev
->asic
->copy
.dma_ring_index
;
3084 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
3085 u32 size_in_dw
, cur_size_in_dw
;
3089 r
= radeon_semaphore_create(rdev
, &sem
);
3091 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3095 size_in_dw
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
) / 4;
3096 num_loops
= DIV_ROUND_UP(size_in_dw
, 0xFFFE);
3097 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 4 + 8);
3099 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3100 radeon_semaphore_free(rdev
, &sem
, NULL
);
3104 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
3105 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
3107 radeon_fence_note_sync(*fence
, ring
->idx
);
3109 radeon_semaphore_free(rdev
, &sem
, NULL
);
3112 for (i
= 0; i
< num_loops
; i
++) {
3113 cur_size_in_dw
= size_in_dw
;
3114 if (cur_size_in_dw
> 0xFFFE)
3115 cur_size_in_dw
= 0xFFFE;
3116 size_in_dw
-= cur_size_in_dw
;
3117 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_COPY
, 0, 0, cur_size_in_dw
));
3118 radeon_ring_write(ring
, dst_offset
& 0xfffffffc);
3119 radeon_ring_write(ring
, src_offset
& 0xfffffffc);
3120 radeon_ring_write(ring
, (((upper_32_bits(dst_offset
) & 0xff) << 16) |
3121 (upper_32_bits(src_offset
) & 0xff)));
3122 src_offset
+= cur_size_in_dw
* 4;
3123 dst_offset
+= cur_size_in_dw
* 4;
3126 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
3128 radeon_ring_unlock_undo(rdev
, ring
);
3132 radeon_ring_unlock_commit(rdev
, ring
);
3133 radeon_semaphore_free(rdev
, &sem
, *fence
);
3138 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
3139 uint32_t tiling_flags
, uint32_t pitch
,
3140 uint32_t offset
, uint32_t obj_size
)
3142 /* FIXME: implement */
3146 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
3148 /* FIXME: implement */
3151 static int r600_startup(struct radeon_device
*rdev
)
3153 struct radeon_ring
*ring
;
3156 /* enable pcie gen2 link */
3157 r600_pcie_gen2_enable(rdev
);
3159 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
3160 r
= r600_init_microcode(rdev
);
3162 DRM_ERROR("Failed to load firmware!\n");
3167 r
= r600_vram_scratch_init(rdev
);
3171 r600_mc_program(rdev
);
3172 if (rdev
->flags
& RADEON_IS_AGP
) {
3173 r600_agp_enable(rdev
);
3175 r
= r600_pcie_gart_enable(rdev
);
3179 r600_gpu_init(rdev
);
3180 r
= r600_blit_init(rdev
);
3182 r600_blit_fini(rdev
);
3183 rdev
->asic
->copy
.copy
= NULL
;
3184 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
3187 /* allocate wb buffer */
3188 r
= radeon_wb_init(rdev
);
3192 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3194 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
3198 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
3200 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
3205 r
= r600_irq_init(rdev
);
3207 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
3208 radeon_irq_kms_fini(rdev
);
3213 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
3214 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
3215 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
3216 0, 0xfffff, RADEON_CP_PACKET2
);
3220 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
3221 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
3222 DMA_RB_RPTR
, DMA_RB_WPTR
,
3223 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
3227 r
= r600_cp_load_microcode(rdev
);
3230 r
= r600_cp_resume(rdev
);
3234 r
= r600_dma_resume(rdev
);
3238 r
= radeon_ib_pool_init(rdev
);
3240 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
3244 r
= r600_audio_init(rdev
);
3246 DRM_ERROR("radeon: audio init failed\n");
3253 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
3257 temp
= RREG32(CONFIG_CNTL
);
3258 if (state
== false) {
3264 WREG32(CONFIG_CNTL
, temp
);
3267 int r600_resume(struct radeon_device
*rdev
)
3271 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3272 * posting will perform necessary task to bring back GPU into good
3276 atom_asic_init(rdev
->mode_info
.atom_context
);
3278 rdev
->accel_working
= true;
3279 r
= r600_startup(rdev
);
3281 DRM_ERROR("r600 startup failed on resume\n");
3282 rdev
->accel_working
= false;
3289 int r600_suspend(struct radeon_device
*rdev
)
3291 r600_audio_fini(rdev
);
3293 r600_dma_stop(rdev
);
3294 r600_irq_suspend(rdev
);
3295 radeon_wb_disable(rdev
);
3296 r600_pcie_gart_disable(rdev
);
3301 /* Plan is to move initialization in that function and use
3302 * helper function so that radeon_device_init pretty much
3303 * do nothing more than calling asic specific function. This
3304 * should also allow to remove a bunch of callback function
3307 int r600_init(struct radeon_device
*rdev
)
3311 if (r600_debugfs_mc_info_init(rdev
)) {
3312 DRM_ERROR("Failed to register debugfs file for mc !\n");
3315 if (!radeon_get_bios(rdev
)) {
3316 if (ASIC_IS_AVIVO(rdev
))
3319 /* Must be an ATOMBIOS */
3320 if (!rdev
->is_atom_bios
) {
3321 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
3324 r
= radeon_atombios_init(rdev
);
3327 /* Post card if necessary */
3328 if (!radeon_card_posted(rdev
)) {
3330 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
3333 DRM_INFO("GPU not posted. posting now...\n");
3334 atom_asic_init(rdev
->mode_info
.atom_context
);
3336 /* Initialize scratch registers */
3337 r600_scratch_init(rdev
);
3338 /* Initialize surface registers */
3339 radeon_surface_init(rdev
);
3340 /* Initialize clocks */
3341 radeon_get_clock_info(rdev
->ddev
);
3343 r
= radeon_fence_driver_init(rdev
);
3346 if (rdev
->flags
& RADEON_IS_AGP
) {
3347 r
= radeon_agp_init(rdev
);
3349 radeon_agp_disable(rdev
);
3351 r
= r600_mc_init(rdev
);
3354 /* Memory manager */
3355 r
= radeon_bo_init(rdev
);
3359 r
= radeon_irq_kms_init(rdev
);
3363 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
3364 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
3366 rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ring_obj
= NULL
;
3367 r600_ring_init(rdev
, &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
], 64 * 1024);
3369 rdev
->ih
.ring_obj
= NULL
;
3370 r600_ih_ring_init(rdev
, 64 * 1024);
3372 r
= r600_pcie_gart_init(rdev
);
3376 rdev
->accel_working
= true;
3377 r
= r600_startup(rdev
);
3379 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
3381 r600_dma_fini(rdev
);
3382 r600_irq_fini(rdev
);
3383 radeon_wb_fini(rdev
);
3384 radeon_ib_pool_fini(rdev
);
3385 radeon_irq_kms_fini(rdev
);
3386 r600_pcie_gart_fini(rdev
);
3387 rdev
->accel_working
= false;
3393 void r600_fini(struct radeon_device
*rdev
)
3395 r600_audio_fini(rdev
);
3396 r600_blit_fini(rdev
);
3398 r600_dma_fini(rdev
);
3399 r600_irq_fini(rdev
);
3400 radeon_wb_fini(rdev
);
3401 radeon_ib_pool_fini(rdev
);
3402 radeon_irq_kms_fini(rdev
);
3403 r600_pcie_gart_fini(rdev
);
3404 r600_vram_scratch_fini(rdev
);
3405 radeon_agp_fini(rdev
);
3406 radeon_gem_fini(rdev
);
3407 radeon_fence_driver_fini(rdev
);
3408 radeon_bo_fini(rdev
);
3409 radeon_atombios_fini(rdev
);
3418 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3420 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3423 if (ring
->rptr_save_reg
) {
3424 next_rptr
= ring
->wptr
+ 3 + 4;
3425 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
3426 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
3427 PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
3428 radeon_ring_write(ring
, next_rptr
);
3429 } else if (rdev
->wb
.enabled
) {
3430 next_rptr
= ring
->wptr
+ 5 + 4;
3431 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_WRITE
, 3));
3432 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
3433 radeon_ring_write(ring
, (upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff) | (1 << 18));
3434 radeon_ring_write(ring
, next_rptr
);
3435 radeon_ring_write(ring
, 0);
3438 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
3439 radeon_ring_write(ring
,
3443 (ib
->gpu_addr
& 0xFFFFFFFC));
3444 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
3445 radeon_ring_write(ring
, ib
->length_dw
);
3448 void r600_uvd_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3450 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3452 radeon_ring_write(ring
, PACKET0(UVD_RBC_IB_BASE
, 0));
3453 radeon_ring_write(ring
, ib
->gpu_addr
);
3454 radeon_ring_write(ring
, PACKET0(UVD_RBC_IB_SIZE
, 0));
3455 radeon_ring_write(ring
, ib
->length_dw
);
3458 int r600_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3460 struct radeon_ib ib
;
3466 r
= radeon_scratch_get(rdev
, &scratch
);
3468 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
3471 WREG32(scratch
, 0xCAFEDEAD);
3472 r
= radeon_ib_get(rdev
, ring
->idx
, &ib
, NULL
, 256);
3474 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
3477 ib
.ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
3478 ib
.ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
3479 ib
.ptr
[2] = 0xDEADBEEF;
3481 r
= radeon_ib_schedule(rdev
, &ib
, NULL
);
3483 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
3486 r
= radeon_fence_wait(ib
.fence
, false);
3488 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3491 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3492 tmp
= RREG32(scratch
);
3493 if (tmp
== 0xDEADBEEF)
3497 if (i
< rdev
->usec_timeout
) {
3498 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib
.fence
->ring
, i
);
3500 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3505 radeon_ib_free(rdev
, &ib
);
3507 radeon_scratch_free(rdev
, scratch
);
3512 * r600_dma_ib_test - test an IB on the DMA engine
3514 * @rdev: radeon_device pointer
3515 * @ring: radeon_ring structure holding ring information
3517 * Test a simple IB in the DMA ring (r6xx-SI).
3518 * Returns 0 on success, error on failure.
3520 int r600_dma_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3522 struct radeon_ib ib
;
3525 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
3529 DRM_ERROR("invalid vram scratch pointer\n");
3536 r
= radeon_ib_get(rdev
, ring
->idx
, &ib
, NULL
, 256);
3538 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
3542 ib
.ptr
[0] = DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1);
3543 ib
.ptr
[1] = rdev
->vram_scratch
.gpu_addr
& 0xfffffffc;
3544 ib
.ptr
[2] = upper_32_bits(rdev
->vram_scratch
.gpu_addr
) & 0xff;
3545 ib
.ptr
[3] = 0xDEADBEEF;
3548 r
= radeon_ib_schedule(rdev
, &ib
, NULL
);
3550 radeon_ib_free(rdev
, &ib
);
3551 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
3554 r
= radeon_fence_wait(ib
.fence
, false);
3556 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3559 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3561 if (tmp
== 0xDEADBEEF)
3565 if (i
< rdev
->usec_timeout
) {
3566 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib
.fence
->ring
, i
);
3568 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp
);
3571 radeon_ib_free(rdev
, &ib
);
3575 int r600_uvd_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
3577 struct radeon_fence
*fence
= NULL
;
3580 r
= radeon_set_uvd_clocks(rdev
, 53300, 40000);
3582 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r
);
3586 r
= radeon_uvd_get_create_msg(rdev
, ring
->idx
, 1, NULL
);
3588 DRM_ERROR("radeon: failed to get create msg (%d).\n", r
);
3592 r
= radeon_uvd_get_destroy_msg(rdev
, ring
->idx
, 1, &fence
);
3594 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r
);
3598 r
= radeon_fence_wait(fence
, false);
3600 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
3603 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
3605 radeon_fence_unref(&fence
);
3606 radeon_set_uvd_clocks(rdev
, 0, 0);
3611 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3613 * @rdev: radeon_device pointer
3614 * @ib: IB object to schedule
3616 * Schedule an IB in the DMA ring (r6xx-r7xx).
3618 void r600_dma_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3620 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
3622 if (rdev
->wb
.enabled
) {
3623 u32 next_rptr
= ring
->wptr
+ 4;
3624 while ((next_rptr
& 7) != 5)
3627 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 1));
3628 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
3629 radeon_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xff);
3630 radeon_ring_write(ring
, next_rptr
);
3633 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3634 * Pad as necessary with NOPs.
3636 while ((ring
->wptr
& 7) != 5)
3637 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
3638 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER
, 0, 0, 0));
3639 radeon_ring_write(ring
, (ib
->gpu_addr
& 0xFFFFFFE0));
3640 radeon_ring_write(ring
, (ib
->length_dw
<< 16) | (upper_32_bits(ib
->gpu_addr
) & 0xFF));
3647 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3648 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3649 * writing to the ring and the GPU consuming, the GPU writes to the ring
3650 * and host consumes. As the host irq handler processes interrupts, it
3651 * increments the rptr. When the rptr catches up with the wptr, all the
3652 * current interrupts have been processed.
3655 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
3659 /* Align ring size */
3660 rb_bufsz
= drm_order(ring_size
/ 4);
3661 ring_size
= (1 << rb_bufsz
) * 4;
3662 rdev
->ih
.ring_size
= ring_size
;
3663 rdev
->ih
.ptr_mask
= rdev
->ih
.ring_size
- 1;
3667 int r600_ih_ring_alloc(struct radeon_device
*rdev
)
3671 /* Allocate ring buffer */
3672 if (rdev
->ih
.ring_obj
== NULL
) {
3673 r
= radeon_bo_create(rdev
, rdev
->ih
.ring_size
,
3675 RADEON_GEM_DOMAIN_GTT
,
3676 NULL
, &rdev
->ih
.ring_obj
);
3678 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
3681 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
3682 if (unlikely(r
!= 0))
3684 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
3685 RADEON_GEM_DOMAIN_GTT
,
3686 &rdev
->ih
.gpu_addr
);
3688 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3689 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
3692 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
3693 (void **)&rdev
->ih
.ring
);
3694 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3696 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
3703 void r600_ih_ring_fini(struct radeon_device
*rdev
)
3706 if (rdev
->ih
.ring_obj
) {
3707 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
3708 if (likely(r
== 0)) {
3709 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
3710 radeon_bo_unpin(rdev
->ih
.ring_obj
);
3711 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
3713 radeon_bo_unref(&rdev
->ih
.ring_obj
);
3714 rdev
->ih
.ring
= NULL
;
3715 rdev
->ih
.ring_obj
= NULL
;
3719 void r600_rlc_stop(struct radeon_device
*rdev
)
3722 if ((rdev
->family
>= CHIP_RV770
) &&
3723 (rdev
->family
<= CHIP_RV740
)) {
3724 /* r7xx asics need to soft reset RLC before halting */
3725 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
3726 RREG32(SRBM_SOFT_RESET
);
3728 WREG32(SRBM_SOFT_RESET
, 0);
3729 RREG32(SRBM_SOFT_RESET
);
3732 WREG32(RLC_CNTL
, 0);
3735 static void r600_rlc_start(struct radeon_device
*rdev
)
3737 WREG32(RLC_CNTL
, RLC_ENABLE
);
3740 static int r600_rlc_init(struct radeon_device
*rdev
)
3743 const __be32
*fw_data
;
3748 r600_rlc_stop(rdev
);
3750 WREG32(RLC_HB_CNTL
, 0);
3752 if (rdev
->family
== CHIP_ARUBA
) {
3753 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE
, rdev
->rlc
.save_restore_gpu_addr
>> 8);
3754 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE
, rdev
->rlc
.clear_state_gpu_addr
>> 8);
3756 if (rdev
->family
<= CHIP_CAYMAN
) {
3757 WREG32(RLC_HB_BASE
, 0);
3758 WREG32(RLC_HB_RPTR
, 0);
3759 WREG32(RLC_HB_WPTR
, 0);
3761 if (rdev
->family
<= CHIP_CAICOS
) {
3762 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
3763 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
3765 WREG32(RLC_MC_CNTL
, 0);
3766 WREG32(RLC_UCODE_CNTL
, 0);
3768 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
3769 if (rdev
->family
>= CHIP_ARUBA
) {
3770 for (i
= 0; i
< ARUBA_RLC_UCODE_SIZE
; i
++) {
3771 WREG32(RLC_UCODE_ADDR
, i
);
3772 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3774 } else if (rdev
->family
>= CHIP_CAYMAN
) {
3775 for (i
= 0; i
< CAYMAN_RLC_UCODE_SIZE
; i
++) {
3776 WREG32(RLC_UCODE_ADDR
, i
);
3777 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3779 } else if (rdev
->family
>= CHIP_CEDAR
) {
3780 for (i
= 0; i
< EVERGREEN_RLC_UCODE_SIZE
; i
++) {
3781 WREG32(RLC_UCODE_ADDR
, i
);
3782 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3784 } else if (rdev
->family
>= CHIP_RV770
) {
3785 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
3786 WREG32(RLC_UCODE_ADDR
, i
);
3787 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3790 for (i
= 0; i
< RLC_UCODE_SIZE
; i
++) {
3791 WREG32(RLC_UCODE_ADDR
, i
);
3792 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3795 WREG32(RLC_UCODE_ADDR
, 0);
3797 r600_rlc_start(rdev
);
3802 static void r600_enable_interrupts(struct radeon_device
*rdev
)
3804 u32 ih_cntl
= RREG32(IH_CNTL
);
3805 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3807 ih_cntl
|= ENABLE_INTR
;
3808 ih_rb_cntl
|= IH_RB_ENABLE
;
3809 WREG32(IH_CNTL
, ih_cntl
);
3810 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3811 rdev
->ih
.enabled
= true;
3814 void r600_disable_interrupts(struct radeon_device
*rdev
)
3816 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3817 u32 ih_cntl
= RREG32(IH_CNTL
);
3819 ih_rb_cntl
&= ~IH_RB_ENABLE
;
3820 ih_cntl
&= ~ENABLE_INTR
;
3821 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3822 WREG32(IH_CNTL
, ih_cntl
);
3823 /* set rptr, wptr to 0 */
3824 WREG32(IH_RB_RPTR
, 0);
3825 WREG32(IH_RB_WPTR
, 0);
3826 rdev
->ih
.enabled
= false;
3830 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
3834 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
3835 tmp
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
3836 WREG32(DMA_CNTL
, tmp
);
3837 WREG32(GRBM_INT_CNTL
, 0);
3838 WREG32(DxMODE_INT_MASK
, 0);
3839 WREG32(D1GRPH_INTERRUPT_CONTROL
, 0);
3840 WREG32(D2GRPH_INTERRUPT_CONTROL
, 0);
3841 if (ASIC_IS_DCE3(rdev
)) {
3842 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
3843 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
3844 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3845 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3846 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3847 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3848 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3849 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3850 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3851 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3852 if (ASIC_IS_DCE32(rdev
)) {
3853 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3854 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3855 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3856 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3857 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3858 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
3859 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3860 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
3862 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3863 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
3864 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3865 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
3868 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
3869 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
3870 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
3871 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
3872 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
3873 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
3874 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
3875 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
3876 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3877 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
3878 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3879 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
3883 int r600_irq_init(struct radeon_device
*rdev
)
3887 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
3890 ret
= r600_ih_ring_alloc(rdev
);
3895 r600_disable_interrupts(rdev
);
3898 ret
= r600_rlc_init(rdev
);
3900 r600_ih_ring_fini(rdev
);
3904 /* setup interrupt control */
3905 /* set dummy read address to ring address */
3906 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
3907 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
3908 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3909 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3911 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
3912 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3913 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
3914 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
3916 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
3917 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
3919 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
3920 IH_WPTR_OVERFLOW_CLEAR
|
3923 if (rdev
->wb
.enabled
)
3924 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
3926 /* set the writeback address whether it's enabled or not */
3927 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
3928 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
3930 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3932 /* set rptr, wptr to 0 */
3933 WREG32(IH_RB_RPTR
, 0);
3934 WREG32(IH_RB_WPTR
, 0);
3936 /* Default settings for IH_CNTL (disabled at first) */
3937 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3938 /* RPTR_REARM only works if msi's are enabled */
3939 if (rdev
->msi_enabled
)
3940 ih_cntl
|= RPTR_REARM
;
3941 WREG32(IH_CNTL
, ih_cntl
);
3943 /* force the active interrupt state to all disabled */
3944 if (rdev
->family
>= CHIP_CEDAR
)
3945 evergreen_disable_interrupt_state(rdev
);
3947 r600_disable_interrupt_state(rdev
);
3949 /* at this point everything should be setup correctly to enable master */
3950 pci_set_master(rdev
->pdev
);
3953 r600_enable_interrupts(rdev
);
3958 void r600_irq_suspend(struct radeon_device
*rdev
)
3960 r600_irq_disable(rdev
);
3961 r600_rlc_stop(rdev
);
3964 void r600_irq_fini(struct radeon_device
*rdev
)
3966 r600_irq_suspend(rdev
);
3967 r600_ih_ring_fini(rdev
);
3970 int r600_irq_set(struct radeon_device
*rdev
)
3972 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
3974 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
3975 u32 grbm_int_cntl
= 0;
3977 u32 d1grph
= 0, d2grph
= 0;
3980 if (!rdev
->irq
.installed
) {
3981 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3984 /* don't enable anything if the ih is disabled */
3985 if (!rdev
->ih
.enabled
) {
3986 r600_disable_interrupts(rdev
);
3987 /* force the active interrupt state to all disabled */
3988 r600_disable_interrupt_state(rdev
);
3992 if (ASIC_IS_DCE3(rdev
)) {
3993 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3994 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3995 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3996 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3997 if (ASIC_IS_DCE32(rdev
)) {
3998 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3999 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4000 hdmi0
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
4001 hdmi1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
4003 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4004 hdmi1
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4007 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4008 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4009 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
4010 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4011 hdmi1
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
4013 dma_cntl
= RREG32(DMA_CNTL
) & ~TRAP_ENABLE
;
4015 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
4016 DRM_DEBUG("r600_irq_set: sw int\n");
4017 cp_int_cntl
|= RB_INT_ENABLE
;
4018 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
4021 if (atomic_read(&rdev
->irq
.ring_int
[R600_RING_TYPE_DMA_INDEX
])) {
4022 DRM_DEBUG("r600_irq_set: sw int dma\n");
4023 dma_cntl
|= TRAP_ENABLE
;
4026 if (rdev
->irq
.crtc_vblank_int
[0] ||
4027 atomic_read(&rdev
->irq
.pflip
[0])) {
4028 DRM_DEBUG("r600_irq_set: vblank 0\n");
4029 mode_int
|= D1MODE_VBLANK_INT_MASK
;
4031 if (rdev
->irq
.crtc_vblank_int
[1] ||
4032 atomic_read(&rdev
->irq
.pflip
[1])) {
4033 DRM_DEBUG("r600_irq_set: vblank 1\n");
4034 mode_int
|= D2MODE_VBLANK_INT_MASK
;
4036 if (rdev
->irq
.hpd
[0]) {
4037 DRM_DEBUG("r600_irq_set: hpd 1\n");
4038 hpd1
|= DC_HPDx_INT_EN
;
4040 if (rdev
->irq
.hpd
[1]) {
4041 DRM_DEBUG("r600_irq_set: hpd 2\n");
4042 hpd2
|= DC_HPDx_INT_EN
;
4044 if (rdev
->irq
.hpd
[2]) {
4045 DRM_DEBUG("r600_irq_set: hpd 3\n");
4046 hpd3
|= DC_HPDx_INT_EN
;
4048 if (rdev
->irq
.hpd
[3]) {
4049 DRM_DEBUG("r600_irq_set: hpd 4\n");
4050 hpd4
|= DC_HPDx_INT_EN
;
4052 if (rdev
->irq
.hpd
[4]) {
4053 DRM_DEBUG("r600_irq_set: hpd 5\n");
4054 hpd5
|= DC_HPDx_INT_EN
;
4056 if (rdev
->irq
.hpd
[5]) {
4057 DRM_DEBUG("r600_irq_set: hpd 6\n");
4058 hpd6
|= DC_HPDx_INT_EN
;
4060 if (rdev
->irq
.afmt
[0]) {
4061 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4062 hdmi0
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
4064 if (rdev
->irq
.afmt
[1]) {
4065 DRM_DEBUG("r600_irq_set: hdmi 0\n");
4066 hdmi1
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
4069 WREG32(CP_INT_CNTL
, cp_int_cntl
);
4070 WREG32(DMA_CNTL
, dma_cntl
);
4071 WREG32(DxMODE_INT_MASK
, mode_int
);
4072 WREG32(D1GRPH_INTERRUPT_CONTROL
, d1grph
);
4073 WREG32(D2GRPH_INTERRUPT_CONTROL
, d2grph
);
4074 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
4075 if (ASIC_IS_DCE3(rdev
)) {
4076 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
4077 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
4078 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
4079 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
4080 if (ASIC_IS_DCE32(rdev
)) {
4081 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
4082 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
4083 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, hdmi0
);
4084 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, hdmi1
);
4086 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
4087 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
4090 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
4091 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
4092 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
4093 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
4094 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
4100 static void r600_irq_ack(struct radeon_device
*rdev
)
4104 if (ASIC_IS_DCE3(rdev
)) {
4105 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
4106 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
4107 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
4108 if (ASIC_IS_DCE32(rdev
)) {
4109 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET0
);
4110 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET1
);
4112 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
4113 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(DCE3_HDMI1_STATUS
);
4116 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
4117 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
4118 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= 0;
4119 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
4120 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(HDMI1_STATUS
);
4122 rdev
->irq
.stat_regs
.r600
.d1grph_int
= RREG32(D1GRPH_INTERRUPT_STATUS
);
4123 rdev
->irq
.stat_regs
.r600
.d2grph_int
= RREG32(D2GRPH_INTERRUPT_STATUS
);
4125 if (rdev
->irq
.stat_regs
.r600
.d1grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
4126 WREG32(D1GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
4127 if (rdev
->irq
.stat_regs
.r600
.d2grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
4128 WREG32(D2GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
4129 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
4130 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
4131 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
)
4132 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
4133 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
)
4134 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
4135 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
)
4136 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
4137 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
4138 if (ASIC_IS_DCE3(rdev
)) {
4139 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
4140 tmp
|= DC_HPDx_INT_ACK
;
4141 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
4143 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
4144 tmp
|= DC_HPDx_INT_ACK
;
4145 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
4148 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
4149 if (ASIC_IS_DCE3(rdev
)) {
4150 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
4151 tmp
|= DC_HPDx_INT_ACK
;
4152 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
4154 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
4155 tmp
|= DC_HPDx_INT_ACK
;
4156 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
4159 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
4160 if (ASIC_IS_DCE3(rdev
)) {
4161 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
4162 tmp
|= DC_HPDx_INT_ACK
;
4163 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
4165 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
4166 tmp
|= DC_HPDx_INT_ACK
;
4167 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
4170 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
4171 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
4172 tmp
|= DC_HPDx_INT_ACK
;
4173 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
4175 if (ASIC_IS_DCE32(rdev
)) {
4176 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
4177 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
4178 tmp
|= DC_HPDx_INT_ACK
;
4179 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
4181 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
4182 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
4183 tmp
|= DC_HPDx_INT_ACK
;
4184 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
4186 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& AFMT_AZ_FORMAT_WTRIG
) {
4187 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
);
4188 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
4189 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
4191 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& AFMT_AZ_FORMAT_WTRIG
) {
4192 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
);
4193 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
4194 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
4197 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4198 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
);
4199 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4200 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
4202 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4203 if (ASIC_IS_DCE3(rdev
)) {
4204 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
);
4205 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4206 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4208 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
);
4209 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
4210 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
4216 void r600_irq_disable(struct radeon_device
*rdev
)
4218 r600_disable_interrupts(rdev
);
4219 /* Wait and acknowledge irq */
4222 r600_disable_interrupt_state(rdev
);
4225 static u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
4229 if (rdev
->wb
.enabled
)
4230 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
4232 wptr
= RREG32(IH_RB_WPTR
);
4234 if (wptr
& RB_OVERFLOW
) {
4235 /* When a ring buffer overflow happen start parsing interrupt
4236 * from the last not overwritten vector (wptr + 16). Hopefully
4237 * this should allow us to catchup.
4239 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4240 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
4241 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
4242 tmp
= RREG32(IH_RB_CNTL
);
4243 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
4244 WREG32(IH_RB_CNTL
, tmp
);
4246 return (wptr
& rdev
->ih
.ptr_mask
);
4250 * Each IV ring entry is 128 bits:
4251 * [7:0] - interrupt source id
4253 * [59:32] - interrupt source data
4254 * [127:60] - reserved
4256 * The basic interrupt vector entries
4257 * are decoded as follows:
4258 * src_id src_data description
4263 * 19 0 FP Hot plug detection A
4264 * 19 1 FP Hot plug detection B
4265 * 19 2 DAC A auto-detection
4266 * 19 3 DAC B auto-detection
4272 * 181 - EOP Interrupt
4275 * Note, these are based on r600 and may need to be
4276 * adjusted or added to on newer asics
4279 int r600_irq_process(struct radeon_device
*rdev
)
4283 u32 src_id
, src_data
;
4285 bool queue_hotplug
= false;
4286 bool queue_hdmi
= false;
4288 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
4291 /* No MSIs, need a dummy read to flush PCI DMAs */
4292 if (!rdev
->msi_enabled
)
4295 wptr
= r600_get_ih_wptr(rdev
);
4298 /* is somebody else already processing irqs? */
4299 if (atomic_xchg(&rdev
->ih
.lock
, 1))
4302 rptr
= rdev
->ih
.rptr
;
4303 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
4305 /* Order reading of wptr vs. reading of IH ring data */
4308 /* display interrupts */
4311 while (rptr
!= wptr
) {
4312 /* wptr/rptr are in bytes! */
4313 ring_index
= rptr
/ 4;
4314 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
4315 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
4318 case 1: /* D1 vblank/vline */
4320 case 0: /* D1 vblank */
4321 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
4322 if (rdev
->irq
.crtc_vblank_int
[0]) {
4323 drm_handle_vblank(rdev
->ddev
, 0);
4324 rdev
->pm
.vblank_sync
= true;
4325 wake_up(&rdev
->irq
.vblank_queue
);
4327 if (atomic_read(&rdev
->irq
.pflip
[0]))
4328 radeon_crtc_handle_flip(rdev
, 0);
4329 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
4330 DRM_DEBUG("IH: D1 vblank\n");
4333 case 1: /* D1 vline */
4334 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
4335 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
4336 DRM_DEBUG("IH: D1 vline\n");
4340 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4344 case 5: /* D2 vblank/vline */
4346 case 0: /* D2 vblank */
4347 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
) {
4348 if (rdev
->irq
.crtc_vblank_int
[1]) {
4349 drm_handle_vblank(rdev
->ddev
, 1);
4350 rdev
->pm
.vblank_sync
= true;
4351 wake_up(&rdev
->irq
.vblank_queue
);
4353 if (atomic_read(&rdev
->irq
.pflip
[1]))
4354 radeon_crtc_handle_flip(rdev
, 1);
4355 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
4356 DRM_DEBUG("IH: D2 vblank\n");
4359 case 1: /* D1 vline */
4360 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
) {
4361 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
4362 DRM_DEBUG("IH: D2 vline\n");
4366 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4370 case 19: /* HPD/DAC hotplug */
4373 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
4374 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD1_INTERRUPT
;
4375 queue_hotplug
= true;
4376 DRM_DEBUG("IH: HPD1\n");
4380 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
4381 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD2_INTERRUPT
;
4382 queue_hotplug
= true;
4383 DRM_DEBUG("IH: HPD2\n");
4387 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
4388 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
4389 queue_hotplug
= true;
4390 DRM_DEBUG("IH: HPD3\n");
4394 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
4395 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
4396 queue_hotplug
= true;
4397 DRM_DEBUG("IH: HPD4\n");
4401 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
4402 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD5_INTERRUPT
;
4403 queue_hotplug
= true;
4404 DRM_DEBUG("IH: HPD5\n");
4408 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
4409 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD6_INTERRUPT
;
4410 queue_hotplug
= true;
4411 DRM_DEBUG("IH: HPD6\n");
4415 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4422 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4423 rdev
->irq
.stat_regs
.r600
.hdmi0_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
4425 DRM_DEBUG("IH: HDMI0\n");
4429 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
4430 rdev
->irq
.stat_regs
.r600
.hdmi1_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
4432 DRM_DEBUG("IH: HDMI1\n");
4436 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4440 case 176: /* CP_INT in ring buffer */
4441 case 177: /* CP_INT in IB1 */
4442 case 178: /* CP_INT in IB2 */
4443 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
4444 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
4446 case 181: /* CP EOP event */
4447 DRM_DEBUG("IH: CP EOP\n");
4448 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
4450 case 224: /* DMA trap event */
4451 DRM_DEBUG("IH: DMA trap\n");
4452 radeon_fence_process(rdev
, R600_RING_TYPE_DMA_INDEX
);
4454 case 233: /* GUI IDLE */
4455 DRM_DEBUG("IH: GUI idle\n");
4458 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
4462 /* wptr/rptr are in bytes! */
4464 rptr
&= rdev
->ih
.ptr_mask
;
4467 schedule_work(&rdev
->hotplug_work
);
4469 schedule_work(&rdev
->audio_work
);
4470 rdev
->ih
.rptr
= rptr
;
4471 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
4472 atomic_set(&rdev
->ih
.lock
, 0);
4474 /* make sure wptr hasn't changed while processing */
4475 wptr
= r600_get_ih_wptr(rdev
);
4485 #if defined(CONFIG_DEBUG_FS)
4487 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
4489 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4490 struct drm_device
*dev
= node
->minor
->dev
;
4491 struct radeon_device
*rdev
= dev
->dev_private
;
4493 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
4494 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
4498 static struct drm_info_list r600_mc_info_list
[] = {
4499 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
4503 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
4505 #if defined(CONFIG_DEBUG_FS)
4506 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));
4513 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4514 * rdev: radeon device structure
4515 * bo: buffer object struct which userspace is waiting for idle
4517 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4518 * through ring buffer, this leads to corruption in rendering, see
4519 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4520 * directly perform HDP flush by writing register through MMIO.
4522 void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
)
4524 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4525 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4526 * This seems to cause problems on some AGP cards. Just use the old
4529 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
4530 rdev
->vram_scratch
.ptr
&& !(rdev
->flags
& RADEON_IS_AGP
)) {
4531 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
4534 WREG32(HDP_DEBUG1
, 0);
4535 tmp
= readl((void __iomem
*)ptr
);
4537 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
4540 void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
4542 u32 link_width_cntl
, mask
;
4544 if (rdev
->flags
& RADEON_IS_IGP
)
4547 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4550 /* x2 cards have a special sequence */
4551 if (ASIC_IS_X2(rdev
))
4554 radeon_gui_idle(rdev
);
4558 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
4561 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
4564 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
4567 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
4570 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
4573 /* not actually supported */
4574 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
4577 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
4580 DRM_ERROR("invalid pcie lane request: %d\n", lanes
);
4584 link_width_cntl
= RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
4585 link_width_cntl
&= ~RADEON_PCIE_LC_LINK_WIDTH_MASK
;
4586 link_width_cntl
|= mask
<< RADEON_PCIE_LC_LINK_WIDTH_SHIFT
;
4587 link_width_cntl
|= (RADEON_PCIE_LC_RECONFIG_NOW
|
4588 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
);
4590 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4593 int r600_get_pcie_lanes(struct radeon_device
*rdev
)
4595 u32 link_width_cntl
;
4597 if (rdev
->flags
& RADEON_IS_IGP
)
4600 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4603 /* x2 cards have a special sequence */
4604 if (ASIC_IS_X2(rdev
))
4607 radeon_gui_idle(rdev
);
4609 link_width_cntl
= RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
4611 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
4612 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
4614 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
4616 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
4618 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
4620 case RADEON_PCIE_LC_LINK_WIDTH_X12
:
4621 /* not actually supported */
4623 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
4624 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
4630 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
)
4632 u32 link_width_cntl
, lanes
, speed_cntl
, training_cntl
, tmp
;
4635 if (radeon_pcie_gen2
== 0)
4638 if (rdev
->flags
& RADEON_IS_IGP
)
4641 if (!(rdev
->flags
& RADEON_IS_PCIE
))
4644 /* x2 cards have a special sequence */
4645 if (ASIC_IS_X2(rdev
))
4648 /* only RV6xx+ chips are supported */
4649 if (rdev
->family
<= CHIP_R600
)
4652 if ((rdev
->pdev
->bus
->max_bus_speed
!= PCIE_SPEED_5_0GT
) &&
4653 (rdev
->pdev
->bus
->max_bus_speed
!= PCIE_SPEED_8_0GT
))
4656 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4657 if (speed_cntl
& LC_CURRENT_DATA_RATE
) {
4658 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4662 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4664 /* 55 nm r6xx asics */
4665 if ((rdev
->family
== CHIP_RV670
) ||
4666 (rdev
->family
== CHIP_RV620
) ||
4667 (rdev
->family
== CHIP_RV635
)) {
4668 /* advertise upconfig capability */
4669 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4670 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
4671 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4672 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4673 if (link_width_cntl
& LC_RENEGOTIATION_SUPPORT
) {
4674 lanes
= (link_width_cntl
& LC_LINK_WIDTH_RD_MASK
) >> LC_LINK_WIDTH_RD_SHIFT
;
4675 link_width_cntl
&= ~(LC_LINK_WIDTH_MASK
|
4676 LC_RECONFIG_ARC_MISSING_ESCAPE
);
4677 link_width_cntl
|= lanes
| LC_RECONFIG_NOW
| LC_RENEGOTIATE_EN
;
4678 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4680 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
4681 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4685 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4686 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
4687 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
4689 /* 55 nm r6xx asics */
4690 if ((rdev
->family
== CHIP_RV670
) ||
4691 (rdev
->family
== CHIP_RV620
) ||
4692 (rdev
->family
== CHIP_RV635
)) {
4693 WREG32(MM_CFGREGS_CNTL
, 0x8);
4694 link_cntl2
= RREG32(0x4088);
4695 WREG32(MM_CFGREGS_CNTL
, 0);
4696 /* not supported yet */
4697 if (link_cntl2
& SELECTABLE_DEEMPHASIS
)
4701 speed_cntl
&= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
;
4702 speed_cntl
|= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
);
4703 speed_cntl
&= ~LC_VOLTAGE_TIMER_SEL_MASK
;
4704 speed_cntl
&= ~LC_FORCE_DIS_HW_SPEED_CHANGE
;
4705 speed_cntl
|= LC_FORCE_EN_HW_SPEED_CHANGE
;
4706 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4708 tmp
= RREG32(0x541c);
4709 WREG32(0x541c, tmp
| 0x8);
4710 WREG32(MM_CFGREGS_CNTL
, MM_WR_TO_CFG_EN
);
4711 link_cntl2
= RREG16(0x4088);
4712 link_cntl2
&= ~TARGET_LINK_SPEED_MASK
;
4714 WREG16(0x4088, link_cntl2
);
4715 WREG32(MM_CFGREGS_CNTL
, 0);
4717 if ((rdev
->family
== CHIP_RV670
) ||
4718 (rdev
->family
== CHIP_RV620
) ||
4719 (rdev
->family
== CHIP_RV635
)) {
4720 training_cntl
= RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL
);
4721 training_cntl
&= ~LC_POINT_7_PLUS_EN
;
4722 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL
, training_cntl
);
4724 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4725 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
4726 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4729 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
);
4730 speed_cntl
|= LC_GEN2_EN_STRAP
;
4731 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
, speed_cntl
);
4734 link_width_cntl
= RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
);
4735 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4737 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
4739 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
4740 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
4745 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4747 * @rdev: radeon_device pointer
4749 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4750 * Returns the 64 bit clock counter snapshot.
4752 uint64_t r600_get_gpu_clock_counter(struct radeon_device
*rdev
)
4756 mutex_lock(&rdev
->gpu_clock_mutex
);
4757 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4758 clock
= (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB
) |
4759 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4760 mutex_unlock(&rdev
->gpu_clock_mutex
);