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Merge branch 'late/board' into devel-late
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
33 #include "drmP.h"
34 #include "radeon_drm.h"
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
38 #include "r600d.h"
39 #include "atom.h"
40 #include "avivod.h"
41
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
53
54 /* Firmware Names */
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
96
97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
98
99 /* r600,rv610,rv630,rv620,rv635,rv670 */
100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
101 void r600_gpu_init(struct radeon_device *rdev);
102 void r600_fini(struct radeon_device *rdev);
103 void r600_irq_disable(struct radeon_device *rdev);
104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
105
106 /* get temperature in millidegrees */
107 int rv6xx_get_temp(struct radeon_device *rdev)
108 {
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
110 ASIC_T_SHIFT;
111 int actual_temp = temp & 0xff;
112
113 if (temp & 0x100)
114 actual_temp -= 256;
115
116 return actual_temp * 1000;
117 }
118
119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
120 {
121 int i;
122
123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
125
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
129
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
132
133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
137 rdev->pm.dynpm_can_downclock = false;
138 break;
139 case DYNPM_ACTION_DOWNCLOCK:
140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
142 rdev->pm.dynpm_can_downclock = false;
143 } else {
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
147 continue;
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
151 break;
152 } else {
153 rdev->pm.requested_power_state_index = i;
154 break;
155 }
156 }
157 } else {
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
161 else
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
164 }
165 }
166 rdev->pm.requested_clock_mode_index = 0;
167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
173 }
174 break;
175 case DYNPM_ACTION_UPCLOCK:
176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
178 rdev->pm.dynpm_can_upclock = false;
179 } else {
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
183 continue;
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
187 break;
188 } else {
189 rdev->pm.requested_power_state_index = i;
190 break;
191 }
192 }
193 } else
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
196 }
197 rdev->pm.requested_clock_mode_index = 0;
198 break;
199 case DYNPM_ACTION_DEFAULT:
200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
202 rdev->pm.dynpm_can_upclock = false;
203 break;
204 case DYNPM_ACTION_NONE:
205 default:
206 DRM_ERROR("Requested mode for not defined action\n");
207 return;
208 }
209 } else {
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
218 continue;
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
222 break;
223 }
224 }
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
228 } else
229 rdev->pm.requested_power_state_index = 1;
230
231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
233 rdev->pm.requested_clock_mode_index = 0;
234 rdev->pm.dynpm_can_downclock = false;
235 break;
236 case DYNPM_ACTION_DOWNCLOCK:
237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
240 rdev->pm.dynpm_can_downclock = false;
241 } else
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
244 } else {
245 rdev->pm.requested_clock_mode_index = 0;
246 rdev->pm.dynpm_can_downclock = false;
247 }
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
254 }
255 break;
256 case DYNPM_ACTION_UPCLOCK:
257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
261 rdev->pm.dynpm_can_upclock = false;
262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
265 } else {
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
268 rdev->pm.dynpm_can_upclock = false;
269 }
270 break;
271 case DYNPM_ACTION_DEFAULT:
272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
274 rdev->pm.dynpm_can_upclock = false;
275 break;
276 case DYNPM_ACTION_NONE:
277 default:
278 DRM_ERROR("Requested mode for not defined action\n");
279 return;
280 }
281 }
282
283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 pcie_lanes);
290 }
291
292 void rs780_pm_init_profile(struct radeon_device *rdev)
293 {
294 if (rdev->pm.num_power_states == 2) {
295 /* default */
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 /* low sh */
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
305 /* mid sh */
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
310 /* high sh */
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 /* low mh */
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
320 /* mid mh */
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
325 /* high mh */
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
331 /* default */
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
336 /* low sh */
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
341 /* mid sh */
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
346 /* high sh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351 /* low mh */
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
356 /* mid mh */
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
361 /* high mh */
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
366 } else {
367 /* default */
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
372 /* low sh */
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
377 /* mid sh */
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
382 /* high sh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
387 /* low mh */
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
392 /* mid mh */
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
397 /* high mh */
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
402 }
403 }
404
405 void r600_pm_init_profile(struct radeon_device *rdev)
406 {
407 int idx;
408
409 if (rdev->family == CHIP_R600) {
410 /* XXX */
411 /* default */
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
416 /* low sh */
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
421 /* mid sh */
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
426 /* high sh */
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
431 /* low mh */
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
436 /* mid mh */
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
441 /* high mh */
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
446 } else {
447 if (rdev->pm.num_power_states < 4) {
448 /* default */
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
453 /* low sh */
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
458 /* mid sh */
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
463 /* high sh */
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
468 /* low mh */
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
473 /* low mh */
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
478 /* high mh */
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
483 } else {
484 /* default */
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
489 /* low sh */
490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
492 else
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
498 /* mid sh */
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
503 /* high sh */
504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
509 /* low mh */
510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
512 else
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
518 /* mid mh */
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
523 /* high mh */
524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
529 }
530 }
531 }
532
533 void r600_pm_misc(struct radeon_device *rdev)
534 {
535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
539
540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
543 return;
544 if (voltage->voltage != rdev->pm.current_vddc) {
545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
546 rdev->pm.current_vddc = voltage->voltage;
547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
548 }
549 }
550 }
551
552 bool r600_gui_idle(struct radeon_device *rdev)
553 {
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
555 return false;
556 else
557 return true;
558 }
559
560 /* hpd for digital panel detect/disconnect */
561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562 {
563 bool connected = false;
564
565 if (ASIC_IS_DCE3(rdev)) {
566 switch (hpd) {
567 case RADEON_HPD_1:
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
569 connected = true;
570 break;
571 case RADEON_HPD_2:
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
573 connected = true;
574 break;
575 case RADEON_HPD_3:
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
577 connected = true;
578 break;
579 case RADEON_HPD_4:
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
581 connected = true;
582 break;
583 /* DCE 3.2 */
584 case RADEON_HPD_5:
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
586 connected = true;
587 break;
588 case RADEON_HPD_6:
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 default:
593 break;
594 }
595 } else {
596 switch (hpd) {
597 case RADEON_HPD_1:
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_2:
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
603 connected = true;
604 break;
605 case RADEON_HPD_3:
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
607 connected = true;
608 break;
609 default:
610 break;
611 }
612 }
613 return connected;
614 }
615
616 void r600_hpd_set_polarity(struct radeon_device *rdev,
617 enum radeon_hpd_id hpd)
618 {
619 u32 tmp;
620 bool connected = r600_hpd_sense(rdev, hpd);
621
622 if (ASIC_IS_DCE3(rdev)) {
623 switch (hpd) {
624 case RADEON_HPD_1:
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
626 if (connected)
627 tmp &= ~DC_HPDx_INT_POLARITY;
628 else
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
631 break;
632 case RADEON_HPD_2:
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
634 if (connected)
635 tmp &= ~DC_HPDx_INT_POLARITY;
636 else
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
639 break;
640 case RADEON_HPD_3:
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
642 if (connected)
643 tmp &= ~DC_HPDx_INT_POLARITY;
644 else
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
647 break;
648 case RADEON_HPD_4:
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
650 if (connected)
651 tmp &= ~DC_HPDx_INT_POLARITY;
652 else
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
655 break;
656 case RADEON_HPD_5:
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
658 if (connected)
659 tmp &= ~DC_HPDx_INT_POLARITY;
660 else
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
663 break;
664 /* DCE 3.2 */
665 case RADEON_HPD_6:
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
667 if (connected)
668 tmp &= ~DC_HPDx_INT_POLARITY;
669 else
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
672 break;
673 default:
674 break;
675 }
676 } else {
677 switch (hpd) {
678 case RADEON_HPD_1:
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
682 else
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
685 break;
686 case RADEON_HPD_2:
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
690 else
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
693 break;
694 case RADEON_HPD_3:
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
696 if (connected)
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
698 else
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
701 break;
702 default:
703 break;
704 }
705 }
706 }
707
708 void r600_hpd_init(struct radeon_device *rdev)
709 {
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
712
713 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
714 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
715
716 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
717 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
718 /* don't try to enable hpd on eDP or LVDS avoid breaking the
719 * aux dp channel on imac and help (but not completely fix)
720 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
721 */
722 continue;
723 }
724 if (ASIC_IS_DCE3(rdev)) {
725 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
726 if (ASIC_IS_DCE32(rdev))
727 tmp |= DC_HPDx_EN;
728
729 switch (radeon_connector->hpd.hpd) {
730 case RADEON_HPD_1:
731 WREG32(DC_HPD1_CONTROL, tmp);
732 rdev->irq.hpd[0] = true;
733 break;
734 case RADEON_HPD_2:
735 WREG32(DC_HPD2_CONTROL, tmp);
736 rdev->irq.hpd[1] = true;
737 break;
738 case RADEON_HPD_3:
739 WREG32(DC_HPD3_CONTROL, tmp);
740 rdev->irq.hpd[2] = true;
741 break;
742 case RADEON_HPD_4:
743 WREG32(DC_HPD4_CONTROL, tmp);
744 rdev->irq.hpd[3] = true;
745 break;
746 /* DCE 3.2 */
747 case RADEON_HPD_5:
748 WREG32(DC_HPD5_CONTROL, tmp);
749 rdev->irq.hpd[4] = true;
750 break;
751 case RADEON_HPD_6:
752 WREG32(DC_HPD6_CONTROL, tmp);
753 rdev->irq.hpd[5] = true;
754 break;
755 default:
756 break;
757 }
758 } else {
759 switch (radeon_connector->hpd.hpd) {
760 case RADEON_HPD_1:
761 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
762 rdev->irq.hpd[0] = true;
763 break;
764 case RADEON_HPD_2:
765 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
766 rdev->irq.hpd[1] = true;
767 break;
768 case RADEON_HPD_3:
769 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
770 rdev->irq.hpd[2] = true;
771 break;
772 default:
773 break;
774 }
775 }
776 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
777 }
778 if (rdev->irq.installed)
779 r600_irq_set(rdev);
780 }
781
782 void r600_hpd_fini(struct radeon_device *rdev)
783 {
784 struct drm_device *dev = rdev->ddev;
785 struct drm_connector *connector;
786
787 if (ASIC_IS_DCE3(rdev)) {
788 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
789 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
790 switch (radeon_connector->hpd.hpd) {
791 case RADEON_HPD_1:
792 WREG32(DC_HPD1_CONTROL, 0);
793 rdev->irq.hpd[0] = false;
794 break;
795 case RADEON_HPD_2:
796 WREG32(DC_HPD2_CONTROL, 0);
797 rdev->irq.hpd[1] = false;
798 break;
799 case RADEON_HPD_3:
800 WREG32(DC_HPD3_CONTROL, 0);
801 rdev->irq.hpd[2] = false;
802 break;
803 case RADEON_HPD_4:
804 WREG32(DC_HPD4_CONTROL, 0);
805 rdev->irq.hpd[3] = false;
806 break;
807 /* DCE 3.2 */
808 case RADEON_HPD_5:
809 WREG32(DC_HPD5_CONTROL, 0);
810 rdev->irq.hpd[4] = false;
811 break;
812 case RADEON_HPD_6:
813 WREG32(DC_HPD6_CONTROL, 0);
814 rdev->irq.hpd[5] = false;
815 break;
816 default:
817 break;
818 }
819 }
820 } else {
821 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
822 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
823 switch (radeon_connector->hpd.hpd) {
824 case RADEON_HPD_1:
825 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
826 rdev->irq.hpd[0] = false;
827 break;
828 case RADEON_HPD_2:
829 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
830 rdev->irq.hpd[1] = false;
831 break;
832 case RADEON_HPD_3:
833 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
834 rdev->irq.hpd[2] = false;
835 break;
836 default:
837 break;
838 }
839 }
840 }
841 }
842
843 /*
844 * R600 PCIE GART
845 */
846 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
847 {
848 unsigned i;
849 u32 tmp;
850
851 /* flush hdp cache so updates hit vram */
852 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
853 !(rdev->flags & RADEON_IS_AGP)) {
854 void __iomem *ptr = (void *)rdev->gart.ptr;
855 u32 tmp;
856
857 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
858 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
859 * This seems to cause problems on some AGP cards. Just use the old
860 * method for them.
861 */
862 WREG32(HDP_DEBUG1, 0);
863 tmp = readl((void __iomem *)ptr);
864 } else
865 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
866
867 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
868 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
869 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
870 for (i = 0; i < rdev->usec_timeout; i++) {
871 /* read MC_STATUS */
872 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
873 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
874 if (tmp == 2) {
875 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
876 return;
877 }
878 if (tmp) {
879 return;
880 }
881 udelay(1);
882 }
883 }
884
885 int r600_pcie_gart_init(struct radeon_device *rdev)
886 {
887 int r;
888
889 if (rdev->gart.robj) {
890 WARN(1, "R600 PCIE GART already initialized\n");
891 return 0;
892 }
893 /* Initialize common gart structure */
894 r = radeon_gart_init(rdev);
895 if (r)
896 return r;
897 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
898 return radeon_gart_table_vram_alloc(rdev);
899 }
900
901 int r600_pcie_gart_enable(struct radeon_device *rdev)
902 {
903 u32 tmp;
904 int r, i;
905
906 if (rdev->gart.robj == NULL) {
907 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
908 return -EINVAL;
909 }
910 r = radeon_gart_table_vram_pin(rdev);
911 if (r)
912 return r;
913 radeon_gart_restore(rdev);
914
915 /* Setup L2 cache */
916 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
917 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
918 EFFECTIVE_L2_QUEUE_SIZE(7));
919 WREG32(VM_L2_CNTL2, 0);
920 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
921 /* Setup TLB control */
922 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
923 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
924 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
925 ENABLE_WAIT_L2_QUERY;
926 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
929 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
931 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
939 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
940 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
941 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
942 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
943 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
944 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
945 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
946 (u32)(rdev->dummy_page.addr >> 12));
947 for (i = 1; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
949
950 r600_pcie_gart_tlb_flush(rdev);
951 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
952 (unsigned)(rdev->mc.gtt_size >> 20),
953 (unsigned long long)rdev->gart.table_addr);
954 rdev->gart.ready = true;
955 return 0;
956 }
957
958 void r600_pcie_gart_disable(struct radeon_device *rdev)
959 {
960 u32 tmp;
961 int i;
962
963 /* Disable all tables */
964 for (i = 0; i < 7; i++)
965 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
966
967 /* Disable L2 cache */
968 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
969 EFFECTIVE_L2_QUEUE_SIZE(7));
970 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
971 /* Setup L1 TLB control */
972 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
973 ENABLE_WAIT_L2_QUERY;
974 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
987 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
988 radeon_gart_table_vram_unpin(rdev);
989 }
990
991 void r600_pcie_gart_fini(struct radeon_device *rdev)
992 {
993 radeon_gart_fini(rdev);
994 r600_pcie_gart_disable(rdev);
995 radeon_gart_table_vram_free(rdev);
996 }
997
998 void r600_agp_enable(struct radeon_device *rdev)
999 {
1000 u32 tmp;
1001 int i;
1002
1003 /* Setup L2 cache */
1004 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1005 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1006 EFFECTIVE_L2_QUEUE_SIZE(7));
1007 WREG32(VM_L2_CNTL2, 0);
1008 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1009 /* Setup TLB control */
1010 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1011 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1012 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1013 ENABLE_WAIT_L2_QUERY;
1014 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1028 for (i = 0; i < 7; i++)
1029 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1030 }
1031
1032 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1033 {
1034 unsigned i;
1035 u32 tmp;
1036
1037 for (i = 0; i < rdev->usec_timeout; i++) {
1038 /* read MC_STATUS */
1039 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1040 if (!tmp)
1041 return 0;
1042 udelay(1);
1043 }
1044 return -1;
1045 }
1046
1047 static void r600_mc_program(struct radeon_device *rdev)
1048 {
1049 struct rv515_mc_save save;
1050 u32 tmp;
1051 int i, j;
1052
1053 /* Initialize HDP */
1054 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1055 WREG32((0x2c14 + j), 0x00000000);
1056 WREG32((0x2c18 + j), 0x00000000);
1057 WREG32((0x2c1c + j), 0x00000000);
1058 WREG32((0x2c20 + j), 0x00000000);
1059 WREG32((0x2c24 + j), 0x00000000);
1060 }
1061 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1062
1063 rv515_mc_stop(rdev, &save);
1064 if (r600_mc_wait_for_idle(rdev)) {
1065 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1066 }
1067 /* Lockout access through VGA aperture (doesn't exist before R600) */
1068 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1069 /* Update configuration */
1070 if (rdev->flags & RADEON_IS_AGP) {
1071 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1072 /* VRAM before AGP */
1073 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1074 rdev->mc.vram_start >> 12);
1075 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1076 rdev->mc.gtt_end >> 12);
1077 } else {
1078 /* VRAM after AGP */
1079 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1080 rdev->mc.gtt_start >> 12);
1081 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1082 rdev->mc.vram_end >> 12);
1083 }
1084 } else {
1085 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1086 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1087 }
1088 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1089 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1090 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1091 WREG32(MC_VM_FB_LOCATION, tmp);
1092 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1093 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1094 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1095 if (rdev->flags & RADEON_IS_AGP) {
1096 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1097 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1098 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1099 } else {
1100 WREG32(MC_VM_AGP_BASE, 0);
1101 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1102 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1103 }
1104 if (r600_mc_wait_for_idle(rdev)) {
1105 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1106 }
1107 rv515_mc_resume(rdev, &save);
1108 /* we need to own VRAM, so turn off the VGA renderer here
1109 * to stop it overwriting our objects */
1110 rv515_vga_render_disable(rdev);
1111 }
1112
1113 /**
1114 * r600_vram_gtt_location - try to find VRAM & GTT location
1115 * @rdev: radeon device structure holding all necessary informations
1116 * @mc: memory controller structure holding memory informations
1117 *
1118 * Function will place try to place VRAM at same place as in CPU (PCI)
1119 * address space as some GPU seems to have issue when we reprogram at
1120 * different address space.
1121 *
1122 * If there is not enough space to fit the unvisible VRAM after the
1123 * aperture then we limit the VRAM size to the aperture.
1124 *
1125 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1126 * them to be in one from GPU point of view so that we can program GPU to
1127 * catch access outside them (weird GPU policy see ??).
1128 *
1129 * This function will never fails, worst case are limiting VRAM or GTT.
1130 *
1131 * Note: GTT start, end, size should be initialized before calling this
1132 * function on AGP platform.
1133 */
1134 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1135 {
1136 u64 size_bf, size_af;
1137
1138 if (mc->mc_vram_size > 0xE0000000) {
1139 /* leave room for at least 512M GTT */
1140 dev_warn(rdev->dev, "limiting VRAM\n");
1141 mc->real_vram_size = 0xE0000000;
1142 mc->mc_vram_size = 0xE0000000;
1143 }
1144 if (rdev->flags & RADEON_IS_AGP) {
1145 size_bf = mc->gtt_start;
1146 size_af = 0xFFFFFFFF - mc->gtt_end;
1147 if (size_bf > size_af) {
1148 if (mc->mc_vram_size > size_bf) {
1149 dev_warn(rdev->dev, "limiting VRAM\n");
1150 mc->real_vram_size = size_bf;
1151 mc->mc_vram_size = size_bf;
1152 }
1153 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1154 } else {
1155 if (mc->mc_vram_size > size_af) {
1156 dev_warn(rdev->dev, "limiting VRAM\n");
1157 mc->real_vram_size = size_af;
1158 mc->mc_vram_size = size_af;
1159 }
1160 mc->vram_start = mc->gtt_end + 1;
1161 }
1162 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1163 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1164 mc->mc_vram_size >> 20, mc->vram_start,
1165 mc->vram_end, mc->real_vram_size >> 20);
1166 } else {
1167 u64 base = 0;
1168 if (rdev->flags & RADEON_IS_IGP) {
1169 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1170 base <<= 24;
1171 }
1172 radeon_vram_location(rdev, &rdev->mc, base);
1173 rdev->mc.gtt_base_align = 0;
1174 radeon_gtt_location(rdev, mc);
1175 }
1176 }
1177
1178 int r600_mc_init(struct radeon_device *rdev)
1179 {
1180 u32 tmp;
1181 int chansize, numchan;
1182
1183 /* Get VRAM informations */
1184 rdev->mc.vram_is_ddr = true;
1185 tmp = RREG32(RAMCFG);
1186 if (tmp & CHANSIZE_OVERRIDE) {
1187 chansize = 16;
1188 } else if (tmp & CHANSIZE_MASK) {
1189 chansize = 64;
1190 } else {
1191 chansize = 32;
1192 }
1193 tmp = RREG32(CHMAP);
1194 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1195 case 0:
1196 default:
1197 numchan = 1;
1198 break;
1199 case 1:
1200 numchan = 2;
1201 break;
1202 case 2:
1203 numchan = 4;
1204 break;
1205 case 3:
1206 numchan = 8;
1207 break;
1208 }
1209 rdev->mc.vram_width = numchan * chansize;
1210 /* Could aper size report 0 ? */
1211 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1212 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1213 /* Setup GPU memory space */
1214 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1215 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1216 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1217 r600_vram_gtt_location(rdev, &rdev->mc);
1218
1219 if (rdev->flags & RADEON_IS_IGP) {
1220 rs690_pm_info(rdev);
1221 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1222 }
1223 radeon_update_bandwidth_info(rdev);
1224 return 0;
1225 }
1226
1227 int r600_vram_scratch_init(struct radeon_device *rdev)
1228 {
1229 int r;
1230
1231 if (rdev->vram_scratch.robj == NULL) {
1232 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1233 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1234 NULL, &rdev->vram_scratch.robj);
1235 if (r) {
1236 return r;
1237 }
1238 }
1239
1240 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1241 if (unlikely(r != 0))
1242 return r;
1243 r = radeon_bo_pin(rdev->vram_scratch.robj,
1244 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1245 if (r) {
1246 radeon_bo_unreserve(rdev->vram_scratch.robj);
1247 return r;
1248 }
1249 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1250 (void **)&rdev->vram_scratch.ptr);
1251 if (r)
1252 radeon_bo_unpin(rdev->vram_scratch.robj);
1253 radeon_bo_unreserve(rdev->vram_scratch.robj);
1254
1255 return r;
1256 }
1257
1258 void r600_vram_scratch_fini(struct radeon_device *rdev)
1259 {
1260 int r;
1261
1262 if (rdev->vram_scratch.robj == NULL) {
1263 return;
1264 }
1265 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1266 if (likely(r == 0)) {
1267 radeon_bo_kunmap(rdev->vram_scratch.robj);
1268 radeon_bo_unpin(rdev->vram_scratch.robj);
1269 radeon_bo_unreserve(rdev->vram_scratch.robj);
1270 }
1271 radeon_bo_unref(&rdev->vram_scratch.robj);
1272 }
1273
1274 /* We doesn't check that the GPU really needs a reset we simply do the
1275 * reset, it's up to the caller to determine if the GPU needs one. We
1276 * might add an helper function to check that.
1277 */
1278 int r600_gpu_soft_reset(struct radeon_device *rdev)
1279 {
1280 struct rv515_mc_save save;
1281 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1282 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1283 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1284 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1285 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1286 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1287 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1288 S_008010_GUI_ACTIVE(1);
1289 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1290 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1291 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1292 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1293 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1294 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1295 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1296 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1297 u32 tmp;
1298
1299 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1300 return 0;
1301
1302 dev_info(rdev->dev, "GPU softreset \n");
1303 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1304 RREG32(R_008010_GRBM_STATUS));
1305 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1306 RREG32(R_008014_GRBM_STATUS2));
1307 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1308 RREG32(R_000E50_SRBM_STATUS));
1309 rv515_mc_stop(rdev, &save);
1310 if (r600_mc_wait_for_idle(rdev)) {
1311 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1312 }
1313 /* Disable CP parsing/prefetching */
1314 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1315 /* Check if any of the rendering block is busy and reset it */
1316 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1317 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1318 tmp = S_008020_SOFT_RESET_CR(1) |
1319 S_008020_SOFT_RESET_DB(1) |
1320 S_008020_SOFT_RESET_CB(1) |
1321 S_008020_SOFT_RESET_PA(1) |
1322 S_008020_SOFT_RESET_SC(1) |
1323 S_008020_SOFT_RESET_SMX(1) |
1324 S_008020_SOFT_RESET_SPI(1) |
1325 S_008020_SOFT_RESET_SX(1) |
1326 S_008020_SOFT_RESET_SH(1) |
1327 S_008020_SOFT_RESET_TC(1) |
1328 S_008020_SOFT_RESET_TA(1) |
1329 S_008020_SOFT_RESET_VC(1) |
1330 S_008020_SOFT_RESET_VGT(1);
1331 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1332 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1333 RREG32(R_008020_GRBM_SOFT_RESET);
1334 mdelay(15);
1335 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1336 }
1337 /* Reset CP (we always reset CP) */
1338 tmp = S_008020_SOFT_RESET_CP(1);
1339 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1340 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1341 RREG32(R_008020_GRBM_SOFT_RESET);
1342 mdelay(15);
1343 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1344 /* Wait a little for things to settle down */
1345 mdelay(1);
1346 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1347 RREG32(R_008010_GRBM_STATUS));
1348 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1349 RREG32(R_008014_GRBM_STATUS2));
1350 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1351 RREG32(R_000E50_SRBM_STATUS));
1352 rv515_mc_resume(rdev, &save);
1353 return 0;
1354 }
1355
1356 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1357 {
1358 u32 srbm_status;
1359 u32 grbm_status;
1360 u32 grbm_status2;
1361
1362 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1363 grbm_status = RREG32(R_008010_GRBM_STATUS);
1364 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1365 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1366 radeon_ring_lockup_update(ring);
1367 return false;
1368 }
1369 /* force CP activities */
1370 radeon_ring_force_activity(rdev, ring);
1371 return radeon_ring_test_lockup(rdev, ring);
1372 }
1373
1374 int r600_asic_reset(struct radeon_device *rdev)
1375 {
1376 return r600_gpu_soft_reset(rdev);
1377 }
1378
1379 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1380 u32 num_backends,
1381 u32 backend_disable_mask)
1382 {
1383 u32 backend_map = 0;
1384 u32 enabled_backends_mask;
1385 u32 enabled_backends_count;
1386 u32 cur_pipe;
1387 u32 swizzle_pipe[R6XX_MAX_PIPES];
1388 u32 cur_backend;
1389 u32 i;
1390
1391 if (num_tile_pipes > R6XX_MAX_PIPES)
1392 num_tile_pipes = R6XX_MAX_PIPES;
1393 if (num_tile_pipes < 1)
1394 num_tile_pipes = 1;
1395 if (num_backends > R6XX_MAX_BACKENDS)
1396 num_backends = R6XX_MAX_BACKENDS;
1397 if (num_backends < 1)
1398 num_backends = 1;
1399
1400 enabled_backends_mask = 0;
1401 enabled_backends_count = 0;
1402 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1403 if (((backend_disable_mask >> i) & 1) == 0) {
1404 enabled_backends_mask |= (1 << i);
1405 ++enabled_backends_count;
1406 }
1407 if (enabled_backends_count == num_backends)
1408 break;
1409 }
1410
1411 if (enabled_backends_count == 0) {
1412 enabled_backends_mask = 1;
1413 enabled_backends_count = 1;
1414 }
1415
1416 if (enabled_backends_count != num_backends)
1417 num_backends = enabled_backends_count;
1418
1419 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1420 switch (num_tile_pipes) {
1421 case 1:
1422 swizzle_pipe[0] = 0;
1423 break;
1424 case 2:
1425 swizzle_pipe[0] = 0;
1426 swizzle_pipe[1] = 1;
1427 break;
1428 case 3:
1429 swizzle_pipe[0] = 0;
1430 swizzle_pipe[1] = 1;
1431 swizzle_pipe[2] = 2;
1432 break;
1433 case 4:
1434 swizzle_pipe[0] = 0;
1435 swizzle_pipe[1] = 1;
1436 swizzle_pipe[2] = 2;
1437 swizzle_pipe[3] = 3;
1438 break;
1439 case 5:
1440 swizzle_pipe[0] = 0;
1441 swizzle_pipe[1] = 1;
1442 swizzle_pipe[2] = 2;
1443 swizzle_pipe[3] = 3;
1444 swizzle_pipe[4] = 4;
1445 break;
1446 case 6:
1447 swizzle_pipe[0] = 0;
1448 swizzle_pipe[1] = 2;
1449 swizzle_pipe[2] = 4;
1450 swizzle_pipe[3] = 5;
1451 swizzle_pipe[4] = 1;
1452 swizzle_pipe[5] = 3;
1453 break;
1454 case 7:
1455 swizzle_pipe[0] = 0;
1456 swizzle_pipe[1] = 2;
1457 swizzle_pipe[2] = 4;
1458 swizzle_pipe[3] = 6;
1459 swizzle_pipe[4] = 1;
1460 swizzle_pipe[5] = 3;
1461 swizzle_pipe[6] = 5;
1462 break;
1463 case 8:
1464 swizzle_pipe[0] = 0;
1465 swizzle_pipe[1] = 2;
1466 swizzle_pipe[2] = 4;
1467 swizzle_pipe[3] = 6;
1468 swizzle_pipe[4] = 1;
1469 swizzle_pipe[5] = 3;
1470 swizzle_pipe[6] = 5;
1471 swizzle_pipe[7] = 7;
1472 break;
1473 }
1474
1475 cur_backend = 0;
1476 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1477 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1478 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1479
1480 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1481
1482 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1483 }
1484
1485 return backend_map;
1486 }
1487
1488 int r600_count_pipe_bits(uint32_t val)
1489 {
1490 int i, ret = 0;
1491
1492 for (i = 0; i < 32; i++) {
1493 ret += val & 1;
1494 val >>= 1;
1495 }
1496 return ret;
1497 }
1498
1499 void r600_gpu_init(struct radeon_device *rdev)
1500 {
1501 u32 tiling_config;
1502 u32 ramcfg;
1503 u32 backend_map;
1504 u32 cc_rb_backend_disable;
1505 u32 cc_gc_shader_pipe_config;
1506 u32 tmp;
1507 int i, j;
1508 u32 sq_config;
1509 u32 sq_gpr_resource_mgmt_1 = 0;
1510 u32 sq_gpr_resource_mgmt_2 = 0;
1511 u32 sq_thread_resource_mgmt = 0;
1512 u32 sq_stack_resource_mgmt_1 = 0;
1513 u32 sq_stack_resource_mgmt_2 = 0;
1514
1515 /* FIXME: implement */
1516 switch (rdev->family) {
1517 case CHIP_R600:
1518 rdev->config.r600.max_pipes = 4;
1519 rdev->config.r600.max_tile_pipes = 8;
1520 rdev->config.r600.max_simds = 4;
1521 rdev->config.r600.max_backends = 4;
1522 rdev->config.r600.max_gprs = 256;
1523 rdev->config.r600.max_threads = 192;
1524 rdev->config.r600.max_stack_entries = 256;
1525 rdev->config.r600.max_hw_contexts = 8;
1526 rdev->config.r600.max_gs_threads = 16;
1527 rdev->config.r600.sx_max_export_size = 128;
1528 rdev->config.r600.sx_max_export_pos_size = 16;
1529 rdev->config.r600.sx_max_export_smx_size = 128;
1530 rdev->config.r600.sq_num_cf_insts = 2;
1531 break;
1532 case CHIP_RV630:
1533 case CHIP_RV635:
1534 rdev->config.r600.max_pipes = 2;
1535 rdev->config.r600.max_tile_pipes = 2;
1536 rdev->config.r600.max_simds = 3;
1537 rdev->config.r600.max_backends = 1;
1538 rdev->config.r600.max_gprs = 128;
1539 rdev->config.r600.max_threads = 192;
1540 rdev->config.r600.max_stack_entries = 128;
1541 rdev->config.r600.max_hw_contexts = 8;
1542 rdev->config.r600.max_gs_threads = 4;
1543 rdev->config.r600.sx_max_export_size = 128;
1544 rdev->config.r600.sx_max_export_pos_size = 16;
1545 rdev->config.r600.sx_max_export_smx_size = 128;
1546 rdev->config.r600.sq_num_cf_insts = 2;
1547 break;
1548 case CHIP_RV610:
1549 case CHIP_RV620:
1550 case CHIP_RS780:
1551 case CHIP_RS880:
1552 rdev->config.r600.max_pipes = 1;
1553 rdev->config.r600.max_tile_pipes = 1;
1554 rdev->config.r600.max_simds = 2;
1555 rdev->config.r600.max_backends = 1;
1556 rdev->config.r600.max_gprs = 128;
1557 rdev->config.r600.max_threads = 192;
1558 rdev->config.r600.max_stack_entries = 128;
1559 rdev->config.r600.max_hw_contexts = 4;
1560 rdev->config.r600.max_gs_threads = 4;
1561 rdev->config.r600.sx_max_export_size = 128;
1562 rdev->config.r600.sx_max_export_pos_size = 16;
1563 rdev->config.r600.sx_max_export_smx_size = 128;
1564 rdev->config.r600.sq_num_cf_insts = 1;
1565 break;
1566 case CHIP_RV670:
1567 rdev->config.r600.max_pipes = 4;
1568 rdev->config.r600.max_tile_pipes = 4;
1569 rdev->config.r600.max_simds = 4;
1570 rdev->config.r600.max_backends = 4;
1571 rdev->config.r600.max_gprs = 192;
1572 rdev->config.r600.max_threads = 192;
1573 rdev->config.r600.max_stack_entries = 256;
1574 rdev->config.r600.max_hw_contexts = 8;
1575 rdev->config.r600.max_gs_threads = 16;
1576 rdev->config.r600.sx_max_export_size = 128;
1577 rdev->config.r600.sx_max_export_pos_size = 16;
1578 rdev->config.r600.sx_max_export_smx_size = 128;
1579 rdev->config.r600.sq_num_cf_insts = 2;
1580 break;
1581 default:
1582 break;
1583 }
1584
1585 /* Initialize HDP */
1586 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1587 WREG32((0x2c14 + j), 0x00000000);
1588 WREG32((0x2c18 + j), 0x00000000);
1589 WREG32((0x2c1c + j), 0x00000000);
1590 WREG32((0x2c20 + j), 0x00000000);
1591 WREG32((0x2c24 + j), 0x00000000);
1592 }
1593
1594 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1595
1596 /* Setup tiling */
1597 tiling_config = 0;
1598 ramcfg = RREG32(RAMCFG);
1599 switch (rdev->config.r600.max_tile_pipes) {
1600 case 1:
1601 tiling_config |= PIPE_TILING(0);
1602 break;
1603 case 2:
1604 tiling_config |= PIPE_TILING(1);
1605 break;
1606 case 4:
1607 tiling_config |= PIPE_TILING(2);
1608 break;
1609 case 8:
1610 tiling_config |= PIPE_TILING(3);
1611 break;
1612 default:
1613 break;
1614 }
1615 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1616 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1617 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1618 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1619 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1620 rdev->config.r600.tiling_group_size = 512;
1621 else
1622 rdev->config.r600.tiling_group_size = 256;
1623 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1624 if (tmp > 3) {
1625 tiling_config |= ROW_TILING(3);
1626 tiling_config |= SAMPLE_SPLIT(3);
1627 } else {
1628 tiling_config |= ROW_TILING(tmp);
1629 tiling_config |= SAMPLE_SPLIT(tmp);
1630 }
1631 tiling_config |= BANK_SWAPS(1);
1632
1633 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1634 cc_rb_backend_disable |=
1635 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1636
1637 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1638 cc_gc_shader_pipe_config |=
1639 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1640 cc_gc_shader_pipe_config |=
1641 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1642
1643 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1644 (R6XX_MAX_BACKENDS -
1645 r600_count_pipe_bits((cc_rb_backend_disable &
1646 R6XX_MAX_BACKENDS_MASK) >> 16)),
1647 (cc_rb_backend_disable >> 16));
1648 rdev->config.r600.tile_config = tiling_config;
1649 rdev->config.r600.backend_map = backend_map;
1650 tiling_config |= BACKEND_MAP(backend_map);
1651 WREG32(GB_TILING_CONFIG, tiling_config);
1652 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1653 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1654
1655 /* Setup pipes */
1656 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1657 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1658 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1659
1660 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1661 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1662 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1663
1664 /* Setup some CP states */
1665 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1666 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1667
1668 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1669 SYNC_WALKER | SYNC_ALIGNER));
1670 /* Setup various GPU states */
1671 if (rdev->family == CHIP_RV670)
1672 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1673
1674 tmp = RREG32(SX_DEBUG_1);
1675 tmp |= SMX_EVENT_RELEASE;
1676 if ((rdev->family > CHIP_R600))
1677 tmp |= ENABLE_NEW_SMX_ADDRESS;
1678 WREG32(SX_DEBUG_1, tmp);
1679
1680 if (((rdev->family) == CHIP_R600) ||
1681 ((rdev->family) == CHIP_RV630) ||
1682 ((rdev->family) == CHIP_RV610) ||
1683 ((rdev->family) == CHIP_RV620) ||
1684 ((rdev->family) == CHIP_RS780) ||
1685 ((rdev->family) == CHIP_RS880)) {
1686 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1687 } else {
1688 WREG32(DB_DEBUG, 0);
1689 }
1690 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1691 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1692
1693 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1694 WREG32(VGT_NUM_INSTANCES, 0);
1695
1696 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1697 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1698
1699 tmp = RREG32(SQ_MS_FIFO_SIZES);
1700 if (((rdev->family) == CHIP_RV610) ||
1701 ((rdev->family) == CHIP_RV620) ||
1702 ((rdev->family) == CHIP_RS780) ||
1703 ((rdev->family) == CHIP_RS880)) {
1704 tmp = (CACHE_FIFO_SIZE(0xa) |
1705 FETCH_FIFO_HIWATER(0xa) |
1706 DONE_FIFO_HIWATER(0xe0) |
1707 ALU_UPDATE_FIFO_HIWATER(0x8));
1708 } else if (((rdev->family) == CHIP_R600) ||
1709 ((rdev->family) == CHIP_RV630)) {
1710 tmp &= ~DONE_FIFO_HIWATER(0xff);
1711 tmp |= DONE_FIFO_HIWATER(0x4);
1712 }
1713 WREG32(SQ_MS_FIFO_SIZES, tmp);
1714
1715 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1716 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1717 */
1718 sq_config = RREG32(SQ_CONFIG);
1719 sq_config &= ~(PS_PRIO(3) |
1720 VS_PRIO(3) |
1721 GS_PRIO(3) |
1722 ES_PRIO(3));
1723 sq_config |= (DX9_CONSTS |
1724 VC_ENABLE |
1725 PS_PRIO(0) |
1726 VS_PRIO(1) |
1727 GS_PRIO(2) |
1728 ES_PRIO(3));
1729
1730 if ((rdev->family) == CHIP_R600) {
1731 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1732 NUM_VS_GPRS(124) |
1733 NUM_CLAUSE_TEMP_GPRS(4));
1734 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1735 NUM_ES_GPRS(0));
1736 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1737 NUM_VS_THREADS(48) |
1738 NUM_GS_THREADS(4) |
1739 NUM_ES_THREADS(4));
1740 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1741 NUM_VS_STACK_ENTRIES(128));
1742 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1743 NUM_ES_STACK_ENTRIES(0));
1744 } else if (((rdev->family) == CHIP_RV610) ||
1745 ((rdev->family) == CHIP_RV620) ||
1746 ((rdev->family) == CHIP_RS780) ||
1747 ((rdev->family) == CHIP_RS880)) {
1748 /* no vertex cache */
1749 sq_config &= ~VC_ENABLE;
1750
1751 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1752 NUM_VS_GPRS(44) |
1753 NUM_CLAUSE_TEMP_GPRS(2));
1754 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1755 NUM_ES_GPRS(17));
1756 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1757 NUM_VS_THREADS(78) |
1758 NUM_GS_THREADS(4) |
1759 NUM_ES_THREADS(31));
1760 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1761 NUM_VS_STACK_ENTRIES(40));
1762 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1763 NUM_ES_STACK_ENTRIES(16));
1764 } else if (((rdev->family) == CHIP_RV630) ||
1765 ((rdev->family) == CHIP_RV635)) {
1766 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1767 NUM_VS_GPRS(44) |
1768 NUM_CLAUSE_TEMP_GPRS(2));
1769 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1770 NUM_ES_GPRS(18));
1771 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1772 NUM_VS_THREADS(78) |
1773 NUM_GS_THREADS(4) |
1774 NUM_ES_THREADS(31));
1775 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1776 NUM_VS_STACK_ENTRIES(40));
1777 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1778 NUM_ES_STACK_ENTRIES(16));
1779 } else if ((rdev->family) == CHIP_RV670) {
1780 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1781 NUM_VS_GPRS(44) |
1782 NUM_CLAUSE_TEMP_GPRS(2));
1783 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1784 NUM_ES_GPRS(17));
1785 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1786 NUM_VS_THREADS(78) |
1787 NUM_GS_THREADS(4) |
1788 NUM_ES_THREADS(31));
1789 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1790 NUM_VS_STACK_ENTRIES(64));
1791 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1792 NUM_ES_STACK_ENTRIES(64));
1793 }
1794
1795 WREG32(SQ_CONFIG, sq_config);
1796 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1797 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1798 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1799 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1800 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1801
1802 if (((rdev->family) == CHIP_RV610) ||
1803 ((rdev->family) == CHIP_RV620) ||
1804 ((rdev->family) == CHIP_RS780) ||
1805 ((rdev->family) == CHIP_RS880)) {
1806 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1807 } else {
1808 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1809 }
1810
1811 /* More default values. 2D/3D driver should adjust as needed */
1812 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1813 S1_X(0x4) | S1_Y(0xc)));
1814 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1815 S1_X(0x2) | S1_Y(0x2) |
1816 S2_X(0xa) | S2_Y(0x6) |
1817 S3_X(0x6) | S3_Y(0xa)));
1818 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1819 S1_X(0x4) | S1_Y(0xc) |
1820 S2_X(0x1) | S2_Y(0x6) |
1821 S3_X(0xa) | S3_Y(0xe)));
1822 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1823 S5_X(0x0) | S5_Y(0x0) |
1824 S6_X(0xb) | S6_Y(0x4) |
1825 S7_X(0x7) | S7_Y(0x8)));
1826
1827 WREG32(VGT_STRMOUT_EN, 0);
1828 tmp = rdev->config.r600.max_pipes * 16;
1829 switch (rdev->family) {
1830 case CHIP_RV610:
1831 case CHIP_RV620:
1832 case CHIP_RS780:
1833 case CHIP_RS880:
1834 tmp += 32;
1835 break;
1836 case CHIP_RV670:
1837 tmp += 128;
1838 break;
1839 default:
1840 break;
1841 }
1842 if (tmp > 256) {
1843 tmp = 256;
1844 }
1845 WREG32(VGT_ES_PER_GS, 128);
1846 WREG32(VGT_GS_PER_ES, tmp);
1847 WREG32(VGT_GS_PER_VS, 2);
1848 WREG32(VGT_GS_VERTEX_REUSE, 16);
1849
1850 /* more default values. 2D/3D driver should adjust as needed */
1851 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1852 WREG32(VGT_STRMOUT_EN, 0);
1853 WREG32(SX_MISC, 0);
1854 WREG32(PA_SC_MODE_CNTL, 0);
1855 WREG32(PA_SC_AA_CONFIG, 0);
1856 WREG32(PA_SC_LINE_STIPPLE, 0);
1857 WREG32(SPI_INPUT_Z, 0);
1858 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1859 WREG32(CB_COLOR7_FRAG, 0);
1860
1861 /* Clear render buffer base addresses */
1862 WREG32(CB_COLOR0_BASE, 0);
1863 WREG32(CB_COLOR1_BASE, 0);
1864 WREG32(CB_COLOR2_BASE, 0);
1865 WREG32(CB_COLOR3_BASE, 0);
1866 WREG32(CB_COLOR4_BASE, 0);
1867 WREG32(CB_COLOR5_BASE, 0);
1868 WREG32(CB_COLOR6_BASE, 0);
1869 WREG32(CB_COLOR7_BASE, 0);
1870 WREG32(CB_COLOR7_FRAG, 0);
1871
1872 switch (rdev->family) {
1873 case CHIP_RV610:
1874 case CHIP_RV620:
1875 case CHIP_RS780:
1876 case CHIP_RS880:
1877 tmp = TC_L2_SIZE(8);
1878 break;
1879 case CHIP_RV630:
1880 case CHIP_RV635:
1881 tmp = TC_L2_SIZE(4);
1882 break;
1883 case CHIP_R600:
1884 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1885 break;
1886 default:
1887 tmp = TC_L2_SIZE(0);
1888 break;
1889 }
1890 WREG32(TC_CNTL, tmp);
1891
1892 tmp = RREG32(HDP_HOST_PATH_CNTL);
1893 WREG32(HDP_HOST_PATH_CNTL, tmp);
1894
1895 tmp = RREG32(ARB_POP);
1896 tmp |= ENABLE_TC128;
1897 WREG32(ARB_POP, tmp);
1898
1899 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1900 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1901 NUM_CLIP_SEQ(3)));
1902 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1903 }
1904
1905
1906 /*
1907 * Indirect registers accessor
1908 */
1909 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1910 {
1911 u32 r;
1912
1913 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1914 (void)RREG32(PCIE_PORT_INDEX);
1915 r = RREG32(PCIE_PORT_DATA);
1916 return r;
1917 }
1918
1919 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1920 {
1921 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1922 (void)RREG32(PCIE_PORT_INDEX);
1923 WREG32(PCIE_PORT_DATA, (v));
1924 (void)RREG32(PCIE_PORT_DATA);
1925 }
1926
1927 /*
1928 * CP & Ring
1929 */
1930 void r600_cp_stop(struct radeon_device *rdev)
1931 {
1932 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1933 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1934 WREG32(SCRATCH_UMSK, 0);
1935 }
1936
1937 int r600_init_microcode(struct radeon_device *rdev)
1938 {
1939 struct platform_device *pdev;
1940 const char *chip_name;
1941 const char *rlc_chip_name;
1942 size_t pfp_req_size, me_req_size, rlc_req_size;
1943 char fw_name[30];
1944 int err;
1945
1946 DRM_DEBUG("\n");
1947
1948 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1949 err = IS_ERR(pdev);
1950 if (err) {
1951 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1952 return -EINVAL;
1953 }
1954
1955 switch (rdev->family) {
1956 case CHIP_R600:
1957 chip_name = "R600";
1958 rlc_chip_name = "R600";
1959 break;
1960 case CHIP_RV610:
1961 chip_name = "RV610";
1962 rlc_chip_name = "R600";
1963 break;
1964 case CHIP_RV630:
1965 chip_name = "RV630";
1966 rlc_chip_name = "R600";
1967 break;
1968 case CHIP_RV620:
1969 chip_name = "RV620";
1970 rlc_chip_name = "R600";
1971 break;
1972 case CHIP_RV635:
1973 chip_name = "RV635";
1974 rlc_chip_name = "R600";
1975 break;
1976 case CHIP_RV670:
1977 chip_name = "RV670";
1978 rlc_chip_name = "R600";
1979 break;
1980 case CHIP_RS780:
1981 case CHIP_RS880:
1982 chip_name = "RS780";
1983 rlc_chip_name = "R600";
1984 break;
1985 case CHIP_RV770:
1986 chip_name = "RV770";
1987 rlc_chip_name = "R700";
1988 break;
1989 case CHIP_RV730:
1990 case CHIP_RV740:
1991 chip_name = "RV730";
1992 rlc_chip_name = "R700";
1993 break;
1994 case CHIP_RV710:
1995 chip_name = "RV710";
1996 rlc_chip_name = "R700";
1997 break;
1998 case CHIP_CEDAR:
1999 chip_name = "CEDAR";
2000 rlc_chip_name = "CEDAR";
2001 break;
2002 case CHIP_REDWOOD:
2003 chip_name = "REDWOOD";
2004 rlc_chip_name = "REDWOOD";
2005 break;
2006 case CHIP_JUNIPER:
2007 chip_name = "JUNIPER";
2008 rlc_chip_name = "JUNIPER";
2009 break;
2010 case CHIP_CYPRESS:
2011 case CHIP_HEMLOCK:
2012 chip_name = "CYPRESS";
2013 rlc_chip_name = "CYPRESS";
2014 break;
2015 case CHIP_PALM:
2016 chip_name = "PALM";
2017 rlc_chip_name = "SUMO";
2018 break;
2019 case CHIP_SUMO:
2020 chip_name = "SUMO";
2021 rlc_chip_name = "SUMO";
2022 break;
2023 case CHIP_SUMO2:
2024 chip_name = "SUMO2";
2025 rlc_chip_name = "SUMO";
2026 break;
2027 default: BUG();
2028 }
2029
2030 if (rdev->family >= CHIP_CEDAR) {
2031 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2032 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2033 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2034 } else if (rdev->family >= CHIP_RV770) {
2035 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2036 me_req_size = R700_PM4_UCODE_SIZE * 4;
2037 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2038 } else {
2039 pfp_req_size = PFP_UCODE_SIZE * 4;
2040 me_req_size = PM4_UCODE_SIZE * 12;
2041 rlc_req_size = RLC_UCODE_SIZE * 4;
2042 }
2043
2044 DRM_INFO("Loading %s Microcode\n", chip_name);
2045
2046 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2047 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2048 if (err)
2049 goto out;
2050 if (rdev->pfp_fw->size != pfp_req_size) {
2051 printk(KERN_ERR
2052 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2053 rdev->pfp_fw->size, fw_name);
2054 err = -EINVAL;
2055 goto out;
2056 }
2057
2058 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2059 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2060 if (err)
2061 goto out;
2062 if (rdev->me_fw->size != me_req_size) {
2063 printk(KERN_ERR
2064 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2065 rdev->me_fw->size, fw_name);
2066 err = -EINVAL;
2067 }
2068
2069 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2070 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2071 if (err)
2072 goto out;
2073 if (rdev->rlc_fw->size != rlc_req_size) {
2074 printk(KERN_ERR
2075 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2076 rdev->rlc_fw->size, fw_name);
2077 err = -EINVAL;
2078 }
2079
2080 out:
2081 platform_device_unregister(pdev);
2082
2083 if (err) {
2084 if (err != -EINVAL)
2085 printk(KERN_ERR
2086 "r600_cp: Failed to load firmware \"%s\"\n",
2087 fw_name);
2088 release_firmware(rdev->pfp_fw);
2089 rdev->pfp_fw = NULL;
2090 release_firmware(rdev->me_fw);
2091 rdev->me_fw = NULL;
2092 release_firmware(rdev->rlc_fw);
2093 rdev->rlc_fw = NULL;
2094 }
2095 return err;
2096 }
2097
2098 static int r600_cp_load_microcode(struct radeon_device *rdev)
2099 {
2100 const __be32 *fw_data;
2101 int i;
2102
2103 if (!rdev->me_fw || !rdev->pfp_fw)
2104 return -EINVAL;
2105
2106 r600_cp_stop(rdev);
2107
2108 WREG32(CP_RB_CNTL,
2109 #ifdef __BIG_ENDIAN
2110 BUF_SWAP_32BIT |
2111 #endif
2112 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2113
2114 /* Reset cp */
2115 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2116 RREG32(GRBM_SOFT_RESET);
2117 mdelay(15);
2118 WREG32(GRBM_SOFT_RESET, 0);
2119
2120 WREG32(CP_ME_RAM_WADDR, 0);
2121
2122 fw_data = (const __be32 *)rdev->me_fw->data;
2123 WREG32(CP_ME_RAM_WADDR, 0);
2124 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2125 WREG32(CP_ME_RAM_DATA,
2126 be32_to_cpup(fw_data++));
2127
2128 fw_data = (const __be32 *)rdev->pfp_fw->data;
2129 WREG32(CP_PFP_UCODE_ADDR, 0);
2130 for (i = 0; i < PFP_UCODE_SIZE; i++)
2131 WREG32(CP_PFP_UCODE_DATA,
2132 be32_to_cpup(fw_data++));
2133
2134 WREG32(CP_PFP_UCODE_ADDR, 0);
2135 WREG32(CP_ME_RAM_WADDR, 0);
2136 WREG32(CP_ME_RAM_RADDR, 0);
2137 return 0;
2138 }
2139
2140 int r600_cp_start(struct radeon_device *rdev)
2141 {
2142 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2143 int r;
2144 uint32_t cp_me;
2145
2146 r = radeon_ring_lock(rdev, ring, 7);
2147 if (r) {
2148 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2149 return r;
2150 }
2151 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2152 radeon_ring_write(ring, 0x1);
2153 if (rdev->family >= CHIP_RV770) {
2154 radeon_ring_write(ring, 0x0);
2155 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2156 } else {
2157 radeon_ring_write(ring, 0x3);
2158 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2159 }
2160 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2161 radeon_ring_write(ring, 0);
2162 radeon_ring_write(ring, 0);
2163 radeon_ring_unlock_commit(rdev, ring);
2164
2165 cp_me = 0xff;
2166 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2167 return 0;
2168 }
2169
2170 int r600_cp_resume(struct radeon_device *rdev)
2171 {
2172 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2173 u32 tmp;
2174 u32 rb_bufsz;
2175 int r;
2176
2177 /* Reset cp */
2178 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2179 RREG32(GRBM_SOFT_RESET);
2180 mdelay(15);
2181 WREG32(GRBM_SOFT_RESET, 0);
2182
2183 /* Set ring buffer size */
2184 rb_bufsz = drm_order(ring->ring_size / 8);
2185 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2186 #ifdef __BIG_ENDIAN
2187 tmp |= BUF_SWAP_32BIT;
2188 #endif
2189 WREG32(CP_RB_CNTL, tmp);
2190 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2191
2192 /* Set the write pointer delay */
2193 WREG32(CP_RB_WPTR_DELAY, 0);
2194
2195 /* Initialize the ring buffer's read and write pointers */
2196 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2197 WREG32(CP_RB_RPTR_WR, 0);
2198 ring->wptr = 0;
2199 WREG32(CP_RB_WPTR, ring->wptr);
2200
2201 /* set the wb address whether it's enabled or not */
2202 WREG32(CP_RB_RPTR_ADDR,
2203 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2204 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2205 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2206
2207 if (rdev->wb.enabled)
2208 WREG32(SCRATCH_UMSK, 0xff);
2209 else {
2210 tmp |= RB_NO_UPDATE;
2211 WREG32(SCRATCH_UMSK, 0);
2212 }
2213
2214 mdelay(1);
2215 WREG32(CP_RB_CNTL, tmp);
2216
2217 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2218 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2219
2220 ring->rptr = RREG32(CP_RB_RPTR);
2221
2222 r600_cp_start(rdev);
2223 ring->ready = true;
2224 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2225 if (r) {
2226 ring->ready = false;
2227 return r;
2228 }
2229 return 0;
2230 }
2231
2232 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2233 {
2234 u32 rb_bufsz;
2235
2236 /* Align ring size */
2237 rb_bufsz = drm_order(ring_size / 8);
2238 ring_size = (1 << (rb_bufsz + 1)) * 4;
2239 ring->ring_size = ring_size;
2240 ring->align_mask = 16 - 1;
2241 }
2242
2243 void r600_cp_fini(struct radeon_device *rdev)
2244 {
2245 r600_cp_stop(rdev);
2246 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2247 }
2248
2249
2250 /*
2251 * GPU scratch registers helpers function.
2252 */
2253 void r600_scratch_init(struct radeon_device *rdev)
2254 {
2255 int i;
2256
2257 rdev->scratch.num_reg = 7;
2258 rdev->scratch.reg_base = SCRATCH_REG0;
2259 for (i = 0; i < rdev->scratch.num_reg; i++) {
2260 rdev->scratch.free[i] = true;
2261 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2262 }
2263 }
2264
2265 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2266 {
2267 uint32_t scratch;
2268 uint32_t tmp = 0;
2269 unsigned i, ridx = radeon_ring_index(rdev, ring);
2270 int r;
2271
2272 r = radeon_scratch_get(rdev, &scratch);
2273 if (r) {
2274 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2275 return r;
2276 }
2277 WREG32(scratch, 0xCAFEDEAD);
2278 r = radeon_ring_lock(rdev, ring, 3);
2279 if (r) {
2280 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
2281 radeon_scratch_free(rdev, scratch);
2282 return r;
2283 }
2284 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2285 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2286 radeon_ring_write(ring, 0xDEADBEEF);
2287 radeon_ring_unlock_commit(rdev, ring);
2288 for (i = 0; i < rdev->usec_timeout; i++) {
2289 tmp = RREG32(scratch);
2290 if (tmp == 0xDEADBEEF)
2291 break;
2292 DRM_UDELAY(1);
2293 }
2294 if (i < rdev->usec_timeout) {
2295 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
2296 } else {
2297 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2298 ridx, scratch, tmp);
2299 r = -EINVAL;
2300 }
2301 radeon_scratch_free(rdev, scratch);
2302 return r;
2303 }
2304
2305 void r600_fence_ring_emit(struct radeon_device *rdev,
2306 struct radeon_fence *fence)
2307 {
2308 struct radeon_ring *ring = &rdev->ring[fence->ring];
2309
2310 if (rdev->wb.use_event) {
2311 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2312 /* flush read cache over gart */
2313 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2314 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2315 PACKET3_VC_ACTION_ENA |
2316 PACKET3_SH_ACTION_ENA);
2317 radeon_ring_write(ring, 0xFFFFFFFF);
2318 radeon_ring_write(ring, 0);
2319 radeon_ring_write(ring, 10); /* poll interval */
2320 /* EVENT_WRITE_EOP - flush caches, send int */
2321 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2322 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2323 radeon_ring_write(ring, addr & 0xffffffff);
2324 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2325 radeon_ring_write(ring, fence->seq);
2326 radeon_ring_write(ring, 0);
2327 } else {
2328 /* flush read cache over gart */
2329 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2330 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2331 PACKET3_VC_ACTION_ENA |
2332 PACKET3_SH_ACTION_ENA);
2333 radeon_ring_write(ring, 0xFFFFFFFF);
2334 radeon_ring_write(ring, 0);
2335 radeon_ring_write(ring, 10); /* poll interval */
2336 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2337 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2338 /* wait for 3D idle clean */
2339 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2340 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2341 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2342 /* Emit fence sequence & fire IRQ */
2343 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2344 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2345 radeon_ring_write(ring, fence->seq);
2346 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2347 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2348 radeon_ring_write(ring, RB_INT_STAT);
2349 }
2350 }
2351
2352 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2353 struct radeon_ring *ring,
2354 struct radeon_semaphore *semaphore,
2355 bool emit_wait)
2356 {
2357 uint64_t addr = semaphore->gpu_addr;
2358 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2359
2360 if (rdev->family < CHIP_CAYMAN)
2361 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2362
2363 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2364 radeon_ring_write(ring, addr & 0xffffffff);
2365 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2366 }
2367
2368 int r600_copy_blit(struct radeon_device *rdev,
2369 uint64_t src_offset,
2370 uint64_t dst_offset,
2371 unsigned num_gpu_pages,
2372 struct radeon_fence *fence)
2373 {
2374 struct radeon_sa_bo *vb = NULL;
2375 int r;
2376
2377 r = r600_blit_prepare_copy(rdev, num_gpu_pages, &vb);
2378 if (r) {
2379 return r;
2380 }
2381 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2382 r600_blit_done_copy(rdev, fence, vb);
2383 return 0;
2384 }
2385
2386 void r600_blit_suspend(struct radeon_device *rdev)
2387 {
2388 int r;
2389
2390 /* unpin shaders bo */
2391 if (rdev->r600_blit.shader_obj) {
2392 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2393 if (!r) {
2394 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2395 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2396 }
2397 }
2398 }
2399
2400 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2401 uint32_t tiling_flags, uint32_t pitch,
2402 uint32_t offset, uint32_t obj_size)
2403 {
2404 /* FIXME: implement */
2405 return 0;
2406 }
2407
2408 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2409 {
2410 /* FIXME: implement */
2411 }
2412
2413 int r600_startup(struct radeon_device *rdev)
2414 {
2415 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2416 int r;
2417
2418 /* enable pcie gen2 link */
2419 r600_pcie_gen2_enable(rdev);
2420
2421 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2422 r = r600_init_microcode(rdev);
2423 if (r) {
2424 DRM_ERROR("Failed to load firmware!\n");
2425 return r;
2426 }
2427 }
2428
2429 r = r600_vram_scratch_init(rdev);
2430 if (r)
2431 return r;
2432
2433 r600_mc_program(rdev);
2434 if (rdev->flags & RADEON_IS_AGP) {
2435 r600_agp_enable(rdev);
2436 } else {
2437 r = r600_pcie_gart_enable(rdev);
2438 if (r)
2439 return r;
2440 }
2441 r600_gpu_init(rdev);
2442 r = r600_blit_init(rdev);
2443 if (r) {
2444 r600_blit_fini(rdev);
2445 rdev->asic->copy.copy = NULL;
2446 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2447 }
2448
2449 /* allocate wb buffer */
2450 r = radeon_wb_init(rdev);
2451 if (r)
2452 return r;
2453
2454 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2455 if (r) {
2456 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2457 return r;
2458 }
2459
2460 /* Enable IRQ */
2461 r = r600_irq_init(rdev);
2462 if (r) {
2463 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2464 radeon_irq_kms_fini(rdev);
2465 return r;
2466 }
2467 r600_irq_set(rdev);
2468
2469 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2470 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2471 0, 0xfffff, RADEON_CP_PACKET2);
2472
2473 if (r)
2474 return r;
2475 r = r600_cp_load_microcode(rdev);
2476 if (r)
2477 return r;
2478 r = r600_cp_resume(rdev);
2479 if (r)
2480 return r;
2481
2482 r = radeon_ib_pool_start(rdev);
2483 if (r)
2484 return r;
2485
2486 r = radeon_ib_ring_tests(rdev);
2487 if (r)
2488 return r;
2489
2490 return 0;
2491 }
2492
2493 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2494 {
2495 uint32_t temp;
2496
2497 temp = RREG32(CONFIG_CNTL);
2498 if (state == false) {
2499 temp &= ~(1<<0);
2500 temp |= (1<<1);
2501 } else {
2502 temp &= ~(1<<1);
2503 }
2504 WREG32(CONFIG_CNTL, temp);
2505 }
2506
2507 int r600_resume(struct radeon_device *rdev)
2508 {
2509 int r;
2510
2511 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2512 * posting will perform necessary task to bring back GPU into good
2513 * shape.
2514 */
2515 /* post card */
2516 atom_asic_init(rdev->mode_info.atom_context);
2517
2518 rdev->accel_working = true;
2519 r = r600_startup(rdev);
2520 if (r) {
2521 DRM_ERROR("r600 startup failed on resume\n");
2522 rdev->accel_working = false;
2523 return r;
2524 }
2525
2526 r = r600_audio_init(rdev);
2527 if (r) {
2528 DRM_ERROR("radeon: audio resume failed\n");
2529 return r;
2530 }
2531
2532 return r;
2533 }
2534
2535 int r600_suspend(struct radeon_device *rdev)
2536 {
2537 r600_audio_fini(rdev);
2538 radeon_ib_pool_suspend(rdev);
2539 r600_blit_suspend(rdev);
2540 /* FIXME: we should wait for ring to be empty */
2541 r600_cp_stop(rdev);
2542 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2543 r600_irq_suspend(rdev);
2544 radeon_wb_disable(rdev);
2545 r600_pcie_gart_disable(rdev);
2546
2547 return 0;
2548 }
2549
2550 /* Plan is to move initialization in that function and use
2551 * helper function so that radeon_device_init pretty much
2552 * do nothing more than calling asic specific function. This
2553 * should also allow to remove a bunch of callback function
2554 * like vram_info.
2555 */
2556 int r600_init(struct radeon_device *rdev)
2557 {
2558 int r;
2559
2560 if (r600_debugfs_mc_info_init(rdev)) {
2561 DRM_ERROR("Failed to register debugfs file for mc !\n");
2562 }
2563 /* Read BIOS */
2564 if (!radeon_get_bios(rdev)) {
2565 if (ASIC_IS_AVIVO(rdev))
2566 return -EINVAL;
2567 }
2568 /* Must be an ATOMBIOS */
2569 if (!rdev->is_atom_bios) {
2570 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2571 return -EINVAL;
2572 }
2573 r = radeon_atombios_init(rdev);
2574 if (r)
2575 return r;
2576 /* Post card if necessary */
2577 if (!radeon_card_posted(rdev)) {
2578 if (!rdev->bios) {
2579 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2580 return -EINVAL;
2581 }
2582 DRM_INFO("GPU not posted. posting now...\n");
2583 atom_asic_init(rdev->mode_info.atom_context);
2584 }
2585 /* Initialize scratch registers */
2586 r600_scratch_init(rdev);
2587 /* Initialize surface registers */
2588 radeon_surface_init(rdev);
2589 /* Initialize clocks */
2590 radeon_get_clock_info(rdev->ddev);
2591 /* Fence driver */
2592 r = radeon_fence_driver_init(rdev);
2593 if (r)
2594 return r;
2595 if (rdev->flags & RADEON_IS_AGP) {
2596 r = radeon_agp_init(rdev);
2597 if (r)
2598 radeon_agp_disable(rdev);
2599 }
2600 r = r600_mc_init(rdev);
2601 if (r)
2602 return r;
2603 /* Memory manager */
2604 r = radeon_bo_init(rdev);
2605 if (r)
2606 return r;
2607
2608 r = radeon_irq_kms_init(rdev);
2609 if (r)
2610 return r;
2611
2612 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2613 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2614
2615 rdev->ih.ring_obj = NULL;
2616 r600_ih_ring_init(rdev, 64 * 1024);
2617
2618 r = r600_pcie_gart_init(rdev);
2619 if (r)
2620 return r;
2621
2622 r = radeon_ib_pool_init(rdev);
2623 rdev->accel_working = true;
2624 if (r) {
2625 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2626 rdev->accel_working = false;
2627 }
2628
2629 r = r600_startup(rdev);
2630 if (r) {
2631 dev_err(rdev->dev, "disabling GPU acceleration\n");
2632 r600_cp_fini(rdev);
2633 r600_irq_fini(rdev);
2634 radeon_wb_fini(rdev);
2635 r100_ib_fini(rdev);
2636 radeon_irq_kms_fini(rdev);
2637 r600_pcie_gart_fini(rdev);
2638 rdev->accel_working = false;
2639 }
2640
2641 r = r600_audio_init(rdev);
2642 if (r)
2643 return r; /* TODO error handling */
2644 return 0;
2645 }
2646
2647 void r600_fini(struct radeon_device *rdev)
2648 {
2649 r600_audio_fini(rdev);
2650 r600_blit_fini(rdev);
2651 r600_cp_fini(rdev);
2652 r600_irq_fini(rdev);
2653 radeon_wb_fini(rdev);
2654 r100_ib_fini(rdev);
2655 radeon_irq_kms_fini(rdev);
2656 r600_pcie_gart_fini(rdev);
2657 r600_vram_scratch_fini(rdev);
2658 radeon_agp_fini(rdev);
2659 radeon_gem_fini(rdev);
2660 radeon_fence_driver_fini(rdev);
2661 radeon_bo_fini(rdev);
2662 radeon_atombios_fini(rdev);
2663 kfree(rdev->bios);
2664 rdev->bios = NULL;
2665 }
2666
2667
2668 /*
2669 * CS stuff
2670 */
2671 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2672 {
2673 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
2674
2675 /* FIXME: implement */
2676 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2677 radeon_ring_write(ring,
2678 #ifdef __BIG_ENDIAN
2679 (2 << 0) |
2680 #endif
2681 (ib->gpu_addr & 0xFFFFFFFC));
2682 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2683 radeon_ring_write(ring, ib->length_dw);
2684 }
2685
2686 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2687 {
2688 struct radeon_ib ib;
2689 uint32_t scratch;
2690 uint32_t tmp = 0;
2691 unsigned i;
2692 int r;
2693 int ring_index = radeon_ring_index(rdev, ring);
2694
2695 r = radeon_scratch_get(rdev, &scratch);
2696 if (r) {
2697 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2698 return r;
2699 }
2700 WREG32(scratch, 0xCAFEDEAD);
2701 r = radeon_ib_get(rdev, ring_index, &ib, 256);
2702 if (r) {
2703 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2704 return r;
2705 }
2706 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2707 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2708 ib.ptr[2] = 0xDEADBEEF;
2709 ib.length_dw = 3;
2710 r = radeon_ib_schedule(rdev, &ib);
2711 if (r) {
2712 radeon_scratch_free(rdev, scratch);
2713 radeon_ib_free(rdev, &ib);
2714 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2715 return r;
2716 }
2717 r = radeon_fence_wait(ib.fence, false);
2718 if (r) {
2719 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2720 return r;
2721 }
2722 for (i = 0; i < rdev->usec_timeout; i++) {
2723 tmp = RREG32(scratch);
2724 if (tmp == 0xDEADBEEF)
2725 break;
2726 DRM_UDELAY(1);
2727 }
2728 if (i < rdev->usec_timeout) {
2729 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
2730 } else {
2731 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2732 scratch, tmp);
2733 r = -EINVAL;
2734 }
2735 radeon_scratch_free(rdev, scratch);
2736 radeon_ib_free(rdev, &ib);
2737 return r;
2738 }
2739
2740 /*
2741 * Interrupts
2742 *
2743 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2744 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2745 * writing to the ring and the GPU consuming, the GPU writes to the ring
2746 * and host consumes. As the host irq handler processes interrupts, it
2747 * increments the rptr. When the rptr catches up with the wptr, all the
2748 * current interrupts have been processed.
2749 */
2750
2751 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2752 {
2753 u32 rb_bufsz;
2754
2755 /* Align ring size */
2756 rb_bufsz = drm_order(ring_size / 4);
2757 ring_size = (1 << rb_bufsz) * 4;
2758 rdev->ih.ring_size = ring_size;
2759 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2760 rdev->ih.rptr = 0;
2761 }
2762
2763 int r600_ih_ring_alloc(struct radeon_device *rdev)
2764 {
2765 int r;
2766
2767 /* Allocate ring buffer */
2768 if (rdev->ih.ring_obj == NULL) {
2769 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2770 PAGE_SIZE, true,
2771 RADEON_GEM_DOMAIN_GTT,
2772 NULL, &rdev->ih.ring_obj);
2773 if (r) {
2774 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2775 return r;
2776 }
2777 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2778 if (unlikely(r != 0))
2779 return r;
2780 r = radeon_bo_pin(rdev->ih.ring_obj,
2781 RADEON_GEM_DOMAIN_GTT,
2782 &rdev->ih.gpu_addr);
2783 if (r) {
2784 radeon_bo_unreserve(rdev->ih.ring_obj);
2785 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2786 return r;
2787 }
2788 r = radeon_bo_kmap(rdev->ih.ring_obj,
2789 (void **)&rdev->ih.ring);
2790 radeon_bo_unreserve(rdev->ih.ring_obj);
2791 if (r) {
2792 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2793 return r;
2794 }
2795 }
2796 return 0;
2797 }
2798
2799 void r600_ih_ring_fini(struct radeon_device *rdev)
2800 {
2801 int r;
2802 if (rdev->ih.ring_obj) {
2803 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2804 if (likely(r == 0)) {
2805 radeon_bo_kunmap(rdev->ih.ring_obj);
2806 radeon_bo_unpin(rdev->ih.ring_obj);
2807 radeon_bo_unreserve(rdev->ih.ring_obj);
2808 }
2809 radeon_bo_unref(&rdev->ih.ring_obj);
2810 rdev->ih.ring = NULL;
2811 rdev->ih.ring_obj = NULL;
2812 }
2813 }
2814
2815 void r600_rlc_stop(struct radeon_device *rdev)
2816 {
2817
2818 if ((rdev->family >= CHIP_RV770) &&
2819 (rdev->family <= CHIP_RV740)) {
2820 /* r7xx asics need to soft reset RLC before halting */
2821 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2822 RREG32(SRBM_SOFT_RESET);
2823 mdelay(15);
2824 WREG32(SRBM_SOFT_RESET, 0);
2825 RREG32(SRBM_SOFT_RESET);
2826 }
2827
2828 WREG32(RLC_CNTL, 0);
2829 }
2830
2831 static void r600_rlc_start(struct radeon_device *rdev)
2832 {
2833 WREG32(RLC_CNTL, RLC_ENABLE);
2834 }
2835
2836 static int r600_rlc_init(struct radeon_device *rdev)
2837 {
2838 u32 i;
2839 const __be32 *fw_data;
2840
2841 if (!rdev->rlc_fw)
2842 return -EINVAL;
2843
2844 r600_rlc_stop(rdev);
2845
2846 WREG32(RLC_HB_CNTL, 0);
2847
2848 if (rdev->family == CHIP_ARUBA) {
2849 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2850 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2851 }
2852 if (rdev->family <= CHIP_CAYMAN) {
2853 WREG32(RLC_HB_BASE, 0);
2854 WREG32(RLC_HB_RPTR, 0);
2855 WREG32(RLC_HB_WPTR, 0);
2856 }
2857 if (rdev->family <= CHIP_CAICOS) {
2858 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2859 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2860 }
2861 WREG32(RLC_MC_CNTL, 0);
2862 WREG32(RLC_UCODE_CNTL, 0);
2863
2864 fw_data = (const __be32 *)rdev->rlc_fw->data;
2865 if (rdev->family >= CHIP_ARUBA) {
2866 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
2867 WREG32(RLC_UCODE_ADDR, i);
2868 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2869 }
2870 } else if (rdev->family >= CHIP_CAYMAN) {
2871 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2872 WREG32(RLC_UCODE_ADDR, i);
2873 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2874 }
2875 } else if (rdev->family >= CHIP_CEDAR) {
2876 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2877 WREG32(RLC_UCODE_ADDR, i);
2878 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2879 }
2880 } else if (rdev->family >= CHIP_RV770) {
2881 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2882 WREG32(RLC_UCODE_ADDR, i);
2883 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2884 }
2885 } else {
2886 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2887 WREG32(RLC_UCODE_ADDR, i);
2888 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2889 }
2890 }
2891 WREG32(RLC_UCODE_ADDR, 0);
2892
2893 r600_rlc_start(rdev);
2894
2895 return 0;
2896 }
2897
2898 static void r600_enable_interrupts(struct radeon_device *rdev)
2899 {
2900 u32 ih_cntl = RREG32(IH_CNTL);
2901 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2902
2903 ih_cntl |= ENABLE_INTR;
2904 ih_rb_cntl |= IH_RB_ENABLE;
2905 WREG32(IH_CNTL, ih_cntl);
2906 WREG32(IH_RB_CNTL, ih_rb_cntl);
2907 rdev->ih.enabled = true;
2908 }
2909
2910 void r600_disable_interrupts(struct radeon_device *rdev)
2911 {
2912 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2913 u32 ih_cntl = RREG32(IH_CNTL);
2914
2915 ih_rb_cntl &= ~IH_RB_ENABLE;
2916 ih_cntl &= ~ENABLE_INTR;
2917 WREG32(IH_RB_CNTL, ih_rb_cntl);
2918 WREG32(IH_CNTL, ih_cntl);
2919 /* set rptr, wptr to 0 */
2920 WREG32(IH_RB_RPTR, 0);
2921 WREG32(IH_RB_WPTR, 0);
2922 rdev->ih.enabled = false;
2923 rdev->ih.wptr = 0;
2924 rdev->ih.rptr = 0;
2925 }
2926
2927 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2928 {
2929 u32 tmp;
2930
2931 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2932 WREG32(GRBM_INT_CNTL, 0);
2933 WREG32(DxMODE_INT_MASK, 0);
2934 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2935 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2936 if (ASIC_IS_DCE3(rdev)) {
2937 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2938 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2939 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2940 WREG32(DC_HPD1_INT_CONTROL, tmp);
2941 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2942 WREG32(DC_HPD2_INT_CONTROL, tmp);
2943 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2944 WREG32(DC_HPD3_INT_CONTROL, tmp);
2945 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2946 WREG32(DC_HPD4_INT_CONTROL, tmp);
2947 if (ASIC_IS_DCE32(rdev)) {
2948 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2949 WREG32(DC_HPD5_INT_CONTROL, tmp);
2950 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2951 WREG32(DC_HPD6_INT_CONTROL, tmp);
2952 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2953 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
2954 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2955 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
2956 } else {
2957 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2958 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2959 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2960 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
2961 }
2962 } else {
2963 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2964 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2965 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2966 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2967 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2968 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2969 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2970 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2971 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2972 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
2973 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
2974 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
2975 }
2976 }
2977
2978 int r600_irq_init(struct radeon_device *rdev)
2979 {
2980 int ret = 0;
2981 int rb_bufsz;
2982 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2983
2984 /* allocate ring */
2985 ret = r600_ih_ring_alloc(rdev);
2986 if (ret)
2987 return ret;
2988
2989 /* disable irqs */
2990 r600_disable_interrupts(rdev);
2991
2992 /* init rlc */
2993 ret = r600_rlc_init(rdev);
2994 if (ret) {
2995 r600_ih_ring_fini(rdev);
2996 return ret;
2997 }
2998
2999 /* setup interrupt control */
3000 /* set dummy read address to ring address */
3001 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3002 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3003 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3004 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3005 */
3006 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3007 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3008 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3009 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3010
3011 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3012 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3013
3014 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3015 IH_WPTR_OVERFLOW_CLEAR |
3016 (rb_bufsz << 1));
3017
3018 if (rdev->wb.enabled)
3019 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3020
3021 /* set the writeback address whether it's enabled or not */
3022 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3023 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3024
3025 WREG32(IH_RB_CNTL, ih_rb_cntl);
3026
3027 /* set rptr, wptr to 0 */
3028 WREG32(IH_RB_RPTR, 0);
3029 WREG32(IH_RB_WPTR, 0);
3030
3031 /* Default settings for IH_CNTL (disabled at first) */
3032 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3033 /* RPTR_REARM only works if msi's are enabled */
3034 if (rdev->msi_enabled)
3035 ih_cntl |= RPTR_REARM;
3036 WREG32(IH_CNTL, ih_cntl);
3037
3038 /* force the active interrupt state to all disabled */
3039 if (rdev->family >= CHIP_CEDAR)
3040 evergreen_disable_interrupt_state(rdev);
3041 else
3042 r600_disable_interrupt_state(rdev);
3043
3044 /* at this point everything should be setup correctly to enable master */
3045 pci_set_master(rdev->pdev);
3046
3047 /* enable irqs */
3048 r600_enable_interrupts(rdev);
3049
3050 return ret;
3051 }
3052
3053 void r600_irq_suspend(struct radeon_device *rdev)
3054 {
3055 r600_irq_disable(rdev);
3056 r600_rlc_stop(rdev);
3057 }
3058
3059 void r600_irq_fini(struct radeon_device *rdev)
3060 {
3061 r600_irq_suspend(rdev);
3062 r600_ih_ring_fini(rdev);
3063 }
3064
3065 int r600_irq_set(struct radeon_device *rdev)
3066 {
3067 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3068 u32 mode_int = 0;
3069 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3070 u32 grbm_int_cntl = 0;
3071 u32 hdmi0, hdmi1;
3072 u32 d1grph = 0, d2grph = 0;
3073
3074 if (!rdev->irq.installed) {
3075 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3076 return -EINVAL;
3077 }
3078 /* don't enable anything if the ih is disabled */
3079 if (!rdev->ih.enabled) {
3080 r600_disable_interrupts(rdev);
3081 /* force the active interrupt state to all disabled */
3082 r600_disable_interrupt_state(rdev);
3083 return 0;
3084 }
3085
3086 if (ASIC_IS_DCE3(rdev)) {
3087 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3088 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3089 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3090 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3091 if (ASIC_IS_DCE32(rdev)) {
3092 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3093 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3094 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3095 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3096 } else {
3097 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3098 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3099 }
3100 } else {
3101 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3102 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3103 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3104 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3105 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3106 }
3107
3108 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3109 DRM_DEBUG("r600_irq_set: sw int\n");
3110 cp_int_cntl |= RB_INT_ENABLE;
3111 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3112 }
3113 if (rdev->irq.crtc_vblank_int[0] ||
3114 rdev->irq.pflip[0]) {
3115 DRM_DEBUG("r600_irq_set: vblank 0\n");
3116 mode_int |= D1MODE_VBLANK_INT_MASK;
3117 }
3118 if (rdev->irq.crtc_vblank_int[1] ||
3119 rdev->irq.pflip[1]) {
3120 DRM_DEBUG("r600_irq_set: vblank 1\n");
3121 mode_int |= D2MODE_VBLANK_INT_MASK;
3122 }
3123 if (rdev->irq.hpd[0]) {
3124 DRM_DEBUG("r600_irq_set: hpd 1\n");
3125 hpd1 |= DC_HPDx_INT_EN;
3126 }
3127 if (rdev->irq.hpd[1]) {
3128 DRM_DEBUG("r600_irq_set: hpd 2\n");
3129 hpd2 |= DC_HPDx_INT_EN;
3130 }
3131 if (rdev->irq.hpd[2]) {
3132 DRM_DEBUG("r600_irq_set: hpd 3\n");
3133 hpd3 |= DC_HPDx_INT_EN;
3134 }
3135 if (rdev->irq.hpd[3]) {
3136 DRM_DEBUG("r600_irq_set: hpd 4\n");
3137 hpd4 |= DC_HPDx_INT_EN;
3138 }
3139 if (rdev->irq.hpd[4]) {
3140 DRM_DEBUG("r600_irq_set: hpd 5\n");
3141 hpd5 |= DC_HPDx_INT_EN;
3142 }
3143 if (rdev->irq.hpd[5]) {
3144 DRM_DEBUG("r600_irq_set: hpd 6\n");
3145 hpd6 |= DC_HPDx_INT_EN;
3146 }
3147 if (rdev->irq.afmt[0]) {
3148 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3149 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3150 }
3151 if (rdev->irq.afmt[1]) {
3152 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3153 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3154 }
3155 if (rdev->irq.gui_idle) {
3156 DRM_DEBUG("gui idle\n");
3157 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3158 }
3159
3160 WREG32(CP_INT_CNTL, cp_int_cntl);
3161 WREG32(DxMODE_INT_MASK, mode_int);
3162 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3163 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3164 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3165 if (ASIC_IS_DCE3(rdev)) {
3166 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3167 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3168 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3169 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3170 if (ASIC_IS_DCE32(rdev)) {
3171 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3172 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3173 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3174 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3175 } else {
3176 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3177 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3178 }
3179 } else {
3180 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3181 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3182 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3183 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3184 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3185 }
3186
3187 return 0;
3188 }
3189
3190 static void r600_irq_ack(struct radeon_device *rdev)
3191 {
3192 u32 tmp;
3193
3194 if (ASIC_IS_DCE3(rdev)) {
3195 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3196 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3197 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3198 if (ASIC_IS_DCE32(rdev)) {
3199 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3200 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3201 } else {
3202 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3203 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3204 }
3205 } else {
3206 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3207 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3208 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3209 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3210 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3211 }
3212 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3213 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3214
3215 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3216 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3217 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3218 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3219 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3220 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3221 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3222 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3223 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3224 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3225 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3226 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3227 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3228 if (ASIC_IS_DCE3(rdev)) {
3229 tmp = RREG32(DC_HPD1_INT_CONTROL);
3230 tmp |= DC_HPDx_INT_ACK;
3231 WREG32(DC_HPD1_INT_CONTROL, tmp);
3232 } else {
3233 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3234 tmp |= DC_HPDx_INT_ACK;
3235 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3236 }
3237 }
3238 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3239 if (ASIC_IS_DCE3(rdev)) {
3240 tmp = RREG32(DC_HPD2_INT_CONTROL);
3241 tmp |= DC_HPDx_INT_ACK;
3242 WREG32(DC_HPD2_INT_CONTROL, tmp);
3243 } else {
3244 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3245 tmp |= DC_HPDx_INT_ACK;
3246 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3247 }
3248 }
3249 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3250 if (ASIC_IS_DCE3(rdev)) {
3251 tmp = RREG32(DC_HPD3_INT_CONTROL);
3252 tmp |= DC_HPDx_INT_ACK;
3253 WREG32(DC_HPD3_INT_CONTROL, tmp);
3254 } else {
3255 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3256 tmp |= DC_HPDx_INT_ACK;
3257 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3258 }
3259 }
3260 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3261 tmp = RREG32(DC_HPD4_INT_CONTROL);
3262 tmp |= DC_HPDx_INT_ACK;
3263 WREG32(DC_HPD4_INT_CONTROL, tmp);
3264 }
3265 if (ASIC_IS_DCE32(rdev)) {
3266 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3267 tmp = RREG32(DC_HPD5_INT_CONTROL);
3268 tmp |= DC_HPDx_INT_ACK;
3269 WREG32(DC_HPD5_INT_CONTROL, tmp);
3270 }
3271 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3272 tmp = RREG32(DC_HPD5_INT_CONTROL);
3273 tmp |= DC_HPDx_INT_ACK;
3274 WREG32(DC_HPD6_INT_CONTROL, tmp);
3275 }
3276 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3277 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3278 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3279 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3280 }
3281 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3282 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3283 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3284 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3285 }
3286 } else {
3287 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3288 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3289 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3290 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3291 }
3292 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3293 if (ASIC_IS_DCE3(rdev)) {
3294 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3295 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3296 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3297 } else {
3298 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3299 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3300 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3301 }
3302 }
3303 }
3304 }
3305
3306 void r600_irq_disable(struct radeon_device *rdev)
3307 {
3308 r600_disable_interrupts(rdev);
3309 /* Wait and acknowledge irq */
3310 mdelay(1);
3311 r600_irq_ack(rdev);
3312 r600_disable_interrupt_state(rdev);
3313 }
3314
3315 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3316 {
3317 u32 wptr, tmp;
3318
3319 if (rdev->wb.enabled)
3320 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3321 else
3322 wptr = RREG32(IH_RB_WPTR);
3323
3324 if (wptr & RB_OVERFLOW) {
3325 /* When a ring buffer overflow happen start parsing interrupt
3326 * from the last not overwritten vector (wptr + 16). Hopefully
3327 * this should allow us to catchup.
3328 */
3329 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3330 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3331 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3332 tmp = RREG32(IH_RB_CNTL);
3333 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3334 WREG32(IH_RB_CNTL, tmp);
3335 }
3336 return (wptr & rdev->ih.ptr_mask);
3337 }
3338
3339 /* r600 IV Ring
3340 * Each IV ring entry is 128 bits:
3341 * [7:0] - interrupt source id
3342 * [31:8] - reserved
3343 * [59:32] - interrupt source data
3344 * [127:60] - reserved
3345 *
3346 * The basic interrupt vector entries
3347 * are decoded as follows:
3348 * src_id src_data description
3349 * 1 0 D1 Vblank
3350 * 1 1 D1 Vline
3351 * 5 0 D2 Vblank
3352 * 5 1 D2 Vline
3353 * 19 0 FP Hot plug detection A
3354 * 19 1 FP Hot plug detection B
3355 * 19 2 DAC A auto-detection
3356 * 19 3 DAC B auto-detection
3357 * 21 4 HDMI block A
3358 * 21 5 HDMI block B
3359 * 176 - CP_INT RB
3360 * 177 - CP_INT IB1
3361 * 178 - CP_INT IB2
3362 * 181 - EOP Interrupt
3363 * 233 - GUI Idle
3364 *
3365 * Note, these are based on r600 and may need to be
3366 * adjusted or added to on newer asics
3367 */
3368
3369 int r600_irq_process(struct radeon_device *rdev)
3370 {
3371 u32 wptr;
3372 u32 rptr;
3373 u32 src_id, src_data;
3374 u32 ring_index;
3375 unsigned long flags;
3376 bool queue_hotplug = false;
3377 bool queue_hdmi = false;
3378
3379 if (!rdev->ih.enabled || rdev->shutdown)
3380 return IRQ_NONE;
3381
3382 /* No MSIs, need a dummy read to flush PCI DMAs */
3383 if (!rdev->msi_enabled)
3384 RREG32(IH_RB_WPTR);
3385
3386 wptr = r600_get_ih_wptr(rdev);
3387 rptr = rdev->ih.rptr;
3388 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3389
3390 spin_lock_irqsave(&rdev->ih.lock, flags);
3391
3392 if (rptr == wptr) {
3393 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3394 return IRQ_NONE;
3395 }
3396
3397 restart_ih:
3398 /* Order reading of wptr vs. reading of IH ring data */
3399 rmb();
3400
3401 /* display interrupts */
3402 r600_irq_ack(rdev);
3403
3404 rdev->ih.wptr = wptr;
3405 while (rptr != wptr) {
3406 /* wptr/rptr are in bytes! */
3407 ring_index = rptr / 4;
3408 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3409 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3410
3411 switch (src_id) {
3412 case 1: /* D1 vblank/vline */
3413 switch (src_data) {
3414 case 0: /* D1 vblank */
3415 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3416 if (rdev->irq.crtc_vblank_int[0]) {
3417 drm_handle_vblank(rdev->ddev, 0);
3418 rdev->pm.vblank_sync = true;
3419 wake_up(&rdev->irq.vblank_queue);
3420 }
3421 if (rdev->irq.pflip[0])
3422 radeon_crtc_handle_flip(rdev, 0);
3423 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3424 DRM_DEBUG("IH: D1 vblank\n");
3425 }
3426 break;
3427 case 1: /* D1 vline */
3428 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3429 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3430 DRM_DEBUG("IH: D1 vline\n");
3431 }
3432 break;
3433 default:
3434 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3435 break;
3436 }
3437 break;
3438 case 5: /* D2 vblank/vline */
3439 switch (src_data) {
3440 case 0: /* D2 vblank */
3441 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3442 if (rdev->irq.crtc_vblank_int[1]) {
3443 drm_handle_vblank(rdev->ddev, 1);
3444 rdev->pm.vblank_sync = true;
3445 wake_up(&rdev->irq.vblank_queue);
3446 }
3447 if (rdev->irq.pflip[1])
3448 radeon_crtc_handle_flip(rdev, 1);
3449 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3450 DRM_DEBUG("IH: D2 vblank\n");
3451 }
3452 break;
3453 case 1: /* D1 vline */
3454 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3455 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3456 DRM_DEBUG("IH: D2 vline\n");
3457 }
3458 break;
3459 default:
3460 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3461 break;
3462 }
3463 break;
3464 case 19: /* HPD/DAC hotplug */
3465 switch (src_data) {
3466 case 0:
3467 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3468 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3469 queue_hotplug = true;
3470 DRM_DEBUG("IH: HPD1\n");
3471 }
3472 break;
3473 case 1:
3474 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3475 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3476 queue_hotplug = true;
3477 DRM_DEBUG("IH: HPD2\n");
3478 }
3479 break;
3480 case 4:
3481 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3482 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3483 queue_hotplug = true;
3484 DRM_DEBUG("IH: HPD3\n");
3485 }
3486 break;
3487 case 5:
3488 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3489 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3490 queue_hotplug = true;
3491 DRM_DEBUG("IH: HPD4\n");
3492 }
3493 break;
3494 case 10:
3495 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3496 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3497 queue_hotplug = true;
3498 DRM_DEBUG("IH: HPD5\n");
3499 }
3500 break;
3501 case 12:
3502 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3503 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3504 queue_hotplug = true;
3505 DRM_DEBUG("IH: HPD6\n");
3506 }
3507 break;
3508 default:
3509 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3510 break;
3511 }
3512 break;
3513 case 21: /* hdmi */
3514 switch (src_data) {
3515 case 4:
3516 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3517 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3518 queue_hdmi = true;
3519 DRM_DEBUG("IH: HDMI0\n");
3520 }
3521 break;
3522 case 5:
3523 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3524 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3525 queue_hdmi = true;
3526 DRM_DEBUG("IH: HDMI1\n");
3527 }
3528 break;
3529 default:
3530 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3531 break;
3532 }
3533 break;
3534 case 176: /* CP_INT in ring buffer */
3535 case 177: /* CP_INT in IB1 */
3536 case 178: /* CP_INT in IB2 */
3537 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3538 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3539 break;
3540 case 181: /* CP EOP event */
3541 DRM_DEBUG("IH: CP EOP\n");
3542 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3543 break;
3544 case 233: /* GUI IDLE */
3545 DRM_DEBUG("IH: GUI idle\n");
3546 rdev->pm.gui_idle = true;
3547 wake_up(&rdev->irq.idle_queue);
3548 break;
3549 default:
3550 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3551 break;
3552 }
3553
3554 /* wptr/rptr are in bytes! */
3555 rptr += 16;
3556 rptr &= rdev->ih.ptr_mask;
3557 }
3558 /* make sure wptr hasn't changed while processing */
3559 wptr = r600_get_ih_wptr(rdev);
3560 if (wptr != rdev->ih.wptr)
3561 goto restart_ih;
3562 if (queue_hotplug)
3563 schedule_work(&rdev->hotplug_work);
3564 if (queue_hdmi)
3565 schedule_work(&rdev->audio_work);
3566 rdev->ih.rptr = rptr;
3567 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3568 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3569 return IRQ_HANDLED;
3570 }
3571
3572 /*
3573 * Debugfs info
3574 */
3575 #if defined(CONFIG_DEBUG_FS)
3576
3577 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3578 {
3579 struct drm_info_node *node = (struct drm_info_node *) m->private;
3580 struct drm_device *dev = node->minor->dev;
3581 struct radeon_device *rdev = dev->dev_private;
3582
3583 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3584 DREG32_SYS(m, rdev, VM_L2_STATUS);
3585 return 0;
3586 }
3587
3588 static struct drm_info_list r600_mc_info_list[] = {
3589 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3590 };
3591 #endif
3592
3593 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3594 {
3595 #if defined(CONFIG_DEBUG_FS)
3596 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3597 #else
3598 return 0;
3599 #endif
3600 }
3601
3602 /**
3603 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3604 * rdev: radeon device structure
3605 * bo: buffer object struct which userspace is waiting for idle
3606 *
3607 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3608 * through ring buffer, this leads to corruption in rendering, see
3609 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3610 * directly perform HDP flush by writing register through MMIO.
3611 */
3612 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3613 {
3614 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3615 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3616 * This seems to cause problems on some AGP cards. Just use the old
3617 * method for them.
3618 */
3619 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3620 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3621 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3622 u32 tmp;
3623
3624 WREG32(HDP_DEBUG1, 0);
3625 tmp = readl((void __iomem *)ptr);
3626 } else
3627 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3628 }
3629
3630 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3631 {
3632 u32 link_width_cntl, mask, target_reg;
3633
3634 if (rdev->flags & RADEON_IS_IGP)
3635 return;
3636
3637 if (!(rdev->flags & RADEON_IS_PCIE))
3638 return;
3639
3640 /* x2 cards have a special sequence */
3641 if (ASIC_IS_X2(rdev))
3642 return;
3643
3644 /* FIXME wait for idle */
3645
3646 switch (lanes) {
3647 case 0:
3648 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3649 break;
3650 case 1:
3651 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3652 break;
3653 case 2:
3654 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3655 break;
3656 case 4:
3657 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3658 break;
3659 case 8:
3660 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3661 break;
3662 case 12:
3663 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3664 break;
3665 case 16:
3666 default:
3667 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3668 break;
3669 }
3670
3671 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3672
3673 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3674 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3675 return;
3676
3677 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3678 return;
3679
3680 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3681 RADEON_PCIE_LC_RECONFIG_NOW |
3682 R600_PCIE_LC_RENEGOTIATE_EN |
3683 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3684 link_width_cntl |= mask;
3685
3686 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3687
3688 /* some northbridges can renegotiate the link rather than requiring
3689 * a complete re-config.
3690 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3691 */
3692 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3693 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3694 else
3695 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3696
3697 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3698 RADEON_PCIE_LC_RECONFIG_NOW));
3699
3700 if (rdev->family >= CHIP_RV770)
3701 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3702 else
3703 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3704
3705 /* wait for lane set to complete */
3706 link_width_cntl = RREG32(target_reg);
3707 while (link_width_cntl == 0xffffffff)
3708 link_width_cntl = RREG32(target_reg);
3709
3710 }
3711
3712 int r600_get_pcie_lanes(struct radeon_device *rdev)
3713 {
3714 u32 link_width_cntl;
3715
3716 if (rdev->flags & RADEON_IS_IGP)
3717 return 0;
3718
3719 if (!(rdev->flags & RADEON_IS_PCIE))
3720 return 0;
3721
3722 /* x2 cards have a special sequence */
3723 if (ASIC_IS_X2(rdev))
3724 return 0;
3725
3726 /* FIXME wait for idle */
3727
3728 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3729
3730 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3731 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3732 return 0;
3733 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3734 return 1;
3735 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3736 return 2;
3737 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3738 return 4;
3739 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3740 return 8;
3741 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3742 default:
3743 return 16;
3744 }
3745 }
3746
3747 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3748 {
3749 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3750 u16 link_cntl2;
3751
3752 if (radeon_pcie_gen2 == 0)
3753 return;
3754
3755 if (rdev->flags & RADEON_IS_IGP)
3756 return;
3757
3758 if (!(rdev->flags & RADEON_IS_PCIE))
3759 return;
3760
3761 /* x2 cards have a special sequence */
3762 if (ASIC_IS_X2(rdev))
3763 return;
3764
3765 /* only RV6xx+ chips are supported */
3766 if (rdev->family <= CHIP_R600)
3767 return;
3768
3769 /* 55 nm r6xx asics */
3770 if ((rdev->family == CHIP_RV670) ||
3771 (rdev->family == CHIP_RV620) ||
3772 (rdev->family == CHIP_RV635)) {
3773 /* advertise upconfig capability */
3774 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3775 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3776 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3777 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3778 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3779 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3780 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3781 LC_RECONFIG_ARC_MISSING_ESCAPE);
3782 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3783 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3784 } else {
3785 link_width_cntl |= LC_UPCONFIGURE_DIS;
3786 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3787 }
3788 }
3789
3790 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3791 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3792 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3793
3794 /* 55 nm r6xx asics */
3795 if ((rdev->family == CHIP_RV670) ||
3796 (rdev->family == CHIP_RV620) ||
3797 (rdev->family == CHIP_RV635)) {
3798 WREG32(MM_CFGREGS_CNTL, 0x8);
3799 link_cntl2 = RREG32(0x4088);
3800 WREG32(MM_CFGREGS_CNTL, 0);
3801 /* not supported yet */
3802 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3803 return;
3804 }
3805
3806 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3807 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3808 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3809 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3810 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3811 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3812
3813 tmp = RREG32(0x541c);
3814 WREG32(0x541c, tmp | 0x8);
3815 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3816 link_cntl2 = RREG16(0x4088);
3817 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3818 link_cntl2 |= 0x2;
3819 WREG16(0x4088, link_cntl2);
3820 WREG32(MM_CFGREGS_CNTL, 0);
3821
3822 if ((rdev->family == CHIP_RV670) ||
3823 (rdev->family == CHIP_RV620) ||
3824 (rdev->family == CHIP_RV635)) {
3825 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3826 training_cntl &= ~LC_POINT_7_PLUS_EN;
3827 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3828 } else {
3829 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3830 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3831 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3832 }
3833
3834 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3835 speed_cntl |= LC_GEN2_EN_STRAP;
3836 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3837
3838 } else {
3839 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3840 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3841 if (1)
3842 link_width_cntl |= LC_UPCONFIGURE_DIS;
3843 else
3844 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3845 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3846 }
3847 }
Linux kernel - Deliverables
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