2 * Copyright 2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
26 * ------------------------ This file is DEPRECATED! -------------------------
29 #include <drm/radeon_drm.h>
30 #include "radeon_drv.h"
32 #include "r600_blit_shaders.h"
34 #define DI_PT_RECTLIST 0x11
35 #define DI_INDEX_SIZE_16_BIT 0x0
36 #define DI_SRC_SEL_AUTO_INDEX 0x2
40 #define FMT_8_8_8_8 0x1a
42 #define COLOR_5_6_5 0x8
43 #define COLOR_8_8_8_8 0x1a
46 set_render_target(drm_radeon_private_t
*dev_priv
, int format
, int w
, int h
, u64 gpu_addr
)
57 cb_color_info
= ((format
<< 2) | (1 << 27));
59 slice
= ((w
* h
) / 64) - 1;
61 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_R600
) &&
62 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_RV770
)) {
64 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
65 OUT_RING((R600_CB_COLOR0_BASE
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
66 OUT_RING(gpu_addr
>> 8);
67 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE
, 0));
71 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
72 OUT_RING((R600_CB_COLOR0_BASE
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
73 OUT_RING(gpu_addr
>> 8);
76 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
77 OUT_RING((R600_CB_COLOR0_SIZE
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
78 OUT_RING((pitch
<< 0) | (slice
<< 10));
80 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
81 OUT_RING((R600_CB_COLOR0_VIEW
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
84 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
85 OUT_RING((R600_CB_COLOR0_INFO
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
86 OUT_RING(cb_color_info
);
88 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
89 OUT_RING((R600_CB_COLOR0_TILE
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
92 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
93 OUT_RING((R600_CB_COLOR0_FRAG
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
96 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
97 OUT_RING((R600_CB_COLOR0_MASK
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
104 cp_set_surface_sync(drm_radeon_private_t
*dev_priv
,
105 u32 sync_type
, u32 size
, u64 mc_addr
)
111 if (size
== 0xffffffff)
112 cp_coher_size
= 0xffffffff;
114 cp_coher_size
= ((size
+ 255) >> 8);
117 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC
, 3));
119 OUT_RING(cp_coher_size
);
120 OUT_RING((mc_addr
>> 8));
121 OUT_RING(10); /* poll interval */
126 set_shaders(struct drm_device
*dev
)
128 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
132 uint32_t sq_pgm_resources
;
137 vs
= (u32
*) ((char *)dev
->agp_buffer_map
->handle
+ dev_priv
->blit_vb
->offset
);
138 ps
= (u32
*) ((char *)dev
->agp_buffer_map
->handle
+ dev_priv
->blit_vb
->offset
+ 256);
140 for (i
= 0; i
< r6xx_vs_size
; i
++)
141 vs
[i
] = cpu_to_le32(r6xx_vs
[i
]);
142 for (i
= 0; i
< r6xx_ps_size
; i
++)
143 ps
[i
] = cpu_to_le32(r6xx_ps
[i
]);
145 dev_priv
->blit_vb
->used
= 512;
147 gpu_addr
= dev_priv
->gart_buffers_offset
+ dev_priv
->blit_vb
->offset
;
149 /* setup shader regs */
150 sq_pgm_resources
= (1 << 0);
154 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
155 OUT_RING((R600_SQ_PGM_START_VS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
156 OUT_RING(gpu_addr
>> 8);
158 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
159 OUT_RING((R600_SQ_PGM_RESOURCES_VS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
160 OUT_RING(sq_pgm_resources
);
162 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
163 OUT_RING((R600_SQ_PGM_CF_OFFSET_VS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
167 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
168 OUT_RING((R600_SQ_PGM_START_PS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
169 OUT_RING((gpu_addr
+ 256) >> 8);
171 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
172 OUT_RING((R600_SQ_PGM_RESOURCES_PS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
173 OUT_RING(sq_pgm_resources
| (1 << 28));
175 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
176 OUT_RING((R600_SQ_PGM_EXPORTS_PS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
179 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 1));
180 OUT_RING((R600_SQ_PGM_CF_OFFSET_PS
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
184 cp_set_surface_sync(dev_priv
,
185 R600_SH_ACTION_ENA
, 512, gpu_addr
);
189 set_vtx_resource(drm_radeon_private_t
*dev_priv
, u64 gpu_addr
)
191 uint32_t sq_vtx_constant_word2
;
195 sq_vtx_constant_word2
= (((gpu_addr
>> 32) & 0xff) | (16 << 8));
197 sq_vtx_constant_word2
|= (2 << 30);
201 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
203 OUT_RING(gpu_addr
& 0xffffffff);
205 OUT_RING(sq_vtx_constant_word2
);
209 OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER
<< 30);
212 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
213 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
214 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
215 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
) ||
216 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
))
217 cp_set_surface_sync(dev_priv
,
218 R600_TC_ACTION_ENA
, 48, gpu_addr
);
220 cp_set_surface_sync(dev_priv
,
221 R600_VC_ACTION_ENA
, 48, gpu_addr
);
225 set_tex_resource(drm_radeon_private_t
*dev_priv
,
226 int format
, int w
, int h
, int pitch
, u64 gpu_addr
)
228 uint32_t sq_tex_resource_word0
, sq_tex_resource_word1
, sq_tex_resource_word4
;
235 sq_tex_resource_word0
= (1 << 0);
236 sq_tex_resource_word0
|= ((((pitch
>> 3) - 1) << 8) |
239 sq_tex_resource_word1
= (format
<< 26);
240 sq_tex_resource_word1
|= ((h
- 1) << 0);
242 sq_tex_resource_word4
= ((1 << 14) |
249 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
251 OUT_RING(sq_tex_resource_word0
);
252 OUT_RING(sq_tex_resource_word1
);
253 OUT_RING(gpu_addr
>> 8);
254 OUT_RING(gpu_addr
>> 8);
255 OUT_RING(sq_tex_resource_word4
);
257 OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE
<< 30);
263 set_scissors(drm_radeon_private_t
*dev_priv
, int x1
, int y1
, int x2
, int y2
)
269 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 2));
270 OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
271 OUT_RING((x1
<< 0) | (y1
<< 16));
272 OUT_RING((x2
<< 0) | (y2
<< 16));
274 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 2));
275 OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
276 OUT_RING((x1
<< 0) | (y1
<< 16) | (1 << 31));
277 OUT_RING((x2
<< 0) | (y2
<< 16));
279 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG
, 2));
280 OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL
- R600_SET_CONTEXT_REG_OFFSET
) >> 2);
281 OUT_RING((x1
<< 0) | (y1
<< 16) | (1 << 31));
282 OUT_RING((x2
<< 0) | (y2
<< 16));
287 draw_auto(drm_radeon_private_t
*dev_priv
)
293 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
294 OUT_RING((R600_VGT_PRIMITIVE_TYPE
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
295 OUT_RING(DI_PT_RECTLIST
);
297 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
299 OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT
);
301 OUT_RING(DI_INDEX_SIZE_16_BIT
);
304 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
307 OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
309 OUT_RING(DI_SRC_SEL_AUTO_INDEX
);
316 set_default_state(drm_radeon_private_t
*dev_priv
)
319 u32 sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
;
320 u32 sq_thread_resource_mgmt
, sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
;
321 int num_ps_gprs
, num_vs_gprs
, num_temp_gprs
, num_gs_gprs
, num_es_gprs
;
322 int num_ps_threads
, num_vs_threads
, num_gs_threads
, num_es_threads
;
323 int num_ps_stack_entries
, num_vs_stack_entries
, num_gs_stack_entries
, num_es_stack_entries
;
326 switch ((dev_priv
->flags
& RADEON_FAMILY_MASK
)) {
333 num_ps_threads
= 136;
337 num_ps_stack_entries
= 128;
338 num_vs_stack_entries
= 128;
339 num_gs_stack_entries
= 0;
340 num_es_stack_entries
= 0;
349 num_ps_threads
= 144;
353 num_ps_stack_entries
= 40;
354 num_vs_stack_entries
= 40;
355 num_gs_stack_entries
= 32;
356 num_es_stack_entries
= 16;
368 num_ps_threads
= 136;
372 num_ps_stack_entries
= 40;
373 num_vs_stack_entries
= 40;
374 num_gs_stack_entries
= 32;
375 num_es_stack_entries
= 16;
383 num_ps_threads
= 136;
387 num_ps_stack_entries
= 40;
388 num_vs_stack_entries
= 40;
389 num_gs_stack_entries
= 32;
390 num_es_stack_entries
= 16;
398 num_ps_threads
= 188;
402 num_ps_stack_entries
= 256;
403 num_vs_stack_entries
= 256;
404 num_gs_stack_entries
= 0;
405 num_es_stack_entries
= 0;
414 num_ps_threads
= 188;
418 num_ps_stack_entries
= 128;
419 num_vs_stack_entries
= 128;
420 num_gs_stack_entries
= 0;
421 num_es_stack_entries
= 0;
429 num_ps_threads
= 144;
433 num_ps_stack_entries
= 128;
434 num_vs_stack_entries
= 128;
435 num_gs_stack_entries
= 0;
436 num_es_stack_entries
= 0;
440 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
441 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
442 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
443 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
) ||
444 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
))
447 sq_config
= R600_VC_ENABLE
;
449 sq_config
|= (R600_DX9_CONSTS
|
450 R600_ALU_INST_PREFER_VECTOR
|
456 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(num_ps_gprs
) |
457 R600_NUM_VS_GPRS(num_vs_gprs
) |
458 R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
));
459 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(num_gs_gprs
) |
460 R600_NUM_ES_GPRS(num_es_gprs
));
461 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(num_ps_threads
) |
462 R600_NUM_VS_THREADS(num_vs_threads
) |
463 R600_NUM_GS_THREADS(num_gs_threads
) |
464 R600_NUM_ES_THREADS(num_es_threads
));
465 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
) |
466 R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
));
467 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
) |
468 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries
));
470 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
) {
471 BEGIN_RING(r7xx_default_size
+ 10);
472 for (i
= 0; i
< r7xx_default_size
; i
++)
473 OUT_RING(r7xx_default_state
[i
]);
475 BEGIN_RING(r6xx_default_size
+ 10);
476 for (i
= 0; i
< r6xx_default_size
; i
++)
477 OUT_RING(r6xx_default_state
[i
]);
479 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
480 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT
);
482 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 6));
483 OUT_RING((R600_SQ_CONFIG
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
485 OUT_RING(sq_gpr_resource_mgmt_1
);
486 OUT_RING(sq_gpr_resource_mgmt_2
);
487 OUT_RING(sq_thread_resource_mgmt
);
488 OUT_RING(sq_stack_resource_mgmt_1
);
489 OUT_RING(sq_stack_resource_mgmt_2
);
493 static int r600_nomm_get_vb(struct drm_device
*dev
)
495 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
496 dev_priv
->blit_vb
= radeon_freelist_get(dev
);
497 if (!dev_priv
->blit_vb
) {
498 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
504 static void r600_nomm_put_vb(struct drm_device
*dev
)
506 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
508 dev_priv
->blit_vb
->used
= 0;
509 radeon_cp_discard_buffer(dev
, dev_priv
->blit_vb
->file_priv
->master
, dev_priv
->blit_vb
);
512 static void *r600_nomm_get_vb_ptr(struct drm_device
*dev
)
514 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
515 return (((char *)dev
->agp_buffer_map
->handle
+
516 dev_priv
->blit_vb
->offset
+ dev_priv
->blit_vb
->used
));
520 r600_prepare_blit_copy(struct drm_device
*dev
, struct drm_file
*file_priv
)
522 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
526 ret
= r600_nomm_get_vb(dev
);
530 dev_priv
->blit_vb
->file_priv
= file_priv
;
532 set_default_state(dev_priv
);
540 r600_done_blit_copy(struct drm_device
*dev
)
542 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
547 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
548 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT
);
549 /* wait for 3D idle clean */
550 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
551 OUT_RING((R600_WAIT_UNTIL
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
552 OUT_RING(RADEON_WAIT_3D_IDLE
| RADEON_WAIT_3D_IDLECLEAN
);
557 r600_nomm_put_vb(dev
);
561 r600_blit_copy(struct drm_device
*dev
,
562 uint64_t src_gpu_addr
, uint64_t dst_gpu_addr
,
565 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
570 vb
= r600_nomm_get_vb_ptr(dev
);
572 if ((size_bytes
& 3) || (src_gpu_addr
& 3) || (dst_gpu_addr
& 3)) {
576 int cur_size
= size_bytes
;
577 int src_x
= src_gpu_addr
& 255;
578 int dst_x
= dst_gpu_addr
& 255;
580 src_gpu_addr
= src_gpu_addr
& ~255;
581 dst_gpu_addr
= dst_gpu_addr
& ~255;
583 if (!src_x
&& !dst_x
) {
584 h
= (cur_size
/ max_bytes
);
590 cur_size
= max_bytes
;
592 if (cur_size
> max_bytes
)
593 cur_size
= max_bytes
;
594 if (cur_size
> (max_bytes
- dst_x
))
595 cur_size
= (max_bytes
- dst_x
);
596 if (cur_size
> (max_bytes
- src_x
))
597 cur_size
= (max_bytes
- src_x
);
600 if ((dev_priv
->blit_vb
->used
+ 48) > dev_priv
->blit_vb
->total
) {
602 r600_nomm_put_vb(dev
);
603 r600_nomm_get_vb(dev
);
604 if (!dev_priv
->blit_vb
)
607 vb
= r600_nomm_get_vb_ptr(dev
);
610 vb
[0] = int2float(dst_x
);
612 vb
[2] = int2float(src_x
);
615 vb
[4] = int2float(dst_x
);
616 vb
[5] = int2float(h
);
617 vb
[6] = int2float(src_x
);
618 vb
[7] = int2float(h
);
620 vb
[8] = int2float(dst_x
+ cur_size
);
621 vb
[9] = int2float(h
);
622 vb
[10] = int2float(src_x
+ cur_size
);
623 vb
[11] = int2float(h
);
626 set_tex_resource(dev_priv
, FMT_8
,
627 src_x
+ cur_size
, h
, src_x
+ cur_size
,
630 cp_set_surface_sync(dev_priv
,
631 R600_TC_ACTION_ENA
, (src_x
+ cur_size
* h
), src_gpu_addr
);
634 set_render_target(dev_priv
, COLOR_8
,
639 set_scissors(dev_priv
, dst_x
, 0, dst_x
+ cur_size
, h
);
641 /* Vertex buffer setup */
642 vb_addr
= dev_priv
->gart_buffers_offset
+
643 dev_priv
->blit_vb
->offset
+
644 dev_priv
->blit_vb
->used
;
645 set_vtx_resource(dev_priv
, vb_addr
);
650 cp_set_surface_sync(dev_priv
,
651 R600_CB_ACTION_ENA
| R600_CB0_DEST_BASE_ENA
,
652 cur_size
* h
, dst_gpu_addr
);
655 dev_priv
->blit_vb
->used
+= 12 * 4;
657 src_gpu_addr
+= cur_size
* h
;
658 dst_gpu_addr
+= cur_size
* h
;
659 size_bytes
-= cur_size
* h
;
662 max_bytes
= 8192 * 4;
665 int cur_size
= size_bytes
;
666 int src_x
= (src_gpu_addr
& 255);
667 int dst_x
= (dst_gpu_addr
& 255);
669 src_gpu_addr
= src_gpu_addr
& ~255;
670 dst_gpu_addr
= dst_gpu_addr
& ~255;
672 if (!src_x
&& !dst_x
) {
673 h
= (cur_size
/ max_bytes
);
679 cur_size
= max_bytes
;
681 if (cur_size
> max_bytes
)
682 cur_size
= max_bytes
;
683 if (cur_size
> (max_bytes
- dst_x
))
684 cur_size
= (max_bytes
- dst_x
);
685 if (cur_size
> (max_bytes
- src_x
))
686 cur_size
= (max_bytes
- src_x
);
689 if ((dev_priv
->blit_vb
->used
+ 48) > dev_priv
->blit_vb
->total
) {
690 r600_nomm_put_vb(dev
);
691 r600_nomm_get_vb(dev
);
692 if (!dev_priv
->blit_vb
)
696 vb
= r600_nomm_get_vb_ptr(dev
);
699 vb
[0] = int2float(dst_x
/ 4);
701 vb
[2] = int2float(src_x
/ 4);
704 vb
[4] = int2float(dst_x
/ 4);
705 vb
[5] = int2float(h
);
706 vb
[6] = int2float(src_x
/ 4);
707 vb
[7] = int2float(h
);
709 vb
[8] = int2float((dst_x
+ cur_size
) / 4);
710 vb
[9] = int2float(h
);
711 vb
[10] = int2float((src_x
+ cur_size
) / 4);
712 vb
[11] = int2float(h
);
715 set_tex_resource(dev_priv
, FMT_8_8_8_8
,
716 (src_x
+ cur_size
) / 4,
717 h
, (src_x
+ cur_size
) / 4,
720 cp_set_surface_sync(dev_priv
,
721 R600_TC_ACTION_ENA
, (src_x
+ cur_size
* h
), src_gpu_addr
);
724 set_render_target(dev_priv
, COLOR_8_8_8_8
,
725 (dst_x
+ cur_size
) / 4, h
,
729 set_scissors(dev_priv
, (dst_x
/ 4), 0, (dst_x
+ cur_size
/ 4), h
);
731 /* Vertex buffer setup */
732 vb_addr
= dev_priv
->gart_buffers_offset
+
733 dev_priv
->blit_vb
->offset
+
734 dev_priv
->blit_vb
->used
;
735 set_vtx_resource(dev_priv
, vb_addr
);
740 cp_set_surface_sync(dev_priv
,
741 R600_CB_ACTION_ENA
| R600_CB0_DEST_BASE_ENA
,
742 cur_size
* h
, dst_gpu_addr
);
745 dev_priv
->blit_vb
->used
+= 12 * 4;
747 src_gpu_addr
+= cur_size
* h
;
748 dst_gpu_addr
+= cur_size
* h
;
749 size_bytes
-= cur_size
* h
;
755 r600_blit_swap(struct drm_device
*dev
,
756 uint64_t src_gpu_addr
, uint64_t dst_gpu_addr
,
757 int sx
, int sy
, int dx
, int dy
,
758 int w
, int h
, int src_pitch
, int dst_pitch
, int cpp
)
760 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
761 int cb_format
, tex_format
;
762 int sx2
, sy2
, dx2
, dy2
;
766 if ((dev_priv
->blit_vb
->used
+ 48) > dev_priv
->blit_vb
->total
) {
768 r600_nomm_put_vb(dev
);
769 r600_nomm_get_vb(dev
);
770 if (!dev_priv
->blit_vb
)
775 vb
= r600_nomm_get_vb_ptr(dev
);
782 vb
[0] = int2float(dx
);
783 vb
[1] = int2float(dy
);
784 vb
[2] = int2float(sx
);
785 vb
[3] = int2float(sy
);
787 vb
[4] = int2float(dx
);
788 vb
[5] = int2float(dy2
);
789 vb
[6] = int2float(sx
);
790 vb
[7] = int2float(sy2
);
792 vb
[8] = int2float(dx2
);
793 vb
[9] = int2float(dy2
);
794 vb
[10] = int2float(sx2
);
795 vb
[11] = int2float(sy2
);
799 cb_format
= COLOR_8_8_8_8
;
800 tex_format
= FMT_8_8_8_8
;
803 cb_format
= COLOR_5_6_5
;
804 tex_format
= FMT_5_6_5
;
813 set_tex_resource(dev_priv
, tex_format
,
815 sy2
, src_pitch
/ cpp
,
818 cp_set_surface_sync(dev_priv
,
819 R600_TC_ACTION_ENA
, src_pitch
* sy2
, src_gpu_addr
);
822 set_render_target(dev_priv
, cb_format
,
823 dst_pitch
/ cpp
, dy2
,
827 set_scissors(dev_priv
, dx
, dy
, dx2
, dy2
);
829 /* Vertex buffer setup */
830 vb_addr
= dev_priv
->gart_buffers_offset
+
831 dev_priv
->blit_vb
->offset
+
832 dev_priv
->blit_vb
->used
;
833 set_vtx_resource(dev_priv
, vb_addr
);
838 cp_set_surface_sync(dev_priv
,
839 R600_CB_ACTION_ENA
| R600_CB0_DEST_BASE_ENA
,
840 dst_pitch
* dy2
, dst_gpu_addr
);
842 dev_priv
->blit_vb
->used
+= 12 * 4;