2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include <drm/radeon_drm.h>
31 #include "r600_blit_shaders.h"
32 #include "radeon_blit_common.h"
34 /* 23 bits of float fractional data */
35 #define I2F_FRAC_BITS 23
36 #define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
39 * Converts unsigned integer into 32-bit IEEE floating point representation.
40 * Will be exact from 0 to 2^24. Above that, we round towards zero
41 * as the fractional bits will not fit in a float. (It would be better to
42 * round towards even as the fpu does, but that is slower.)
44 __pure
uint32_t int2float(uint32_t x
)
46 uint32_t msb
, exponent
, fraction
;
51 /* Get location of the most significant bit */
55 * Use a rotate instead of a shift because that works both leftwards
56 * and rightwards due to the mod(32) behaviour. This means we don't
57 * need to check to see if we are above 2^24 or not.
59 fraction
= ror32(x
, (msb
- I2F_FRAC_BITS
) & 0x1f) & I2F_MASK
;
60 exponent
= (127 + msb
) << I2F_FRAC_BITS
;
62 return fraction
+ exponent
;
65 /* emits 21 on rv770+, 23 on r600 */
67 set_render_target(struct radeon_device
*rdev
, int format
,
68 int w
, int h
, u64 gpu_addr
)
70 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
78 cb_color_info
= CB_FORMAT(format
) |
79 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM
) |
80 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1
);
82 slice
= ((w
* h
) / 64) - 1;
84 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
85 radeon_ring_write(ring
, (CB_COLOR0_BASE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
86 radeon_ring_write(ring
, gpu_addr
>> 8);
88 if (rdev
->family
> CHIP_R600
&& rdev
->family
< CHIP_RV770
) {
89 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_BASE_UPDATE
, 0));
90 radeon_ring_write(ring
, 2 << 0);
93 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
94 radeon_ring_write(ring
, (CB_COLOR0_SIZE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
95 radeon_ring_write(ring
, (pitch
<< 0) | (slice
<< 10));
97 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
98 radeon_ring_write(ring
, (CB_COLOR0_VIEW
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
99 radeon_ring_write(ring
, 0);
101 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
102 radeon_ring_write(ring
, (CB_COLOR0_INFO
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
103 radeon_ring_write(ring
, cb_color_info
);
105 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
106 radeon_ring_write(ring
, (CB_COLOR0_TILE
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
107 radeon_ring_write(ring
, 0);
109 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
110 radeon_ring_write(ring
, (CB_COLOR0_FRAG
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
111 radeon_ring_write(ring
, 0);
113 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
114 radeon_ring_write(ring
, (CB_COLOR0_MASK
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
115 radeon_ring_write(ring
, 0);
120 cp_set_surface_sync(struct radeon_device
*rdev
,
121 u32 sync_type
, u32 size
,
124 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
127 if (size
== 0xffffffff)
128 cp_coher_size
= 0xffffffff;
130 cp_coher_size
= ((size
+ 255) >> 8);
132 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
133 radeon_ring_write(ring
, sync_type
);
134 radeon_ring_write(ring
, cp_coher_size
);
135 radeon_ring_write(ring
, mc_addr
>> 8);
136 radeon_ring_write(ring
, 10); /* poll interval */
139 /* emits 21dw + 1 surface sync = 26dw */
141 set_shaders(struct radeon_device
*rdev
)
143 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
145 u32 sq_pgm_resources
;
147 /* setup shader regs */
148 sq_pgm_resources
= (1 << 0);
151 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
152 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
153 radeon_ring_write(ring
, (SQ_PGM_START_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
154 radeon_ring_write(ring
, gpu_addr
>> 8);
156 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
157 radeon_ring_write(ring
, (SQ_PGM_RESOURCES_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
158 radeon_ring_write(ring
, sq_pgm_resources
);
160 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
161 radeon_ring_write(ring
, (SQ_PGM_CF_OFFSET_VS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
162 radeon_ring_write(ring
, 0);
165 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.ps_offset
;
166 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
167 radeon_ring_write(ring
, (SQ_PGM_START_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
168 radeon_ring_write(ring
, gpu_addr
>> 8);
170 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
171 radeon_ring_write(ring
, (SQ_PGM_RESOURCES_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
172 radeon_ring_write(ring
, sq_pgm_resources
| (1 << 28));
174 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
175 radeon_ring_write(ring
, (SQ_PGM_EXPORTS_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
176 radeon_ring_write(ring
, 2);
178 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 1));
179 radeon_ring_write(ring
, (SQ_PGM_CF_OFFSET_PS
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
180 radeon_ring_write(ring
, 0);
182 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.vs_offset
;
183 cp_set_surface_sync(rdev
, PACKET3_SH_ACTION_ENA
, 512, gpu_addr
);
186 /* emits 9 + 1 sync (5) = 14*/
188 set_vtx_resource(struct radeon_device
*rdev
, u64 gpu_addr
)
190 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
191 u32 sq_vtx_constant_word2
;
193 sq_vtx_constant_word2
= SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr
) & 0xff) |
196 sq_vtx_constant_word2
|= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32
);
199 radeon_ring_write(ring
, PACKET3(PACKET3_SET_RESOURCE
, 7));
200 radeon_ring_write(ring
, 0x460);
201 radeon_ring_write(ring
, gpu_addr
& 0xffffffff);
202 radeon_ring_write(ring
, 48 - 1);
203 radeon_ring_write(ring
, sq_vtx_constant_word2
);
204 radeon_ring_write(ring
, 1 << 0);
205 radeon_ring_write(ring
, 0);
206 radeon_ring_write(ring
, 0);
207 radeon_ring_write(ring
, SQ_TEX_VTX_VALID_BUFFER
<< 30);
209 if ((rdev
->family
== CHIP_RV610
) ||
210 (rdev
->family
== CHIP_RV620
) ||
211 (rdev
->family
== CHIP_RS780
) ||
212 (rdev
->family
== CHIP_RS880
) ||
213 (rdev
->family
== CHIP_RV710
))
214 cp_set_surface_sync(rdev
,
215 PACKET3_TC_ACTION_ENA
, 48, gpu_addr
);
217 cp_set_surface_sync(rdev
,
218 PACKET3_VC_ACTION_ENA
, 48, gpu_addr
);
223 set_tex_resource(struct radeon_device
*rdev
,
224 int format
, int w
, int h
, int pitch
,
225 u64 gpu_addr
, u32 size
)
227 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
228 uint32_t sq_tex_resource_word0
, sq_tex_resource_word1
, sq_tex_resource_word4
;
233 sq_tex_resource_word0
= S_038000_DIM(V_038000_SQ_TEX_DIM_2D
) |
234 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
235 sq_tex_resource_word0
|= S_038000_PITCH((pitch
>> 3) - 1) |
236 S_038000_TEX_WIDTH(w
- 1);
238 sq_tex_resource_word1
= S_038004_DATA_FORMAT(format
);
239 sq_tex_resource_word1
|= S_038004_TEX_HEIGHT(h
- 1);
241 sq_tex_resource_word4
= S_038010_REQUEST_SIZE(1) |
242 S_038010_DST_SEL_X(SQ_SEL_X
) |
243 S_038010_DST_SEL_Y(SQ_SEL_Y
) |
244 S_038010_DST_SEL_Z(SQ_SEL_Z
) |
245 S_038010_DST_SEL_W(SQ_SEL_W
);
247 cp_set_surface_sync(rdev
,
248 PACKET3_TC_ACTION_ENA
, size
, gpu_addr
);
250 radeon_ring_write(ring
, PACKET3(PACKET3_SET_RESOURCE
, 7));
251 radeon_ring_write(ring
, 0);
252 radeon_ring_write(ring
, sq_tex_resource_word0
);
253 radeon_ring_write(ring
, sq_tex_resource_word1
);
254 radeon_ring_write(ring
, gpu_addr
>> 8);
255 radeon_ring_write(ring
, gpu_addr
>> 8);
256 radeon_ring_write(ring
, sq_tex_resource_word4
);
257 radeon_ring_write(ring
, 0);
258 radeon_ring_write(ring
, SQ_TEX_VTX_VALID_TEXTURE
<< 30);
263 set_scissors(struct radeon_device
*rdev
, int x1
, int y1
,
266 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
267 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
268 radeon_ring_write(ring
, (PA_SC_SCREEN_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
269 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16));
270 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
272 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
273 radeon_ring_write(ring
, (PA_SC_GENERIC_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
274 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
275 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
277 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
278 radeon_ring_write(ring
, (PA_SC_WINDOW_SCISSOR_TL
- PACKET3_SET_CONTEXT_REG_OFFSET
) >> 2);
279 radeon_ring_write(ring
, (x1
<< 0) | (y1
<< 16) | (1 << 31));
280 radeon_ring_write(ring
, (x2
<< 0) | (y2
<< 16));
285 draw_auto(struct radeon_device
*rdev
)
287 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
288 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
289 radeon_ring_write(ring
, (VGT_PRIMITIVE_TYPE
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
290 radeon_ring_write(ring
, DI_PT_RECTLIST
);
292 radeon_ring_write(ring
, PACKET3(PACKET3_INDEX_TYPE
, 0));
293 radeon_ring_write(ring
,
297 DI_INDEX_SIZE_16_BIT
);
299 radeon_ring_write(ring
, PACKET3(PACKET3_NUM_INSTANCES
, 0));
300 radeon_ring_write(ring
, 1);
302 radeon_ring_write(ring
, PACKET3(PACKET3_DRAW_INDEX_AUTO
, 1));
303 radeon_ring_write(ring
, 3);
304 radeon_ring_write(ring
, DI_SRC_SEL_AUTO_INDEX
);
310 set_default_state(struct radeon_device
*rdev
)
312 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
313 u32 sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
;
314 u32 sq_thread_resource_mgmt
, sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
;
315 int num_ps_gprs
, num_vs_gprs
, num_temp_gprs
, num_gs_gprs
, num_es_gprs
;
316 int num_ps_threads
, num_vs_threads
, num_gs_threads
, num_es_threads
;
317 int num_ps_stack_entries
, num_vs_stack_entries
, num_gs_stack_entries
, num_es_stack_entries
;
321 switch (rdev
->family
) {
328 num_ps_threads
= 136;
332 num_ps_stack_entries
= 128;
333 num_vs_stack_entries
= 128;
334 num_gs_stack_entries
= 0;
335 num_es_stack_entries
= 0;
344 num_ps_threads
= 144;
348 num_ps_stack_entries
= 40;
349 num_vs_stack_entries
= 40;
350 num_gs_stack_entries
= 32;
351 num_es_stack_entries
= 16;
363 num_ps_threads
= 136;
367 num_ps_stack_entries
= 40;
368 num_vs_stack_entries
= 40;
369 num_gs_stack_entries
= 32;
370 num_es_stack_entries
= 16;
378 num_ps_threads
= 136;
382 num_ps_stack_entries
= 40;
383 num_vs_stack_entries
= 40;
384 num_gs_stack_entries
= 32;
385 num_es_stack_entries
= 16;
393 num_ps_threads
= 188;
397 num_ps_stack_entries
= 256;
398 num_vs_stack_entries
= 256;
399 num_gs_stack_entries
= 0;
400 num_es_stack_entries
= 0;
409 num_ps_threads
= 188;
413 num_ps_stack_entries
= 128;
414 num_vs_stack_entries
= 128;
415 num_gs_stack_entries
= 0;
416 num_es_stack_entries
= 0;
424 num_ps_threads
= 144;
428 num_ps_stack_entries
= 128;
429 num_vs_stack_entries
= 128;
430 num_gs_stack_entries
= 0;
431 num_es_stack_entries
= 0;
435 if ((rdev
->family
== CHIP_RV610
) ||
436 (rdev
->family
== CHIP_RV620
) ||
437 (rdev
->family
== CHIP_RS780
) ||
438 (rdev
->family
== CHIP_RS880
) ||
439 (rdev
->family
== CHIP_RV710
))
442 sq_config
= VC_ENABLE
;
444 sq_config
|= (DX9_CONSTS
|
445 ALU_INST_PREFER_VECTOR
|
451 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(num_ps_gprs
) |
452 NUM_VS_GPRS(num_vs_gprs
) |
453 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
));
454 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(num_gs_gprs
) |
455 NUM_ES_GPRS(num_es_gprs
));
456 sq_thread_resource_mgmt
= (NUM_PS_THREADS(num_ps_threads
) |
457 NUM_VS_THREADS(num_vs_threads
) |
458 NUM_GS_THREADS(num_gs_threads
) |
459 NUM_ES_THREADS(num_es_threads
));
460 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(num_ps_stack_entries
) |
461 NUM_VS_STACK_ENTRIES(num_vs_stack_entries
));
462 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(num_gs_stack_entries
) |
463 NUM_ES_STACK_ENTRIES(num_es_stack_entries
));
465 /* emit an IB pointing at default state */
466 dwords
= ALIGN(rdev
->r600_blit
.state_len
, 0x10);
467 gpu_addr
= rdev
->r600_blit
.shader_gpu_addr
+ rdev
->r600_blit
.state_offset
;
468 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
469 radeon_ring_write(ring
,
473 (gpu_addr
& 0xFFFFFFFC));
474 radeon_ring_write(ring
, upper_32_bits(gpu_addr
) & 0xFF);
475 radeon_ring_write(ring
, dwords
);
478 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 6));
479 radeon_ring_write(ring
, (SQ_CONFIG
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
480 radeon_ring_write(ring
, sq_config
);
481 radeon_ring_write(ring
, sq_gpr_resource_mgmt_1
);
482 radeon_ring_write(ring
, sq_gpr_resource_mgmt_2
);
483 radeon_ring_write(ring
, sq_thread_resource_mgmt
);
484 radeon_ring_write(ring
, sq_stack_resource_mgmt_1
);
485 radeon_ring_write(ring
, sq_stack_resource_mgmt_2
);
488 int r600_blit_init(struct radeon_device
*rdev
)
494 int num_packet2s
= 0;
496 rdev
->r600_blit
.primitives
.set_render_target
= set_render_target
;
497 rdev
->r600_blit
.primitives
.cp_set_surface_sync
= cp_set_surface_sync
;
498 rdev
->r600_blit
.primitives
.set_shaders
= set_shaders
;
499 rdev
->r600_blit
.primitives
.set_vtx_resource
= set_vtx_resource
;
500 rdev
->r600_blit
.primitives
.set_tex_resource
= set_tex_resource
;
501 rdev
->r600_blit
.primitives
.set_scissors
= set_scissors
;
502 rdev
->r600_blit
.primitives
.draw_auto
= draw_auto
;
503 rdev
->r600_blit
.primitives
.set_default_state
= set_default_state
;
505 rdev
->r600_blit
.ring_size_common
= 8; /* sync semaphore */
506 rdev
->r600_blit
.ring_size_common
+= 40; /* shaders + def state */
507 rdev
->r600_blit
.ring_size_common
+= 5; /* done copy */
508 rdev
->r600_blit
.ring_size_common
+= 16; /* fence emit for done copy */
510 rdev
->r600_blit
.ring_size_per_loop
= 76;
511 /* set_render_target emits 2 extra dwords on rv6xx */
512 if (rdev
->family
> CHIP_R600
&& rdev
->family
< CHIP_RV770
)
513 rdev
->r600_blit
.ring_size_per_loop
+= 2;
515 rdev
->r600_blit
.max_dim
= 8192;
517 rdev
->r600_blit
.state_offset
= 0;
519 if (rdev
->family
>= CHIP_RV770
)
520 rdev
->r600_blit
.state_len
= r7xx_default_size
;
522 rdev
->r600_blit
.state_len
= r6xx_default_size
;
524 dwords
= rdev
->r600_blit
.state_len
;
525 while (dwords
& 0xf) {
526 packet2s
[num_packet2s
++] = cpu_to_le32(PACKET2(0));
530 obj_size
= dwords
* 4;
531 obj_size
= ALIGN(obj_size
, 256);
533 rdev
->r600_blit
.vs_offset
= obj_size
;
534 obj_size
+= r6xx_vs_size
* 4;
535 obj_size
= ALIGN(obj_size
, 256);
537 rdev
->r600_blit
.ps_offset
= obj_size
;
538 obj_size
+= r6xx_ps_size
* 4;
539 obj_size
= ALIGN(obj_size
, 256);
541 /* pin copy shader into vram if not already initialized */
542 if (rdev
->r600_blit
.shader_obj
== NULL
) {
543 r
= radeon_bo_create(rdev
, obj_size
, PAGE_SIZE
, true,
544 RADEON_GEM_DOMAIN_VRAM
,
545 NULL
, &rdev
->r600_blit
.shader_obj
);
547 DRM_ERROR("r600 failed to allocate shader\n");
551 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
552 if (unlikely(r
!= 0))
554 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
555 &rdev
->r600_blit
.shader_gpu_addr
);
556 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
558 dev_err(rdev
->dev
, "(%d) pin blit object failed\n", r
);
563 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
565 rdev
->r600_blit
.vs_offset
, rdev
->r600_blit
.ps_offset
);
567 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
568 if (unlikely(r
!= 0))
570 r
= radeon_bo_kmap(rdev
->r600_blit
.shader_obj
, &ptr
);
572 DRM_ERROR("failed to map blit object %d\n", r
);
575 if (rdev
->family
>= CHIP_RV770
)
576 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
577 r7xx_default_state
, rdev
->r600_blit
.state_len
* 4);
579 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
,
580 r6xx_default_state
, rdev
->r600_blit
.state_len
* 4);
582 memcpy_toio(ptr
+ rdev
->r600_blit
.state_offset
+ (rdev
->r600_blit
.state_len
* 4),
583 packet2s
, num_packet2s
* 4);
584 for (i
= 0; i
< r6xx_vs_size
; i
++)
585 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.vs_offset
+ i
* 4) = cpu_to_le32(r6xx_vs
[i
]);
586 for (i
= 0; i
< r6xx_ps_size
; i
++)
587 *(u32
*)((unsigned long)ptr
+ rdev
->r600_blit
.ps_offset
+ i
* 4) = cpu_to_le32(r6xx_ps
[i
]);
588 radeon_bo_kunmap(rdev
->r600_blit
.shader_obj
);
589 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
591 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);
595 void r600_blit_fini(struct radeon_device
*rdev
)
599 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
600 if (rdev
->r600_blit
.shader_obj
== NULL
)
602 /* If we can't reserve the bo, unref should be enough to destroy
603 * it when it becomes idle.
605 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
607 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
608 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
610 radeon_bo_unref(&rdev
->r600_blit
.shader_obj
);
613 static unsigned r600_blit_create_rect(unsigned num_gpu_pages
,
614 int *width
, int *height
, int max_dim
)
617 unsigned pages
= num_gpu_pages
;
620 if (num_gpu_pages
== 0) {
621 /* not supposed to be called with no pages, but just in case */
629 while (num_gpu_pages
/ rect_order
) {
637 max_pages
= (max_dim
* h
) / (RECT_UNIT_W
* RECT_UNIT_H
);
638 if (pages
> max_pages
)
640 w
= (pages
* RECT_UNIT_W
* RECT_UNIT_H
) / h
;
641 w
= (w
/ RECT_UNIT_W
) * RECT_UNIT_W
;
642 pages
= (w
* h
) / (RECT_UNIT_W
* RECT_UNIT_H
);
647 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h
, w
, pages
);
649 /* return width and height only of the caller wants it */
659 int r600_blit_prepare_copy(struct radeon_device
*rdev
, unsigned num_gpu_pages
,
660 struct radeon_fence
**fence
, struct radeon_sa_bo
**vb
,
661 struct radeon_semaphore
**sem
)
663 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
667 int dwords_per_loop
= rdev
->r600_blit
.ring_size_per_loop
;
670 while (num_gpu_pages
) {
672 r600_blit_create_rect(num_gpu_pages
, NULL
, NULL
,
673 rdev
->r600_blit
.max_dim
);
677 /* 48 bytes for vertex per loop */
678 r
= radeon_sa_bo_new(rdev
, &rdev
->ring_tmp_bo
, vb
,
679 (num_loops
*48)+256, 256, true);
684 r
= radeon_semaphore_create(rdev
, sem
);
686 radeon_sa_bo_free(rdev
, vb
, NULL
);
690 /* calculate number of loops correctly */
691 ring_size
= num_loops
* dwords_per_loop
;
692 ring_size
+= rdev
->r600_blit
.ring_size_common
;
693 r
= radeon_ring_lock(rdev
, ring
, ring_size
);
695 radeon_sa_bo_free(rdev
, vb
, NULL
);
696 radeon_semaphore_free(rdev
, sem
, NULL
);
700 if (radeon_fence_need_sync(*fence
, RADEON_RING_TYPE_GFX_INDEX
)) {
701 radeon_semaphore_sync_rings(rdev
, *sem
, (*fence
)->ring
,
702 RADEON_RING_TYPE_GFX_INDEX
);
703 radeon_fence_note_sync(*fence
, RADEON_RING_TYPE_GFX_INDEX
);
705 radeon_semaphore_free(rdev
, sem
, NULL
);
708 rdev
->r600_blit
.primitives
.set_default_state(rdev
);
709 rdev
->r600_blit
.primitives
.set_shaders(rdev
);
713 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
**fence
,
714 struct radeon_sa_bo
*vb
, struct radeon_semaphore
*sem
)
716 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
719 r
= radeon_fence_emit(rdev
, fence
, RADEON_RING_TYPE_GFX_INDEX
);
721 radeon_ring_unlock_undo(rdev
, ring
);
725 radeon_ring_unlock_commit(rdev
, ring
);
726 radeon_sa_bo_free(rdev
, &vb
, *fence
);
727 radeon_semaphore_free(rdev
, &sem
, *fence
);
730 void r600_kms_blit_copy(struct radeon_device
*rdev
,
731 u64 src_gpu_addr
, u64 dst_gpu_addr
,
732 unsigned num_gpu_pages
,
733 struct radeon_sa_bo
*vb
)
738 DRM_DEBUG("emitting copy %16llx %16llx %d\n",
739 src_gpu_addr
, dst_gpu_addr
, num_gpu_pages
);
740 vb_cpu_addr
= (u32
*)radeon_sa_bo_cpu_addr(vb
);
741 vb_gpu_addr
= radeon_sa_bo_gpu_addr(vb
);
743 while (num_gpu_pages
) {
745 unsigned size_in_bytes
;
746 unsigned pages_per_loop
=
747 r600_blit_create_rect(num_gpu_pages
, &w
, &h
,
748 rdev
->r600_blit
.max_dim
);
750 size_in_bytes
= pages_per_loop
* RADEON_GPU_PAGE_SIZE
;
751 DRM_DEBUG("rectangle w=%d h=%d\n", w
, h
);
759 vb_cpu_addr
[5] = int2float(h
);
761 vb_cpu_addr
[7] = int2float(h
);
763 vb_cpu_addr
[8] = int2float(w
);
764 vb_cpu_addr
[9] = int2float(h
);
765 vb_cpu_addr
[10] = int2float(w
);
766 vb_cpu_addr
[11] = int2float(h
);
768 rdev
->r600_blit
.primitives
.set_tex_resource(rdev
, FMT_8_8_8_8
,
769 w
, h
, w
, src_gpu_addr
, size_in_bytes
);
770 rdev
->r600_blit
.primitives
.set_render_target(rdev
, COLOR_8_8_8_8
,
772 rdev
->r600_blit
.primitives
.set_scissors(rdev
, 0, 0, w
, h
);
773 rdev
->r600_blit
.primitives
.set_vtx_resource(rdev
, vb_gpu_addr
);
774 rdev
->r600_blit
.primitives
.draw_auto(rdev
);
775 rdev
->r600_blit
.primitives
.cp_set_surface_sync(rdev
,
776 PACKET3_CB_ACTION_ENA
| PACKET3_CB0_DEST_BASE_ENA
,
777 size_in_bytes
, dst_gpu_addr
);
781 src_gpu_addr
+= size_in_bytes
;
782 dst_gpu_addr
+= size_in_bytes
;
783 num_gpu_pages
-= pages_per_loop
;