projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/r600: fix memory leak introduced with 64k malloc avoidance fix.
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "r600d.h"
31 #include "avivod.h"
32
33 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc);
35 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36 struct radeon_cs_reloc **cs_reloc);
37 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39
40 /**
41 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
42 * @parser: parser structure holding parsing context.
43 * @pkt: where to store packet informations
44 *
45 * Assume that chunk_ib_index is properly set. Will return -EINVAL
46 * if packet is bigger than remaining ib size. or if packets is unknown.
47 **/
48 int r600_cs_packet_parse(struct radeon_cs_parser *p,
49 struct radeon_cs_packet *pkt,
50 unsigned idx)
51 {
52 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
53 uint32_t header;
54
55 if (idx >= ib_chunk->length_dw) {
56 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
57 idx, ib_chunk->length_dw);
58 return -EINVAL;
59 }
60 header = radeon_get_ib_value(p, idx);
61 pkt->idx = idx;
62 pkt->type = CP_PACKET_GET_TYPE(header);
63 pkt->count = CP_PACKET_GET_COUNT(header);
64 pkt->one_reg_wr = 0;
65 switch (pkt->type) {
66 case PACKET_TYPE0:
67 pkt->reg = CP_PACKET0_GET_REG(header);
68 break;
69 case PACKET_TYPE3:
70 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
71 break;
72 case PACKET_TYPE2:
73 pkt->count = -1;
74 break;
75 default:
76 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
77 return -EINVAL;
78 }
79 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
80 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
81 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
82 return -EINVAL;
83 }
84 return 0;
85 }
86
87 /**
88 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
89 * @parser: parser structure holding parsing context.
90 * @data: pointer to relocation data
91 * @offset_start: starting offset
92 * @offset_mask: offset mask (to align start offset on)
93 * @reloc: reloc informations
94 *
95 * Check next packet is relocation packet3, do bo validation and compute
96 * GPU offset using the provided start.
97 **/
98 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
99 struct radeon_cs_reloc **cs_reloc)
100 {
101 struct radeon_cs_chunk *relocs_chunk;
102 struct radeon_cs_packet p3reloc;
103 unsigned idx;
104 int r;
105
106 if (p->chunk_relocs_idx == -1) {
107 DRM_ERROR("No relocation chunk !\n");
108 return -EINVAL;
109 }
110 *cs_reloc = NULL;
111 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
112 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
113 if (r) {
114 return r;
115 }
116 p->idx += p3reloc.count + 2;
117 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
118 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
119 p3reloc.idx);
120 return -EINVAL;
121 }
122 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
123 if (idx >= relocs_chunk->length_dw) {
124 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
125 idx, relocs_chunk->length_dw);
126 return -EINVAL;
127 }
128 /* FIXME: we assume reloc size is 4 dwords */
129 *cs_reloc = p->relocs_ptr[(idx / 4)];
130 return 0;
131 }
132
133 /**
134 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
135 * @parser: parser structure holding parsing context.
136 * @data: pointer to relocation data
137 * @offset_start: starting offset
138 * @offset_mask: offset mask (to align start offset on)
139 * @reloc: reloc informations
140 *
141 * Check next packet is relocation packet3, do bo validation and compute
142 * GPU offset using the provided start.
143 **/
144 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
145 struct radeon_cs_reloc **cs_reloc)
146 {
147 struct radeon_cs_chunk *relocs_chunk;
148 struct radeon_cs_packet p3reloc;
149 unsigned idx;
150 int r;
151
152 if (p->chunk_relocs_idx == -1) {
153 DRM_ERROR("No relocation chunk !\n");
154 return -EINVAL;
155 }
156 *cs_reloc = NULL;
157 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
158 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
159 if (r) {
160 return r;
161 }
162 p->idx += p3reloc.count + 2;
163 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
164 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
165 p3reloc.idx);
166 return -EINVAL;
167 }
168 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
169 if (idx >= relocs_chunk->length_dw) {
170 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
171 idx, relocs_chunk->length_dw);
172 return -EINVAL;
173 }
174 *cs_reloc = &p->relocs[0];
175 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
176 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
177 return 0;
178 }
179
180 /**
181 * r600_cs_packet_next_vline() - parse userspace VLINE packet
182 * @parser: parser structure holding parsing context.
183 *
184 * Userspace sends a special sequence for VLINE waits.
185 * PACKET0 - VLINE_START_END + value
186 * PACKET3 - WAIT_REG_MEM poll vline status reg
187 * RELOC (P3) - crtc_id in reloc.
188 *
189 * This function parses this and relocates the VLINE START END
190 * and WAIT_REG_MEM packets to the correct crtc.
191 * It also detects a switched off crtc and nulls out the
192 * wait in that case.
193 */
194 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
195 {
196 struct drm_mode_object *obj;
197 struct drm_crtc *crtc;
198 struct radeon_crtc *radeon_crtc;
199 struct radeon_cs_packet p3reloc, wait_reg_mem;
200 int crtc_id;
201 int r;
202 uint32_t header, h_idx, reg, wait_reg_mem_info;
203 volatile uint32_t *ib;
204
205 ib = p->ib->ptr;
206
207 /* parse the WAIT_REG_MEM */
208 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
209 if (r)
210 return r;
211
212 /* check its a WAIT_REG_MEM */
213 if (wait_reg_mem.type != PACKET_TYPE3 ||
214 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
215 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
216 r = -EINVAL;
217 return r;
218 }
219
220 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
221 /* bit 4 is reg (0) or mem (1) */
222 if (wait_reg_mem_info & 0x10) {
223 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
224 r = -EINVAL;
225 return r;
226 }
227 /* waiting for value to be equal */
228 if ((wait_reg_mem_info & 0x7) != 0x3) {
229 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
230 r = -EINVAL;
231 return r;
232 }
233 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
234 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
235 r = -EINVAL;
236 return r;
237 }
238
239 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
240 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
241 r = -EINVAL;
242 return r;
243 }
244
245 /* jump over the NOP */
246 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
247 if (r)
248 return r;
249
250 h_idx = p->idx - 2;
251 p->idx += wait_reg_mem.count + 2;
252 p->idx += p3reloc.count + 2;
253
254 header = radeon_get_ib_value(p, h_idx);
255 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
256 reg = header >> 2;
257 mutex_lock(&p->rdev->ddev->mode_config.mutex);
258 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
259 if (!obj) {
260 DRM_ERROR("cannot find crtc %d\n", crtc_id);
261 r = -EINVAL;
262 goto out;
263 }
264 crtc = obj_to_crtc(obj);
265 radeon_crtc = to_radeon_crtc(crtc);
266 crtc_id = radeon_crtc->crtc_id;
267
268 if (!crtc->enabled) {
269 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
270 ib[h_idx + 2] = PACKET2(0);
271 ib[h_idx + 3] = PACKET2(0);
272 ib[h_idx + 4] = PACKET2(0);
273 ib[h_idx + 5] = PACKET2(0);
274 ib[h_idx + 6] = PACKET2(0);
275 ib[h_idx + 7] = PACKET2(0);
276 ib[h_idx + 8] = PACKET2(0);
277 } else if (crtc_id == 1) {
278 switch (reg) {
279 case AVIVO_D1MODE_VLINE_START_END:
280 header &= ~R600_CP_PACKET0_REG_MASK;
281 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
282 break;
283 default:
284 DRM_ERROR("unknown crtc reloc\n");
285 r = -EINVAL;
286 goto out;
287 }
288 ib[h_idx] = header;
289 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
290 }
291 out:
292 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
293 return r;
294 }
295
296 static int r600_packet0_check(struct radeon_cs_parser *p,
297 struct radeon_cs_packet *pkt,
298 unsigned idx, unsigned reg)
299 {
300 int r;
301
302 switch (reg) {
303 case AVIVO_D1MODE_VLINE_START_END:
304 r = r600_cs_packet_parse_vline(p);
305 if (r) {
306 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
307 idx, reg);
308 return r;
309 }
310 break;
311 default:
312 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
313 reg, idx);
314 return -EINVAL;
315 }
316 return 0;
317 }
318
319 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
320 struct radeon_cs_packet *pkt)
321 {
322 unsigned reg, i;
323 unsigned idx;
324 int r;
325
326 idx = pkt->idx + 1;
327 reg = pkt->reg;
328 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
329 r = r600_packet0_check(p, pkt, idx, reg);
330 if (r) {
331 return r;
332 }
333 }
334 return 0;
335 }
336
337 static int r600_packet3_check(struct radeon_cs_parser *p,
338 struct radeon_cs_packet *pkt)
339 {
340 struct radeon_cs_reloc *reloc;
341 volatile u32 *ib;
342 unsigned idx;
343 unsigned i;
344 unsigned start_reg, end_reg, reg;
345 int r;
346 u32 idx_value;
347
348 ib = p->ib->ptr;
349 idx = pkt->idx + 1;
350 idx_value = radeon_get_ib_value(p, idx);
351
352 switch (pkt->opcode) {
353 case PACKET3_START_3D_CMDBUF:
354 if (p->family >= CHIP_RV770 || pkt->count) {
355 DRM_ERROR("bad START_3D\n");
356 return -EINVAL;
357 }
358 break;
359 case PACKET3_CONTEXT_CONTROL:
360 if (pkt->count != 1) {
361 DRM_ERROR("bad CONTEXT_CONTROL\n");
362 return -EINVAL;
363 }
364 break;
365 case PACKET3_INDEX_TYPE:
366 case PACKET3_NUM_INSTANCES:
367 if (pkt->count) {
368 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
369 return -EINVAL;
370 }
371 break;
372 case PACKET3_DRAW_INDEX:
373 if (pkt->count != 3) {
374 DRM_ERROR("bad DRAW_INDEX\n");
375 return -EINVAL;
376 }
377 r = r600_cs_packet_next_reloc(p, &reloc);
378 if (r) {
379 DRM_ERROR("bad DRAW_INDEX\n");
380 return -EINVAL;
381 }
382 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
383 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
384 break;
385 case PACKET3_DRAW_INDEX_AUTO:
386 if (pkt->count != 1) {
387 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
388 return -EINVAL;
389 }
390 break;
391 case PACKET3_DRAW_INDEX_IMMD_BE:
392 case PACKET3_DRAW_INDEX_IMMD:
393 if (pkt->count < 2) {
394 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
395 return -EINVAL;
396 }
397 break;
398 case PACKET3_WAIT_REG_MEM:
399 if (pkt->count != 5) {
400 DRM_ERROR("bad WAIT_REG_MEM\n");
401 return -EINVAL;
402 }
403 /* bit 4 is reg (0) or mem (1) */
404 if (idx_value & 0x10) {
405 r = r600_cs_packet_next_reloc(p, &reloc);
406 if (r) {
407 DRM_ERROR("bad WAIT_REG_MEM\n");
408 return -EINVAL;
409 }
410 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
411 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
412 }
413 break;
414 case PACKET3_SURFACE_SYNC:
415 if (pkt->count != 3) {
416 DRM_ERROR("bad SURFACE_SYNC\n");
417 return -EINVAL;
418 }
419 /* 0xffffffff/0x0 is flush all cache flag */
420 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
421 radeon_get_ib_value(p, idx + 2) != 0) {
422 r = r600_cs_packet_next_reloc(p, &reloc);
423 if (r) {
424 DRM_ERROR("bad SURFACE_SYNC\n");
425 return -EINVAL;
426 }
427 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
428 }
429 break;
430 case PACKET3_EVENT_WRITE:
431 if (pkt->count != 2 && pkt->count != 0) {
432 DRM_ERROR("bad EVENT_WRITE\n");
433 return -EINVAL;
434 }
435 if (pkt->count) {
436 r = r600_cs_packet_next_reloc(p, &reloc);
437 if (r) {
438 DRM_ERROR("bad EVENT_WRITE\n");
439 return -EINVAL;
440 }
441 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
442 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
443 }
444 break;
445 case PACKET3_EVENT_WRITE_EOP:
446 if (pkt->count != 4) {
447 DRM_ERROR("bad EVENT_WRITE_EOP\n");
448 return -EINVAL;
449 }
450 r = r600_cs_packet_next_reloc(p, &reloc);
451 if (r) {
452 DRM_ERROR("bad EVENT_WRITE\n");
453 return -EINVAL;
454 }
455 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
456 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
457 break;
458 case PACKET3_SET_CONFIG_REG:
459 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
460 end_reg = 4 * pkt->count + start_reg - 4;
461 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
462 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
463 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
464 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
465 return -EINVAL;
466 }
467 for (i = 0; i < pkt->count; i++) {
468 reg = start_reg + (4 * i);
469 switch (reg) {
470 case CP_COHER_BASE:
471 /* use PACKET3_SURFACE_SYNC */
472 return -EINVAL;
473 default:
474 break;
475 }
476 }
477 break;
478 case PACKET3_SET_CONTEXT_REG:
479 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
480 end_reg = 4 * pkt->count + start_reg - 4;
481 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
482 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
483 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
484 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
485 return -EINVAL;
486 }
487 for (i = 0; i < pkt->count; i++) {
488 reg = start_reg + (4 * i);
489 switch (reg) {
490 case DB_DEPTH_BASE:
491 case CB_COLOR0_BASE:
492 case CB_COLOR1_BASE:
493 case CB_COLOR2_BASE:
494 case CB_COLOR3_BASE:
495 case CB_COLOR4_BASE:
496 case CB_COLOR5_BASE:
497 case CB_COLOR6_BASE:
498 case CB_COLOR7_BASE:
499 case SQ_PGM_START_FS:
500 case SQ_PGM_START_ES:
501 case SQ_PGM_START_VS:
502 case SQ_PGM_START_GS:
503 case SQ_PGM_START_PS:
504 r = r600_cs_packet_next_reloc(p, &reloc);
505 if (r) {
506 DRM_ERROR("bad SET_CONTEXT_REG "
507 "0x%04X\n", reg);
508 return -EINVAL;
509 }
510 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
511 break;
512 case VGT_DMA_BASE:
513 case VGT_DMA_BASE_HI:
514 /* These should be handled by DRAW_INDEX packet 3 */
515 case VGT_STRMOUT_BASE_OFFSET_0:
516 case VGT_STRMOUT_BASE_OFFSET_1:
517 case VGT_STRMOUT_BASE_OFFSET_2:
518 case VGT_STRMOUT_BASE_OFFSET_3:
519 case VGT_STRMOUT_BASE_OFFSET_HI_0:
520 case VGT_STRMOUT_BASE_OFFSET_HI_1:
521 case VGT_STRMOUT_BASE_OFFSET_HI_2:
522 case VGT_STRMOUT_BASE_OFFSET_HI_3:
523 case VGT_STRMOUT_BUFFER_BASE_0:
524 case VGT_STRMOUT_BUFFER_BASE_1:
525 case VGT_STRMOUT_BUFFER_BASE_2:
526 case VGT_STRMOUT_BUFFER_BASE_3:
527 case VGT_STRMOUT_BUFFER_OFFSET_0:
528 case VGT_STRMOUT_BUFFER_OFFSET_1:
529 case VGT_STRMOUT_BUFFER_OFFSET_2:
530 case VGT_STRMOUT_BUFFER_OFFSET_3:
531 /* These should be handled by STRMOUT_BUFFER packet 3 */
532 DRM_ERROR("bad context reg: 0x%08x\n", reg);
533 return -EINVAL;
534 default:
535 break;
536 }
537 }
538 break;
539 case PACKET3_SET_RESOURCE:
540 if (pkt->count % 7) {
541 DRM_ERROR("bad SET_RESOURCE\n");
542 return -EINVAL;
543 }
544 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
545 end_reg = 4 * pkt->count + start_reg - 4;
546 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
547 (start_reg >= PACKET3_SET_RESOURCE_END) ||
548 (end_reg >= PACKET3_SET_RESOURCE_END)) {
549 DRM_ERROR("bad SET_RESOURCE\n");
550 return -EINVAL;
551 }
552 for (i = 0; i < (pkt->count / 7); i++) {
553 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
554 case SQ_TEX_VTX_VALID_TEXTURE:
555 /* tex base */
556 r = r600_cs_packet_next_reloc(p, &reloc);
557 if (r) {
558 DRM_ERROR("bad SET_RESOURCE\n");
559 return -EINVAL;
560 }
561 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
562 /* tex mip base */
563 r = r600_cs_packet_next_reloc(p, &reloc);
564 if (r) {
565 DRM_ERROR("bad SET_RESOURCE\n");
566 return -EINVAL;
567 }
568 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
569 break;
570 case SQ_TEX_VTX_VALID_BUFFER:
571 /* vtx base */
572 r = r600_cs_packet_next_reloc(p, &reloc);
573 if (r) {
574 DRM_ERROR("bad SET_RESOURCE\n");
575 return -EINVAL;
576 }
577 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
578 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
579 break;
580 case SQ_TEX_VTX_INVALID_TEXTURE:
581 case SQ_TEX_VTX_INVALID_BUFFER:
582 default:
583 DRM_ERROR("bad SET_RESOURCE\n");
584 return -EINVAL;
585 }
586 }
587 break;
588 case PACKET3_SET_ALU_CONST:
589 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
590 end_reg = 4 * pkt->count + start_reg - 4;
591 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
592 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
593 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
594 DRM_ERROR("bad SET_ALU_CONST\n");
595 return -EINVAL;
596 }
597 break;
598 case PACKET3_SET_BOOL_CONST:
599 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
600 end_reg = 4 * pkt->count + start_reg - 4;
601 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
602 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
603 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
604 DRM_ERROR("bad SET_BOOL_CONST\n");
605 return -EINVAL;
606 }
607 break;
608 case PACKET3_SET_LOOP_CONST:
609 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
610 end_reg = 4 * pkt->count + start_reg - 4;
611 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
612 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
613 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
614 DRM_ERROR("bad SET_LOOP_CONST\n");
615 return -EINVAL;
616 }
617 break;
618 case PACKET3_SET_CTL_CONST:
619 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
620 end_reg = 4 * pkt->count + start_reg - 4;
621 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
622 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
623 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
624 DRM_ERROR("bad SET_CTL_CONST\n");
625 return -EINVAL;
626 }
627 break;
628 case PACKET3_SET_SAMPLER:
629 if (pkt->count % 3) {
630 DRM_ERROR("bad SET_SAMPLER\n");
631 return -EINVAL;
632 }
633 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
634 end_reg = 4 * pkt->count + start_reg - 4;
635 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
636 (start_reg >= PACKET3_SET_SAMPLER_END) ||
637 (end_reg >= PACKET3_SET_SAMPLER_END)) {
638 DRM_ERROR("bad SET_SAMPLER\n");
639 return -EINVAL;
640 }
641 break;
642 case PACKET3_SURFACE_BASE_UPDATE:
643 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
644 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
645 return -EINVAL;
646 }
647 if (pkt->count) {
648 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
649 return -EINVAL;
650 }
651 break;
652 case PACKET3_NOP:
653 break;
654 default:
655 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
656 return -EINVAL;
657 }
658 return 0;
659 }
660
661 int r600_cs_parse(struct radeon_cs_parser *p)
662 {
663 struct radeon_cs_packet pkt;
664 int r;
665
666 do {
667 r = r600_cs_packet_parse(p, &pkt, p->idx);
668 if (r) {
669 return r;
670 }
671 p->idx += pkt.count + 2;
672 switch (pkt.type) {
673 case PACKET_TYPE0:
674 r = r600_cs_parse_packet0(p, &pkt);
675 break;
676 case PACKET_TYPE2:
677 break;
678 case PACKET_TYPE3:
679 r = r600_packet3_check(p, &pkt);
680 break;
681 default:
682 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
683 return -EINVAL;
684 }
685 if (r) {
686 return r;
687 }
688 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
689 #if 0
690 for (r = 0; r < p->ib->length_dw; r++) {
691 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
692 mdelay(1);
693 }
694 #endif
695 return 0;
696 }
697
698 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
699 {
700 if (p->chunk_relocs_idx == -1) {
701 return 0;
702 }
703 p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
704 if (p->relocs == NULL) {
705 return -ENOMEM;
706 }
707 return 0;
708 }
709
710 /**
711 * cs_parser_fini() - clean parser states
712 * @parser: parser structure holding parsing context.
713 * @error: error number
714 *
715 * If error is set than unvalidate buffer, otherwise just free memory
716 * used by parsing context.
717 **/
718 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
719 {
720 unsigned i;
721
722 kfree(parser->relocs);
723 for (i = 0; i < parser->nchunks; i++) {
724 kfree(parser->chunks[i].kdata);
725 kfree(parser->chunks[i].kpage[0]);
726 kfree(parser->chunks[i].kpage[1]);
727 }
728 kfree(parser->chunks);
729 kfree(parser->chunks_array);
730 }
731
732 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
733 unsigned family, u32 *ib, int *l)
734 {
735 struct radeon_cs_parser parser;
736 struct radeon_cs_chunk *ib_chunk;
737 struct radeon_ib fake_ib;
738 int r;
739
740 /* initialize parser */
741 memset(&parser, 0, sizeof(struct radeon_cs_parser));
742 parser.filp = filp;
743 parser.rdev = NULL;
744 parser.family = family;
745 parser.ib = &fake_ib;
746 fake_ib.ptr = ib;
747 r = radeon_cs_parser_init(&parser, data);
748 if (r) {
749 DRM_ERROR("Failed to initialize parser !\n");
750 r600_cs_parser_fini(&parser, r);
751 return r;
752 }
753 r = r600_cs_parser_relocs_legacy(&parser);
754 if (r) {
755 DRM_ERROR("Failed to parse relocation !\n");
756 r600_cs_parser_fini(&parser, r);
757 return r;
758 }
759 /* Copy the packet into the IB, the parser will read from the
760 * input memory (cached) and write to the IB (which can be
761 * uncached). */
762 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
763 parser.ib->length_dw = ib_chunk->length_dw;
764 *l = parser.ib->length_dw;
765 r = r600_cs_parse(&parser);
766 if (r) {
767 DRM_ERROR("Invalid command stream !\n");
768 r600_cs_parser_fini(&parser, r);
769 return r;
770 }
771 r = radeon_cs_finish_pages(&parser);
772 if (r) {
773 DRM_ERROR("Invalid command stream !\n");
774 r600_cs_parser_fini(&parser, r);
775 return r;
776 }
777 r600_cs_parser_fini(&parser, r);
778 return r;
779 }
780
781 void r600_cs_legacy_init(void)
782 {
783 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
784 }
Linux kernel - Deliverables
This page took 0.054713 seconds and 5 git commands to generate.