2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kernel.h>
32 #include "r600_reg_safe.h"
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser
*p
,
35 struct radeon_cs_reloc
**cs_reloc
);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser
*p
,
37 struct radeon_cs_reloc
**cs_reloc
);
38 typedef int (*next_reloc_t
)(struct radeon_cs_parser
*, struct radeon_cs_reloc
**);
39 static next_reloc_t r600_cs_packet_next_reloc
= &r600_cs_packet_next_reloc_mm
;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device
*dev
, u32
*npipes
, u32
*nbanks
, u32
*group_size
);
43 struct r600_cs_track
{
44 /* configuration we miror so that we use same code btw kms/ums */
51 u32 cb_color_base_last
[8];
52 struct radeon_bo
*cb_color_bo
[8];
53 u64 cb_color_bo_mc
[8];
54 u32 cb_color_bo_offset
[8];
55 struct radeon_bo
*cb_color_frag_bo
[8];
56 struct radeon_bo
*cb_color_tile_bo
[8];
58 u32 cb_color_size_idx
[8];
63 u32 vgt_strmout_buffer_en
;
66 u32 db_depth_size_idx
;
70 struct radeon_bo
*db_bo
;
74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 }
77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 }
79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
88 enum radeon_family min_family
;
91 static const struct gpu_formats color_formats_table
[] = {
93 FMT_8_BIT(V_038004_COLOR_8
, 1),
94 FMT_8_BIT(V_038004_COLOR_4_4
, 1),
95 FMT_8_BIT(V_038004_COLOR_3_3_2
, 1),
96 FMT_8_BIT(V_038004_FMT_1
, 0),
99 FMT_16_BIT(V_038004_COLOR_16
, 1),
100 FMT_16_BIT(V_038004_COLOR_16_FLOAT
, 1),
101 FMT_16_BIT(V_038004_COLOR_8_8
, 1),
102 FMT_16_BIT(V_038004_COLOR_5_6_5
, 1),
103 FMT_16_BIT(V_038004_COLOR_6_5_5
, 1),
104 FMT_16_BIT(V_038004_COLOR_1_5_5_5
, 1),
105 FMT_16_BIT(V_038004_COLOR_4_4_4_4
, 1),
106 FMT_16_BIT(V_038004_COLOR_5_5_5_1
, 1),
109 FMT_24_BIT(V_038004_FMT_8_8_8
),
112 FMT_32_BIT(V_038004_COLOR_32
, 1),
113 FMT_32_BIT(V_038004_COLOR_32_FLOAT
, 1),
114 FMT_32_BIT(V_038004_COLOR_16_16
, 1),
115 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT
, 1),
116 FMT_32_BIT(V_038004_COLOR_8_24
, 1),
117 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT
, 1),
118 FMT_32_BIT(V_038004_COLOR_24_8
, 1),
119 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT
, 1),
120 FMT_32_BIT(V_038004_COLOR_10_11_11
, 1),
121 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT
, 1),
122 FMT_32_BIT(V_038004_COLOR_11_11_10
, 1),
123 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT
, 1),
124 FMT_32_BIT(V_038004_COLOR_2_10_10_10
, 1),
125 FMT_32_BIT(V_038004_COLOR_8_8_8_8
, 1),
126 FMT_32_BIT(V_038004_COLOR_10_10_10_2
, 1),
127 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP
, 0),
128 FMT_32_BIT(V_038004_FMT_32_AS_8
, 0),
129 FMT_32_BIT(V_038004_FMT_32_AS_8_8
, 0),
132 FMT_48_BIT(V_038004_FMT_16_16_16
),
133 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT
),
136 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT
, 1),
137 FMT_64_BIT(V_038004_COLOR_32_32
, 1),
138 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT
, 1),
139 FMT_64_BIT(V_038004_COLOR_16_16_16_16
, 1),
140 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT
, 1),
142 FMT_96_BIT(V_038004_FMT_32_32_32
),
143 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT
),
146 FMT_128_BIT(V_038004_COLOR_32_32_32_32
, 1),
147 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT
, 1),
149 [V_038004_FMT_GB_GR
] = { 2, 1, 4, 0 },
150 [V_038004_FMT_BG_RG
] = { 2, 1, 4, 0 },
152 /* block compressed formats */
153 [V_038004_FMT_BC1
] = { 4, 4, 8, 0 },
154 [V_038004_FMT_BC2
] = { 4, 4, 16, 0 },
155 [V_038004_FMT_BC3
] = { 4, 4, 16, 0 },
156 [V_038004_FMT_BC4
] = { 4, 4, 8, 0 },
157 [V_038004_FMT_BC5
] = { 4, 4, 16, 0},
158 [V_038004_FMT_BC6
] = { 4, 4, 16, 0, CHIP_CEDAR
}, /* Evergreen-only */
159 [V_038004_FMT_BC7
] = { 4, 4, 16, 0, CHIP_CEDAR
}, /* Evergreen-only */
161 /* The other Evergreen formats */
162 [V_038004_FMT_32_AS_32_32_32_32
] = { 1, 1, 4, 0, CHIP_CEDAR
},
165 static inline bool fmt_is_valid_color(u32 format
)
167 if (format
>= ARRAY_SIZE(color_formats_table
))
170 if (color_formats_table
[format
].valid_color
)
176 static inline bool fmt_is_valid_texture(u32 format
, enum radeon_family family
)
178 if (format
>= ARRAY_SIZE(color_formats_table
))
181 if (family
< color_formats_table
[format
].min_family
)
184 if (color_formats_table
[format
].blockwidth
> 0)
190 static inline int fmt_get_blocksize(u32 format
)
192 if (format
>= ARRAY_SIZE(color_formats_table
))
195 return color_formats_table
[format
].blocksize
;
198 static inline int fmt_get_nblocksx(u32 format
, u32 w
)
202 if (format
>= ARRAY_SIZE(color_formats_table
))
205 bw
= color_formats_table
[format
].blockwidth
;
209 return (w
+ bw
- 1) / bw
;
212 static inline int fmt_get_nblocksy(u32 format
, u32 h
)
216 if (format
>= ARRAY_SIZE(color_formats_table
))
219 bh
= color_formats_table
[format
].blockheight
;
223 return (h
+ bh
- 1) / bh
;
226 static inline int r600_bpe_from_format(u32
*bpe
, u32 format
)
230 if (format
>= ARRAY_SIZE(color_formats_table
))
233 res
= color_formats_table
[format
].blocksize
;
245 struct array_mode_checker
{
254 /* returns alignment in pixels for pitch/height/depth and bytes for base */
255 static inline int r600_get_array_mode_alignment(struct array_mode_checker
*values
,
263 u32 macro_tile_width
= values
->nbanks
;
264 u32 macro_tile_height
= values
->npipes
;
265 u32 tile_bytes
= tile_width
* tile_height
* values
->blocksize
* values
->nsamples
;
266 u32 macro_tile_bytes
= macro_tile_width
* macro_tile_height
* tile_bytes
;
268 switch (values
->array_mode
) {
269 case ARRAY_LINEAR_GENERAL
:
270 /* technically tile_width/_height for pitch/height */
271 *pitch_align
= 1; /* tile_width */
272 *height_align
= 1; /* tile_height */
276 case ARRAY_LINEAR_ALIGNED
:
277 *pitch_align
= max((u32
)64, (u32
)(values
->group_size
/ values
->blocksize
));
278 *height_align
= tile_height
;
280 *base_align
= values
->group_size
;
282 case ARRAY_1D_TILED_THIN1
:
283 *pitch_align
= max((u32
)tile_width
,
284 (u32
)(values
->group_size
/
285 (tile_height
* values
->blocksize
* values
->nsamples
)));
286 *height_align
= tile_height
;
288 *base_align
= values
->group_size
;
290 case ARRAY_2D_TILED_THIN1
:
291 *pitch_align
= max((u32
)macro_tile_width
,
292 (u32
)(((values
->group_size
/ tile_height
) /
293 (values
->blocksize
* values
->nsamples
)) *
294 values
->nbanks
)) * tile_width
;
295 *height_align
= macro_tile_height
* tile_height
;
297 *base_align
= max(macro_tile_bytes
,
298 (*pitch_align
) * values
->blocksize
* (*height_align
) * values
->nsamples
);
307 static void r600_cs_track_init(struct r600_cs_track
*track
)
311 /* assume DX9 mode */
312 track
->sq_config
= DX9_CONSTS
;
313 for (i
= 0; i
< 8; i
++) {
314 track
->cb_color_base_last
[i
] = 0;
315 track
->cb_color_size
[i
] = 0;
316 track
->cb_color_size_idx
[i
] = 0;
317 track
->cb_color_info
[i
] = 0;
318 track
->cb_color_bo
[i
] = NULL
;
319 track
->cb_color_bo_offset
[i
] = 0xFFFFFFFF;
320 track
->cb_color_bo_mc
[i
] = 0xFFFFFFFF;
322 track
->cb_target_mask
= 0xFFFFFFFF;
323 track
->cb_shader_mask
= 0xFFFFFFFF;
325 track
->db_bo_mc
= 0xFFFFFFFF;
326 /* assume the biggest format and that htile is enabled */
327 track
->db_depth_info
= 7 | (1 << 25);
328 track
->db_depth_view
= 0xFFFFC000;
329 track
->db_depth_size
= 0xFFFFFFFF;
330 track
->db_depth_size_idx
= 0;
331 track
->db_depth_control
= 0xFFFFFFFF;
334 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser
*p
, int i
)
336 struct r600_cs_track
*track
= p
->track
;
337 u32 slice_tile_max
, size
, tmp
;
338 u32 height
, height_align
, pitch
, pitch_align
, depth_align
;
339 u64 base_offset
, base_align
;
340 struct array_mode_checker array_check
;
341 volatile u32
*ib
= p
->ib
->ptr
;
344 if (G_0280A0_TILE_MODE(track
->cb_color_info
[i
])) {
345 dev_warn(p
->dev
, "FMASK or CMASK buffer are not supported by this kernel\n");
348 size
= radeon_bo_size(track
->cb_color_bo
[i
]) - track
->cb_color_bo_offset
[i
];
349 format
= G_0280A0_FORMAT(track
->cb_color_info
[i
]);
350 if (!fmt_is_valid_color(format
)) {
351 dev_warn(p
->dev
, "%s:%d cb invalid format %d for %d (0x%08X)\n",
352 __func__
, __LINE__
, format
,
353 i
, track
->cb_color_info
[i
]);
356 /* pitch in pixels */
357 pitch
= (G_028060_PITCH_TILE_MAX(track
->cb_color_size
[i
]) + 1) * 8;
358 slice_tile_max
= G_028060_SLICE_TILE_MAX(track
->cb_color_size
[i
]) + 1;
359 slice_tile_max
*= 64;
360 height
= slice_tile_max
/ pitch
;
363 array_mode
= G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]);
365 base_offset
= track
->cb_color_bo_mc
[i
] + track
->cb_color_bo_offset
[i
];
366 array_check
.array_mode
= array_mode
;
367 array_check
.group_size
= track
->group_size
;
368 array_check
.nbanks
= track
->nbanks
;
369 array_check
.npipes
= track
->npipes
;
370 array_check
.nsamples
= track
->nsamples
;
371 array_check
.blocksize
= fmt_get_blocksize(format
);
372 if (r600_get_array_mode_alignment(&array_check
,
373 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
374 dev_warn(p
->dev
, "%s invalid tiling %d for %d (0x%08X)\n", __func__
,
375 G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]), i
,
376 track
->cb_color_info
[i
]);
379 switch (array_mode
) {
380 case V_0280A0_ARRAY_LINEAR_GENERAL
:
382 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
384 case V_0280A0_ARRAY_1D_TILED_THIN1
:
385 /* avoid breaking userspace */
389 case V_0280A0_ARRAY_2D_TILED_THIN1
:
392 dev_warn(p
->dev
, "%s invalid tiling %d for %d (0x%08X)\n", __func__
,
393 G_0280A0_ARRAY_MODE(track
->cb_color_info
[i
]), i
,
394 track
->cb_color_info
[i
]);
398 if (!IS_ALIGNED(pitch
, pitch_align
)) {
399 dev_warn(p
->dev
, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
400 __func__
, __LINE__
, pitch
, pitch_align
, array_mode
);
403 if (!IS_ALIGNED(height
, height_align
)) {
404 dev_warn(p
->dev
, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
405 __func__
, __LINE__
, height
, height_align
, array_mode
);
408 if (!IS_ALIGNED(base_offset
, base_align
)) {
409 dev_warn(p
->dev
, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__
, i
,
410 base_offset
, base_align
, array_mode
);
415 tmp
= fmt_get_nblocksy(format
, height
) * fmt_get_nblocksx(format
, pitch
) * fmt_get_blocksize(format
);
416 if ((tmp
+ track
->cb_color_bo_offset
[i
]) > radeon_bo_size(track
->cb_color_bo
[i
])) {
417 if (array_mode
== V_0280A0_ARRAY_LINEAR_GENERAL
) {
418 /* the initial DDX does bad things with the CB size occasionally */
419 /* it rounds up height too far for slice tile max but the BO is smaller */
420 /* r600c,g also seem to flush at bad times in some apps resulting in
421 * bogus values here. So for linear just allow anything to avoid breaking
425 dev_warn(p
->dev
, "%s offset[%d] %d %d %d %lu too big\n", __func__
, i
,
427 track
->cb_color_bo_offset
[i
], tmp
,
428 radeon_bo_size(track
->cb_color_bo
[i
]));
433 tmp
= (height
* pitch
) >> 6;
434 if (tmp
< slice_tile_max
)
435 slice_tile_max
= tmp
;
436 tmp
= S_028060_PITCH_TILE_MAX((pitch
/ 8) - 1) |
437 S_028060_SLICE_TILE_MAX(slice_tile_max
- 1);
438 ib
[track
->cb_color_size_idx
[i
]] = tmp
;
442 static int r600_cs_track_check(struct radeon_cs_parser
*p
)
444 struct r600_cs_track
*track
= p
->track
;
447 volatile u32
*ib
= p
->ib
->ptr
;
449 /* on legacy kernel we don't perform advanced check */
452 /* we don't support out buffer yet */
453 if (track
->vgt_strmout_en
|| track
->vgt_strmout_buffer_en
) {
454 dev_warn(p
->dev
, "this kernel doesn't support SMX output buffer\n");
457 /* check that we have a cb for each enabled target, we don't check
458 * shader_mask because it seems mesa isn't always setting it :(
460 tmp
= track
->cb_target_mask
;
461 for (i
= 0; i
< 8; i
++) {
462 if ((tmp
>> (i
* 4)) & 0xF) {
463 /* at least one component is enabled */
464 if (track
->cb_color_bo
[i
] == NULL
) {
465 dev_warn(p
->dev
, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
466 __func__
, __LINE__
, track
->cb_target_mask
, track
->cb_shader_mask
, i
);
469 /* perform rewrite of CB_COLOR[0-7]_SIZE */
470 r
= r600_cs_track_validate_cb(p
, i
);
475 /* Check depth buffer */
476 if (G_028800_STENCIL_ENABLE(track
->db_depth_control
) ||
477 G_028800_Z_ENABLE(track
->db_depth_control
)) {
478 u32 nviews
, bpe
, ntiles
, size
, slice_tile_max
;
479 u32 height
, height_align
, pitch
, pitch_align
, depth_align
;
480 u64 base_offset
, base_align
;
481 struct array_mode_checker array_check
;
484 if (track
->db_bo
== NULL
) {
485 dev_warn(p
->dev
, "z/stencil with no depth buffer\n");
488 if (G_028010_TILE_SURFACE_ENABLE(track
->db_depth_info
)) {
489 dev_warn(p
->dev
, "this kernel doesn't support z/stencil htile\n");
492 switch (G_028010_FORMAT(track
->db_depth_info
)) {
493 case V_028010_DEPTH_16
:
496 case V_028010_DEPTH_X8_24
:
497 case V_028010_DEPTH_8_24
:
498 case V_028010_DEPTH_X8_24_FLOAT
:
499 case V_028010_DEPTH_8_24_FLOAT
:
500 case V_028010_DEPTH_32_FLOAT
:
503 case V_028010_DEPTH_X24_8_32_FLOAT
:
507 dev_warn(p
->dev
, "z/stencil with invalid format %d\n", G_028010_FORMAT(track
->db_depth_info
));
510 if ((track
->db_depth_size
& 0xFFFFFC00) == 0xFFFFFC00) {
511 if (!track
->db_depth_size_idx
) {
512 dev_warn(p
->dev
, "z/stencil buffer size not set\n");
515 tmp
= radeon_bo_size(track
->db_bo
) - track
->db_offset
;
516 tmp
= (tmp
/ bpe
) >> 6;
518 dev_warn(p
->dev
, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
519 track
->db_depth_size
, bpe
, track
->db_offset
,
520 radeon_bo_size(track
->db_bo
));
523 ib
[track
->db_depth_size_idx
] = S_028000_SLICE_TILE_MAX(tmp
- 1) | (track
->db_depth_size
& 0x3FF);
525 size
= radeon_bo_size(track
->db_bo
);
526 /* pitch in pixels */
527 pitch
= (G_028000_PITCH_TILE_MAX(track
->db_depth_size
) + 1) * 8;
528 slice_tile_max
= G_028000_SLICE_TILE_MAX(track
->db_depth_size
) + 1;
529 slice_tile_max
*= 64;
530 height
= slice_tile_max
/ pitch
;
533 base_offset
= track
->db_bo_mc
+ track
->db_offset
;
534 array_mode
= G_028010_ARRAY_MODE(track
->db_depth_info
);
535 array_check
.array_mode
= array_mode
;
536 array_check
.group_size
= track
->group_size
;
537 array_check
.nbanks
= track
->nbanks
;
538 array_check
.npipes
= track
->npipes
;
539 array_check
.nsamples
= track
->nsamples
;
540 array_check
.blocksize
= bpe
;
541 if (r600_get_array_mode_alignment(&array_check
,
542 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
543 dev_warn(p
->dev
, "%s invalid tiling %d (0x%08X)\n", __func__
,
544 G_028010_ARRAY_MODE(track
->db_depth_info
),
545 track
->db_depth_info
);
548 switch (array_mode
) {
549 case V_028010_ARRAY_1D_TILED_THIN1
:
550 /* don't break userspace */
553 case V_028010_ARRAY_2D_TILED_THIN1
:
556 dev_warn(p
->dev
, "%s invalid tiling %d (0x%08X)\n", __func__
,
557 G_028010_ARRAY_MODE(track
->db_depth_info
),
558 track
->db_depth_info
);
562 if (!IS_ALIGNED(pitch
, pitch_align
)) {
563 dev_warn(p
->dev
, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
564 __func__
, __LINE__
, pitch
, pitch_align
, array_mode
);
567 if (!IS_ALIGNED(height
, height_align
)) {
568 dev_warn(p
->dev
, "%s:%d db height (%d, 0x%x, %d) invalid\n",
569 __func__
, __LINE__
, height
, height_align
, array_mode
);
572 if (!IS_ALIGNED(base_offset
, base_align
)) {
573 dev_warn(p
->dev
, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__
, i
,
574 base_offset
, base_align
, array_mode
);
578 ntiles
= G_028000_SLICE_TILE_MAX(track
->db_depth_size
) + 1;
579 nviews
= G_028004_SLICE_MAX(track
->db_depth_view
) + 1;
580 tmp
= ntiles
* bpe
* 64 * nviews
;
581 if ((tmp
+ track
->db_offset
) > radeon_bo_size(track
->db_bo
)) {
582 dev_warn(p
->dev
, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
584 track
->db_depth_size
, ntiles
, nviews
, bpe
, tmp
+ track
->db_offset
,
585 radeon_bo_size(track
->db_bo
));
594 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
595 * @parser: parser structure holding parsing context.
596 * @pkt: where to store packet informations
598 * Assume that chunk_ib_index is properly set. Will return -EINVAL
599 * if packet is bigger than remaining ib size. or if packets is unknown.
601 int r600_cs_packet_parse(struct radeon_cs_parser
*p
,
602 struct radeon_cs_packet
*pkt
,
605 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
608 if (idx
>= ib_chunk
->length_dw
) {
609 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
610 idx
, ib_chunk
->length_dw
);
613 header
= radeon_get_ib_value(p
, idx
);
615 pkt
->type
= CP_PACKET_GET_TYPE(header
);
616 pkt
->count
= CP_PACKET_GET_COUNT(header
);
620 pkt
->reg
= CP_PACKET0_GET_REG(header
);
623 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
629 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
632 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
633 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
634 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
641 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
642 * @parser: parser structure holding parsing context.
643 * @data: pointer to relocation data
644 * @offset_start: starting offset
645 * @offset_mask: offset mask (to align start offset on)
646 * @reloc: reloc informations
648 * Check next packet is relocation packet3, do bo validation and compute
649 * GPU offset using the provided start.
651 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser
*p
,
652 struct radeon_cs_reloc
**cs_reloc
)
654 struct radeon_cs_chunk
*relocs_chunk
;
655 struct radeon_cs_packet p3reloc
;
659 if (p
->chunk_relocs_idx
== -1) {
660 DRM_ERROR("No relocation chunk !\n");
664 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
665 r
= r600_cs_packet_parse(p
, &p3reloc
, p
->idx
);
669 p
->idx
+= p3reloc
.count
+ 2;
670 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
671 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
675 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
676 if (idx
>= relocs_chunk
->length_dw
) {
677 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
678 idx
, relocs_chunk
->length_dw
);
681 /* FIXME: we assume reloc size is 4 dwords */
682 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
687 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
688 * @parser: parser structure holding parsing context.
689 * @data: pointer to relocation data
690 * @offset_start: starting offset
691 * @offset_mask: offset mask (to align start offset on)
692 * @reloc: reloc informations
694 * Check next packet is relocation packet3, do bo validation and compute
695 * GPU offset using the provided start.
697 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser
*p
,
698 struct radeon_cs_reloc
**cs_reloc
)
700 struct radeon_cs_chunk
*relocs_chunk
;
701 struct radeon_cs_packet p3reloc
;
705 if (p
->chunk_relocs_idx
== -1) {
706 DRM_ERROR("No relocation chunk !\n");
710 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
711 r
= r600_cs_packet_parse(p
, &p3reloc
, p
->idx
);
715 p
->idx
+= p3reloc
.count
+ 2;
716 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
717 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
721 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
722 if (idx
>= relocs_chunk
->length_dw
) {
723 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
724 idx
, relocs_chunk
->length_dw
);
727 *cs_reloc
= p
->relocs
;
728 (*cs_reloc
)->lobj
.gpu_offset
= (u64
)relocs_chunk
->kdata
[idx
+ 3] << 32;
729 (*cs_reloc
)->lobj
.gpu_offset
|= relocs_chunk
->kdata
[idx
+ 0];
734 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
735 * @parser: parser structure holding parsing context.
737 * Check next packet is relocation packet3, do bo validation and compute
738 * GPU offset using the provided start.
740 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser
*p
)
742 struct radeon_cs_packet p3reloc
;
745 r
= r600_cs_packet_parse(p
, &p3reloc
, p
->idx
);
749 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
756 * r600_cs_packet_next_vline() - parse userspace VLINE packet
757 * @parser: parser structure holding parsing context.
759 * Userspace sends a special sequence for VLINE waits.
760 * PACKET0 - VLINE_START_END + value
761 * PACKET3 - WAIT_REG_MEM poll vline status reg
762 * RELOC (P3) - crtc_id in reloc.
764 * This function parses this and relocates the VLINE START END
765 * and WAIT_REG_MEM packets to the correct crtc.
766 * It also detects a switched off crtc and nulls out the
769 static int r600_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
771 struct drm_mode_object
*obj
;
772 struct drm_crtc
*crtc
;
773 struct radeon_crtc
*radeon_crtc
;
774 struct radeon_cs_packet p3reloc
, wait_reg_mem
;
777 uint32_t header
, h_idx
, reg
, wait_reg_mem_info
;
778 volatile uint32_t *ib
;
782 /* parse the WAIT_REG_MEM */
783 r
= r600_cs_packet_parse(p
, &wait_reg_mem
, p
->idx
);
787 /* check its a WAIT_REG_MEM */
788 if (wait_reg_mem
.type
!= PACKET_TYPE3
||
789 wait_reg_mem
.opcode
!= PACKET3_WAIT_REG_MEM
) {
790 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
794 wait_reg_mem_info
= radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 1);
795 /* bit 4 is reg (0) or mem (1) */
796 if (wait_reg_mem_info
& 0x10) {
797 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
800 /* waiting for value to be equal */
801 if ((wait_reg_mem_info
& 0x7) != 0x3) {
802 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
805 if ((radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 2) << 2) != AVIVO_D1MODE_VLINE_STATUS
) {
806 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
810 if (radeon_get_ib_value(p
, wait_reg_mem
.idx
+ 5) != AVIVO_D1MODE_VLINE_STAT
) {
811 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
815 /* jump over the NOP */
816 r
= r600_cs_packet_parse(p
, &p3reloc
, p
->idx
+ wait_reg_mem
.count
+ 2);
821 p
->idx
+= wait_reg_mem
.count
+ 2;
822 p
->idx
+= p3reloc
.count
+ 2;
824 header
= radeon_get_ib_value(p
, h_idx
);
825 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 2 + 7 + 1);
826 reg
= CP_PACKET0_GET_REG(header
);
828 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
830 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
833 crtc
= obj_to_crtc(obj
);
834 radeon_crtc
= to_radeon_crtc(crtc
);
835 crtc_id
= radeon_crtc
->crtc_id
;
837 if (!crtc
->enabled
) {
838 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
839 ib
[h_idx
+ 2] = PACKET2(0);
840 ib
[h_idx
+ 3] = PACKET2(0);
841 ib
[h_idx
+ 4] = PACKET2(0);
842 ib
[h_idx
+ 5] = PACKET2(0);
843 ib
[h_idx
+ 6] = PACKET2(0);
844 ib
[h_idx
+ 7] = PACKET2(0);
845 ib
[h_idx
+ 8] = PACKET2(0);
846 } else if (crtc_id
== 1) {
848 case AVIVO_D1MODE_VLINE_START_END
:
849 header
&= ~R600_CP_PACKET0_REG_MASK
;
850 header
|= AVIVO_D2MODE_VLINE_START_END
>> 2;
853 DRM_ERROR("unknown crtc reloc\n");
857 ib
[h_idx
+ 4] = AVIVO_D2MODE_VLINE_STATUS
>> 2;
863 static int r600_packet0_check(struct radeon_cs_parser
*p
,
864 struct radeon_cs_packet
*pkt
,
865 unsigned idx
, unsigned reg
)
870 case AVIVO_D1MODE_VLINE_START_END
:
871 r
= r600_cs_packet_parse_vline(p
);
873 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
879 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
886 static int r600_cs_parse_packet0(struct radeon_cs_parser
*p
,
887 struct radeon_cs_packet
*pkt
)
895 for (i
= 0; i
<= pkt
->count
; i
++, idx
++, reg
+= 4) {
896 r
= r600_packet0_check(p
, pkt
, idx
, reg
);
905 * r600_cs_check_reg() - check if register is authorized or not
906 * @parser: parser structure holding parsing context
907 * @reg: register we are testing
908 * @idx: index into the cs buffer
910 * This function will test against r600_reg_safe_bm and return 0
911 * if register is safe. If register is not flag as safe this function
912 * will test it against a list of register needind special handling.
914 static inline int r600_cs_check_reg(struct radeon_cs_parser
*p
, u32 reg
, u32 idx
)
916 struct r600_cs_track
*track
= (struct r600_cs_track
*)p
->track
;
917 struct radeon_cs_reloc
*reloc
;
918 u32 last_reg
= ARRAY_SIZE(r600_reg_safe_bm
);
924 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
927 m
= 1 << ((reg
>> 2) & 31);
928 if (!(r600_reg_safe_bm
[i
] & m
))
932 /* force following reg to 0 in an attempt to disable out buffer
933 * which will need us to better understand how it works to perform
934 * security check on it (Jerome)
936 case R_0288A8_SQ_ESGS_RING_ITEMSIZE
:
937 case R_008C44_SQ_ESGS_RING_SIZE
:
938 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE
:
939 case R_008C54_SQ_ESTMP_RING_SIZE
:
940 case R_0288C0_SQ_FBUF_RING_ITEMSIZE
:
941 case R_008C74_SQ_FBUF_RING_SIZE
:
942 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE
:
943 case R_008C5C_SQ_GSTMP_RING_SIZE
:
944 case R_0288AC_SQ_GSVS_RING_ITEMSIZE
:
945 case R_008C4C_SQ_GSVS_RING_SIZE
:
946 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE
:
947 case R_008C6C_SQ_PSTMP_RING_SIZE
:
948 case R_0288C4_SQ_REDUC_RING_ITEMSIZE
:
949 case R_008C7C_SQ_REDUC_RING_SIZE
:
950 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE
:
951 case R_008C64_SQ_VSTMP_RING_SIZE
:
952 case R_0288C8_SQ_GS_VERT_ITEMSIZE
:
953 /* get value to populate the IB don't remove */
954 tmp
=radeon_get_ib_value(p
, idx
);
958 track
->sq_config
= radeon_get_ib_value(p
, idx
);
960 case R_028800_DB_DEPTH_CONTROL
:
961 track
->db_depth_control
= radeon_get_ib_value(p
, idx
);
963 case R_028010_DB_DEPTH_INFO
:
964 if (r600_cs_packet_next_is_pkt3_nop(p
)) {
965 r
= r600_cs_packet_next_reloc(p
, &reloc
);
967 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
971 track
->db_depth_info
= radeon_get_ib_value(p
, idx
);
972 ib
[idx
] &= C_028010_ARRAY_MODE
;
973 track
->db_depth_info
&= C_028010_ARRAY_MODE
;
974 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
975 ib
[idx
] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1
);
976 track
->db_depth_info
|= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1
);
978 ib
[idx
] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1
);
979 track
->db_depth_info
|= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1
);
982 track
->db_depth_info
= radeon_get_ib_value(p
, idx
);
984 case R_028004_DB_DEPTH_VIEW
:
985 track
->db_depth_view
= radeon_get_ib_value(p
, idx
);
987 case R_028000_DB_DEPTH_SIZE
:
988 track
->db_depth_size
= radeon_get_ib_value(p
, idx
);
989 track
->db_depth_size_idx
= idx
;
991 case R_028AB0_VGT_STRMOUT_EN
:
992 track
->vgt_strmout_en
= radeon_get_ib_value(p
, idx
);
994 case R_028B20_VGT_STRMOUT_BUFFER_EN
:
995 track
->vgt_strmout_buffer_en
= radeon_get_ib_value(p
, idx
);
997 case R_028238_CB_TARGET_MASK
:
998 track
->cb_target_mask
= radeon_get_ib_value(p
, idx
);
1000 case R_02823C_CB_SHADER_MASK
:
1001 track
->cb_shader_mask
= radeon_get_ib_value(p
, idx
);
1003 case R_028C04_PA_SC_AA_CONFIG
:
1004 tmp
= G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p
, idx
));
1005 track
->nsamples
= 1 << tmp
;
1007 case R_0280A0_CB_COLOR0_INFO
:
1008 case R_0280A4_CB_COLOR1_INFO
:
1009 case R_0280A8_CB_COLOR2_INFO
:
1010 case R_0280AC_CB_COLOR3_INFO
:
1011 case R_0280B0_CB_COLOR4_INFO
:
1012 case R_0280B4_CB_COLOR5_INFO
:
1013 case R_0280B8_CB_COLOR6_INFO
:
1014 case R_0280BC_CB_COLOR7_INFO
:
1015 if (r600_cs_packet_next_is_pkt3_nop(p
)) {
1016 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1018 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1021 tmp
= (reg
- R_0280A0_CB_COLOR0_INFO
) / 4;
1022 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1023 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
) {
1024 ib
[idx
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1
);
1025 track
->cb_color_info
[tmp
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1
);
1026 } else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
) {
1027 ib
[idx
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1
);
1028 track
->cb_color_info
[tmp
] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1
);
1031 tmp
= (reg
- R_0280A0_CB_COLOR0_INFO
) / 4;
1032 track
->cb_color_info
[tmp
] = radeon_get_ib_value(p
, idx
);
1035 case R_028060_CB_COLOR0_SIZE
:
1036 case R_028064_CB_COLOR1_SIZE
:
1037 case R_028068_CB_COLOR2_SIZE
:
1038 case R_02806C_CB_COLOR3_SIZE
:
1039 case R_028070_CB_COLOR4_SIZE
:
1040 case R_028074_CB_COLOR5_SIZE
:
1041 case R_028078_CB_COLOR6_SIZE
:
1042 case R_02807C_CB_COLOR7_SIZE
:
1043 tmp
= (reg
- R_028060_CB_COLOR0_SIZE
) / 4;
1044 track
->cb_color_size
[tmp
] = radeon_get_ib_value(p
, idx
);
1045 track
->cb_color_size_idx
[tmp
] = idx
;
1047 /* This register were added late, there is userspace
1048 * which does provide relocation for those but set
1049 * 0 offset. In order to avoid breaking old userspace
1050 * we detect this and set address to point to last
1051 * CB_COLOR0_BASE, note that if userspace doesn't set
1052 * CB_COLOR0_BASE before this register we will report
1053 * error. Old userspace always set CB_COLOR0_BASE
1054 * before any of this.
1056 case R_0280E0_CB_COLOR0_FRAG
:
1057 case R_0280E4_CB_COLOR1_FRAG
:
1058 case R_0280E8_CB_COLOR2_FRAG
:
1059 case R_0280EC_CB_COLOR3_FRAG
:
1060 case R_0280F0_CB_COLOR4_FRAG
:
1061 case R_0280F4_CB_COLOR5_FRAG
:
1062 case R_0280F8_CB_COLOR6_FRAG
:
1063 case R_0280FC_CB_COLOR7_FRAG
:
1064 tmp
= (reg
- R_0280E0_CB_COLOR0_FRAG
) / 4;
1065 if (!r600_cs_packet_next_is_pkt3_nop(p
)) {
1066 if (!track
->cb_color_base_last
[tmp
]) {
1067 dev_err(p
->dev
, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg
);
1070 ib
[idx
] = track
->cb_color_base_last
[tmp
];
1071 track
->cb_color_frag_bo
[tmp
] = track
->cb_color_bo
[tmp
];
1073 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1075 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1078 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1079 track
->cb_color_frag_bo
[tmp
] = reloc
->robj
;
1082 case R_0280C0_CB_COLOR0_TILE
:
1083 case R_0280C4_CB_COLOR1_TILE
:
1084 case R_0280C8_CB_COLOR2_TILE
:
1085 case R_0280CC_CB_COLOR3_TILE
:
1086 case R_0280D0_CB_COLOR4_TILE
:
1087 case R_0280D4_CB_COLOR5_TILE
:
1088 case R_0280D8_CB_COLOR6_TILE
:
1089 case R_0280DC_CB_COLOR7_TILE
:
1090 tmp
= (reg
- R_0280C0_CB_COLOR0_TILE
) / 4;
1091 if (!r600_cs_packet_next_is_pkt3_nop(p
)) {
1092 if (!track
->cb_color_base_last
[tmp
]) {
1093 dev_err(p
->dev
, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg
);
1096 ib
[idx
] = track
->cb_color_base_last
[tmp
];
1097 track
->cb_color_tile_bo
[tmp
] = track
->cb_color_bo
[tmp
];
1099 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1101 dev_err(p
->dev
, "bad SET_CONTEXT_REG 0x%04X\n", reg
);
1104 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1105 track
->cb_color_tile_bo
[tmp
] = reloc
->robj
;
1108 case CB_COLOR0_BASE
:
1109 case CB_COLOR1_BASE
:
1110 case CB_COLOR2_BASE
:
1111 case CB_COLOR3_BASE
:
1112 case CB_COLOR4_BASE
:
1113 case CB_COLOR5_BASE
:
1114 case CB_COLOR6_BASE
:
1115 case CB_COLOR7_BASE
:
1116 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1118 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1122 tmp
= (reg
- CB_COLOR0_BASE
) / 4;
1123 track
->cb_color_bo_offset
[tmp
] = radeon_get_ib_value(p
, idx
) << 8;
1124 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1125 track
->cb_color_base_last
[tmp
] = ib
[idx
];
1126 track
->cb_color_bo
[tmp
] = reloc
->robj
;
1127 track
->cb_color_bo_mc
[tmp
] = reloc
->lobj
.gpu_offset
;
1130 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1132 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1136 track
->db_offset
= radeon_get_ib_value(p
, idx
) << 8;
1137 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1138 track
->db_bo
= reloc
->robj
;
1139 track
->db_bo_mc
= reloc
->lobj
.gpu_offset
;
1141 case DB_HTILE_DATA_BASE
:
1142 case SQ_PGM_START_FS
:
1143 case SQ_PGM_START_ES
:
1144 case SQ_PGM_START_VS
:
1145 case SQ_PGM_START_GS
:
1146 case SQ_PGM_START_PS
:
1147 case SQ_ALU_CONST_CACHE_GS_0
:
1148 case SQ_ALU_CONST_CACHE_GS_1
:
1149 case SQ_ALU_CONST_CACHE_GS_2
:
1150 case SQ_ALU_CONST_CACHE_GS_3
:
1151 case SQ_ALU_CONST_CACHE_GS_4
:
1152 case SQ_ALU_CONST_CACHE_GS_5
:
1153 case SQ_ALU_CONST_CACHE_GS_6
:
1154 case SQ_ALU_CONST_CACHE_GS_7
:
1155 case SQ_ALU_CONST_CACHE_GS_8
:
1156 case SQ_ALU_CONST_CACHE_GS_9
:
1157 case SQ_ALU_CONST_CACHE_GS_10
:
1158 case SQ_ALU_CONST_CACHE_GS_11
:
1159 case SQ_ALU_CONST_CACHE_GS_12
:
1160 case SQ_ALU_CONST_CACHE_GS_13
:
1161 case SQ_ALU_CONST_CACHE_GS_14
:
1162 case SQ_ALU_CONST_CACHE_GS_15
:
1163 case SQ_ALU_CONST_CACHE_PS_0
:
1164 case SQ_ALU_CONST_CACHE_PS_1
:
1165 case SQ_ALU_CONST_CACHE_PS_2
:
1166 case SQ_ALU_CONST_CACHE_PS_3
:
1167 case SQ_ALU_CONST_CACHE_PS_4
:
1168 case SQ_ALU_CONST_CACHE_PS_5
:
1169 case SQ_ALU_CONST_CACHE_PS_6
:
1170 case SQ_ALU_CONST_CACHE_PS_7
:
1171 case SQ_ALU_CONST_CACHE_PS_8
:
1172 case SQ_ALU_CONST_CACHE_PS_9
:
1173 case SQ_ALU_CONST_CACHE_PS_10
:
1174 case SQ_ALU_CONST_CACHE_PS_11
:
1175 case SQ_ALU_CONST_CACHE_PS_12
:
1176 case SQ_ALU_CONST_CACHE_PS_13
:
1177 case SQ_ALU_CONST_CACHE_PS_14
:
1178 case SQ_ALU_CONST_CACHE_PS_15
:
1179 case SQ_ALU_CONST_CACHE_VS_0
:
1180 case SQ_ALU_CONST_CACHE_VS_1
:
1181 case SQ_ALU_CONST_CACHE_VS_2
:
1182 case SQ_ALU_CONST_CACHE_VS_3
:
1183 case SQ_ALU_CONST_CACHE_VS_4
:
1184 case SQ_ALU_CONST_CACHE_VS_5
:
1185 case SQ_ALU_CONST_CACHE_VS_6
:
1186 case SQ_ALU_CONST_CACHE_VS_7
:
1187 case SQ_ALU_CONST_CACHE_VS_8
:
1188 case SQ_ALU_CONST_CACHE_VS_9
:
1189 case SQ_ALU_CONST_CACHE_VS_10
:
1190 case SQ_ALU_CONST_CACHE_VS_11
:
1191 case SQ_ALU_CONST_CACHE_VS_12
:
1192 case SQ_ALU_CONST_CACHE_VS_13
:
1193 case SQ_ALU_CONST_CACHE_VS_14
:
1194 case SQ_ALU_CONST_CACHE_VS_15
:
1195 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1197 dev_warn(p
->dev
, "bad SET_CONTEXT_REG "
1201 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1203 case SX_MEMORY_EXPORT_BASE
:
1204 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1206 dev_warn(p
->dev
, "bad SET_CONFIG_REG "
1210 ib
[idx
] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1213 dev_warn(p
->dev
, "forbidden register 0x%08x at %d\n", reg
, idx
);
1219 static inline unsigned mip_minify(unsigned size
, unsigned level
)
1223 val
= max(1U, size
>> level
);
1225 val
= roundup_pow_of_two(val
);
1229 static void r600_texture_size(unsigned nfaces
, unsigned blevel
, unsigned llevel
,
1230 unsigned w0
, unsigned h0
, unsigned d0
, unsigned format
,
1231 unsigned block_align
, unsigned height_align
, unsigned base_align
,
1232 unsigned *l0_size
, unsigned *mipmap_size
)
1234 unsigned offset
, i
, level
;
1235 unsigned width
, height
, depth
, size
;
1238 unsigned nlevels
= llevel
- blevel
+ 1;
1241 blocksize
= fmt_get_blocksize(format
);
1243 w0
= mip_minify(w0
, 0);
1244 h0
= mip_minify(h0
, 0);
1245 d0
= mip_minify(d0
, 0);
1246 for(i
= 0, offset
= 0, level
= blevel
; i
< nlevels
; i
++, level
++) {
1247 width
= mip_minify(w0
, i
);
1248 nbx
= fmt_get_nblocksx(format
, width
);
1250 nbx
= round_up(nbx
, block_align
);
1252 height
= mip_minify(h0
, i
);
1253 nby
= fmt_get_nblocksy(format
, height
);
1254 nby
= round_up(nby
, height_align
);
1256 depth
= mip_minify(d0
, i
);
1258 size
= nbx
* nby
* blocksize
;
1267 if (i
== 0 || i
== 1)
1268 offset
= round_up(offset
, base_align
);
1272 *mipmap_size
= offset
;
1274 *mipmap_size
= *l0_size
;
1276 *mipmap_size
-= *l0_size
;
1280 * r600_check_texture_resource() - check if register is authorized or not
1281 * @p: parser structure holding parsing context
1282 * @idx: index into the cs buffer
1283 * @texture: texture's bo structure
1284 * @mipmap: mipmap's bo structure
1286 * This function will check that the resource has valid field and that
1287 * the texture and mipmap bo object are big enough to cover this resource.
1289 static inline int r600_check_texture_resource(struct radeon_cs_parser
*p
, u32 idx
,
1290 struct radeon_bo
*texture
,
1291 struct radeon_bo
*mipmap
,
1296 struct r600_cs_track
*track
= p
->track
;
1297 u32 nfaces
, llevel
, blevel
, w0
, h0
, d0
;
1298 u32 word0
, word1
, l0_size
, mipmap_size
, word2
, word3
;
1299 u32 height_align
, pitch
, pitch_align
, depth_align
;
1300 u32 array
, barray
, larray
;
1302 struct array_mode_checker array_check
;
1305 /* on legacy kernel we don't perform advanced check */
1306 if (p
->rdev
== NULL
)
1309 /* convert to bytes */
1313 word0
= radeon_get_ib_value(p
, idx
+ 0);
1314 if (tiling_flags
& RADEON_TILING_MACRO
)
1315 word0
|= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1316 else if (tiling_flags
& RADEON_TILING_MICRO
)
1317 word0
|= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1318 word1
= radeon_get_ib_value(p
, idx
+ 1);
1319 w0
= G_038000_TEX_WIDTH(word0
) + 1;
1320 h0
= G_038004_TEX_HEIGHT(word1
) + 1;
1321 d0
= G_038004_TEX_DEPTH(word1
);
1323 switch (G_038000_DIM(word0
)) {
1324 case V_038000_SQ_TEX_DIM_1D
:
1325 case V_038000_SQ_TEX_DIM_2D
:
1326 case V_038000_SQ_TEX_DIM_3D
:
1328 case V_038000_SQ_TEX_DIM_CUBEMAP
:
1329 if (p
->family
>= CHIP_RV770
)
1334 case V_038000_SQ_TEX_DIM_1D_ARRAY
:
1335 case V_038000_SQ_TEX_DIM_2D_ARRAY
:
1338 case V_038000_SQ_TEX_DIM_2D_MSAA
:
1339 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
1341 dev_warn(p
->dev
, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0
));
1344 format
= G_038004_DATA_FORMAT(word1
);
1345 if (!fmt_is_valid_texture(format
, p
->family
)) {
1346 dev_warn(p
->dev
, "%s:%d texture invalid format %d\n",
1347 __func__
, __LINE__
, format
);
1351 /* pitch in texels */
1352 pitch
= (G_038000_PITCH(word0
) + 1) * 8;
1353 array_check
.array_mode
= G_038000_TILE_MODE(word0
);
1354 array_check
.group_size
= track
->group_size
;
1355 array_check
.nbanks
= track
->nbanks
;
1356 array_check
.npipes
= track
->npipes
;
1357 array_check
.nsamples
= 1;
1358 array_check
.blocksize
= fmt_get_blocksize(format
);
1359 if (r600_get_array_mode_alignment(&array_check
,
1360 &pitch_align
, &height_align
, &depth_align
, &base_align
)) {
1361 dev_warn(p
->dev
, "%s:%d tex array mode (%d) invalid\n",
1362 __func__
, __LINE__
, G_038000_TILE_MODE(word0
));
1366 /* XXX check height as well... */
1368 if (!IS_ALIGNED(pitch
, pitch_align
)) {
1369 dev_warn(p
->dev
, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1370 __func__
, __LINE__
, pitch
, pitch_align
, G_038000_TILE_MODE(word0
));
1373 if (!IS_ALIGNED(base_offset
, base_align
)) {
1374 dev_warn(p
->dev
, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1375 __func__
, __LINE__
, base_offset
, base_align
, G_038000_TILE_MODE(word0
));
1378 if (!IS_ALIGNED(mip_offset
, base_align
)) {
1379 dev_warn(p
->dev
, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1380 __func__
, __LINE__
, mip_offset
, base_align
, G_038000_TILE_MODE(word0
));
1384 word2
= radeon_get_ib_value(p
, idx
+ 2) << 8;
1385 word3
= radeon_get_ib_value(p
, idx
+ 3) << 8;
1387 word0
= radeon_get_ib_value(p
, idx
+ 4);
1388 word1
= radeon_get_ib_value(p
, idx
+ 5);
1389 blevel
= G_038010_BASE_LEVEL(word0
);
1390 llevel
= G_038014_LAST_LEVEL(word1
);
1392 barray
= G_038014_BASE_ARRAY(word1
);
1393 larray
= G_038014_LAST_ARRAY(word1
);
1395 nfaces
= larray
- barray
+ 1;
1397 r600_texture_size(nfaces
, blevel
, llevel
, w0
, h0
, d0
, format
,
1398 pitch_align
, height_align
, base_align
,
1399 &l0_size
, &mipmap_size
);
1400 /* using get ib will give us the offset into the texture bo */
1401 if ((l0_size
+ word2
) > radeon_bo_size(texture
)) {
1402 dev_warn(p
->dev
, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1403 w0
, h0
, format
, word2
, l0_size
, radeon_bo_size(texture
));
1404 dev_warn(p
->dev
, "alignments %d %d %d %lld\n", pitch
, pitch_align
, height_align
, base_align
);
1407 /* using get ib will give us the offset into the mipmap bo */
1408 word3
= radeon_get_ib_value(p
, idx
+ 3) << 8;
1409 if ((mipmap_size
+ word3
) > radeon_bo_size(mipmap
)) {
1410 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1411 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1416 static int r600_packet3_check(struct radeon_cs_parser
*p
,
1417 struct radeon_cs_packet
*pkt
)
1419 struct radeon_cs_reloc
*reloc
;
1420 struct r600_cs_track
*track
;
1424 unsigned start_reg
, end_reg
, reg
;
1428 track
= (struct r600_cs_track
*)p
->track
;
1431 idx_value
= radeon_get_ib_value(p
, idx
);
1433 switch (pkt
->opcode
) {
1434 case PACKET3_SET_PREDICATION
:
1438 if (pkt
->count
!= 1) {
1439 DRM_ERROR("bad SET PREDICATION\n");
1443 tmp
= radeon_get_ib_value(p
, idx
+ 1);
1444 pred_op
= (tmp
>> 16) & 0x7;
1446 /* for the clear predicate operation */
1451 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op
);
1455 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1457 DRM_ERROR("bad SET PREDICATION\n");
1461 ib
[idx
+ 0] = idx_value
+ (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
1462 ib
[idx
+ 1] = tmp
+ (upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff);
1466 case PACKET3_START_3D_CMDBUF
:
1467 if (p
->family
>= CHIP_RV770
|| pkt
->count
) {
1468 DRM_ERROR("bad START_3D\n");
1472 case PACKET3_CONTEXT_CONTROL
:
1473 if (pkt
->count
!= 1) {
1474 DRM_ERROR("bad CONTEXT_CONTROL\n");
1478 case PACKET3_INDEX_TYPE
:
1479 case PACKET3_NUM_INSTANCES
:
1481 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1485 case PACKET3_DRAW_INDEX
:
1486 if (pkt
->count
!= 3) {
1487 DRM_ERROR("bad DRAW_INDEX\n");
1490 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1492 DRM_ERROR("bad DRAW_INDEX\n");
1495 ib
[idx
+0] = idx_value
+ (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
1496 ib
[idx
+1] += upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff;
1497 r
= r600_cs_track_check(p
);
1499 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
1503 case PACKET3_DRAW_INDEX_AUTO
:
1504 if (pkt
->count
!= 1) {
1505 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1508 r
= r600_cs_track_check(p
);
1510 dev_warn(p
->dev
, "%s:%d invalid cmd stream %d\n", __func__
, __LINE__
, idx
);
1514 case PACKET3_DRAW_INDEX_IMMD_BE
:
1515 case PACKET3_DRAW_INDEX_IMMD
:
1516 if (pkt
->count
< 2) {
1517 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1520 r
= r600_cs_track_check(p
);
1522 dev_warn(p
->dev
, "%s:%d invalid cmd stream\n", __func__
, __LINE__
);
1526 case PACKET3_WAIT_REG_MEM
:
1527 if (pkt
->count
!= 5) {
1528 DRM_ERROR("bad WAIT_REG_MEM\n");
1531 /* bit 4 is reg (0) or mem (1) */
1532 if (idx_value
& 0x10) {
1533 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1535 DRM_ERROR("bad WAIT_REG_MEM\n");
1538 ib
[idx
+1] += (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
1539 ib
[idx
+2] += upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff;
1542 case PACKET3_SURFACE_SYNC
:
1543 if (pkt
->count
!= 3) {
1544 DRM_ERROR("bad SURFACE_SYNC\n");
1547 /* 0xffffffff/0x0 is flush all cache flag */
1548 if (radeon_get_ib_value(p
, idx
+ 1) != 0xffffffff ||
1549 radeon_get_ib_value(p
, idx
+ 2) != 0) {
1550 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1552 DRM_ERROR("bad SURFACE_SYNC\n");
1555 ib
[idx
+2] += (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1558 case PACKET3_EVENT_WRITE
:
1559 if (pkt
->count
!= 2 && pkt
->count
!= 0) {
1560 DRM_ERROR("bad EVENT_WRITE\n");
1564 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1566 DRM_ERROR("bad EVENT_WRITE\n");
1569 ib
[idx
+1] += (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
1570 ib
[idx
+2] += upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff;
1573 case PACKET3_EVENT_WRITE_EOP
:
1574 if (pkt
->count
!= 4) {
1575 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1578 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1580 DRM_ERROR("bad EVENT_WRITE\n");
1583 ib
[idx
+1] += (u32
)(reloc
->lobj
.gpu_offset
& 0xffffffff);
1584 ib
[idx
+2] += upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff;
1586 case PACKET3_SET_CONFIG_REG
:
1587 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONFIG_REG_OFFSET
;
1588 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1589 if ((start_reg
< PACKET3_SET_CONFIG_REG_OFFSET
) ||
1590 (start_reg
>= PACKET3_SET_CONFIG_REG_END
) ||
1591 (end_reg
>= PACKET3_SET_CONFIG_REG_END
)) {
1592 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1595 for (i
= 0; i
< pkt
->count
; i
++) {
1596 reg
= start_reg
+ (4 * i
);
1597 r
= r600_cs_check_reg(p
, reg
, idx
+1+i
);
1602 case PACKET3_SET_CONTEXT_REG
:
1603 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONTEXT_REG_OFFSET
;
1604 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1605 if ((start_reg
< PACKET3_SET_CONTEXT_REG_OFFSET
) ||
1606 (start_reg
>= PACKET3_SET_CONTEXT_REG_END
) ||
1607 (end_reg
>= PACKET3_SET_CONTEXT_REG_END
)) {
1608 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1611 for (i
= 0; i
< pkt
->count
; i
++) {
1612 reg
= start_reg
+ (4 * i
);
1613 r
= r600_cs_check_reg(p
, reg
, idx
+1+i
);
1618 case PACKET3_SET_RESOURCE
:
1619 if (pkt
->count
% 7) {
1620 DRM_ERROR("bad SET_RESOURCE\n");
1623 start_reg
= (idx_value
<< 2) + PACKET3_SET_RESOURCE_OFFSET
;
1624 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1625 if ((start_reg
< PACKET3_SET_RESOURCE_OFFSET
) ||
1626 (start_reg
>= PACKET3_SET_RESOURCE_END
) ||
1627 (end_reg
>= PACKET3_SET_RESOURCE_END
)) {
1628 DRM_ERROR("bad SET_RESOURCE\n");
1631 for (i
= 0; i
< (pkt
->count
/ 7); i
++) {
1632 struct radeon_bo
*texture
, *mipmap
;
1633 u32 size
, offset
, base_offset
, mip_offset
;
1635 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p
, idx
+(i
*7)+6+1))) {
1636 case SQ_TEX_VTX_VALID_TEXTURE
:
1638 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1640 DRM_ERROR("bad SET_RESOURCE\n");
1643 base_offset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1644 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1645 ib
[idx
+1+(i
*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1646 else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1647 ib
[idx
+1+(i
*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1648 texture
= reloc
->robj
;
1650 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1652 DRM_ERROR("bad SET_RESOURCE\n");
1655 mip_offset
= (u32
)((reloc
->lobj
.gpu_offset
>> 8) & 0xffffffff);
1656 mipmap
= reloc
->robj
;
1657 r
= r600_check_texture_resource(p
, idx
+(i
*7)+1,
1659 base_offset
+ radeon_get_ib_value(p
, idx
+1+(i
*7)+2),
1660 mip_offset
+ radeon_get_ib_value(p
, idx
+1+(i
*7)+3),
1661 reloc
->lobj
.tiling_flags
);
1664 ib
[idx
+1+(i
*7)+2] += base_offset
;
1665 ib
[idx
+1+(i
*7)+3] += mip_offset
;
1667 case SQ_TEX_VTX_VALID_BUFFER
:
1669 r
= r600_cs_packet_next_reloc(p
, &reloc
);
1671 DRM_ERROR("bad SET_RESOURCE\n");
1674 offset
= radeon_get_ib_value(p
, idx
+1+(i
*7)+0);
1675 size
= radeon_get_ib_value(p
, idx
+1+(i
*7)+1) + 1;
1676 if (p
->rdev
&& (size
+ offset
) > radeon_bo_size(reloc
->robj
)) {
1677 /* force size to size of the buffer */
1678 dev_warn(p
->dev
, "vbo resource seems too big (%d) for the bo (%ld)\n",
1679 size
+ offset
, radeon_bo_size(reloc
->robj
));
1680 ib
[idx
+1+(i
*7)+1] = radeon_bo_size(reloc
->robj
);
1682 ib
[idx
+1+(i
*7)+0] += (u32
)((reloc
->lobj
.gpu_offset
) & 0xffffffff);
1683 ib
[idx
+1+(i
*7)+2] += upper_32_bits(reloc
->lobj
.gpu_offset
) & 0xff;
1685 case SQ_TEX_VTX_INVALID_TEXTURE
:
1686 case SQ_TEX_VTX_INVALID_BUFFER
:
1688 DRM_ERROR("bad SET_RESOURCE\n");
1693 case PACKET3_SET_ALU_CONST
:
1694 if (track
->sq_config
& DX9_CONSTS
) {
1695 start_reg
= (idx_value
<< 2) + PACKET3_SET_ALU_CONST_OFFSET
;
1696 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1697 if ((start_reg
< PACKET3_SET_ALU_CONST_OFFSET
) ||
1698 (start_reg
>= PACKET3_SET_ALU_CONST_END
) ||
1699 (end_reg
>= PACKET3_SET_ALU_CONST_END
)) {
1700 DRM_ERROR("bad SET_ALU_CONST\n");
1705 case PACKET3_SET_BOOL_CONST
:
1706 start_reg
= (idx_value
<< 2) + PACKET3_SET_BOOL_CONST_OFFSET
;
1707 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1708 if ((start_reg
< PACKET3_SET_BOOL_CONST_OFFSET
) ||
1709 (start_reg
>= PACKET3_SET_BOOL_CONST_END
) ||
1710 (end_reg
>= PACKET3_SET_BOOL_CONST_END
)) {
1711 DRM_ERROR("bad SET_BOOL_CONST\n");
1715 case PACKET3_SET_LOOP_CONST
:
1716 start_reg
= (idx_value
<< 2) + PACKET3_SET_LOOP_CONST_OFFSET
;
1717 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1718 if ((start_reg
< PACKET3_SET_LOOP_CONST_OFFSET
) ||
1719 (start_reg
>= PACKET3_SET_LOOP_CONST_END
) ||
1720 (end_reg
>= PACKET3_SET_LOOP_CONST_END
)) {
1721 DRM_ERROR("bad SET_LOOP_CONST\n");
1725 case PACKET3_SET_CTL_CONST
:
1726 start_reg
= (idx_value
<< 2) + PACKET3_SET_CTL_CONST_OFFSET
;
1727 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1728 if ((start_reg
< PACKET3_SET_CTL_CONST_OFFSET
) ||
1729 (start_reg
>= PACKET3_SET_CTL_CONST_END
) ||
1730 (end_reg
>= PACKET3_SET_CTL_CONST_END
)) {
1731 DRM_ERROR("bad SET_CTL_CONST\n");
1735 case PACKET3_SET_SAMPLER
:
1736 if (pkt
->count
% 3) {
1737 DRM_ERROR("bad SET_SAMPLER\n");
1740 start_reg
= (idx_value
<< 2) + PACKET3_SET_SAMPLER_OFFSET
;
1741 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
1742 if ((start_reg
< PACKET3_SET_SAMPLER_OFFSET
) ||
1743 (start_reg
>= PACKET3_SET_SAMPLER_END
) ||
1744 (end_reg
>= PACKET3_SET_SAMPLER_END
)) {
1745 DRM_ERROR("bad SET_SAMPLER\n");
1749 case PACKET3_SURFACE_BASE_UPDATE
:
1750 if (p
->family
>= CHIP_RV770
|| p
->family
== CHIP_R600
) {
1751 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1755 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1762 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1768 int r600_cs_parse(struct radeon_cs_parser
*p
)
1770 struct radeon_cs_packet pkt
;
1771 struct r600_cs_track
*track
;
1774 if (p
->track
== NULL
) {
1775 /* initialize tracker, we are in kms */
1776 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1779 r600_cs_track_init(track
);
1780 if (p
->rdev
->family
< CHIP_RV770
) {
1781 track
->npipes
= p
->rdev
->config
.r600
.tiling_npipes
;
1782 track
->nbanks
= p
->rdev
->config
.r600
.tiling_nbanks
;
1783 track
->group_size
= p
->rdev
->config
.r600
.tiling_group_size
;
1784 } else if (p
->rdev
->family
<= CHIP_RV740
) {
1785 track
->npipes
= p
->rdev
->config
.rv770
.tiling_npipes
;
1786 track
->nbanks
= p
->rdev
->config
.rv770
.tiling_nbanks
;
1787 track
->group_size
= p
->rdev
->config
.rv770
.tiling_group_size
;
1792 r
= r600_cs_packet_parse(p
, &pkt
, p
->idx
);
1798 p
->idx
+= pkt
.count
+ 2;
1801 r
= r600_cs_parse_packet0(p
, &pkt
);
1806 r
= r600_packet3_check(p
, &pkt
);
1809 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
1819 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1821 for (r
= 0; r
< p
->ib
->length_dw
; r
++) {
1822 printk(KERN_INFO
"%05d 0x%08X\n", r
, p
->ib
->ptr
[r
]);
1831 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser
*p
)
1833 if (p
->chunk_relocs_idx
== -1) {
1836 p
->relocs
= kzalloc(sizeof(struct radeon_cs_reloc
), GFP_KERNEL
);
1837 if (p
->relocs
== NULL
) {
1844 * cs_parser_fini() - clean parser states
1845 * @parser: parser structure holding parsing context.
1846 * @error: error number
1848 * If error is set than unvalidate buffer, otherwise just free memory
1849 * used by parsing context.
1851 static void r600_cs_parser_fini(struct radeon_cs_parser
*parser
, int error
)
1855 kfree(parser
->relocs
);
1856 for (i
= 0; i
< parser
->nchunks
; i
++) {
1857 kfree(parser
->chunks
[i
].kdata
);
1858 kfree(parser
->chunks
[i
].kpage
[0]);
1859 kfree(parser
->chunks
[i
].kpage
[1]);
1861 kfree(parser
->chunks
);
1862 kfree(parser
->chunks_array
);
1865 int r600_cs_legacy(struct drm_device
*dev
, void *data
, struct drm_file
*filp
,
1866 unsigned family
, u32
*ib
, int *l
)
1868 struct radeon_cs_parser parser
;
1869 struct radeon_cs_chunk
*ib_chunk
;
1870 struct radeon_ib fake_ib
;
1871 struct r600_cs_track
*track
;
1874 /* initialize tracker */
1875 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1878 r600_cs_track_init(track
);
1879 r600_cs_legacy_get_tiling_conf(dev
, &track
->npipes
, &track
->nbanks
, &track
->group_size
);
1880 /* initialize parser */
1881 memset(&parser
, 0, sizeof(struct radeon_cs_parser
));
1883 parser
.dev
= &dev
->pdev
->dev
;
1885 parser
.family
= family
;
1886 parser
.ib
= &fake_ib
;
1887 parser
.track
= track
;
1889 r
= radeon_cs_parser_init(&parser
, data
);
1891 DRM_ERROR("Failed to initialize parser !\n");
1892 r600_cs_parser_fini(&parser
, r
);
1895 r
= r600_cs_parser_relocs_legacy(&parser
);
1897 DRM_ERROR("Failed to parse relocation !\n");
1898 r600_cs_parser_fini(&parser
, r
);
1901 /* Copy the packet into the IB, the parser will read from the
1902 * input memory (cached) and write to the IB (which can be
1904 ib_chunk
= &parser
.chunks
[parser
.chunk_ib_idx
];
1905 parser
.ib
->length_dw
= ib_chunk
->length_dw
;
1906 *l
= parser
.ib
->length_dw
;
1907 r
= r600_cs_parse(&parser
);
1909 DRM_ERROR("Invalid command stream !\n");
1910 r600_cs_parser_fini(&parser
, r
);
1913 r
= radeon_cs_finish_pages(&parser
);
1915 DRM_ERROR("Invalid command stream !\n");
1916 r600_cs_parser_fini(&parser
, r
);
1919 r600_cs_parser_fini(&parser
, r
);
1923 void r600_cs_legacy_init(void)
1925 r600_cs_packet_next_reloc
= &r600_cs_packet_next_reloc_nomm
;