drivers/gpu/drm/radeon/r600_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  */
  26 #include <linux/hdmi.h>
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "r600d.h"
  32 #include "atom.h"
  33
  34 /*
  35  * HDMI color format
  36  */
  37 enum r600_hdmi_color_format {
  38         RGB = 0,
  39         YCC_422 = 1,
  40         YCC_444 = 2
  41 };
  42
  43 /*
  44  * IEC60958 status bits
  45  */
  46 enum r600_hdmi_iec_status_bits {
  47         AUDIO_STATUS_DIG_ENABLE   = 0x01,
  48         AUDIO_STATUS_V            = 0x02,
  49         AUDIO_STATUS_VCFG         = 0x04,
  50         AUDIO_STATUS_EMPHASIS     = 0x08,
  51         AUDIO_STATUS_COPYRIGHT    = 0x10,
  52         AUDIO_STATUS_NONAUDIO     = 0x20,
  53         AUDIO_STATUS_PROFESSIONAL = 0x40,
  54         AUDIO_STATUS_LEVEL        = 0x80
  55 };
  56
  57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
  58     /*       32kHz        44.1kHz       48kHz    */
  59     /* Clock      N     CTS      N     CTS      N     CTS */
  60     {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
  61     {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
  62     {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
  63     {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
  64     {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
  65     {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
  66     {  74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /*  74.25/1.001 MHz */
  67     {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
  68     { 148351, 11648, 421875,  8918, 234375,  5824, 140625 }, /* 148.50/1.001 MHz */
  69     { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
  70     {      0,  4096,      0,  6272,      0,  6144,      0 }  /* Other */
  71 };
  72
  73 /*
  74  * calculate CTS value if it's not found in the table
  75  */
  76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
  77 {
  78         if (*CTS == 0)
  79                 *CTS = clock * N / (128 * freq) * 1000;
  80         DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
  81                   N, *CTS, freq);
  82 }
  83
  84 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
  85 {
  86         struct radeon_hdmi_acr res;
  87         u8 i;
  88
  89         for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
  90              r600_hdmi_predefined_acr[i].clock != 0; i++)
  91                 ;
  92         res = r600_hdmi_predefined_acr[i];
  93
  94         /* In case some CTS are missing */
  95         r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
  96         r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
  97         r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
  98
  99         return res;
 100 }
 101
 102 /*
 103  * update the N and CTS parameters for a given pixel clock rate
 104  */
 105 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
 106 {
 107         struct drm_device *dev = encoder->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
 110         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 111         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 112         uint32_t offset = dig->afmt->offset;
 113
 114         WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
 115         WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
 116
 117         WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
 118         WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
 119
 120         WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
 121         WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
 122 }
 123
 124 /*
 125  * build a HDMI Video Info Frame
 126  */
 127 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 128                                            void *buffer, size_t size)
 129 {
 130         struct drm_device *dev = encoder->dev;
 131         struct radeon_device *rdev = dev->dev_private;
 132         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 133         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 134         uint32_t offset = dig->afmt->offset;
 135         uint8_t *frame = buffer + 3;
 136         uint8_t *header = buffer;
 137
 138         WREG32(HDMI0_AVI_INFO0 + offset,
 139                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 140         WREG32(HDMI0_AVI_INFO1 + offset,
 141                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 142         WREG32(HDMI0_AVI_INFO2 + offset,
 143                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 144         WREG32(HDMI0_AVI_INFO3 + offset,
 145                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 146 }
 147
 148 /*
 149  * build a Audio Info Frame
 150  */
 151 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
 152                                              const void *buffer, size_t size)
 153 {
 154         struct drm_device *dev = encoder->dev;
 155         struct radeon_device *rdev = dev->dev_private;
 156         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 157         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 158         uint32_t offset = dig->afmt->offset;
 159         const u8 *frame = buffer + 3;
 160
 161         WREG32(HDMI0_AUDIO_INFO0 + offset,
 162                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 163         WREG32(HDMI0_AUDIO_INFO1 + offset,
 164                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
 165 }
 166
 167 /*
 168  * test if audio buffer is filled enough to start playing
 169  */
 170 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 175         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 176         uint32_t offset = dig->afmt->offset;
 177
 178         return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
 179 }
 180
 181 /*
 182  * have buffer status changed since last call?
 183  */
 184 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
 185 {
 186         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 187         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 188         int status, result;
 189
 190         if (!dig->afmt || !dig->afmt->enabled)
 191                 return 0;
 192
 193         status = r600_hdmi_is_audio_buffer_filled(encoder);
 194         result = dig->afmt->last_buffer_filled_status != status;
 195         dig->afmt->last_buffer_filled_status = status;
 196
 197         return result;
 198 }
 199
 200 /*
 201  * write the audio workaround status to the hardware
 202  */
 203 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
 204 {
 205         struct drm_device *dev = encoder->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 208         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 209         uint32_t offset = dig->afmt->offset;
 210         bool hdmi_audio_workaround = false; /* FIXME */
 211         u32 value;
 212
 213         if (!hdmi_audio_workaround ||
 214             r600_hdmi_is_audio_buffer_filled(encoder))
 215                 value = 0; /* disable workaround */
 216         else
 217                 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
 218         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
 219                  value, ~HDMI0_AUDIO_TEST_EN);
 220 }
 221
 222 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 223 {
 224         struct drm_device *dev = encoder->dev;
 225         struct radeon_device *rdev = dev->dev_private;
 226         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 227         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 228         u32 base_rate = 24000;
 229         u32 max_ratio = clock / base_rate;
 230         u32 dto_phase;
 231         u32 dto_modulo = clock;
 232         u32 wallclock_ratio;
 233         u32 dto_cntl;
 234
 235         if (!dig || !dig->afmt)
 236                 return;
 237
 238         if (max_ratio >= 8) {
 239                 dto_phase = 192 * 1000;
 240                 wallclock_ratio = 3;
 241         } else if (max_ratio >= 4) {
 242                 dto_phase = 96 * 1000;
 243                 wallclock_ratio = 2;
 244         } else if (max_ratio >= 2) {
 245                 dto_phase = 48 * 1000;
 246                 wallclock_ratio = 1;
 247         } else {
 248                 dto_phase = 24 * 1000;
 249                 wallclock_ratio = 0;
 250         }
 251
 252         /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
 253          * doesn't matter which one you use.  Just use the first one.
 254          */
 255         /* XXX two dtos; generally use dto0 for hdmi */
 256         /* Express [24MHz / target pixel clock] as an exact rational
 257          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 258          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 259          */
 260         if (ASIC_IS_DCE3(rdev)) {
 261                 /* according to the reg specs, this should DCE3.2 only, but in
 262                  * practice it seems to cover DCE3.0 as well.
 263                  */
 264                 if (dig->dig_encoder == 0) {
 265                         dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 266                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 267                         WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 268                         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 269                         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 270                         WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
 271                 } else {
 272                         dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 273                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 274                         WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
 275                         WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
 276                         WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
 277                         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
 278                 }
 279         } else {
 280                 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
 281                 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
 282                        AUDIO_DTO_MODULE(clock / 10));
 283         }
 284 }
 285
 286 static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
 287 {
 288         struct radeon_device *rdev = encoder->dev->dev_private;
 289         struct drm_connector *connector;
 290         struct radeon_connector *radeon_connector = NULL;
 291         u32 tmp;
 292         u8 *sadb;
 293         int sad_count;
 294
 295         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 296                 if (connector->encoder == encoder)
 297                         radeon_connector = to_radeon_connector(connector);
 298         }
 299
 300         if (!radeon_connector) {
 301                 DRM_ERROR("Couldn't find encoder's connector\n");
 302                 return;
 303         }
 304
 305         sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
 306         if (sad_count < 0) {
 307                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
 308                 return;
 309         }
 310
 311         /* program the speaker allocation */
 312         tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 313         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 314         /* set HDMI mode */
 315         tmp |= HDMI_CONNECTION;
 316         if (sad_count)
 317                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 318         else
 319                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 320         WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 321
 322         kfree(sadb);
 323 }
 324
 325 static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
 326 {
 327         struct radeon_device *rdev = encoder->dev->dev_private;
 328         struct drm_connector *connector;
 329         struct radeon_connector *radeon_connector = NULL;
 330         struct cea_sad *sads;
 331         int i, sad_count;
 332
 333         static const u16 eld_reg_to_type[][2] = {
 334                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 335                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 336                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 337                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 338                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 339                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 340                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 341                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 342                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 343                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 344                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 345                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 346         };
 347
 348         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 349                 if (connector->encoder == encoder)
 350                         radeon_connector = to_radeon_connector(connector);
 351         }
 352
 353         if (!radeon_connector) {
 354                 DRM_ERROR("Couldn't find encoder's connector\n");
 355                 return;
 356         }
 357
 358         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 359         if (sad_count < 0) {
 360                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 361                 return;
 362         }
 363         BUG_ON(!sads);
 364
 365         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 366                 u32 value = 0;
 367                 int j;
 368
 369                 for (j = 0; j < sad_count; j++) {
 370                         struct cea_sad *sad = &sads[j];
 371
 372                         if (sad->format == eld_reg_to_type[i][1]) {
 373                                 value = MAX_CHANNELS(sad->channels) |
 374                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 375                                         SUPPORTED_FREQUENCIES(sad->freq);
 376                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 377                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 378                                 break;
 379                         }
 380                 }
 381                 WREG32(eld_reg_to_type[i][0], value);
 382         }
 383
 384         kfree(sads);
 385 }
 386
 387 /*
 388  * update the info frames with the data from the current display mode
 389  */
 390 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 391 {
 392         struct drm_device *dev = encoder->dev;
 393         struct radeon_device *rdev = dev->dev_private;
 394         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 395         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 396         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 397         struct hdmi_avi_infoframe frame;
 398         uint32_t offset;
 399         ssize_t err;
 400
 401         if (!dig || !dig->afmt)
 402                 return;
 403
 404         /* Silent, r600_hdmi_enable will raise WARN for us */
 405         if (!dig->afmt->enabled)
 406                 return;
 407         offset = dig->afmt->offset;
 408
 409         r600_audio_set_dto(encoder, mode->clock);
 410
 411         WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 412                HDMI0_NULL_SEND); /* send null packets when required */
 413
 414         WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
 415
 416         if (ASIC_IS_DCE32(rdev)) {
 417                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 418                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 419                        HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 420                 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 421                        AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
 422                        AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 423         } else {
 424                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 425                        HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
 426                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 427                        HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
 428                        HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 429         }
 430
 431         if (ASIC_IS_DCE32(rdev)) {
 432                 dce3_2_afmt_write_speaker_allocation(encoder);
 433                 dce3_2_afmt_write_sad_regs(encoder);
 434         }
 435
 436         WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
 437                HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
 438                HDMI0_ACR_SOURCE); /* select SW CTS value */
 439
 440         WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 441                HDMI0_NULL_SEND | /* send null packets when required */
 442                HDMI0_GC_SEND | /* send general control packets */
 443                HDMI0_GC_CONT); /* send general control packets every frame */
 444
 445         /* TODO: HDMI0_AUDIO_INFO_UPDATE */
 446         WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
 447                HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
 448                HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
 449                HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 450                HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
 451
 452         WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
 453                HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
 454                HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 455
 456         WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
 457
 458         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 459         if (err < 0) {
 460                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 461                 return;
 462         }
 463
 464         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 465         if (err < 0) {
 466                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 467                 return;
 468         }
 469
 470         r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 471         r600_hdmi_update_ACR(encoder, mode->clock);
 472
 473         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 474         WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 475         WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
 476         WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
 477         WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
 478
 479         r600_hdmi_audio_workaround(encoder);
 480 }
 481
 482 /*
 483  * update settings with current parameters from audio engine
 484  */
 485 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
 486 {
 487         struct drm_device *dev = encoder->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 490         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 491         struct r600_audio_pin audio = r600_audio_status(rdev);
 492         uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
 493         struct hdmi_audio_infoframe frame;
 494         uint32_t offset;
 495         uint32_t iec;
 496         ssize_t err;
 497
 498         if (!dig->afmt || !dig->afmt->enabled)
 499                 return;
 500         offset = dig->afmt->offset;
 501
 502         DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
 503                  r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
 504                   audio.channels, audio.rate, audio.bits_per_sample);
 505         DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
 506                   (int)audio.status_bits, (int)audio.category_code);
 507
 508         iec = 0;
 509         if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
 510                 iec |= 1 << 0;
 511         if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
 512                 iec |= 1 << 1;
 513         if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
 514                 iec |= 1 << 2;
 515         if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
 516                 iec |= 1 << 3;
 517
 518         iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
 519
 520         switch (audio.rate) {
 521         case 32000:
 522                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
 523                 break;
 524         case 44100:
 525                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
 526                 break;
 527         case 48000:
 528                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
 529                 break;
 530         case 88200:
 531                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
 532                 break;
 533         case 96000:
 534                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
 535                 break;
 536         case 176400:
 537                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
 538                 break;
 539         case 192000:
 540                 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
 541                 break;
 542         }
 543
 544         WREG32(HDMI0_60958_0 + offset, iec);
 545
 546         iec = 0;
 547         switch (audio.bits_per_sample) {
 548         case 16:
 549                 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
 550                 break;
 551         case 20:
 552                 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
 553                 break;
 554         case 24:
 555                 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
 556                 break;
 557         }
 558         if (audio.status_bits & AUDIO_STATUS_V)
 559                 iec |= 0x5 << 16;
 560         WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
 561
 562         err = hdmi_audio_infoframe_init(&frame);
 563         if (err < 0) {
 564                 DRM_ERROR("failed to setup audio infoframe\n");
 565                 return;
 566         }
 567
 568         frame.channels = audio.channels;
 569
 570         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 571         if (err < 0) {
 572                 DRM_ERROR("failed to pack audio infoframe\n");
 573                 return;
 574         }
 575
 576         r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
 577         r600_hdmi_audio_workaround(encoder);
 578 }
 579
 580 /*
 581  * enable the HDMI engine
 582  */
 583 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
 584 {
 585         struct drm_device *dev = encoder->dev;
 586         struct radeon_device *rdev = dev->dev_private;
 587         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 588         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 589         u32 hdmi = HDMI0_ERROR_ACK;
 590
 591         if (!dig || !dig->afmt)
 592                 return;
 593
 594         /* Silent, r600_hdmi_enable will raise WARN for us */
 595         if (enable && dig->afmt->enabled)
 596                 return;
 597         if (!enable && !dig->afmt->enabled)
 598                 return;
 599
 600         if (enable)
 601                 dig->afmt->pin = r600_audio_get_pin(rdev);
 602         else
 603                 dig->afmt->pin = NULL;
 604
 605         /* Older chipsets require setting HDMI and routing manually */
 606         if (!ASIC_IS_DCE3(rdev)) {
 607                 if (enable)
 608                         hdmi |= HDMI0_ENABLE;
 609                 switch (radeon_encoder->encoder_id) {
 610                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 611                         if (enable) {
 612                                 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
 613                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
 614                         } else {
 615                                 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
 616                         }
 617                         break;
 618                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 619                         if (enable) {
 620                                 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
 621                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
 622                         } else {
 623                                 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
 624                         }
 625                         break;
 626                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
 627                         if (enable) {
 628                                 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
 629                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
 630                         } else {
 631                                 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
 632                         }
 633                         break;
 634                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 635                         if (enable)
 636                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
 637                         break;
 638                 default:
 639                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
 640                                 radeon_encoder->encoder_id);
 641                         break;
 642                 }
 643                 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
 644         }
 645
 646         if (rdev->irq.installed) {
 647                 /* if irq is available use it */
 648                 /* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
 649                 if (enable)
 650                         radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
 651                 else
 652                         radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
 653         }
 654
 655         dig->afmt->enabled = enable;
 656
 657         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 658                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 659 }
 660