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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100
101 /*
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 * symbol;
104 */
105 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
107 /* RADEON_IB_POOL_SIZE must be a power of 2 */
108 #define RADEON_IB_POOL_SIZE 16
109 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
110 #define RADEONFB_CONN_LIMIT 4
111 #define RADEON_BIOS_NUM_SCRATCH 8
112
113 /* max number of rings */
114 #define RADEON_NUM_RINGS 6
115
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
122
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132 /* R600+ */
133 #define R600_RING_TYPE_UVD_INDEX 5
134
135 /* hardcode those limit for now */
136 #define RADEON_VA_IB_OFFSET (1 << 20)
137 #define RADEON_VA_RESERVED_SIZE (8 << 20)
138 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
139
140 /* reset flags */
141 #define RADEON_RESET_GFX (1 << 0)
142 #define RADEON_RESET_COMPUTE (1 << 1)
143 #define RADEON_RESET_DMA (1 << 2)
144 #define RADEON_RESET_CP (1 << 3)
145 #define RADEON_RESET_GRBM (1 << 4)
146 #define RADEON_RESET_DMA1 (1 << 5)
147 #define RADEON_RESET_RLC (1 << 6)
148 #define RADEON_RESET_SEM (1 << 7)
149 #define RADEON_RESET_IH (1 << 8)
150 #define RADEON_RESET_VMC (1 << 9)
151 #define RADEON_RESET_MC (1 << 10)
152 #define RADEON_RESET_DISPLAY (1 << 11)
153
154 /* max cursor sizes (in pixels) */
155 #define CURSOR_WIDTH 64
156 #define CURSOR_HEIGHT 64
157
158 #define CIK_CURSOR_WIDTH 128
159 #define CIK_CURSOR_HEIGHT 128
160
161 /*
162 * Errata workarounds.
163 */
164 enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
168 };
169
170
171 struct radeon_device;
172
173
174 /*
175 * BIOS.
176 */
177 bool radeon_get_bios(struct radeon_device *rdev);
178
179 /*
180 * Dummy page
181 */
182 struct radeon_dummy_page {
183 struct page *page;
184 dma_addr_t addr;
185 };
186 int radeon_dummy_page_init(struct radeon_device *rdev);
187 void radeon_dummy_page_fini(struct radeon_device *rdev);
188
189
190 /*
191 * Clocks
192 */
193 struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
196 struct radeon_pll dcpll;
197 struct radeon_pll spll;
198 struct radeon_pll mpll;
199 /* 10 Khz units */
200 uint32_t default_mclk;
201 uint32_t default_sclk;
202 uint32_t default_dispclk;
203 uint32_t dp_extclk;
204 uint32_t max_pixel_clock;
205 };
206
207 /*
208 * Power management
209 */
210 int radeon_pm_init(struct radeon_device *rdev);
211 void radeon_pm_fini(struct radeon_device *rdev);
212 void radeon_pm_compute_clocks(struct radeon_device *rdev);
213 void radeon_pm_suspend(struct radeon_device *rdev);
214 void radeon_pm_resume(struct radeon_device *rdev);
215 void radeon_combios_get_power_modes(struct radeon_device *rdev);
216 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
217 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
218 u8 clock_type,
219 u32 clock,
220 bool strobe_mode,
221 struct atom_clock_dividers *dividers);
222 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
223 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
224 u16 voltage_level, u8 voltage_type,
225 u32 *gpio_value, u32 *gpio_mask);
226 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
227 u32 eng_clock, u32 mem_clock);
228 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
229 u8 voltage_type, u16 *voltage_step);
230 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
231 u8 voltage_type,
232 u16 nominal_voltage,
233 u16 *true_voltage);
234 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
235 u8 voltage_type, u16 *min_voltage);
236 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
237 u8 voltage_type, u16 *max_voltage);
238 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
239 u8 voltage_type,
240 struct atom_voltage_table *voltage_table);
241 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type);
242 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
243 u32 mem_clock);
244 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
245 u32 mem_clock);
246 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
247 u8 module_index,
248 struct atom_mc_reg_table *reg_table);
249 int radeon_atom_get_memory_info(struct radeon_device *rdev,
250 u8 module_index, struct atom_memory_info *mem_info);
251 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
252 bool gddr5, u8 module_index,
253 struct atom_memory_clock_range_table *mclk_range_table);
254 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
255 u16 voltage_id, u16 *voltage);
256 void rs690_pm_info(struct radeon_device *rdev);
257 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
258 unsigned *bankh, unsigned *mtaspect,
259 unsigned *tile_split);
260
261 /*
262 * Fences.
263 */
264 struct radeon_fence_driver {
265 uint32_t scratch_reg;
266 uint64_t gpu_addr;
267 volatile uint32_t *cpu_addr;
268 /* sync_seq is protected by ring emission lock */
269 uint64_t sync_seq[RADEON_NUM_RINGS];
270 atomic64_t last_seq;
271 unsigned long last_activity;
272 bool initialized;
273 };
274
275 struct radeon_fence {
276 struct radeon_device *rdev;
277 struct kref kref;
278 /* protected by radeon_fence.lock */
279 uint64_t seq;
280 /* RB, DMA, etc. */
281 unsigned ring;
282 };
283
284 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
285 int radeon_fence_driver_init(struct radeon_device *rdev);
286 void radeon_fence_driver_fini(struct radeon_device *rdev);
287 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
288 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
289 void radeon_fence_process(struct radeon_device *rdev, int ring);
290 bool radeon_fence_signaled(struct radeon_fence *fence);
291 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
292 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
293 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
294 int radeon_fence_wait_any(struct radeon_device *rdev,
295 struct radeon_fence **fences,
296 bool intr);
297 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
298 void radeon_fence_unref(struct radeon_fence **fence);
299 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
300 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
301 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
302 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
303 struct radeon_fence *b)
304 {
305 if (!a) {
306 return b;
307 }
308
309 if (!b) {
310 return a;
311 }
312
313 BUG_ON(a->ring != b->ring);
314
315 if (a->seq > b->seq) {
316 return a;
317 } else {
318 return b;
319 }
320 }
321
322 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
323 struct radeon_fence *b)
324 {
325 if (!a) {
326 return false;
327 }
328
329 if (!b) {
330 return true;
331 }
332
333 BUG_ON(a->ring != b->ring);
334
335 return a->seq < b->seq;
336 }
337
338 /*
339 * Tiling registers
340 */
341 struct radeon_surface_reg {
342 struct radeon_bo *bo;
343 };
344
345 #define RADEON_GEM_MAX_SURFACES 8
346
347 /*
348 * TTM.
349 */
350 struct radeon_mman {
351 struct ttm_bo_global_ref bo_global_ref;
352 struct drm_global_reference mem_global_ref;
353 struct ttm_bo_device bdev;
354 bool mem_global_referenced;
355 bool initialized;
356 };
357
358 /* bo virtual address in a specific vm */
359 struct radeon_bo_va {
360 /* protected by bo being reserved */
361 struct list_head bo_list;
362 uint64_t soffset;
363 uint64_t eoffset;
364 uint32_t flags;
365 bool valid;
366 unsigned ref_count;
367
368 /* protected by vm mutex */
369 struct list_head vm_list;
370
371 /* constant after initialization */
372 struct radeon_vm *vm;
373 struct radeon_bo *bo;
374 };
375
376 struct radeon_bo {
377 /* Protected by gem.mutex */
378 struct list_head list;
379 /* Protected by tbo.reserved */
380 u32 placements[3];
381 struct ttm_placement placement;
382 struct ttm_buffer_object tbo;
383 struct ttm_bo_kmap_obj kmap;
384 unsigned pin_count;
385 void *kptr;
386 u32 tiling_flags;
387 u32 pitch;
388 int surface_reg;
389 /* list of all virtual address to which this bo
390 * is associated to
391 */
392 struct list_head va;
393 /* Constant after initialization */
394 struct radeon_device *rdev;
395 struct drm_gem_object gem_base;
396
397 struct ttm_bo_kmap_obj dma_buf_vmap;
398 pid_t pid;
399 };
400 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
401
402 struct radeon_bo_list {
403 struct ttm_validate_buffer tv;
404 struct radeon_bo *bo;
405 uint64_t gpu_offset;
406 bool written;
407 unsigned domain;
408 unsigned alt_domain;
409 u32 tiling_flags;
410 };
411
412 int radeon_gem_debugfs_init(struct radeon_device *rdev);
413
414 /* sub-allocation manager, it has to be protected by another lock.
415 * By conception this is an helper for other part of the driver
416 * like the indirect buffer or semaphore, which both have their
417 * locking.
418 *
419 * Principe is simple, we keep a list of sub allocation in offset
420 * order (first entry has offset == 0, last entry has the highest
421 * offset).
422 *
423 * When allocating new object we first check if there is room at
424 * the end total_size - (last_object_offset + last_object_size) >=
425 * alloc_size. If so we allocate new object there.
426 *
427 * When there is not enough room at the end, we start waiting for
428 * each sub object until we reach object_offset+object_size >=
429 * alloc_size, this object then become the sub object we return.
430 *
431 * Alignment can't be bigger than page size.
432 *
433 * Hole are not considered for allocation to keep things simple.
434 * Assumption is that there won't be hole (all object on same
435 * alignment).
436 */
437 struct radeon_sa_manager {
438 wait_queue_head_t wq;
439 struct radeon_bo *bo;
440 struct list_head *hole;
441 struct list_head flist[RADEON_NUM_RINGS];
442 struct list_head olist;
443 unsigned size;
444 uint64_t gpu_addr;
445 void *cpu_ptr;
446 uint32_t domain;
447 };
448
449 struct radeon_sa_bo;
450
451 /* sub-allocation buffer */
452 struct radeon_sa_bo {
453 struct list_head olist;
454 struct list_head flist;
455 struct radeon_sa_manager *manager;
456 unsigned soffset;
457 unsigned eoffset;
458 struct radeon_fence *fence;
459 };
460
461 /*
462 * GEM objects.
463 */
464 struct radeon_gem {
465 struct mutex mutex;
466 struct list_head objects;
467 };
468
469 int radeon_gem_init(struct radeon_device *rdev);
470 void radeon_gem_fini(struct radeon_device *rdev);
471 int radeon_gem_object_create(struct radeon_device *rdev, int size,
472 int alignment, int initial_domain,
473 bool discardable, bool kernel,
474 struct drm_gem_object **obj);
475
476 int radeon_mode_dumb_create(struct drm_file *file_priv,
477 struct drm_device *dev,
478 struct drm_mode_create_dumb *args);
479 int radeon_mode_dumb_mmap(struct drm_file *filp,
480 struct drm_device *dev,
481 uint32_t handle, uint64_t *offset_p);
482 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
483 struct drm_device *dev,
484 uint32_t handle);
485
486 /*
487 * Semaphores.
488 */
489 /* everything here is constant */
490 struct radeon_semaphore {
491 struct radeon_sa_bo *sa_bo;
492 signed waiters;
493 uint64_t gpu_addr;
494 };
495
496 int radeon_semaphore_create(struct radeon_device *rdev,
497 struct radeon_semaphore **semaphore);
498 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
499 struct radeon_semaphore *semaphore);
500 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
501 struct radeon_semaphore *semaphore);
502 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
503 struct radeon_semaphore *semaphore,
504 int signaler, int waiter);
505 void radeon_semaphore_free(struct radeon_device *rdev,
506 struct radeon_semaphore **semaphore,
507 struct radeon_fence *fence);
508
509 /*
510 * GART structures, functions & helpers
511 */
512 struct radeon_mc;
513
514 #define RADEON_GPU_PAGE_SIZE 4096
515 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
516 #define RADEON_GPU_PAGE_SHIFT 12
517 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
518
519 struct radeon_gart {
520 dma_addr_t table_addr;
521 struct radeon_bo *robj;
522 void *ptr;
523 unsigned num_gpu_pages;
524 unsigned num_cpu_pages;
525 unsigned table_size;
526 struct page **pages;
527 dma_addr_t *pages_addr;
528 bool ready;
529 };
530
531 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
532 void radeon_gart_table_ram_free(struct radeon_device *rdev);
533 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
534 void radeon_gart_table_vram_free(struct radeon_device *rdev);
535 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
536 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
537 int radeon_gart_init(struct radeon_device *rdev);
538 void radeon_gart_fini(struct radeon_device *rdev);
539 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
540 int pages);
541 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
542 int pages, struct page **pagelist,
543 dma_addr_t *dma_addr);
544 void radeon_gart_restore(struct radeon_device *rdev);
545
546
547 /*
548 * GPU MC structures, functions & helpers
549 */
550 struct radeon_mc {
551 resource_size_t aper_size;
552 resource_size_t aper_base;
553 resource_size_t agp_base;
554 /* for some chips with <= 32MB we need to lie
555 * about vram size near mc fb location */
556 u64 mc_vram_size;
557 u64 visible_vram_size;
558 u64 gtt_size;
559 u64 gtt_start;
560 u64 gtt_end;
561 u64 vram_start;
562 u64 vram_end;
563 unsigned vram_width;
564 u64 real_vram_size;
565 int vram_mtrr;
566 bool vram_is_ddr;
567 bool igp_sideport_enabled;
568 u64 gtt_base_align;
569 u64 mc_mask;
570 };
571
572 bool radeon_combios_sideport_present(struct radeon_device *rdev);
573 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
574
575 /*
576 * GPU scratch registers structures, functions & helpers
577 */
578 struct radeon_scratch {
579 unsigned num_reg;
580 uint32_t reg_base;
581 bool free[32];
582 uint32_t reg[32];
583 };
584
585 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
586 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
587
588 /*
589 * GPU doorbell structures, functions & helpers
590 */
591 struct radeon_doorbell {
592 u32 num_pages;
593 bool free[1024];
594 /* doorbell mmio */
595 resource_size_t base;
596 resource_size_t size;
597 void __iomem *ptr;
598 };
599
600 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
601 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
602
603 /*
604 * IRQS.
605 */
606
607 struct radeon_unpin_work {
608 struct work_struct work;
609 struct radeon_device *rdev;
610 int crtc_id;
611 struct radeon_fence *fence;
612 struct drm_pending_vblank_event *event;
613 struct radeon_bo *old_rbo;
614 u64 new_crtc_base;
615 };
616
617 struct r500_irq_stat_regs {
618 u32 disp_int;
619 u32 hdmi0_status;
620 };
621
622 struct r600_irq_stat_regs {
623 u32 disp_int;
624 u32 disp_int_cont;
625 u32 disp_int_cont2;
626 u32 d1grph_int;
627 u32 d2grph_int;
628 u32 hdmi0_status;
629 u32 hdmi1_status;
630 };
631
632 struct evergreen_irq_stat_regs {
633 u32 disp_int;
634 u32 disp_int_cont;
635 u32 disp_int_cont2;
636 u32 disp_int_cont3;
637 u32 disp_int_cont4;
638 u32 disp_int_cont5;
639 u32 d1grph_int;
640 u32 d2grph_int;
641 u32 d3grph_int;
642 u32 d4grph_int;
643 u32 d5grph_int;
644 u32 d6grph_int;
645 u32 afmt_status1;
646 u32 afmt_status2;
647 u32 afmt_status3;
648 u32 afmt_status4;
649 u32 afmt_status5;
650 u32 afmt_status6;
651 };
652
653 struct cik_irq_stat_regs {
654 u32 disp_int;
655 u32 disp_int_cont;
656 u32 disp_int_cont2;
657 u32 disp_int_cont3;
658 u32 disp_int_cont4;
659 u32 disp_int_cont5;
660 u32 disp_int_cont6;
661 };
662
663 union radeon_irq_stat_regs {
664 struct r500_irq_stat_regs r500;
665 struct r600_irq_stat_regs r600;
666 struct evergreen_irq_stat_regs evergreen;
667 struct cik_irq_stat_regs cik;
668 };
669
670 #define RADEON_MAX_HPD_PINS 6
671 #define RADEON_MAX_CRTCS 6
672 #define RADEON_MAX_AFMT_BLOCKS 6
673
674 struct radeon_irq {
675 bool installed;
676 spinlock_t lock;
677 atomic_t ring_int[RADEON_NUM_RINGS];
678 bool crtc_vblank_int[RADEON_MAX_CRTCS];
679 atomic_t pflip[RADEON_MAX_CRTCS];
680 wait_queue_head_t vblank_queue;
681 bool hpd[RADEON_MAX_HPD_PINS];
682 bool afmt[RADEON_MAX_AFMT_BLOCKS];
683 union radeon_irq_stat_regs stat_regs;
684 };
685
686 int radeon_irq_kms_init(struct radeon_device *rdev);
687 void radeon_irq_kms_fini(struct radeon_device *rdev);
688 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
689 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
690 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
691 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
692 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
693 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
694 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
695 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
696
697 /*
698 * CP & rings.
699 */
700
701 struct radeon_ib {
702 struct radeon_sa_bo *sa_bo;
703 uint32_t length_dw;
704 uint64_t gpu_addr;
705 uint32_t *ptr;
706 int ring;
707 struct radeon_fence *fence;
708 struct radeon_vm *vm;
709 bool is_const_ib;
710 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
711 struct radeon_semaphore *semaphore;
712 };
713
714 struct radeon_ring {
715 struct radeon_bo *ring_obj;
716 volatile uint32_t *ring;
717 unsigned rptr;
718 unsigned rptr_offs;
719 unsigned rptr_reg;
720 unsigned rptr_save_reg;
721 u64 next_rptr_gpu_addr;
722 volatile u32 *next_rptr_cpu_addr;
723 unsigned wptr;
724 unsigned wptr_old;
725 unsigned wptr_reg;
726 unsigned ring_size;
727 unsigned ring_free_dw;
728 int count_dw;
729 unsigned long last_activity;
730 unsigned last_rptr;
731 uint64_t gpu_addr;
732 uint32_t align_mask;
733 uint32_t ptr_mask;
734 bool ready;
735 u32 ptr_reg_shift;
736 u32 ptr_reg_mask;
737 u32 nop;
738 u32 idx;
739 u64 last_semaphore_signal_addr;
740 u64 last_semaphore_wait_addr;
741 /* for CIK queues */
742 u32 me;
743 u32 pipe;
744 u32 queue;
745 struct radeon_bo *mqd_obj;
746 u32 doorbell_page_num;
747 u32 doorbell_offset;
748 unsigned wptr_offs;
749 };
750
751 struct radeon_mec {
752 struct radeon_bo *hpd_eop_obj;
753 u64 hpd_eop_gpu_addr;
754 u32 num_pipe;
755 u32 num_mec;
756 u32 num_queue;
757 };
758
759 /*
760 * VM
761 */
762
763 /* maximum number of VMIDs */
764 #define RADEON_NUM_VM 16
765
766 /* defines number of bits in page table versus page directory,
767 * a page is 4KB so we have 12 bits offset, 9 bits in the page
768 * table and the remaining 19 bits are in the page directory */
769 #define RADEON_VM_BLOCK_SIZE 9
770
771 /* number of entries in page table */
772 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
773
774 struct radeon_vm {
775 struct list_head list;
776 struct list_head va;
777 unsigned id;
778
779 /* contains the page directory */
780 struct radeon_sa_bo *page_directory;
781 uint64_t pd_gpu_addr;
782
783 /* array of page tables, one for each page directory entry */
784 struct radeon_sa_bo **page_tables;
785
786 struct mutex mutex;
787 /* last fence for cs using this vm */
788 struct radeon_fence *fence;
789 /* last flush or NULL if we still need to flush */
790 struct radeon_fence *last_flush;
791 };
792
793 struct radeon_vm_manager {
794 struct mutex lock;
795 struct list_head lru_vm;
796 struct radeon_fence *active[RADEON_NUM_VM];
797 struct radeon_sa_manager sa_manager;
798 uint32_t max_pfn;
799 /* number of VMIDs */
800 unsigned nvm;
801 /* vram base address for page table entry */
802 u64 vram_base_offset;
803 /* is vm enabled? */
804 bool enabled;
805 };
806
807 /*
808 * file private structure
809 */
810 struct radeon_fpriv {
811 struct radeon_vm vm;
812 };
813
814 /*
815 * R6xx+ IH ring
816 */
817 struct r600_ih {
818 struct radeon_bo *ring_obj;
819 volatile uint32_t *ring;
820 unsigned rptr;
821 unsigned ring_size;
822 uint64_t gpu_addr;
823 uint32_t ptr_mask;
824 atomic_t lock;
825 bool enabled;
826 };
827
828 struct r600_blit_cp_primitives {
829 void (*set_render_target)(struct radeon_device *rdev, int format,
830 int w, int h, u64 gpu_addr);
831 void (*cp_set_surface_sync)(struct radeon_device *rdev,
832 u32 sync_type, u32 size,
833 u64 mc_addr);
834 void (*set_shaders)(struct radeon_device *rdev);
835 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
836 void (*set_tex_resource)(struct radeon_device *rdev,
837 int format, int w, int h, int pitch,
838 u64 gpu_addr, u32 size);
839 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
840 int x2, int y2);
841 void (*draw_auto)(struct radeon_device *rdev);
842 void (*set_default_state)(struct radeon_device *rdev);
843 };
844
845 struct r600_blit {
846 struct radeon_bo *shader_obj;
847 struct r600_blit_cp_primitives primitives;
848 int max_dim;
849 int ring_size_common;
850 int ring_size_per_loop;
851 u64 shader_gpu_addr;
852 u32 vs_offset, ps_offset;
853 u32 state_offset;
854 u32 state_len;
855 };
856
857 /*
858 * RLC stuff
859 */
860 #include "clearstate_defs.h"
861
862 struct radeon_rlc {
863 /* for power gating */
864 struct radeon_bo *save_restore_obj;
865 uint64_t save_restore_gpu_addr;
866 volatile uint32_t *sr_ptr;
867 u32 *reg_list;
868 u32 reg_list_size;
869 /* for clear state */
870 struct radeon_bo *clear_state_obj;
871 uint64_t clear_state_gpu_addr;
872 volatile uint32_t *cs_ptr;
873 struct cs_section_def *cs_data;
874 };
875
876 int radeon_ib_get(struct radeon_device *rdev, int ring,
877 struct radeon_ib *ib, struct radeon_vm *vm,
878 unsigned size);
879 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
880 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
881 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
882 struct radeon_ib *const_ib);
883 int radeon_ib_pool_init(struct radeon_device *rdev);
884 void radeon_ib_pool_fini(struct radeon_device *rdev);
885 int radeon_ib_ring_tests(struct radeon_device *rdev);
886 /* Ring access between begin & end cannot sleep */
887 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
888 struct radeon_ring *ring);
889 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
890 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
891 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
892 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
893 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
894 void radeon_ring_undo(struct radeon_ring *ring);
895 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
896 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
897 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
898 void radeon_ring_lockup_update(struct radeon_ring *ring);
899 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
900 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
901 uint32_t **data);
902 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
903 unsigned size, uint32_t *data);
904 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
905 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
906 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
907 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
908
909
910 /* r600 async dma */
911 void r600_dma_stop(struct radeon_device *rdev);
912 int r600_dma_resume(struct radeon_device *rdev);
913 void r600_dma_fini(struct radeon_device *rdev);
914
915 void cayman_dma_stop(struct radeon_device *rdev);
916 int cayman_dma_resume(struct radeon_device *rdev);
917 void cayman_dma_fini(struct radeon_device *rdev);
918
919 /*
920 * CS.
921 */
922 struct radeon_cs_reloc {
923 struct drm_gem_object *gobj;
924 struct radeon_bo *robj;
925 struct radeon_bo_list lobj;
926 uint32_t handle;
927 uint32_t flags;
928 };
929
930 struct radeon_cs_chunk {
931 uint32_t chunk_id;
932 uint32_t length_dw;
933 int kpage_idx[2];
934 uint32_t *kpage[2];
935 uint32_t *kdata;
936 void __user *user_ptr;
937 int last_copied_page;
938 int last_page_index;
939 };
940
941 struct radeon_cs_parser {
942 struct device *dev;
943 struct radeon_device *rdev;
944 struct drm_file *filp;
945 /* chunks */
946 unsigned nchunks;
947 struct radeon_cs_chunk *chunks;
948 uint64_t *chunks_array;
949 /* IB */
950 unsigned idx;
951 /* relocations */
952 unsigned nrelocs;
953 struct radeon_cs_reloc *relocs;
954 struct radeon_cs_reloc **relocs_ptr;
955 struct list_head validated;
956 unsigned dma_reloc_idx;
957 /* indices of various chunks */
958 int chunk_ib_idx;
959 int chunk_relocs_idx;
960 int chunk_flags_idx;
961 int chunk_const_ib_idx;
962 struct radeon_ib ib;
963 struct radeon_ib const_ib;
964 void *track;
965 unsigned family;
966 int parser_error;
967 u32 cs_flags;
968 u32 ring;
969 s32 priority;
970 };
971
972 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
973 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
974
975 struct radeon_cs_packet {
976 unsigned idx;
977 unsigned type;
978 unsigned reg;
979 unsigned opcode;
980 int count;
981 unsigned one_reg_wr;
982 };
983
984 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
985 struct radeon_cs_packet *pkt,
986 unsigned idx, unsigned reg);
987 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
988 struct radeon_cs_packet *pkt);
989
990
991 /*
992 * AGP
993 */
994 int radeon_agp_init(struct radeon_device *rdev);
995 void radeon_agp_resume(struct radeon_device *rdev);
996 void radeon_agp_suspend(struct radeon_device *rdev);
997 void radeon_agp_fini(struct radeon_device *rdev);
998
999
1000 /*
1001 * Writeback
1002 */
1003 struct radeon_wb {
1004 struct radeon_bo *wb_obj;
1005 volatile uint32_t *wb;
1006 uint64_t gpu_addr;
1007 bool enabled;
1008 bool use_event;
1009 };
1010
1011 #define RADEON_WB_SCRATCH_OFFSET 0
1012 #define RADEON_WB_RING0_NEXT_RPTR 256
1013 #define RADEON_WB_CP_RPTR_OFFSET 1024
1014 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1015 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1016 #define R600_WB_DMA_RPTR_OFFSET 1792
1017 #define R600_WB_IH_WPTR_OFFSET 2048
1018 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1019 #define R600_WB_UVD_RPTR_OFFSET 2560
1020 #define R600_WB_EVENT_OFFSET 3072
1021 #define CIK_WB_CP1_WPTR_OFFSET 3328
1022 #define CIK_WB_CP2_WPTR_OFFSET 3584
1023
1024 /**
1025 * struct radeon_pm - power management datas
1026 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1027 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1028 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1029 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1030 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1031 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1032 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1033 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1034 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1035 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1036 * @needed_bandwidth: current bandwidth needs
1037 *
1038 * It keeps track of various data needed to take powermanagement decision.
1039 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1040 * Equation between gpu/memory clock and available bandwidth is hw dependent
1041 * (type of memory, bus size, efficiency, ...)
1042 */
1043
1044 enum radeon_pm_method {
1045 PM_METHOD_PROFILE,
1046 PM_METHOD_DYNPM,
1047 PM_METHOD_DPM,
1048 };
1049
1050 enum radeon_dynpm_state {
1051 DYNPM_STATE_DISABLED,
1052 DYNPM_STATE_MINIMUM,
1053 DYNPM_STATE_PAUSED,
1054 DYNPM_STATE_ACTIVE,
1055 DYNPM_STATE_SUSPENDED,
1056 };
1057 enum radeon_dynpm_action {
1058 DYNPM_ACTION_NONE,
1059 DYNPM_ACTION_MINIMUM,
1060 DYNPM_ACTION_DOWNCLOCK,
1061 DYNPM_ACTION_UPCLOCK,
1062 DYNPM_ACTION_DEFAULT
1063 };
1064
1065 enum radeon_voltage_type {
1066 VOLTAGE_NONE = 0,
1067 VOLTAGE_GPIO,
1068 VOLTAGE_VDDC,
1069 VOLTAGE_SW
1070 };
1071
1072 enum radeon_pm_state_type {
1073 /* not used for dpm */
1074 POWER_STATE_TYPE_DEFAULT,
1075 POWER_STATE_TYPE_POWERSAVE,
1076 /* user selectable states */
1077 POWER_STATE_TYPE_BATTERY,
1078 POWER_STATE_TYPE_BALANCED,
1079 POWER_STATE_TYPE_PERFORMANCE,
1080 /* internal states */
1081 POWER_STATE_TYPE_INTERNAL_UVD,
1082 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1083 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1084 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1085 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1086 POWER_STATE_TYPE_INTERNAL_BOOT,
1087 POWER_STATE_TYPE_INTERNAL_THERMAL,
1088 POWER_STATE_TYPE_INTERNAL_ACPI,
1089 POWER_STATE_TYPE_INTERNAL_ULV,
1090 };
1091
1092 enum radeon_pm_profile_type {
1093 PM_PROFILE_DEFAULT,
1094 PM_PROFILE_AUTO,
1095 PM_PROFILE_LOW,
1096 PM_PROFILE_MID,
1097 PM_PROFILE_HIGH,
1098 };
1099
1100 #define PM_PROFILE_DEFAULT_IDX 0
1101 #define PM_PROFILE_LOW_SH_IDX 1
1102 #define PM_PROFILE_MID_SH_IDX 2
1103 #define PM_PROFILE_HIGH_SH_IDX 3
1104 #define PM_PROFILE_LOW_MH_IDX 4
1105 #define PM_PROFILE_MID_MH_IDX 5
1106 #define PM_PROFILE_HIGH_MH_IDX 6
1107 #define PM_PROFILE_MAX 7
1108
1109 struct radeon_pm_profile {
1110 int dpms_off_ps_idx;
1111 int dpms_on_ps_idx;
1112 int dpms_off_cm_idx;
1113 int dpms_on_cm_idx;
1114 };
1115
1116 enum radeon_int_thermal_type {
1117 THERMAL_TYPE_NONE,
1118 THERMAL_TYPE_EXTERNAL,
1119 THERMAL_TYPE_EXTERNAL_GPIO,
1120 THERMAL_TYPE_RV6XX,
1121 THERMAL_TYPE_RV770,
1122 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1123 THERMAL_TYPE_EVERGREEN,
1124 THERMAL_TYPE_SUMO,
1125 THERMAL_TYPE_NI,
1126 THERMAL_TYPE_SI,
1127 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1128 THERMAL_TYPE_CI,
1129 };
1130
1131 struct radeon_voltage {
1132 enum radeon_voltage_type type;
1133 /* gpio voltage */
1134 struct radeon_gpio_rec gpio;
1135 u32 delay; /* delay in usec from voltage drop to sclk change */
1136 bool active_high; /* voltage drop is active when bit is high */
1137 /* VDDC voltage */
1138 u8 vddc_id; /* index into vddc voltage table */
1139 u8 vddci_id; /* index into vddci voltage table */
1140 bool vddci_enabled;
1141 /* r6xx+ sw */
1142 u16 voltage;
1143 /* evergreen+ vddci */
1144 u16 vddci;
1145 };
1146
1147 /* clock mode flags */
1148 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1149
1150 struct radeon_pm_clock_info {
1151 /* memory clock */
1152 u32 mclk;
1153 /* engine clock */
1154 u32 sclk;
1155 /* voltage info */
1156 struct radeon_voltage voltage;
1157 /* standardized clock flags */
1158 u32 flags;
1159 };
1160
1161 /* state flags */
1162 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1163
1164 struct radeon_power_state {
1165 enum radeon_pm_state_type type;
1166 struct radeon_pm_clock_info *clock_info;
1167 /* number of valid clock modes in this power state */
1168 int num_clock_modes;
1169 struct radeon_pm_clock_info *default_clock_mode;
1170 /* standardized state flags */
1171 u32 flags;
1172 u32 misc; /* vbios specific flags */
1173 u32 misc2; /* vbios specific flags */
1174 int pcie_lanes; /* pcie lanes */
1175 };
1176
1177 /*
1178 * Some modes are overclocked by very low value, accept them
1179 */
1180 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1181
1182 enum radeon_dpm_auto_throttle_src {
1183 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1184 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1185 };
1186
1187 enum radeon_dpm_event_src {
1188 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1189 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1190 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1191 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1192 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1193 };
1194
1195 struct radeon_ps {
1196 u32 caps; /* vbios flags */
1197 u32 class; /* vbios flags */
1198 u32 class2; /* vbios flags */
1199 /* UVD clocks */
1200 u32 vclk;
1201 u32 dclk;
1202 /* asic priv */
1203 void *ps_priv;
1204 };
1205
1206 struct radeon_dpm_thermal {
1207 /* thermal interrupt work */
1208 struct work_struct work;
1209 /* low temperature threshold */
1210 int min_temp;
1211 /* high temperature threshold */
1212 int max_temp;
1213 /* was interrupt low to high or high to low */
1214 bool high_to_low;
1215 };
1216
1217 struct radeon_dpm {
1218 struct radeon_ps *ps;
1219 /* number of valid power states */
1220 int num_ps;
1221 /* current power state that is active */
1222 struct radeon_ps *current_ps;
1223 /* requested power state */
1224 struct radeon_ps *requested_ps;
1225 /* boot up power state */
1226 struct radeon_ps *boot_ps;
1227 /* default uvd power state */
1228 struct radeon_ps *uvd_ps;
1229 enum radeon_pm_state_type state;
1230 enum radeon_pm_state_type user_state;
1231 u32 platform_caps;
1232 u32 voltage_response_time;
1233 u32 backbias_response_time;
1234 void *priv;
1235 u32 new_active_crtcs;
1236 int new_active_crtc_count;
1237 u32 current_active_crtcs;
1238 int current_active_crtc_count;
1239 /* special states active */
1240 bool thermal_active;
1241 /* thermal handling */
1242 struct radeon_dpm_thermal thermal;
1243 };
1244
1245 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1246 enum radeon_pm_state_type dpm_state);
1247
1248
1249 struct radeon_pm {
1250 struct mutex mutex;
1251 /* write locked while reprogramming mclk */
1252 struct rw_semaphore mclk_lock;
1253 u32 active_crtcs;
1254 int active_crtc_count;
1255 int req_vblank;
1256 bool vblank_sync;
1257 fixed20_12 max_bandwidth;
1258 fixed20_12 igp_sideport_mclk;
1259 fixed20_12 igp_system_mclk;
1260 fixed20_12 igp_ht_link_clk;
1261 fixed20_12 igp_ht_link_width;
1262 fixed20_12 k8_bandwidth;
1263 fixed20_12 sideport_bandwidth;
1264 fixed20_12 ht_bandwidth;
1265 fixed20_12 core_bandwidth;
1266 fixed20_12 sclk;
1267 fixed20_12 mclk;
1268 fixed20_12 needed_bandwidth;
1269 struct radeon_power_state *power_state;
1270 /* number of valid power states */
1271 int num_power_states;
1272 int current_power_state_index;
1273 int current_clock_mode_index;
1274 int requested_power_state_index;
1275 int requested_clock_mode_index;
1276 int default_power_state_index;
1277 u32 current_sclk;
1278 u32 current_mclk;
1279 u16 current_vddc;
1280 u16 current_vddci;
1281 u32 default_sclk;
1282 u32 default_mclk;
1283 u16 default_vddc;
1284 u16 default_vddci;
1285 struct radeon_i2c_chan *i2c_bus;
1286 /* selected pm method */
1287 enum radeon_pm_method pm_method;
1288 /* dynpm power management */
1289 struct delayed_work dynpm_idle_work;
1290 enum radeon_dynpm_state dynpm_state;
1291 enum radeon_dynpm_action dynpm_planned_action;
1292 unsigned long dynpm_action_timeout;
1293 bool dynpm_can_upclock;
1294 bool dynpm_can_downclock;
1295 /* profile-based power management */
1296 enum radeon_pm_profile_type profile;
1297 int profile_index;
1298 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1299 /* internal thermal controller on rv6xx+ */
1300 enum radeon_int_thermal_type int_thermal_type;
1301 struct device *int_hwmon_dev;
1302 /* dpm */
1303 bool dpm_enabled;
1304 struct radeon_dpm dpm;
1305 };
1306
1307 int radeon_pm_get_type_index(struct radeon_device *rdev,
1308 enum radeon_pm_state_type ps_type,
1309 int instance);
1310 /*
1311 * UVD
1312 */
1313 #define RADEON_MAX_UVD_HANDLES 10
1314 #define RADEON_UVD_STACK_SIZE (1024*1024)
1315 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1316
1317 struct radeon_uvd {
1318 struct radeon_bo *vcpu_bo;
1319 void *cpu_addr;
1320 uint64_t gpu_addr;
1321 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1322 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1323 struct delayed_work idle_work;
1324 };
1325
1326 int radeon_uvd_init(struct radeon_device *rdev);
1327 void radeon_uvd_fini(struct radeon_device *rdev);
1328 int radeon_uvd_suspend(struct radeon_device *rdev);
1329 int radeon_uvd_resume(struct radeon_device *rdev);
1330 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1331 uint32_t handle, struct radeon_fence **fence);
1332 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1333 uint32_t handle, struct radeon_fence **fence);
1334 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1335 void radeon_uvd_free_handles(struct radeon_device *rdev,
1336 struct drm_file *filp);
1337 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1338 void radeon_uvd_note_usage(struct radeon_device *rdev);
1339 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1340 unsigned vclk, unsigned dclk,
1341 unsigned vco_min, unsigned vco_max,
1342 unsigned fb_factor, unsigned fb_mask,
1343 unsigned pd_min, unsigned pd_max,
1344 unsigned pd_even,
1345 unsigned *optimal_fb_div,
1346 unsigned *optimal_vclk_div,
1347 unsigned *optimal_dclk_div);
1348 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1349 unsigned cg_upll_func_cntl);
1350
1351 struct r600_audio {
1352 int channels;
1353 int rate;
1354 int bits_per_sample;
1355 u8 status_bits;
1356 u8 category_code;
1357 };
1358
1359 /*
1360 * Benchmarking
1361 */
1362 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1363
1364
1365 /*
1366 * Testing
1367 */
1368 void radeon_test_moves(struct radeon_device *rdev);
1369 void radeon_test_ring_sync(struct radeon_device *rdev,
1370 struct radeon_ring *cpA,
1371 struct radeon_ring *cpB);
1372 void radeon_test_syncing(struct radeon_device *rdev);
1373
1374
1375 /*
1376 * Debugfs
1377 */
1378 struct radeon_debugfs {
1379 struct drm_info_list *files;
1380 unsigned num_files;
1381 };
1382
1383 int radeon_debugfs_add_files(struct radeon_device *rdev,
1384 struct drm_info_list *files,
1385 unsigned nfiles);
1386 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1387
1388
1389 /*
1390 * ASIC specific functions.
1391 */
1392 struct radeon_asic {
1393 int (*init)(struct radeon_device *rdev);
1394 void (*fini)(struct radeon_device *rdev);
1395 int (*resume)(struct radeon_device *rdev);
1396 int (*suspend)(struct radeon_device *rdev);
1397 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1398 int (*asic_reset)(struct radeon_device *rdev);
1399 /* ioctl hw specific callback. Some hw might want to perform special
1400 * operation on specific ioctl. For instance on wait idle some hw
1401 * might want to perform and HDP flush through MMIO as it seems that
1402 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1403 * through ring.
1404 */
1405 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1406 /* check if 3D engine is idle */
1407 bool (*gui_idle)(struct radeon_device *rdev);
1408 /* wait for mc_idle */
1409 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1410 /* get the reference clock */
1411 u32 (*get_xclk)(struct radeon_device *rdev);
1412 /* get the gpu clock counter */
1413 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1414 /* gart */
1415 struct {
1416 void (*tlb_flush)(struct radeon_device *rdev);
1417 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1418 } gart;
1419 struct {
1420 int (*init)(struct radeon_device *rdev);
1421 void (*fini)(struct radeon_device *rdev);
1422
1423 u32 pt_ring_index;
1424 void (*set_page)(struct radeon_device *rdev,
1425 struct radeon_ib *ib,
1426 uint64_t pe,
1427 uint64_t addr, unsigned count,
1428 uint32_t incr, uint32_t flags);
1429 } vm;
1430 /* ring specific callbacks */
1431 struct {
1432 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1433 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1434 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1435 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1436 struct radeon_semaphore *semaphore, bool emit_wait);
1437 int (*cs_parse)(struct radeon_cs_parser *p);
1438 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1439 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1440 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1441 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1442 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1443
1444 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1445 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1446 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1447 } ring[RADEON_NUM_RINGS];
1448 /* irqs */
1449 struct {
1450 int (*set)(struct radeon_device *rdev);
1451 int (*process)(struct radeon_device *rdev);
1452 } irq;
1453 /* displays */
1454 struct {
1455 /* display watermarks */
1456 void (*bandwidth_update)(struct radeon_device *rdev);
1457 /* get frame count */
1458 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1459 /* wait for vblank */
1460 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1461 /* set backlight level */
1462 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1463 /* get backlight level */
1464 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1465 /* audio callbacks */
1466 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1467 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1468 } display;
1469 /* copy functions for bo handling */
1470 struct {
1471 int (*blit)(struct radeon_device *rdev,
1472 uint64_t src_offset,
1473 uint64_t dst_offset,
1474 unsigned num_gpu_pages,
1475 struct radeon_fence **fence);
1476 u32 blit_ring_index;
1477 int (*dma)(struct radeon_device *rdev,
1478 uint64_t src_offset,
1479 uint64_t dst_offset,
1480 unsigned num_gpu_pages,
1481 struct radeon_fence **fence);
1482 u32 dma_ring_index;
1483 /* method used for bo copy */
1484 int (*copy)(struct radeon_device *rdev,
1485 uint64_t src_offset,
1486 uint64_t dst_offset,
1487 unsigned num_gpu_pages,
1488 struct radeon_fence **fence);
1489 /* ring used for bo copies */
1490 u32 copy_ring_index;
1491 } copy;
1492 /* surfaces */
1493 struct {
1494 int (*set_reg)(struct radeon_device *rdev, int reg,
1495 uint32_t tiling_flags, uint32_t pitch,
1496 uint32_t offset, uint32_t obj_size);
1497 void (*clear_reg)(struct radeon_device *rdev, int reg);
1498 } surface;
1499 /* hotplug detect */
1500 struct {
1501 void (*init)(struct radeon_device *rdev);
1502 void (*fini)(struct radeon_device *rdev);
1503 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1504 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1505 } hpd;
1506 /* static power management */
1507 struct {
1508 void (*misc)(struct radeon_device *rdev);
1509 void (*prepare)(struct radeon_device *rdev);
1510 void (*finish)(struct radeon_device *rdev);
1511 void (*init_profile)(struct radeon_device *rdev);
1512 void (*get_dynpm_state)(struct radeon_device *rdev);
1513 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1514 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1515 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1516 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1517 int (*get_pcie_lanes)(struct radeon_device *rdev);
1518 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1519 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1520 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1521 int (*get_temperature)(struct radeon_device *rdev);
1522 } pm;
1523 /* dynamic power management */
1524 struct {
1525 int (*init)(struct radeon_device *rdev);
1526 void (*setup_asic)(struct radeon_device *rdev);
1527 int (*enable)(struct radeon_device *rdev);
1528 void (*disable)(struct radeon_device *rdev);
1529 int (*set_power_state)(struct radeon_device *rdev);
1530 void (*display_configuration_changed)(struct radeon_device *rdev);
1531 void (*fini)(struct radeon_device *rdev);
1532 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1533 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1534 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1535 } dpm;
1536 /* pageflipping */
1537 struct {
1538 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1539 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1540 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1541 } pflip;
1542 };
1543
1544 /*
1545 * Asic structures
1546 */
1547 struct r100_asic {
1548 const unsigned *reg_safe_bm;
1549 unsigned reg_safe_bm_size;
1550 u32 hdp_cntl;
1551 };
1552
1553 struct r300_asic {
1554 const unsigned *reg_safe_bm;
1555 unsigned reg_safe_bm_size;
1556 u32 resync_scratch;
1557 u32 hdp_cntl;
1558 };
1559
1560 struct r600_asic {
1561 unsigned max_pipes;
1562 unsigned max_tile_pipes;
1563 unsigned max_simds;
1564 unsigned max_backends;
1565 unsigned max_gprs;
1566 unsigned max_threads;
1567 unsigned max_stack_entries;
1568 unsigned max_hw_contexts;
1569 unsigned max_gs_threads;
1570 unsigned sx_max_export_size;
1571 unsigned sx_max_export_pos_size;
1572 unsigned sx_max_export_smx_size;
1573 unsigned sq_num_cf_insts;
1574 unsigned tiling_nbanks;
1575 unsigned tiling_npipes;
1576 unsigned tiling_group_size;
1577 unsigned tile_config;
1578 unsigned backend_map;
1579 };
1580
1581 struct rv770_asic {
1582 unsigned max_pipes;
1583 unsigned max_tile_pipes;
1584 unsigned max_simds;
1585 unsigned max_backends;
1586 unsigned max_gprs;
1587 unsigned max_threads;
1588 unsigned max_stack_entries;
1589 unsigned max_hw_contexts;
1590 unsigned max_gs_threads;
1591 unsigned sx_max_export_size;
1592 unsigned sx_max_export_pos_size;
1593 unsigned sx_max_export_smx_size;
1594 unsigned sq_num_cf_insts;
1595 unsigned sx_num_of_sets;
1596 unsigned sc_prim_fifo_size;
1597 unsigned sc_hiz_tile_fifo_size;
1598 unsigned sc_earlyz_tile_fifo_fize;
1599 unsigned tiling_nbanks;
1600 unsigned tiling_npipes;
1601 unsigned tiling_group_size;
1602 unsigned tile_config;
1603 unsigned backend_map;
1604 };
1605
1606 struct evergreen_asic {
1607 unsigned num_ses;
1608 unsigned max_pipes;
1609 unsigned max_tile_pipes;
1610 unsigned max_simds;
1611 unsigned max_backends;
1612 unsigned max_gprs;
1613 unsigned max_threads;
1614 unsigned max_stack_entries;
1615 unsigned max_hw_contexts;
1616 unsigned max_gs_threads;
1617 unsigned sx_max_export_size;
1618 unsigned sx_max_export_pos_size;
1619 unsigned sx_max_export_smx_size;
1620 unsigned sq_num_cf_insts;
1621 unsigned sx_num_of_sets;
1622 unsigned sc_prim_fifo_size;
1623 unsigned sc_hiz_tile_fifo_size;
1624 unsigned sc_earlyz_tile_fifo_size;
1625 unsigned tiling_nbanks;
1626 unsigned tiling_npipes;
1627 unsigned tiling_group_size;
1628 unsigned tile_config;
1629 unsigned backend_map;
1630 };
1631
1632 struct cayman_asic {
1633 unsigned max_shader_engines;
1634 unsigned max_pipes_per_simd;
1635 unsigned max_tile_pipes;
1636 unsigned max_simds_per_se;
1637 unsigned max_backends_per_se;
1638 unsigned max_texture_channel_caches;
1639 unsigned max_gprs;
1640 unsigned max_threads;
1641 unsigned max_gs_threads;
1642 unsigned max_stack_entries;
1643 unsigned sx_num_of_sets;
1644 unsigned sx_max_export_size;
1645 unsigned sx_max_export_pos_size;
1646 unsigned sx_max_export_smx_size;
1647 unsigned max_hw_contexts;
1648 unsigned sq_num_cf_insts;
1649 unsigned sc_prim_fifo_size;
1650 unsigned sc_hiz_tile_fifo_size;
1651 unsigned sc_earlyz_tile_fifo_size;
1652
1653 unsigned num_shader_engines;
1654 unsigned num_shader_pipes_per_simd;
1655 unsigned num_tile_pipes;
1656 unsigned num_simds_per_se;
1657 unsigned num_backends_per_se;
1658 unsigned backend_disable_mask_per_asic;
1659 unsigned backend_map;
1660 unsigned num_texture_channel_caches;
1661 unsigned mem_max_burst_length_bytes;
1662 unsigned mem_row_size_in_kb;
1663 unsigned shader_engine_tile_size;
1664 unsigned num_gpus;
1665 unsigned multi_gpu_tile_size;
1666
1667 unsigned tile_config;
1668 };
1669
1670 struct si_asic {
1671 unsigned max_shader_engines;
1672 unsigned max_tile_pipes;
1673 unsigned max_cu_per_sh;
1674 unsigned max_sh_per_se;
1675 unsigned max_backends_per_se;
1676 unsigned max_texture_channel_caches;
1677 unsigned max_gprs;
1678 unsigned max_gs_threads;
1679 unsigned max_hw_contexts;
1680 unsigned sc_prim_fifo_size_frontend;
1681 unsigned sc_prim_fifo_size_backend;
1682 unsigned sc_hiz_tile_fifo_size;
1683 unsigned sc_earlyz_tile_fifo_size;
1684
1685 unsigned num_tile_pipes;
1686 unsigned num_backends_per_se;
1687 unsigned backend_disable_mask_per_asic;
1688 unsigned backend_map;
1689 unsigned num_texture_channel_caches;
1690 unsigned mem_max_burst_length_bytes;
1691 unsigned mem_row_size_in_kb;
1692 unsigned shader_engine_tile_size;
1693 unsigned num_gpus;
1694 unsigned multi_gpu_tile_size;
1695
1696 unsigned tile_config;
1697 uint32_t tile_mode_array[32];
1698 };
1699
1700 struct cik_asic {
1701 unsigned max_shader_engines;
1702 unsigned max_tile_pipes;
1703 unsigned max_cu_per_sh;
1704 unsigned max_sh_per_se;
1705 unsigned max_backends_per_se;
1706 unsigned max_texture_channel_caches;
1707 unsigned max_gprs;
1708 unsigned max_gs_threads;
1709 unsigned max_hw_contexts;
1710 unsigned sc_prim_fifo_size_frontend;
1711 unsigned sc_prim_fifo_size_backend;
1712 unsigned sc_hiz_tile_fifo_size;
1713 unsigned sc_earlyz_tile_fifo_size;
1714
1715 unsigned num_tile_pipes;
1716 unsigned num_backends_per_se;
1717 unsigned backend_disable_mask_per_asic;
1718 unsigned backend_map;
1719 unsigned num_texture_channel_caches;
1720 unsigned mem_max_burst_length_bytes;
1721 unsigned mem_row_size_in_kb;
1722 unsigned shader_engine_tile_size;
1723 unsigned num_gpus;
1724 unsigned multi_gpu_tile_size;
1725
1726 unsigned tile_config;
1727 uint32_t tile_mode_array[32];
1728 };
1729
1730 union radeon_asic_config {
1731 struct r300_asic r300;
1732 struct r100_asic r100;
1733 struct r600_asic r600;
1734 struct rv770_asic rv770;
1735 struct evergreen_asic evergreen;
1736 struct cayman_asic cayman;
1737 struct si_asic si;
1738 struct cik_asic cik;
1739 };
1740
1741 /*
1742 * asic initizalization from radeon_asic.c
1743 */
1744 void radeon_agp_disable(struct radeon_device *rdev);
1745 int radeon_asic_init(struct radeon_device *rdev);
1746
1747
1748 /*
1749 * IOCTL.
1750 */
1751 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1752 struct drm_file *filp);
1753 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1754 struct drm_file *filp);
1755 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1756 struct drm_file *file_priv);
1757 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1758 struct drm_file *file_priv);
1759 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1760 struct drm_file *file_priv);
1761 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1762 struct drm_file *file_priv);
1763 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1764 struct drm_file *filp);
1765 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1766 struct drm_file *filp);
1767 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1768 struct drm_file *filp);
1769 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1770 struct drm_file *filp);
1771 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1772 struct drm_file *filp);
1773 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1774 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1775 struct drm_file *filp);
1776 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1777 struct drm_file *filp);
1778
1779 /* VRAM scratch page for HDP bug, default vram page */
1780 struct r600_vram_scratch {
1781 struct radeon_bo *robj;
1782 volatile uint32_t *ptr;
1783 u64 gpu_addr;
1784 };
1785
1786 /*
1787 * ACPI
1788 */
1789 struct radeon_atif_notification_cfg {
1790 bool enabled;
1791 int command_code;
1792 };
1793
1794 struct radeon_atif_notifications {
1795 bool display_switch;
1796 bool expansion_mode_change;
1797 bool thermal_state;
1798 bool forced_power_state;
1799 bool system_power_state;
1800 bool display_conf_change;
1801 bool px_gfx_switch;
1802 bool brightness_change;
1803 bool dgpu_display_event;
1804 };
1805
1806 struct radeon_atif_functions {
1807 bool system_params;
1808 bool sbios_requests;
1809 bool select_active_disp;
1810 bool lid_state;
1811 bool get_tv_standard;
1812 bool set_tv_standard;
1813 bool get_panel_expansion_mode;
1814 bool set_panel_expansion_mode;
1815 bool temperature_change;
1816 bool graphics_device_types;
1817 };
1818
1819 struct radeon_atif {
1820 struct radeon_atif_notifications notifications;
1821 struct radeon_atif_functions functions;
1822 struct radeon_atif_notification_cfg notification_cfg;
1823 struct radeon_encoder *encoder_for_bl;
1824 };
1825
1826 struct radeon_atcs_functions {
1827 bool get_ext_state;
1828 bool pcie_perf_req;
1829 bool pcie_dev_rdy;
1830 bool pcie_bus_width;
1831 };
1832
1833 struct radeon_atcs {
1834 struct radeon_atcs_functions functions;
1835 };
1836
1837 /*
1838 * Core structure, functions and helpers.
1839 */
1840 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1841 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1842
1843 struct radeon_device {
1844 struct device *dev;
1845 struct drm_device *ddev;
1846 struct pci_dev *pdev;
1847 struct rw_semaphore exclusive_lock;
1848 /* ASIC */
1849 union radeon_asic_config config;
1850 enum radeon_family family;
1851 unsigned long flags;
1852 int usec_timeout;
1853 enum radeon_pll_errata pll_errata;
1854 int num_gb_pipes;
1855 int num_z_pipes;
1856 int disp_priority;
1857 /* BIOS */
1858 uint8_t *bios;
1859 bool is_atom_bios;
1860 uint16_t bios_header_start;
1861 struct radeon_bo *stollen_vga_memory;
1862 /* Register mmio */
1863 resource_size_t rmmio_base;
1864 resource_size_t rmmio_size;
1865 /* protects concurrent MM_INDEX/DATA based register access */
1866 spinlock_t mmio_idx_lock;
1867 void __iomem *rmmio;
1868 radeon_rreg_t mc_rreg;
1869 radeon_wreg_t mc_wreg;
1870 radeon_rreg_t pll_rreg;
1871 radeon_wreg_t pll_wreg;
1872 uint32_t pcie_reg_mask;
1873 radeon_rreg_t pciep_rreg;
1874 radeon_wreg_t pciep_wreg;
1875 /* io port */
1876 void __iomem *rio_mem;
1877 resource_size_t rio_mem_size;
1878 struct radeon_clock clock;
1879 struct radeon_mc mc;
1880 struct radeon_gart gart;
1881 struct radeon_mode_info mode_info;
1882 struct radeon_scratch scratch;
1883 struct radeon_doorbell doorbell;
1884 struct radeon_mman mman;
1885 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1886 wait_queue_head_t fence_queue;
1887 struct mutex ring_lock;
1888 struct radeon_ring ring[RADEON_NUM_RINGS];
1889 bool ib_pool_ready;
1890 struct radeon_sa_manager ring_tmp_bo;
1891 struct radeon_irq irq;
1892 struct radeon_asic *asic;
1893 struct radeon_gem gem;
1894 struct radeon_pm pm;
1895 struct radeon_uvd uvd;
1896 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1897 struct radeon_wb wb;
1898 struct radeon_dummy_page dummy_page;
1899 bool shutdown;
1900 bool suspend;
1901 bool need_dma32;
1902 bool accel_working;
1903 bool fastfb_working; /* IGP feature*/
1904 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1905 const struct firmware *me_fw; /* all family ME firmware */
1906 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1907 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1908 const struct firmware *mc_fw; /* NI MC firmware */
1909 const struct firmware *ce_fw; /* SI CE firmware */
1910 const struct firmware *uvd_fw; /* UVD firmware */
1911 const struct firmware *mec_fw; /* CIK MEC firmware */
1912 const struct firmware *sdma_fw; /* CIK SDMA firmware */
1913 struct r600_blit r600_blit;
1914 struct r600_vram_scratch vram_scratch;
1915 int msi_enabled; /* msi enabled */
1916 struct r600_ih ih; /* r6/700 interrupt ring */
1917 struct radeon_rlc rlc;
1918 struct radeon_mec mec;
1919 struct work_struct hotplug_work;
1920 struct work_struct audio_work;
1921 struct work_struct reset_work;
1922 int num_crtc; /* number of crtcs */
1923 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1924 bool audio_enabled;
1925 bool has_uvd;
1926 struct r600_audio audio_status; /* audio stuff */
1927 struct notifier_block acpi_nb;
1928 /* only one userspace can use Hyperz features or CMASK at a time */
1929 struct drm_file *hyperz_filp;
1930 struct drm_file *cmask_filp;
1931 /* i2c buses */
1932 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1933 /* debugfs */
1934 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1935 unsigned debugfs_count;
1936 /* virtual memory */
1937 struct radeon_vm_manager vm_manager;
1938 struct mutex gpu_clock_mutex;
1939 /* ACPI interface */
1940 struct radeon_atif atif;
1941 struct radeon_atcs atcs;
1942 };
1943
1944 int radeon_device_init(struct radeon_device *rdev,
1945 struct drm_device *ddev,
1946 struct pci_dev *pdev,
1947 uint32_t flags);
1948 void radeon_device_fini(struct radeon_device *rdev);
1949 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1950
1951 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1952 bool always_indirect);
1953 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1954 bool always_indirect);
1955 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1956 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1957
1958 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
1959 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
1960
1961 /*
1962 * Cast helper
1963 */
1964 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1965
1966 /*
1967 * Registers read & write functions.
1968 */
1969 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1970 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1971 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1972 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1973 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1974 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1975 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1976 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1977 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1978 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1979 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1980 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1981 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1982 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1983 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1984 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1985 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1986 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1987 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1988 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
1989 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
1990 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
1991 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
1992 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
1993 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
1994 #define WREG32_P(reg, val, mask) \
1995 do { \
1996 uint32_t tmp_ = RREG32(reg); \
1997 tmp_ &= (mask); \
1998 tmp_ |= ((val) & ~(mask)); \
1999 WREG32(reg, tmp_); \
2000 } while (0)
2001 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2002 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
2003 #define WREG32_PLL_P(reg, val, mask) \
2004 do { \
2005 uint32_t tmp_ = RREG32_PLL(reg); \
2006 tmp_ &= (mask); \
2007 tmp_ |= ((val) & ~(mask)); \
2008 WREG32_PLL(reg, tmp_); \
2009 } while (0)
2010 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2011 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2012 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2013
2014 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2015 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2016
2017 /*
2018 * Indirect registers accessor
2019 */
2020 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2021 {
2022 uint32_t r;
2023
2024 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2025 r = RREG32(RADEON_PCIE_DATA);
2026 return r;
2027 }
2028
2029 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2030 {
2031 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2032 WREG32(RADEON_PCIE_DATA, (v));
2033 }
2034
2035 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2036 {
2037 u32 r;
2038
2039 WREG32(TN_SMC_IND_INDEX_0, (reg));
2040 r = RREG32(TN_SMC_IND_DATA_0);
2041 return r;
2042 }
2043
2044 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2045 {
2046 WREG32(TN_SMC_IND_INDEX_0, (reg));
2047 WREG32(TN_SMC_IND_DATA_0, (v));
2048 }
2049
2050 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2051 {
2052 u32 r;
2053
2054 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2055 r = RREG32(R600_RCU_DATA);
2056 return r;
2057 }
2058
2059 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2060 {
2061 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2062 WREG32(R600_RCU_DATA, (v));
2063 }
2064
2065 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2066 {
2067 u32 r;
2068
2069 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2070 r = RREG32(EVERGREEN_CG_IND_DATA);
2071 return r;
2072 }
2073
2074 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2075 {
2076 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2077 WREG32(EVERGREEN_CG_IND_DATA, (v));
2078 }
2079
2080 void r100_pll_errata_after_index(struct radeon_device *rdev);
2081
2082
2083 /*
2084 * ASICs helpers.
2085 */
2086 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2087 (rdev->pdev->device == 0x5969))
2088 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2089 (rdev->family == CHIP_RV200) || \
2090 (rdev->family == CHIP_RS100) || \
2091 (rdev->family == CHIP_RS200) || \
2092 (rdev->family == CHIP_RV250) || \
2093 (rdev->family == CHIP_RV280) || \
2094 (rdev->family == CHIP_RS300))
2095 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2096 (rdev->family == CHIP_RV350) || \
2097 (rdev->family == CHIP_R350) || \
2098 (rdev->family == CHIP_RV380) || \
2099 (rdev->family == CHIP_R420) || \
2100 (rdev->family == CHIP_R423) || \
2101 (rdev->family == CHIP_RV410) || \
2102 (rdev->family == CHIP_RS400) || \
2103 (rdev->family == CHIP_RS480))
2104 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2105 (rdev->ddev->pdev->device == 0x9443) || \
2106 (rdev->ddev->pdev->device == 0x944B) || \
2107 (rdev->ddev->pdev->device == 0x9506) || \
2108 (rdev->ddev->pdev->device == 0x9509) || \
2109 (rdev->ddev->pdev->device == 0x950F) || \
2110 (rdev->ddev->pdev->device == 0x689C) || \
2111 (rdev->ddev->pdev->device == 0x689D))
2112 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2113 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2114 (rdev->family == CHIP_RS690) || \
2115 (rdev->family == CHIP_RS740) || \
2116 (rdev->family >= CHIP_R600))
2117 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2118 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2119 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2120 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2121 (rdev->flags & RADEON_IS_IGP))
2122 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2123 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2124 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2125 (rdev->flags & RADEON_IS_IGP))
2126 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2127 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2128 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2129
2130 /*
2131 * BIOS helpers.
2132 */
2133 #define RBIOS8(i) (rdev->bios[i])
2134 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2135 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2136
2137 int radeon_combios_init(struct radeon_device *rdev);
2138 void radeon_combios_fini(struct radeon_device *rdev);
2139 int radeon_atombios_init(struct radeon_device *rdev);
2140 void radeon_atombios_fini(struct radeon_device *rdev);
2141
2142
2143 /*
2144 * RING helpers.
2145 */
2146 #if DRM_DEBUG_CODE == 0
2147 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2148 {
2149 ring->ring[ring->wptr++] = v;
2150 ring->wptr &= ring->ptr_mask;
2151 ring->count_dw--;
2152 ring->ring_free_dw--;
2153 }
2154 #else
2155 /* With debugging this is just too big to inline */
2156 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2157 #endif
2158
2159 /*
2160 * ASICs macro.
2161 */
2162 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2163 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2164 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2165 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2166 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2167 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2168 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2169 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2170 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2171 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2172 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2173 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2174 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2175 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2176 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2177 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2178 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2179 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2180 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2181 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2182 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2183 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2184 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2185 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2186 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2187 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2188 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2189 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2190 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2191 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2192 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2193 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2194 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2195 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2196 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2197 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2198 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2199 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2200 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2201 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2202 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2203 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2204 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2205 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2206 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2207 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2208 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2209 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2210 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2211 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2212 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2213 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2214 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2215 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2216 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2217 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2218 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2219 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2220 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2221 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2222 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2223 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2224 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2225 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2226 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2227 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2228 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2229 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2230 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2231 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2232 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2233 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2234 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2235 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2236 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2237 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2238
2239 /* Common functions */
2240 /* AGP */
2241 extern int radeon_gpu_reset(struct radeon_device *rdev);
2242 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2243 extern void radeon_agp_disable(struct radeon_device *rdev);
2244 extern int radeon_modeset_init(struct radeon_device *rdev);
2245 extern void radeon_modeset_fini(struct radeon_device *rdev);
2246 extern bool radeon_card_posted(struct radeon_device *rdev);
2247 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2248 extern void radeon_update_display_priority(struct radeon_device *rdev);
2249 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2250 extern void radeon_scratch_init(struct radeon_device *rdev);
2251 extern void radeon_wb_fini(struct radeon_device *rdev);
2252 extern int radeon_wb_init(struct radeon_device *rdev);
2253 extern void radeon_wb_disable(struct radeon_device *rdev);
2254 extern void radeon_surface_init(struct radeon_device *rdev);
2255 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2256 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2257 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2258 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2259 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2260 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2261 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2262 extern int radeon_resume_kms(struct drm_device *dev);
2263 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2264 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2265 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2266 const u32 *registers,
2267 const u32 array_size);
2268
2269 /*
2270 * vm
2271 */
2272 int radeon_vm_manager_init(struct radeon_device *rdev);
2273 void radeon_vm_manager_fini(struct radeon_device *rdev);
2274 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2275 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2276 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2277 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2278 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2279 struct radeon_vm *vm, int ring);
2280 void radeon_vm_fence(struct radeon_device *rdev,
2281 struct radeon_vm *vm,
2282 struct radeon_fence *fence);
2283 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2284 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2285 struct radeon_vm *vm,
2286 struct radeon_bo *bo,
2287 struct ttm_mem_reg *mem);
2288 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2289 struct radeon_bo *bo);
2290 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2291 struct radeon_bo *bo);
2292 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2293 struct radeon_vm *vm,
2294 struct radeon_bo *bo);
2295 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2296 struct radeon_bo_va *bo_va,
2297 uint64_t offset,
2298 uint32_t flags);
2299 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2300 struct radeon_bo_va *bo_va);
2301
2302 /* audio */
2303 void r600_audio_update_hdmi(struct work_struct *work);
2304
2305 /*
2306 * R600 vram scratch functions
2307 */
2308 int r600_vram_scratch_init(struct radeon_device *rdev);
2309 void r600_vram_scratch_fini(struct radeon_device *rdev);
2310
2311 /*
2312 * r600 cs checking helper
2313 */
2314 unsigned r600_mip_minify(unsigned size, unsigned level);
2315 bool r600_fmt_is_valid_color(u32 format);
2316 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2317 int r600_fmt_get_blocksize(u32 format);
2318 int r600_fmt_get_nblocksx(u32 format, u32 w);
2319 int r600_fmt_get_nblocksy(u32 format, u32 h);
2320
2321 /*
2322 * r600 functions used by radeon_encoder.c
2323 */
2324 struct radeon_hdmi_acr {
2325 u32 clock;
2326
2327 int n_32khz;
2328 int cts_32khz;
2329
2330 int n_44_1khz;
2331 int cts_44_1khz;
2332
2333 int n_48khz;
2334 int cts_48khz;
2335
2336 };
2337
2338 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2339
2340 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2341 u32 tiling_pipe_num,
2342 u32 max_rb_num,
2343 u32 total_max_rb_num,
2344 u32 enabled_rb_mask);
2345
2346 /*
2347 * evergreen functions used by radeon_encoder.c
2348 */
2349
2350 extern int ni_init_microcode(struct radeon_device *rdev);
2351 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2352
2353 /* radeon_acpi.c */
2354 #if defined(CONFIG_ACPI)
2355 extern int radeon_acpi_init(struct radeon_device *rdev);
2356 extern void radeon_acpi_fini(struct radeon_device *rdev);
2357 #else
2358 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2359 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2360 #endif
2361
2362 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2363 struct radeon_cs_packet *pkt,
2364 unsigned idx);
2365 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2366 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2367 struct radeon_cs_packet *pkt);
2368 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2369 struct radeon_cs_reloc **cs_reloc,
2370 int nomm);
2371 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2372 uint32_t *vline_start_end,
2373 uint32_t *vline_status);
2374
2375 #include "radeon_object.h"
2376
2377 #endif
Linux kernel - Deliverables
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