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drm/radeon: remove duplicates check
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
70
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
76
77 #include <drm/drm_gem.h>
78
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
82
83 /*
84 * Modules parameters.
85 */
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
96 extern int radeon_tv;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
114
115 /*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121 /* RADEON_IB_POOL_SIZE must be a power of 2 */
122 #define RADEON_IB_POOL_SIZE 16
123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
124 #define RADEONFB_CONN_LIMIT 4
125 #define RADEON_BIOS_NUM_SCRATCH 8
126
127 /* internal ring indices */
128 /* r1xx+ has gfx CP ring */
129 #define RADEON_RING_TYPE_GFX_INDEX 0
130
131 /* cayman has 2 compute CP rings */
132 #define CAYMAN_RING_TYPE_CP1_INDEX 1
133 #define CAYMAN_RING_TYPE_CP2_INDEX 2
134
135 /* R600+ has an async dma ring */
136 #define R600_RING_TYPE_DMA_INDEX 3
137 /* cayman add a second async dma ring */
138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
139
140 /* R600+ */
141 #define R600_RING_TYPE_UVD_INDEX 5
142
143 /* TN+ */
144 #define TN_RING_TYPE_VCE1_INDEX 6
145 #define TN_RING_TYPE_VCE2_INDEX 7
146
147 /* max number of rings */
148 #define RADEON_NUM_RINGS 8
149
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
152
153 /* hardcode those limit for now */
154 #define RADEON_VA_IB_OFFSET (1 << 20)
155 #define RADEON_VA_RESERVED_SIZE (8 << 20)
156 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
157
158 /* hard reset data */
159 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
160
161 /* reset flags */
162 #define RADEON_RESET_GFX (1 << 0)
163 #define RADEON_RESET_COMPUTE (1 << 1)
164 #define RADEON_RESET_DMA (1 << 2)
165 #define RADEON_RESET_CP (1 << 3)
166 #define RADEON_RESET_GRBM (1 << 4)
167 #define RADEON_RESET_DMA1 (1 << 5)
168 #define RADEON_RESET_RLC (1 << 6)
169 #define RADEON_RESET_SEM (1 << 7)
170 #define RADEON_RESET_IH (1 << 8)
171 #define RADEON_RESET_VMC (1 << 9)
172 #define RADEON_RESET_MC (1 << 10)
173 #define RADEON_RESET_DISPLAY (1 << 11)
174
175 /* CG block flags */
176 #define RADEON_CG_BLOCK_GFX (1 << 0)
177 #define RADEON_CG_BLOCK_MC (1 << 1)
178 #define RADEON_CG_BLOCK_SDMA (1 << 2)
179 #define RADEON_CG_BLOCK_UVD (1 << 3)
180 #define RADEON_CG_BLOCK_VCE (1 << 4)
181 #define RADEON_CG_BLOCK_HDP (1 << 5)
182 #define RADEON_CG_BLOCK_BIF (1 << 6)
183
184 /* CG flags */
185 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
186 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
187 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
188 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
189 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
190 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
191 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
192 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
193 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
194 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
195 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
196 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
197 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
198 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
199 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
200 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
201 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
202
203 /* PG flags */
204 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
205 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
206 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
207 #define RADEON_PG_SUPPORT_UVD (1 << 3)
208 #define RADEON_PG_SUPPORT_VCE (1 << 4)
209 #define RADEON_PG_SUPPORT_CP (1 << 5)
210 #define RADEON_PG_SUPPORT_GDS (1 << 6)
211 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
212 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
213 #define RADEON_PG_SUPPORT_ACP (1 << 9)
214 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
215
216 /* max cursor sizes (in pixels) */
217 #define CURSOR_WIDTH 64
218 #define CURSOR_HEIGHT 64
219
220 #define CIK_CURSOR_WIDTH 128
221 #define CIK_CURSOR_HEIGHT 128
222
223 /*
224 * Errata workarounds.
225 */
226 enum radeon_pll_errata {
227 CHIP_ERRATA_R300_CG = 0x00000001,
228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
229 CHIP_ERRATA_PLL_DELAY = 0x00000004
230 };
231
232
233 struct radeon_device;
234
235
236 /*
237 * BIOS.
238 */
239 bool radeon_get_bios(struct radeon_device *rdev);
240
241 /*
242 * Dummy page
243 */
244 struct radeon_dummy_page {
245 struct page *page;
246 dma_addr_t addr;
247 };
248 int radeon_dummy_page_init(struct radeon_device *rdev);
249 void radeon_dummy_page_fini(struct radeon_device *rdev);
250
251
252 /*
253 * Clocks
254 */
255 struct radeon_clock {
256 struct radeon_pll p1pll;
257 struct radeon_pll p2pll;
258 struct radeon_pll dcpll;
259 struct radeon_pll spll;
260 struct radeon_pll mpll;
261 /* 10 Khz units */
262 uint32_t default_mclk;
263 uint32_t default_sclk;
264 uint32_t default_dispclk;
265 uint32_t current_dispclk;
266 uint32_t dp_extclk;
267 uint32_t max_pixel_clock;
268 };
269
270 /*
271 * Power management
272 */
273 int radeon_pm_init(struct radeon_device *rdev);
274 int radeon_pm_late_init(struct radeon_device *rdev);
275 void radeon_pm_fini(struct radeon_device *rdev);
276 void radeon_pm_compute_clocks(struct radeon_device *rdev);
277 void radeon_pm_suspend(struct radeon_device *rdev);
278 void radeon_pm_resume(struct radeon_device *rdev);
279 void radeon_combios_get_power_modes(struct radeon_device *rdev);
280 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
281 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
282 u8 clock_type,
283 u32 clock,
284 bool strobe_mode,
285 struct atom_clock_dividers *dividers);
286 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
287 u32 clock,
288 bool strobe_mode,
289 struct atom_mpll_param *mpll_param);
290 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
291 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
292 u16 voltage_level, u8 voltage_type,
293 u32 *gpio_value, u32 *gpio_mask);
294 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
295 u32 eng_clock, u32 mem_clock);
296 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
297 u8 voltage_type, u16 *voltage_step);
298 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
299 u16 voltage_id, u16 *voltage);
300 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
301 u16 *voltage,
302 u16 leakage_idx);
303 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
304 u16 *leakage_id);
305 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
306 u16 *vddc, u16 *vddci,
307 u16 virtual_voltage_id,
308 u16 vbios_voltage_id);
309 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
310 u16 virtual_voltage_id,
311 u16 *voltage);
312 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
313 u8 voltage_type,
314 u16 nominal_voltage,
315 u16 *true_voltage);
316 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
317 u8 voltage_type, u16 *min_voltage);
318 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *max_voltage);
320 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
321 u8 voltage_type, u8 voltage_mode,
322 struct atom_voltage_table *voltage_table);
323 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode);
325 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
326 u8 voltage_type,
327 u8 *svd_gpio_id, u8 *svc_gpio_id);
328 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
329 u32 mem_clock);
330 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
331 u32 mem_clock);
332 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
333 u8 module_index,
334 struct atom_mc_reg_table *reg_table);
335 int radeon_atom_get_memory_info(struct radeon_device *rdev,
336 u8 module_index, struct atom_memory_info *mem_info);
337 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
338 bool gddr5, u8 module_index,
339 struct atom_memory_clock_range_table *mclk_range_table);
340 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
341 u16 voltage_id, u16 *voltage);
342 void rs690_pm_info(struct radeon_device *rdev);
343 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 unsigned *bankh, unsigned *mtaspect,
345 unsigned *tile_split);
346
347 /*
348 * Fences.
349 */
350 struct radeon_fence_driver {
351 struct radeon_device *rdev;
352 uint32_t scratch_reg;
353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
357 atomic64_t last_seq;
358 bool initialized, delayed_irq;
359 struct delayed_work lockup_work;
360 };
361
362 struct radeon_fence {
363 struct fence base;
364
365 struct radeon_device *rdev;
366 uint64_t seq;
367 /* RB, DMA, etc. */
368 unsigned ring;
369 bool is_vm_update;
370
371 wait_queue_t fence_wake;
372 };
373
374 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
375 int radeon_fence_driver_init(struct radeon_device *rdev);
376 void radeon_fence_driver_fini(struct radeon_device *rdev);
377 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
378 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
379 void radeon_fence_process(struct radeon_device *rdev, int ring);
380 bool radeon_fence_signaled(struct radeon_fence *fence);
381 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
382 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
383 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
384 int radeon_fence_wait_any(struct radeon_device *rdev,
385 struct radeon_fence **fences,
386 bool intr);
387 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
388 void radeon_fence_unref(struct radeon_fence **fence);
389 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
390 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
391 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
392 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
393 struct radeon_fence *b)
394 {
395 if (!a) {
396 return b;
397 }
398
399 if (!b) {
400 return a;
401 }
402
403 BUG_ON(a->ring != b->ring);
404
405 if (a->seq > b->seq) {
406 return a;
407 } else {
408 return b;
409 }
410 }
411
412 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
413 struct radeon_fence *b)
414 {
415 if (!a) {
416 return false;
417 }
418
419 if (!b) {
420 return true;
421 }
422
423 BUG_ON(a->ring != b->ring);
424
425 return a->seq < b->seq;
426 }
427
428 /*
429 * Tiling registers
430 */
431 struct radeon_surface_reg {
432 struct radeon_bo *bo;
433 };
434
435 #define RADEON_GEM_MAX_SURFACES 8
436
437 /*
438 * TTM.
439 */
440 struct radeon_mman {
441 struct ttm_bo_global_ref bo_global_ref;
442 struct drm_global_reference mem_global_ref;
443 struct ttm_bo_device bdev;
444 bool mem_global_referenced;
445 bool initialized;
446
447 #if defined(CONFIG_DEBUG_FS)
448 struct dentry *vram;
449 struct dentry *gtt;
450 #endif
451 };
452
453 struct radeon_bo_list {
454 struct radeon_bo *robj;
455 struct ttm_validate_buffer tv;
456 uint64_t gpu_offset;
457 unsigned prefered_domains;
458 unsigned allowed_domains;
459 uint32_t tiling_flags;
460 };
461
462 /* bo virtual address in a specific vm */
463 struct radeon_bo_va {
464 /* protected by bo being reserved */
465 struct list_head bo_list;
466 uint32_t flags;
467 uint64_t addr;
468 struct radeon_fence *last_pt_update;
469 unsigned ref_count;
470
471 /* protected by vm mutex */
472 struct interval_tree_node it;
473 struct list_head vm_status;
474
475 /* constant after initialization */
476 struct radeon_vm *vm;
477 struct radeon_bo *bo;
478 };
479
480 struct radeon_bo {
481 /* Protected by gem.mutex */
482 struct list_head list;
483 /* Protected by tbo.reserved */
484 u32 initial_domain;
485 struct ttm_place placements[4];
486 struct ttm_placement placement;
487 struct ttm_buffer_object tbo;
488 struct ttm_bo_kmap_obj kmap;
489 u32 flags;
490 unsigned pin_count;
491 void *kptr;
492 u32 tiling_flags;
493 u32 pitch;
494 int surface_reg;
495 /* list of all virtual address to which this bo
496 * is associated to
497 */
498 struct list_head va;
499 /* Constant after initialization */
500 struct radeon_device *rdev;
501 struct drm_gem_object gem_base;
502
503 struct ttm_bo_kmap_obj dma_buf_vmap;
504 pid_t pid;
505
506 struct radeon_mn *mn;
507 struct interval_tree_node mn_it;
508 };
509 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
510
511 int radeon_gem_debugfs_init(struct radeon_device *rdev);
512
513 /* sub-allocation manager, it has to be protected by another lock.
514 * By conception this is an helper for other part of the driver
515 * like the indirect buffer or semaphore, which both have their
516 * locking.
517 *
518 * Principe is simple, we keep a list of sub allocation in offset
519 * order (first entry has offset == 0, last entry has the highest
520 * offset).
521 *
522 * When allocating new object we first check if there is room at
523 * the end total_size - (last_object_offset + last_object_size) >=
524 * alloc_size. If so we allocate new object there.
525 *
526 * When there is not enough room at the end, we start waiting for
527 * each sub object until we reach object_offset+object_size >=
528 * alloc_size, this object then become the sub object we return.
529 *
530 * Alignment can't be bigger than page size.
531 *
532 * Hole are not considered for allocation to keep things simple.
533 * Assumption is that there won't be hole (all object on same
534 * alignment).
535 */
536 struct radeon_sa_manager {
537 wait_queue_head_t wq;
538 struct radeon_bo *bo;
539 struct list_head *hole;
540 struct list_head flist[RADEON_NUM_RINGS];
541 struct list_head olist;
542 unsigned size;
543 uint64_t gpu_addr;
544 void *cpu_ptr;
545 uint32_t domain;
546 uint32_t align;
547 };
548
549 struct radeon_sa_bo;
550
551 /* sub-allocation buffer */
552 struct radeon_sa_bo {
553 struct list_head olist;
554 struct list_head flist;
555 struct radeon_sa_manager *manager;
556 unsigned soffset;
557 unsigned eoffset;
558 struct radeon_fence *fence;
559 };
560
561 /*
562 * GEM objects.
563 */
564 struct radeon_gem {
565 struct mutex mutex;
566 struct list_head objects;
567 };
568
569 int radeon_gem_init(struct radeon_device *rdev);
570 void radeon_gem_fini(struct radeon_device *rdev);
571 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
572 int alignment, int initial_domain,
573 u32 flags, bool kernel,
574 struct drm_gem_object **obj);
575
576 int radeon_mode_dumb_create(struct drm_file *file_priv,
577 struct drm_device *dev,
578 struct drm_mode_create_dumb *args);
579 int radeon_mode_dumb_mmap(struct drm_file *filp,
580 struct drm_device *dev,
581 uint32_t handle, uint64_t *offset_p);
582
583 /*
584 * Semaphores.
585 */
586 struct radeon_semaphore {
587 struct radeon_sa_bo *sa_bo;
588 signed waiters;
589 uint64_t gpu_addr;
590 };
591
592 int radeon_semaphore_create(struct radeon_device *rdev,
593 struct radeon_semaphore **semaphore);
594 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
595 struct radeon_semaphore *semaphore);
596 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
597 struct radeon_semaphore *semaphore);
598 void radeon_semaphore_free(struct radeon_device *rdev,
599 struct radeon_semaphore **semaphore,
600 struct radeon_fence *fence);
601
602 /*
603 * Synchronization
604 */
605 struct radeon_sync {
606 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
607 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
608 struct radeon_fence *last_vm_update;
609 };
610
611 void radeon_sync_create(struct radeon_sync *sync);
612 void radeon_sync_fence(struct radeon_sync *sync,
613 struct radeon_fence *fence);
614 int radeon_sync_resv(struct radeon_device *rdev,
615 struct radeon_sync *sync,
616 struct reservation_object *resv,
617 bool shared);
618 int radeon_sync_rings(struct radeon_device *rdev,
619 struct radeon_sync *sync,
620 int waiting_ring);
621 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
622 struct radeon_fence *fence);
623
624 /*
625 * GART structures, functions & helpers
626 */
627 struct radeon_mc;
628
629 #define RADEON_GPU_PAGE_SIZE 4096
630 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
631 #define RADEON_GPU_PAGE_SHIFT 12
632 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
633
634 #define RADEON_GART_PAGE_DUMMY 0
635 #define RADEON_GART_PAGE_VALID (1 << 0)
636 #define RADEON_GART_PAGE_READ (1 << 1)
637 #define RADEON_GART_PAGE_WRITE (1 << 2)
638 #define RADEON_GART_PAGE_SNOOP (1 << 3)
639
640 struct radeon_gart {
641 dma_addr_t table_addr;
642 struct radeon_bo *robj;
643 void *ptr;
644 unsigned num_gpu_pages;
645 unsigned num_cpu_pages;
646 unsigned table_size;
647 struct page **pages;
648 dma_addr_t *pages_addr;
649 bool ready;
650 };
651
652 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
653 void radeon_gart_table_ram_free(struct radeon_device *rdev);
654 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
655 void radeon_gart_table_vram_free(struct radeon_device *rdev);
656 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
657 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
658 int radeon_gart_init(struct radeon_device *rdev);
659 void radeon_gart_fini(struct radeon_device *rdev);
660 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
661 int pages);
662 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
663 int pages, struct page **pagelist,
664 dma_addr_t *dma_addr, uint32_t flags);
665
666
667 /*
668 * GPU MC structures, functions & helpers
669 */
670 struct radeon_mc {
671 resource_size_t aper_size;
672 resource_size_t aper_base;
673 resource_size_t agp_base;
674 /* for some chips with <= 32MB we need to lie
675 * about vram size near mc fb location */
676 u64 mc_vram_size;
677 u64 visible_vram_size;
678 u64 gtt_size;
679 u64 gtt_start;
680 u64 gtt_end;
681 u64 vram_start;
682 u64 vram_end;
683 unsigned vram_width;
684 u64 real_vram_size;
685 int vram_mtrr;
686 bool vram_is_ddr;
687 bool igp_sideport_enabled;
688 u64 gtt_base_align;
689 u64 mc_mask;
690 };
691
692 bool radeon_combios_sideport_present(struct radeon_device *rdev);
693 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
694
695 /*
696 * GPU scratch registers structures, functions & helpers
697 */
698 struct radeon_scratch {
699 unsigned num_reg;
700 uint32_t reg_base;
701 bool free[32];
702 uint32_t reg[32];
703 };
704
705 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
706 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
707
708 /*
709 * GPU doorbell structures, functions & helpers
710 */
711 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
712
713 struct radeon_doorbell {
714 /* doorbell mmio */
715 resource_size_t base;
716 resource_size_t size;
717 u32 __iomem *ptr;
718 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
719 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
720 };
721
722 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
723 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
724 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
725 phys_addr_t *aperture_base,
726 size_t *aperture_size,
727 size_t *start_offset);
728
729 /*
730 * IRQS.
731 */
732
733 struct radeon_flip_work {
734 struct work_struct flip_work;
735 struct work_struct unpin_work;
736 struct radeon_device *rdev;
737 int crtc_id;
738 uint64_t base;
739 struct drm_pending_vblank_event *event;
740 struct radeon_bo *old_rbo;
741 struct fence *fence;
742 };
743
744 struct r500_irq_stat_regs {
745 u32 disp_int;
746 u32 hdmi0_status;
747 };
748
749 struct r600_irq_stat_regs {
750 u32 disp_int;
751 u32 disp_int_cont;
752 u32 disp_int_cont2;
753 u32 d1grph_int;
754 u32 d2grph_int;
755 u32 hdmi0_status;
756 u32 hdmi1_status;
757 };
758
759 struct evergreen_irq_stat_regs {
760 u32 disp_int;
761 u32 disp_int_cont;
762 u32 disp_int_cont2;
763 u32 disp_int_cont3;
764 u32 disp_int_cont4;
765 u32 disp_int_cont5;
766 u32 d1grph_int;
767 u32 d2grph_int;
768 u32 d3grph_int;
769 u32 d4grph_int;
770 u32 d5grph_int;
771 u32 d6grph_int;
772 u32 afmt_status1;
773 u32 afmt_status2;
774 u32 afmt_status3;
775 u32 afmt_status4;
776 u32 afmt_status5;
777 u32 afmt_status6;
778 };
779
780 struct cik_irq_stat_regs {
781 u32 disp_int;
782 u32 disp_int_cont;
783 u32 disp_int_cont2;
784 u32 disp_int_cont3;
785 u32 disp_int_cont4;
786 u32 disp_int_cont5;
787 u32 disp_int_cont6;
788 u32 d1grph_int;
789 u32 d2grph_int;
790 u32 d3grph_int;
791 u32 d4grph_int;
792 u32 d5grph_int;
793 u32 d6grph_int;
794 };
795
796 union radeon_irq_stat_regs {
797 struct r500_irq_stat_regs r500;
798 struct r600_irq_stat_regs r600;
799 struct evergreen_irq_stat_regs evergreen;
800 struct cik_irq_stat_regs cik;
801 };
802
803 struct radeon_irq {
804 bool installed;
805 spinlock_t lock;
806 atomic_t ring_int[RADEON_NUM_RINGS];
807 bool crtc_vblank_int[RADEON_MAX_CRTCS];
808 atomic_t pflip[RADEON_MAX_CRTCS];
809 wait_queue_head_t vblank_queue;
810 bool hpd[RADEON_MAX_HPD_PINS];
811 bool afmt[RADEON_MAX_AFMT_BLOCKS];
812 union radeon_irq_stat_regs stat_regs;
813 bool dpm_thermal;
814 };
815
816 int radeon_irq_kms_init(struct radeon_device *rdev);
817 void radeon_irq_kms_fini(struct radeon_device *rdev);
818 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
819 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
820 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
821 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
822 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
823 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
824 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
825 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
826 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
827
828 /*
829 * CP & rings.
830 */
831
832 struct radeon_ib {
833 struct radeon_sa_bo *sa_bo;
834 uint32_t length_dw;
835 uint64_t gpu_addr;
836 uint32_t *ptr;
837 int ring;
838 struct radeon_fence *fence;
839 struct radeon_vm *vm;
840 bool is_const_ib;
841 struct radeon_sync sync;
842 };
843
844 struct radeon_ring {
845 struct radeon_bo *ring_obj;
846 volatile uint32_t *ring;
847 unsigned rptr_offs;
848 unsigned rptr_save_reg;
849 u64 next_rptr_gpu_addr;
850 volatile u32 *next_rptr_cpu_addr;
851 unsigned wptr;
852 unsigned wptr_old;
853 unsigned ring_size;
854 unsigned ring_free_dw;
855 int count_dw;
856 atomic_t last_rptr;
857 atomic64_t last_activity;
858 uint64_t gpu_addr;
859 uint32_t align_mask;
860 uint32_t ptr_mask;
861 bool ready;
862 u32 nop;
863 u32 idx;
864 u64 last_semaphore_signal_addr;
865 u64 last_semaphore_wait_addr;
866 /* for CIK queues */
867 u32 me;
868 u32 pipe;
869 u32 queue;
870 struct radeon_bo *mqd_obj;
871 u32 doorbell_index;
872 unsigned wptr_offs;
873 };
874
875 struct radeon_mec {
876 struct radeon_bo *hpd_eop_obj;
877 u64 hpd_eop_gpu_addr;
878 u32 num_pipe;
879 u32 num_mec;
880 u32 num_queue;
881 };
882
883 /*
884 * VM
885 */
886
887 /* maximum number of VMIDs */
888 #define RADEON_NUM_VM 16
889
890 /* number of entries in page table */
891 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
892
893 /* PTBs (Page Table Blocks) need to be aligned to 32K */
894 #define RADEON_VM_PTB_ALIGN_SIZE 32768
895 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
896 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
897
898 #define R600_PTE_VALID (1 << 0)
899 #define R600_PTE_SYSTEM (1 << 1)
900 #define R600_PTE_SNOOPED (1 << 2)
901 #define R600_PTE_READABLE (1 << 5)
902 #define R600_PTE_WRITEABLE (1 << 6)
903
904 /* PTE (Page Table Entry) fragment field for different page sizes */
905 #define R600_PTE_FRAG_4KB (0 << 7)
906 #define R600_PTE_FRAG_64KB (4 << 7)
907 #define R600_PTE_FRAG_256KB (6 << 7)
908
909 /* flags needed to be set so we can copy directly from the GART table */
910 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
911 R600_PTE_SYSTEM | R600_PTE_VALID )
912
913 struct radeon_vm_pt {
914 struct radeon_bo *bo;
915 uint64_t addr;
916 };
917
918 struct radeon_vm_id {
919 unsigned id;
920 uint64_t pd_gpu_addr;
921 /* last flushed PD/PT update */
922 struct radeon_fence *flushed_updates;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
925 };
926
927 struct radeon_vm {
928 struct mutex mutex;
929
930 struct rb_root va;
931
932 /* protecting invalidated and freed */
933 spinlock_t status_lock;
934
935 /* BOs moved, but not yet updated in the PT */
936 struct list_head invalidated;
937
938 /* BOs freed, but not yet updated in the PT */
939 struct list_head freed;
940
941 /* contains the page directory */
942 struct radeon_bo *page_directory;
943 unsigned max_pde_used;
944
945 /* array of page tables, one for each page directory entry */
946 struct radeon_vm_pt *page_tables;
947
948 struct radeon_bo_va *ib_bo_va;
949
950 /* for id and flush management per ring */
951 struct radeon_vm_id ids[RADEON_NUM_RINGS];
952 };
953
954 struct radeon_vm_manager {
955 struct radeon_fence *active[RADEON_NUM_VM];
956 uint32_t max_pfn;
957 /* number of VMIDs */
958 unsigned nvm;
959 /* vram base address for page table entry */
960 u64 vram_base_offset;
961 /* is vm enabled? */
962 bool enabled;
963 /* for hw to save the PD addr on suspend/resume */
964 uint32_t saved_table_addr[RADEON_NUM_VM];
965 };
966
967 /*
968 * file private structure
969 */
970 struct radeon_fpriv {
971 struct radeon_vm vm;
972 };
973
974 /*
975 * R6xx+ IH ring
976 */
977 struct r600_ih {
978 struct radeon_bo *ring_obj;
979 volatile uint32_t *ring;
980 unsigned rptr;
981 unsigned ring_size;
982 uint64_t gpu_addr;
983 uint32_t ptr_mask;
984 atomic_t lock;
985 bool enabled;
986 };
987
988 /*
989 * RLC stuff
990 */
991 #include "clearstate_defs.h"
992
993 struct radeon_rlc {
994 /* for power gating */
995 struct radeon_bo *save_restore_obj;
996 uint64_t save_restore_gpu_addr;
997 volatile uint32_t *sr_ptr;
998 const u32 *reg_list;
999 u32 reg_list_size;
1000 /* for clear state */
1001 struct radeon_bo *clear_state_obj;
1002 uint64_t clear_state_gpu_addr;
1003 volatile uint32_t *cs_ptr;
1004 const struct cs_section_def *cs_data;
1005 u32 clear_state_size;
1006 /* for cp tables */
1007 struct radeon_bo *cp_table_obj;
1008 uint64_t cp_table_gpu_addr;
1009 volatile uint32_t *cp_table_ptr;
1010 u32 cp_table_size;
1011 };
1012
1013 int radeon_ib_get(struct radeon_device *rdev, int ring,
1014 struct radeon_ib *ib, struct radeon_vm *vm,
1015 unsigned size);
1016 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1017 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1018 struct radeon_ib *const_ib, bool hdp_flush);
1019 int radeon_ib_pool_init(struct radeon_device *rdev);
1020 void radeon_ib_pool_fini(struct radeon_device *rdev);
1021 int radeon_ib_ring_tests(struct radeon_device *rdev);
1022 /* Ring access between begin & end cannot sleep */
1023 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1024 struct radeon_ring *ring);
1025 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1026 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1027 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1028 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1029 bool hdp_flush);
1030 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1031 bool hdp_flush);
1032 void radeon_ring_undo(struct radeon_ring *ring);
1033 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1034 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1035 void radeon_ring_lockup_update(struct radeon_device *rdev,
1036 struct radeon_ring *ring);
1037 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1038 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1039 uint32_t **data);
1040 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1041 unsigned size, uint32_t *data);
1042 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1043 unsigned rptr_offs, u32 nop);
1044 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1045
1046
1047 /* r600 async dma */
1048 void r600_dma_stop(struct radeon_device *rdev);
1049 int r600_dma_resume(struct radeon_device *rdev);
1050 void r600_dma_fini(struct radeon_device *rdev);
1051
1052 void cayman_dma_stop(struct radeon_device *rdev);
1053 int cayman_dma_resume(struct radeon_device *rdev);
1054 void cayman_dma_fini(struct radeon_device *rdev);
1055
1056 /*
1057 * CS.
1058 */
1059 struct radeon_cs_chunk {
1060 uint32_t chunk_id;
1061 uint32_t length_dw;
1062 uint32_t *kdata;
1063 void __user *user_ptr;
1064 };
1065
1066 struct radeon_cs_parser {
1067 struct device *dev;
1068 struct radeon_device *rdev;
1069 struct drm_file *filp;
1070 /* chunks */
1071 unsigned nchunks;
1072 struct radeon_cs_chunk *chunks;
1073 uint64_t *chunks_array;
1074 /* IB */
1075 unsigned idx;
1076 /* relocations */
1077 unsigned nrelocs;
1078 struct radeon_bo_list *relocs;
1079 struct radeon_bo_list *vm_bos;
1080 struct list_head validated;
1081 unsigned dma_reloc_idx;
1082 /* indices of various chunks */
1083 int chunk_ib_idx;
1084 int chunk_relocs_idx;
1085 int chunk_flags_idx;
1086 int chunk_const_ib_idx;
1087 struct radeon_ib ib;
1088 struct radeon_ib const_ib;
1089 void *track;
1090 unsigned family;
1091 int parser_error;
1092 u32 cs_flags;
1093 u32 ring;
1094 s32 priority;
1095 struct ww_acquire_ctx ticket;
1096 };
1097
1098 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1099 {
1100 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1101
1102 if (ibc->kdata)
1103 return ibc->kdata[idx];
1104 return p->ib.ptr[idx];
1105 }
1106
1107
1108 struct radeon_cs_packet {
1109 unsigned idx;
1110 unsigned type;
1111 unsigned reg;
1112 unsigned opcode;
1113 int count;
1114 unsigned one_reg_wr;
1115 };
1116
1117 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1118 struct radeon_cs_packet *pkt,
1119 unsigned idx, unsigned reg);
1120 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1121 struct radeon_cs_packet *pkt);
1122
1123
1124 /*
1125 * AGP
1126 */
1127 int radeon_agp_init(struct radeon_device *rdev);
1128 void radeon_agp_resume(struct radeon_device *rdev);
1129 void radeon_agp_suspend(struct radeon_device *rdev);
1130 void radeon_agp_fini(struct radeon_device *rdev);
1131
1132
1133 /*
1134 * Writeback
1135 */
1136 struct radeon_wb {
1137 struct radeon_bo *wb_obj;
1138 volatile uint32_t *wb;
1139 uint64_t gpu_addr;
1140 bool enabled;
1141 bool use_event;
1142 };
1143
1144 #define RADEON_WB_SCRATCH_OFFSET 0
1145 #define RADEON_WB_RING0_NEXT_RPTR 256
1146 #define RADEON_WB_CP_RPTR_OFFSET 1024
1147 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1148 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1149 #define R600_WB_DMA_RPTR_OFFSET 1792
1150 #define R600_WB_IH_WPTR_OFFSET 2048
1151 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1152 #define R600_WB_EVENT_OFFSET 3072
1153 #define CIK_WB_CP1_WPTR_OFFSET 3328
1154 #define CIK_WB_CP2_WPTR_OFFSET 3584
1155 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1156 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1157
1158 /**
1159 * struct radeon_pm - power management datas
1160 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1161 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1162 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1163 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1164 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1165 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1166 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1167 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1168 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1169 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1170 * @needed_bandwidth: current bandwidth needs
1171 *
1172 * It keeps track of various data needed to take powermanagement decision.
1173 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1174 * Equation between gpu/memory clock and available bandwidth is hw dependent
1175 * (type of memory, bus size, efficiency, ...)
1176 */
1177
1178 enum radeon_pm_method {
1179 PM_METHOD_PROFILE,
1180 PM_METHOD_DYNPM,
1181 PM_METHOD_DPM,
1182 };
1183
1184 enum radeon_dynpm_state {
1185 DYNPM_STATE_DISABLED,
1186 DYNPM_STATE_MINIMUM,
1187 DYNPM_STATE_PAUSED,
1188 DYNPM_STATE_ACTIVE,
1189 DYNPM_STATE_SUSPENDED,
1190 };
1191 enum radeon_dynpm_action {
1192 DYNPM_ACTION_NONE,
1193 DYNPM_ACTION_MINIMUM,
1194 DYNPM_ACTION_DOWNCLOCK,
1195 DYNPM_ACTION_UPCLOCK,
1196 DYNPM_ACTION_DEFAULT
1197 };
1198
1199 enum radeon_voltage_type {
1200 VOLTAGE_NONE = 0,
1201 VOLTAGE_GPIO,
1202 VOLTAGE_VDDC,
1203 VOLTAGE_SW
1204 };
1205
1206 enum radeon_pm_state_type {
1207 /* not used for dpm */
1208 POWER_STATE_TYPE_DEFAULT,
1209 POWER_STATE_TYPE_POWERSAVE,
1210 /* user selectable states */
1211 POWER_STATE_TYPE_BATTERY,
1212 POWER_STATE_TYPE_BALANCED,
1213 POWER_STATE_TYPE_PERFORMANCE,
1214 /* internal states */
1215 POWER_STATE_TYPE_INTERNAL_UVD,
1216 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1217 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1218 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1219 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1220 POWER_STATE_TYPE_INTERNAL_BOOT,
1221 POWER_STATE_TYPE_INTERNAL_THERMAL,
1222 POWER_STATE_TYPE_INTERNAL_ACPI,
1223 POWER_STATE_TYPE_INTERNAL_ULV,
1224 POWER_STATE_TYPE_INTERNAL_3DPERF,
1225 };
1226
1227 enum radeon_pm_profile_type {
1228 PM_PROFILE_DEFAULT,
1229 PM_PROFILE_AUTO,
1230 PM_PROFILE_LOW,
1231 PM_PROFILE_MID,
1232 PM_PROFILE_HIGH,
1233 };
1234
1235 #define PM_PROFILE_DEFAULT_IDX 0
1236 #define PM_PROFILE_LOW_SH_IDX 1
1237 #define PM_PROFILE_MID_SH_IDX 2
1238 #define PM_PROFILE_HIGH_SH_IDX 3
1239 #define PM_PROFILE_LOW_MH_IDX 4
1240 #define PM_PROFILE_MID_MH_IDX 5
1241 #define PM_PROFILE_HIGH_MH_IDX 6
1242 #define PM_PROFILE_MAX 7
1243
1244 struct radeon_pm_profile {
1245 int dpms_off_ps_idx;
1246 int dpms_on_ps_idx;
1247 int dpms_off_cm_idx;
1248 int dpms_on_cm_idx;
1249 };
1250
1251 enum radeon_int_thermal_type {
1252 THERMAL_TYPE_NONE,
1253 THERMAL_TYPE_EXTERNAL,
1254 THERMAL_TYPE_EXTERNAL_GPIO,
1255 THERMAL_TYPE_RV6XX,
1256 THERMAL_TYPE_RV770,
1257 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1258 THERMAL_TYPE_EVERGREEN,
1259 THERMAL_TYPE_SUMO,
1260 THERMAL_TYPE_NI,
1261 THERMAL_TYPE_SI,
1262 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1263 THERMAL_TYPE_CI,
1264 THERMAL_TYPE_KV,
1265 };
1266
1267 struct radeon_voltage {
1268 enum radeon_voltage_type type;
1269 /* gpio voltage */
1270 struct radeon_gpio_rec gpio;
1271 u32 delay; /* delay in usec from voltage drop to sclk change */
1272 bool active_high; /* voltage drop is active when bit is high */
1273 /* VDDC voltage */
1274 u8 vddc_id; /* index into vddc voltage table */
1275 u8 vddci_id; /* index into vddci voltage table */
1276 bool vddci_enabled;
1277 /* r6xx+ sw */
1278 u16 voltage;
1279 /* evergreen+ vddci */
1280 u16 vddci;
1281 };
1282
1283 /* clock mode flags */
1284 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1285
1286 struct radeon_pm_clock_info {
1287 /* memory clock */
1288 u32 mclk;
1289 /* engine clock */
1290 u32 sclk;
1291 /* voltage info */
1292 struct radeon_voltage voltage;
1293 /* standardized clock flags */
1294 u32 flags;
1295 };
1296
1297 /* state flags */
1298 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1299
1300 struct radeon_power_state {
1301 enum radeon_pm_state_type type;
1302 struct radeon_pm_clock_info *clock_info;
1303 /* number of valid clock modes in this power state */
1304 int num_clock_modes;
1305 struct radeon_pm_clock_info *default_clock_mode;
1306 /* standardized state flags */
1307 u32 flags;
1308 u32 misc; /* vbios specific flags */
1309 u32 misc2; /* vbios specific flags */
1310 int pcie_lanes; /* pcie lanes */
1311 };
1312
1313 /*
1314 * Some modes are overclocked by very low value, accept them
1315 */
1316 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1317
1318 enum radeon_dpm_auto_throttle_src {
1319 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1320 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1321 };
1322
1323 enum radeon_dpm_event_src {
1324 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1325 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1326 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1327 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1328 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1329 };
1330
1331 #define RADEON_MAX_VCE_LEVELS 6
1332
1333 enum radeon_vce_level {
1334 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1335 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1336 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1337 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1338 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1339 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1340 };
1341
1342 struct radeon_ps {
1343 u32 caps; /* vbios flags */
1344 u32 class; /* vbios flags */
1345 u32 class2; /* vbios flags */
1346 /* UVD clocks */
1347 u32 vclk;
1348 u32 dclk;
1349 /* VCE clocks */
1350 u32 evclk;
1351 u32 ecclk;
1352 bool vce_active;
1353 enum radeon_vce_level vce_level;
1354 /* asic priv */
1355 void *ps_priv;
1356 };
1357
1358 struct radeon_dpm_thermal {
1359 /* thermal interrupt work */
1360 struct work_struct work;
1361 /* low temperature threshold */
1362 int min_temp;
1363 /* high temperature threshold */
1364 int max_temp;
1365 /* was interrupt low to high or high to low */
1366 bool high_to_low;
1367 };
1368
1369 enum radeon_clk_action
1370 {
1371 RADEON_SCLK_UP = 1,
1372 RADEON_SCLK_DOWN
1373 };
1374
1375 struct radeon_blacklist_clocks
1376 {
1377 u32 sclk;
1378 u32 mclk;
1379 enum radeon_clk_action action;
1380 };
1381
1382 struct radeon_clock_and_voltage_limits {
1383 u32 sclk;
1384 u32 mclk;
1385 u16 vddc;
1386 u16 vddci;
1387 };
1388
1389 struct radeon_clock_array {
1390 u32 count;
1391 u32 *values;
1392 };
1393
1394 struct radeon_clock_voltage_dependency_entry {
1395 u32 clk;
1396 u16 v;
1397 };
1398
1399 struct radeon_clock_voltage_dependency_table {
1400 u32 count;
1401 struct radeon_clock_voltage_dependency_entry *entries;
1402 };
1403
1404 union radeon_cac_leakage_entry {
1405 struct {
1406 u16 vddc;
1407 u32 leakage;
1408 };
1409 struct {
1410 u16 vddc1;
1411 u16 vddc2;
1412 u16 vddc3;
1413 };
1414 };
1415
1416 struct radeon_cac_leakage_table {
1417 u32 count;
1418 union radeon_cac_leakage_entry *entries;
1419 };
1420
1421 struct radeon_phase_shedding_limits_entry {
1422 u16 voltage;
1423 u32 sclk;
1424 u32 mclk;
1425 };
1426
1427 struct radeon_phase_shedding_limits_table {
1428 u32 count;
1429 struct radeon_phase_shedding_limits_entry *entries;
1430 };
1431
1432 struct radeon_uvd_clock_voltage_dependency_entry {
1433 u32 vclk;
1434 u32 dclk;
1435 u16 v;
1436 };
1437
1438 struct radeon_uvd_clock_voltage_dependency_table {
1439 u8 count;
1440 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1441 };
1442
1443 struct radeon_vce_clock_voltage_dependency_entry {
1444 u32 ecclk;
1445 u32 evclk;
1446 u16 v;
1447 };
1448
1449 struct radeon_vce_clock_voltage_dependency_table {
1450 u8 count;
1451 struct radeon_vce_clock_voltage_dependency_entry *entries;
1452 };
1453
1454 struct radeon_ppm_table {
1455 u8 ppm_design;
1456 u16 cpu_core_number;
1457 u32 platform_tdp;
1458 u32 small_ac_platform_tdp;
1459 u32 platform_tdc;
1460 u32 small_ac_platform_tdc;
1461 u32 apu_tdp;
1462 u32 dgpu_tdp;
1463 u32 dgpu_ulv_power;
1464 u32 tj_max;
1465 };
1466
1467 struct radeon_cac_tdp_table {
1468 u16 tdp;
1469 u16 configurable_tdp;
1470 u16 tdc;
1471 u16 battery_power_limit;
1472 u16 small_power_limit;
1473 u16 low_cac_leakage;
1474 u16 high_cac_leakage;
1475 u16 maximum_power_delivery_limit;
1476 };
1477
1478 struct radeon_dpm_dynamic_state {
1479 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1480 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1481 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1482 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1483 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1484 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1485 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1486 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1487 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1488 struct radeon_clock_array valid_sclk_values;
1489 struct radeon_clock_array valid_mclk_values;
1490 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1491 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1492 u32 mclk_sclk_ratio;
1493 u32 sclk_mclk_delta;
1494 u16 vddc_vddci_delta;
1495 u16 min_vddc_for_pcie_gen2;
1496 struct radeon_cac_leakage_table cac_leakage_table;
1497 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1498 struct radeon_ppm_table *ppm_table;
1499 struct radeon_cac_tdp_table *cac_tdp_table;
1500 };
1501
1502 struct radeon_dpm_fan {
1503 u16 t_min;
1504 u16 t_med;
1505 u16 t_high;
1506 u16 pwm_min;
1507 u16 pwm_med;
1508 u16 pwm_high;
1509 u8 t_hyst;
1510 u32 cycle_delay;
1511 u16 t_max;
1512 u8 control_mode;
1513 u16 default_max_fan_pwm;
1514 u16 default_fan_output_sensitivity;
1515 u16 fan_output_sensitivity;
1516 bool ucode_fan_control;
1517 };
1518
1519 enum radeon_pcie_gen {
1520 RADEON_PCIE_GEN1 = 0,
1521 RADEON_PCIE_GEN2 = 1,
1522 RADEON_PCIE_GEN3 = 2,
1523 RADEON_PCIE_GEN_INVALID = 0xffff
1524 };
1525
1526 enum radeon_dpm_forced_level {
1527 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1528 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1529 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1530 };
1531
1532 struct radeon_vce_state {
1533 /* vce clocks */
1534 u32 evclk;
1535 u32 ecclk;
1536 /* gpu clocks */
1537 u32 sclk;
1538 u32 mclk;
1539 u8 clk_idx;
1540 u8 pstate;
1541 };
1542
1543 struct radeon_dpm {
1544 struct radeon_ps *ps;
1545 /* number of valid power states */
1546 int num_ps;
1547 /* current power state that is active */
1548 struct radeon_ps *current_ps;
1549 /* requested power state */
1550 struct radeon_ps *requested_ps;
1551 /* boot up power state */
1552 struct radeon_ps *boot_ps;
1553 /* default uvd power state */
1554 struct radeon_ps *uvd_ps;
1555 /* vce requirements */
1556 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1557 enum radeon_vce_level vce_level;
1558 enum radeon_pm_state_type state;
1559 enum radeon_pm_state_type user_state;
1560 u32 platform_caps;
1561 u32 voltage_response_time;
1562 u32 backbias_response_time;
1563 void *priv;
1564 u32 new_active_crtcs;
1565 int new_active_crtc_count;
1566 u32 current_active_crtcs;
1567 int current_active_crtc_count;
1568 struct radeon_dpm_dynamic_state dyn_state;
1569 struct radeon_dpm_fan fan;
1570 u32 tdp_limit;
1571 u32 near_tdp_limit;
1572 u32 near_tdp_limit_adjusted;
1573 u32 sq_ramping_threshold;
1574 u32 cac_leakage;
1575 u16 tdp_od_limit;
1576 u32 tdp_adjustment;
1577 u16 load_line_slope;
1578 bool power_control;
1579 bool ac_power;
1580 /* special states active */
1581 bool thermal_active;
1582 bool uvd_active;
1583 bool vce_active;
1584 /* thermal handling */
1585 struct radeon_dpm_thermal thermal;
1586 /* forced levels */
1587 enum radeon_dpm_forced_level forced_level;
1588 /* track UVD streams */
1589 unsigned sd;
1590 unsigned hd;
1591 };
1592
1593 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1594 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1595
1596 struct radeon_pm {
1597 struct mutex mutex;
1598 /* write locked while reprogramming mclk */
1599 struct rw_semaphore mclk_lock;
1600 u32 active_crtcs;
1601 int active_crtc_count;
1602 int req_vblank;
1603 bool vblank_sync;
1604 fixed20_12 max_bandwidth;
1605 fixed20_12 igp_sideport_mclk;
1606 fixed20_12 igp_system_mclk;
1607 fixed20_12 igp_ht_link_clk;
1608 fixed20_12 igp_ht_link_width;
1609 fixed20_12 k8_bandwidth;
1610 fixed20_12 sideport_bandwidth;
1611 fixed20_12 ht_bandwidth;
1612 fixed20_12 core_bandwidth;
1613 fixed20_12 sclk;
1614 fixed20_12 mclk;
1615 fixed20_12 needed_bandwidth;
1616 struct radeon_power_state *power_state;
1617 /* number of valid power states */
1618 int num_power_states;
1619 int current_power_state_index;
1620 int current_clock_mode_index;
1621 int requested_power_state_index;
1622 int requested_clock_mode_index;
1623 int default_power_state_index;
1624 u32 current_sclk;
1625 u32 current_mclk;
1626 u16 current_vddc;
1627 u16 current_vddci;
1628 u32 default_sclk;
1629 u32 default_mclk;
1630 u16 default_vddc;
1631 u16 default_vddci;
1632 struct radeon_i2c_chan *i2c_bus;
1633 /* selected pm method */
1634 enum radeon_pm_method pm_method;
1635 /* dynpm power management */
1636 struct delayed_work dynpm_idle_work;
1637 enum radeon_dynpm_state dynpm_state;
1638 enum radeon_dynpm_action dynpm_planned_action;
1639 unsigned long dynpm_action_timeout;
1640 bool dynpm_can_upclock;
1641 bool dynpm_can_downclock;
1642 /* profile-based power management */
1643 enum radeon_pm_profile_type profile;
1644 int profile_index;
1645 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1646 /* internal thermal controller on rv6xx+ */
1647 enum radeon_int_thermal_type int_thermal_type;
1648 struct device *int_hwmon_dev;
1649 /* fan control parameters */
1650 bool no_fan;
1651 u8 fan_pulses_per_revolution;
1652 u8 fan_min_rpm;
1653 u8 fan_max_rpm;
1654 /* dpm */
1655 bool dpm_enabled;
1656 struct radeon_dpm dpm;
1657 };
1658
1659 int radeon_pm_get_type_index(struct radeon_device *rdev,
1660 enum radeon_pm_state_type ps_type,
1661 int instance);
1662 /*
1663 * UVD
1664 */
1665 #define RADEON_MAX_UVD_HANDLES 10
1666 #define RADEON_UVD_STACK_SIZE (1024*1024)
1667 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1668
1669 struct radeon_uvd {
1670 struct radeon_bo *vcpu_bo;
1671 void *cpu_addr;
1672 uint64_t gpu_addr;
1673 void *saved_bo;
1674 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1675 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1676 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1677 struct delayed_work idle_work;
1678 };
1679
1680 int radeon_uvd_init(struct radeon_device *rdev);
1681 void radeon_uvd_fini(struct radeon_device *rdev);
1682 int radeon_uvd_suspend(struct radeon_device *rdev);
1683 int radeon_uvd_resume(struct radeon_device *rdev);
1684 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1685 uint32_t handle, struct radeon_fence **fence);
1686 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1687 uint32_t handle, struct radeon_fence **fence);
1688 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1689 uint32_t allowed_domains);
1690 void radeon_uvd_free_handles(struct radeon_device *rdev,
1691 struct drm_file *filp);
1692 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1693 void radeon_uvd_note_usage(struct radeon_device *rdev);
1694 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1695 unsigned vclk, unsigned dclk,
1696 unsigned vco_min, unsigned vco_max,
1697 unsigned fb_factor, unsigned fb_mask,
1698 unsigned pd_min, unsigned pd_max,
1699 unsigned pd_even,
1700 unsigned *optimal_fb_div,
1701 unsigned *optimal_vclk_div,
1702 unsigned *optimal_dclk_div);
1703 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1704 unsigned cg_upll_func_cntl);
1705
1706 /*
1707 * VCE
1708 */
1709 #define RADEON_MAX_VCE_HANDLES 16
1710 #define RADEON_VCE_STACK_SIZE (1024*1024)
1711 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1712
1713 struct radeon_vce {
1714 struct radeon_bo *vcpu_bo;
1715 uint64_t gpu_addr;
1716 unsigned fw_version;
1717 unsigned fb_version;
1718 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1719 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1720 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1721 struct delayed_work idle_work;
1722 };
1723
1724 int radeon_vce_init(struct radeon_device *rdev);
1725 void radeon_vce_fini(struct radeon_device *rdev);
1726 int radeon_vce_suspend(struct radeon_device *rdev);
1727 int radeon_vce_resume(struct radeon_device *rdev);
1728 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1729 uint32_t handle, struct radeon_fence **fence);
1730 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1731 uint32_t handle, struct radeon_fence **fence);
1732 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1733 void radeon_vce_note_usage(struct radeon_device *rdev);
1734 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1735 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1736 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1737 struct radeon_ring *ring,
1738 struct radeon_semaphore *semaphore,
1739 bool emit_wait);
1740 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1741 void radeon_vce_fence_emit(struct radeon_device *rdev,
1742 struct radeon_fence *fence);
1743 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1744 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1745
1746 struct r600_audio_pin {
1747 int channels;
1748 int rate;
1749 int bits_per_sample;
1750 u8 status_bits;
1751 u8 category_code;
1752 u32 offset;
1753 bool connected;
1754 u32 id;
1755 };
1756
1757 struct r600_audio {
1758 bool enabled;
1759 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1760 int num_pins;
1761 };
1762
1763 /*
1764 * Benchmarking
1765 */
1766 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1767
1768
1769 /*
1770 * Testing
1771 */
1772 void radeon_test_moves(struct radeon_device *rdev);
1773 void radeon_test_ring_sync(struct radeon_device *rdev,
1774 struct radeon_ring *cpA,
1775 struct radeon_ring *cpB);
1776 void radeon_test_syncing(struct radeon_device *rdev);
1777
1778 /*
1779 * MMU Notifier
1780 */
1781 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1782 void radeon_mn_unregister(struct radeon_bo *bo);
1783
1784 /*
1785 * Debugfs
1786 */
1787 struct radeon_debugfs {
1788 struct drm_info_list *files;
1789 unsigned num_files;
1790 };
1791
1792 int radeon_debugfs_add_files(struct radeon_device *rdev,
1793 struct drm_info_list *files,
1794 unsigned nfiles);
1795 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1796
1797 /*
1798 * ASIC ring specific functions.
1799 */
1800 struct radeon_asic_ring {
1801 /* ring read/write ptr handling */
1802 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1803 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1804 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1805
1806 /* validating and patching of IBs */
1807 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1808 int (*cs_parse)(struct radeon_cs_parser *p);
1809
1810 /* command emmit functions */
1811 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1812 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1813 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1814 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1815 struct radeon_semaphore *semaphore, bool emit_wait);
1816 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1817 unsigned vm_id, uint64_t pd_addr);
1818
1819 /* testing functions */
1820 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1821 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1822 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1823
1824 /* deprecated */
1825 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1826 };
1827
1828 /*
1829 * ASIC specific functions.
1830 */
1831 struct radeon_asic {
1832 int (*init)(struct radeon_device *rdev);
1833 void (*fini)(struct radeon_device *rdev);
1834 int (*resume)(struct radeon_device *rdev);
1835 int (*suspend)(struct radeon_device *rdev);
1836 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1837 int (*asic_reset)(struct radeon_device *rdev);
1838 /* Flush the HDP cache via MMIO */
1839 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1840 /* check if 3D engine is idle */
1841 bool (*gui_idle)(struct radeon_device *rdev);
1842 /* wait for mc_idle */
1843 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1844 /* get the reference clock */
1845 u32 (*get_xclk)(struct radeon_device *rdev);
1846 /* get the gpu clock counter */
1847 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1848 /* gart */
1849 struct {
1850 void (*tlb_flush)(struct radeon_device *rdev);
1851 void (*set_page)(struct radeon_device *rdev, unsigned i,
1852 uint64_t addr, uint32_t flags);
1853 } gart;
1854 struct {
1855 int (*init)(struct radeon_device *rdev);
1856 void (*fini)(struct radeon_device *rdev);
1857 void (*copy_pages)(struct radeon_device *rdev,
1858 struct radeon_ib *ib,
1859 uint64_t pe, uint64_t src,
1860 unsigned count);
1861 void (*write_pages)(struct radeon_device *rdev,
1862 struct radeon_ib *ib,
1863 uint64_t pe,
1864 uint64_t addr, unsigned count,
1865 uint32_t incr, uint32_t flags);
1866 void (*set_pages)(struct radeon_device *rdev,
1867 struct radeon_ib *ib,
1868 uint64_t pe,
1869 uint64_t addr, unsigned count,
1870 uint32_t incr, uint32_t flags);
1871 void (*pad_ib)(struct radeon_ib *ib);
1872 } vm;
1873 /* ring specific callbacks */
1874 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1875 /* irqs */
1876 struct {
1877 int (*set)(struct radeon_device *rdev);
1878 int (*process)(struct radeon_device *rdev);
1879 } irq;
1880 /* displays */
1881 struct {
1882 /* display watermarks */
1883 void (*bandwidth_update)(struct radeon_device *rdev);
1884 /* get frame count */
1885 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1886 /* wait for vblank */
1887 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1888 /* set backlight level */
1889 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1890 /* get backlight level */
1891 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1892 /* audio callbacks */
1893 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1894 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1895 } display;
1896 /* copy functions for bo handling */
1897 struct {
1898 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1899 uint64_t src_offset,
1900 uint64_t dst_offset,
1901 unsigned num_gpu_pages,
1902 struct reservation_object *resv);
1903 u32 blit_ring_index;
1904 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1905 uint64_t src_offset,
1906 uint64_t dst_offset,
1907 unsigned num_gpu_pages,
1908 struct reservation_object *resv);
1909 u32 dma_ring_index;
1910 /* method used for bo copy */
1911 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1912 uint64_t src_offset,
1913 uint64_t dst_offset,
1914 unsigned num_gpu_pages,
1915 struct reservation_object *resv);
1916 /* ring used for bo copies */
1917 u32 copy_ring_index;
1918 } copy;
1919 /* surfaces */
1920 struct {
1921 int (*set_reg)(struct radeon_device *rdev, int reg,
1922 uint32_t tiling_flags, uint32_t pitch,
1923 uint32_t offset, uint32_t obj_size);
1924 void (*clear_reg)(struct radeon_device *rdev, int reg);
1925 } surface;
1926 /* hotplug detect */
1927 struct {
1928 void (*init)(struct radeon_device *rdev);
1929 void (*fini)(struct radeon_device *rdev);
1930 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1931 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1932 } hpd;
1933 /* static power management */
1934 struct {
1935 void (*misc)(struct radeon_device *rdev);
1936 void (*prepare)(struct radeon_device *rdev);
1937 void (*finish)(struct radeon_device *rdev);
1938 void (*init_profile)(struct radeon_device *rdev);
1939 void (*get_dynpm_state)(struct radeon_device *rdev);
1940 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1941 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1942 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1943 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1944 int (*get_pcie_lanes)(struct radeon_device *rdev);
1945 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1946 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1947 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1948 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1949 int (*get_temperature)(struct radeon_device *rdev);
1950 } pm;
1951 /* dynamic power management */
1952 struct {
1953 int (*init)(struct radeon_device *rdev);
1954 void (*setup_asic)(struct radeon_device *rdev);
1955 int (*enable)(struct radeon_device *rdev);
1956 int (*late_enable)(struct radeon_device *rdev);
1957 void (*disable)(struct radeon_device *rdev);
1958 int (*pre_set_power_state)(struct radeon_device *rdev);
1959 int (*set_power_state)(struct radeon_device *rdev);
1960 void (*post_set_power_state)(struct radeon_device *rdev);
1961 void (*display_configuration_changed)(struct radeon_device *rdev);
1962 void (*fini)(struct radeon_device *rdev);
1963 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1964 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1965 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1966 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1967 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1968 bool (*vblank_too_short)(struct radeon_device *rdev);
1969 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1970 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1971 } dpm;
1972 /* pageflipping */
1973 struct {
1974 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1975 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1976 } pflip;
1977 };
1978
1979 /*
1980 * Asic structures
1981 */
1982 struct r100_asic {
1983 const unsigned *reg_safe_bm;
1984 unsigned reg_safe_bm_size;
1985 u32 hdp_cntl;
1986 };
1987
1988 struct r300_asic {
1989 const unsigned *reg_safe_bm;
1990 unsigned reg_safe_bm_size;
1991 u32 resync_scratch;
1992 u32 hdp_cntl;
1993 };
1994
1995 struct r600_asic {
1996 unsigned max_pipes;
1997 unsigned max_tile_pipes;
1998 unsigned max_simds;
1999 unsigned max_backends;
2000 unsigned max_gprs;
2001 unsigned max_threads;
2002 unsigned max_stack_entries;
2003 unsigned max_hw_contexts;
2004 unsigned max_gs_threads;
2005 unsigned sx_max_export_size;
2006 unsigned sx_max_export_pos_size;
2007 unsigned sx_max_export_smx_size;
2008 unsigned sq_num_cf_insts;
2009 unsigned tiling_nbanks;
2010 unsigned tiling_npipes;
2011 unsigned tiling_group_size;
2012 unsigned tile_config;
2013 unsigned backend_map;
2014 unsigned active_simds;
2015 };
2016
2017 struct rv770_asic {
2018 unsigned max_pipes;
2019 unsigned max_tile_pipes;
2020 unsigned max_simds;
2021 unsigned max_backends;
2022 unsigned max_gprs;
2023 unsigned max_threads;
2024 unsigned max_stack_entries;
2025 unsigned max_hw_contexts;
2026 unsigned max_gs_threads;
2027 unsigned sx_max_export_size;
2028 unsigned sx_max_export_pos_size;
2029 unsigned sx_max_export_smx_size;
2030 unsigned sq_num_cf_insts;
2031 unsigned sx_num_of_sets;
2032 unsigned sc_prim_fifo_size;
2033 unsigned sc_hiz_tile_fifo_size;
2034 unsigned sc_earlyz_tile_fifo_fize;
2035 unsigned tiling_nbanks;
2036 unsigned tiling_npipes;
2037 unsigned tiling_group_size;
2038 unsigned tile_config;
2039 unsigned backend_map;
2040 unsigned active_simds;
2041 };
2042
2043 struct evergreen_asic {
2044 unsigned num_ses;
2045 unsigned max_pipes;
2046 unsigned max_tile_pipes;
2047 unsigned max_simds;
2048 unsigned max_backends;
2049 unsigned max_gprs;
2050 unsigned max_threads;
2051 unsigned max_stack_entries;
2052 unsigned max_hw_contexts;
2053 unsigned max_gs_threads;
2054 unsigned sx_max_export_size;
2055 unsigned sx_max_export_pos_size;
2056 unsigned sx_max_export_smx_size;
2057 unsigned sq_num_cf_insts;
2058 unsigned sx_num_of_sets;
2059 unsigned sc_prim_fifo_size;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_size;
2062 unsigned tiling_nbanks;
2063 unsigned tiling_npipes;
2064 unsigned tiling_group_size;
2065 unsigned tile_config;
2066 unsigned backend_map;
2067 unsigned active_simds;
2068 };
2069
2070 struct cayman_asic {
2071 unsigned max_shader_engines;
2072 unsigned max_pipes_per_simd;
2073 unsigned max_tile_pipes;
2074 unsigned max_simds_per_se;
2075 unsigned max_backends_per_se;
2076 unsigned max_texture_channel_caches;
2077 unsigned max_gprs;
2078 unsigned max_threads;
2079 unsigned max_gs_threads;
2080 unsigned max_stack_entries;
2081 unsigned sx_num_of_sets;
2082 unsigned sx_max_export_size;
2083 unsigned sx_max_export_pos_size;
2084 unsigned sx_max_export_smx_size;
2085 unsigned max_hw_contexts;
2086 unsigned sq_num_cf_insts;
2087 unsigned sc_prim_fifo_size;
2088 unsigned sc_hiz_tile_fifo_size;
2089 unsigned sc_earlyz_tile_fifo_size;
2090
2091 unsigned num_shader_engines;
2092 unsigned num_shader_pipes_per_simd;
2093 unsigned num_tile_pipes;
2094 unsigned num_simds_per_se;
2095 unsigned num_backends_per_se;
2096 unsigned backend_disable_mask_per_asic;
2097 unsigned backend_map;
2098 unsigned num_texture_channel_caches;
2099 unsigned mem_max_burst_length_bytes;
2100 unsigned mem_row_size_in_kb;
2101 unsigned shader_engine_tile_size;
2102 unsigned num_gpus;
2103 unsigned multi_gpu_tile_size;
2104
2105 unsigned tile_config;
2106 unsigned active_simds;
2107 };
2108
2109 struct si_asic {
2110 unsigned max_shader_engines;
2111 unsigned max_tile_pipes;
2112 unsigned max_cu_per_sh;
2113 unsigned max_sh_per_se;
2114 unsigned max_backends_per_se;
2115 unsigned max_texture_channel_caches;
2116 unsigned max_gprs;
2117 unsigned max_gs_threads;
2118 unsigned max_hw_contexts;
2119 unsigned sc_prim_fifo_size_frontend;
2120 unsigned sc_prim_fifo_size_backend;
2121 unsigned sc_hiz_tile_fifo_size;
2122 unsigned sc_earlyz_tile_fifo_size;
2123
2124 unsigned num_tile_pipes;
2125 unsigned backend_enable_mask;
2126 unsigned backend_disable_mask_per_asic;
2127 unsigned backend_map;
2128 unsigned num_texture_channel_caches;
2129 unsigned mem_max_burst_length_bytes;
2130 unsigned mem_row_size_in_kb;
2131 unsigned shader_engine_tile_size;
2132 unsigned num_gpus;
2133 unsigned multi_gpu_tile_size;
2134
2135 unsigned tile_config;
2136 uint32_t tile_mode_array[32];
2137 uint32_t active_cus;
2138 };
2139
2140 struct cik_asic {
2141 unsigned max_shader_engines;
2142 unsigned max_tile_pipes;
2143 unsigned max_cu_per_sh;
2144 unsigned max_sh_per_se;
2145 unsigned max_backends_per_se;
2146 unsigned max_texture_channel_caches;
2147 unsigned max_gprs;
2148 unsigned max_gs_threads;
2149 unsigned max_hw_contexts;
2150 unsigned sc_prim_fifo_size_frontend;
2151 unsigned sc_prim_fifo_size_backend;
2152 unsigned sc_hiz_tile_fifo_size;
2153 unsigned sc_earlyz_tile_fifo_size;
2154
2155 unsigned num_tile_pipes;
2156 unsigned backend_enable_mask;
2157 unsigned backend_disable_mask_per_asic;
2158 unsigned backend_map;
2159 unsigned num_texture_channel_caches;
2160 unsigned mem_max_burst_length_bytes;
2161 unsigned mem_row_size_in_kb;
2162 unsigned shader_engine_tile_size;
2163 unsigned num_gpus;
2164 unsigned multi_gpu_tile_size;
2165
2166 unsigned tile_config;
2167 uint32_t tile_mode_array[32];
2168 uint32_t macrotile_mode_array[16];
2169 uint32_t active_cus;
2170 };
2171
2172 union radeon_asic_config {
2173 struct r300_asic r300;
2174 struct r100_asic r100;
2175 struct r600_asic r600;
2176 struct rv770_asic rv770;
2177 struct evergreen_asic evergreen;
2178 struct cayman_asic cayman;
2179 struct si_asic si;
2180 struct cik_asic cik;
2181 };
2182
2183 /*
2184 * asic initizalization from radeon_asic.c
2185 */
2186 void radeon_agp_disable(struct radeon_device *rdev);
2187 int radeon_asic_init(struct radeon_device *rdev);
2188
2189
2190 /*
2191 * IOCTL.
2192 */
2193 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *filp);
2195 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2196 struct drm_file *filp);
2197 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2198 struct drm_file *filp);
2199 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2200 struct drm_file *file_priv);
2201 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2202 struct drm_file *file_priv);
2203 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2204 struct drm_file *file_priv);
2205 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2206 struct drm_file *file_priv);
2207 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2208 struct drm_file *filp);
2209 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2210 struct drm_file *filp);
2211 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *filp);
2213 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2214 struct drm_file *filp);
2215 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2216 struct drm_file *filp);
2217 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *filp);
2219 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2220 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224
2225 /* VRAM scratch page for HDP bug, default vram page */
2226 struct r600_vram_scratch {
2227 struct radeon_bo *robj;
2228 volatile uint32_t *ptr;
2229 u64 gpu_addr;
2230 };
2231
2232 /*
2233 * ACPI
2234 */
2235 struct radeon_atif_notification_cfg {
2236 bool enabled;
2237 int command_code;
2238 };
2239
2240 struct radeon_atif_notifications {
2241 bool display_switch;
2242 bool expansion_mode_change;
2243 bool thermal_state;
2244 bool forced_power_state;
2245 bool system_power_state;
2246 bool display_conf_change;
2247 bool px_gfx_switch;
2248 bool brightness_change;
2249 bool dgpu_display_event;
2250 };
2251
2252 struct radeon_atif_functions {
2253 bool system_params;
2254 bool sbios_requests;
2255 bool select_active_disp;
2256 bool lid_state;
2257 bool get_tv_standard;
2258 bool set_tv_standard;
2259 bool get_panel_expansion_mode;
2260 bool set_panel_expansion_mode;
2261 bool temperature_change;
2262 bool graphics_device_types;
2263 };
2264
2265 struct radeon_atif {
2266 struct radeon_atif_notifications notifications;
2267 struct radeon_atif_functions functions;
2268 struct radeon_atif_notification_cfg notification_cfg;
2269 struct radeon_encoder *encoder_for_bl;
2270 };
2271
2272 struct radeon_atcs_functions {
2273 bool get_ext_state;
2274 bool pcie_perf_req;
2275 bool pcie_dev_rdy;
2276 bool pcie_bus_width;
2277 };
2278
2279 struct radeon_atcs {
2280 struct radeon_atcs_functions functions;
2281 };
2282
2283 /*
2284 * Core structure, functions and helpers.
2285 */
2286 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2287 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2288
2289 struct radeon_device {
2290 struct device *dev;
2291 struct drm_device *ddev;
2292 struct pci_dev *pdev;
2293 struct rw_semaphore exclusive_lock;
2294 /* ASIC */
2295 union radeon_asic_config config;
2296 enum radeon_family family;
2297 unsigned long flags;
2298 int usec_timeout;
2299 enum radeon_pll_errata pll_errata;
2300 int num_gb_pipes;
2301 int num_z_pipes;
2302 int disp_priority;
2303 /* BIOS */
2304 uint8_t *bios;
2305 bool is_atom_bios;
2306 uint16_t bios_header_start;
2307 struct radeon_bo *stollen_vga_memory;
2308 /* Register mmio */
2309 resource_size_t rmmio_base;
2310 resource_size_t rmmio_size;
2311 /* protects concurrent MM_INDEX/DATA based register access */
2312 spinlock_t mmio_idx_lock;
2313 /* protects concurrent SMC based register access */
2314 spinlock_t smc_idx_lock;
2315 /* protects concurrent PLL register access */
2316 spinlock_t pll_idx_lock;
2317 /* protects concurrent MC register access */
2318 spinlock_t mc_idx_lock;
2319 /* protects concurrent PCIE register access */
2320 spinlock_t pcie_idx_lock;
2321 /* protects concurrent PCIE_PORT register access */
2322 spinlock_t pciep_idx_lock;
2323 /* protects concurrent PIF register access */
2324 spinlock_t pif_idx_lock;
2325 /* protects concurrent CG register access */
2326 spinlock_t cg_idx_lock;
2327 /* protects concurrent UVD register access */
2328 spinlock_t uvd_idx_lock;
2329 /* protects concurrent RCU register access */
2330 spinlock_t rcu_idx_lock;
2331 /* protects concurrent DIDT register access */
2332 spinlock_t didt_idx_lock;
2333 /* protects concurrent ENDPOINT (audio) register access */
2334 spinlock_t end_idx_lock;
2335 void __iomem *rmmio;
2336 radeon_rreg_t mc_rreg;
2337 radeon_wreg_t mc_wreg;
2338 radeon_rreg_t pll_rreg;
2339 radeon_wreg_t pll_wreg;
2340 uint32_t pcie_reg_mask;
2341 radeon_rreg_t pciep_rreg;
2342 radeon_wreg_t pciep_wreg;
2343 /* io port */
2344 void __iomem *rio_mem;
2345 resource_size_t rio_mem_size;
2346 struct radeon_clock clock;
2347 struct radeon_mc mc;
2348 struct radeon_gart gart;
2349 struct radeon_mode_info mode_info;
2350 struct radeon_scratch scratch;
2351 struct radeon_doorbell doorbell;
2352 struct radeon_mman mman;
2353 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2354 wait_queue_head_t fence_queue;
2355 unsigned fence_context;
2356 struct mutex ring_lock;
2357 struct radeon_ring ring[RADEON_NUM_RINGS];
2358 bool ib_pool_ready;
2359 struct radeon_sa_manager ring_tmp_bo;
2360 struct radeon_irq irq;
2361 struct radeon_asic *asic;
2362 struct radeon_gem gem;
2363 struct radeon_pm pm;
2364 struct radeon_uvd uvd;
2365 struct radeon_vce vce;
2366 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2367 struct radeon_wb wb;
2368 struct radeon_dummy_page dummy_page;
2369 bool shutdown;
2370 bool suspend;
2371 bool need_dma32;
2372 bool accel_working;
2373 bool fastfb_working; /* IGP feature*/
2374 bool needs_reset, in_reset;
2375 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2376 const struct firmware *me_fw; /* all family ME firmware */
2377 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2378 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2379 const struct firmware *mc_fw; /* NI MC firmware */
2380 const struct firmware *ce_fw; /* SI CE firmware */
2381 const struct firmware *mec_fw; /* CIK MEC firmware */
2382 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2383 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2384 const struct firmware *smc_fw; /* SMC firmware */
2385 const struct firmware *uvd_fw; /* UVD firmware */
2386 const struct firmware *vce_fw; /* VCE firmware */
2387 bool new_fw;
2388 struct r600_vram_scratch vram_scratch;
2389 int msi_enabled; /* msi enabled */
2390 struct r600_ih ih; /* r6/700 interrupt ring */
2391 struct radeon_rlc rlc;
2392 struct radeon_mec mec;
2393 struct work_struct hotplug_work;
2394 struct work_struct audio_work;
2395 int num_crtc; /* number of crtcs */
2396 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2397 bool has_uvd;
2398 struct r600_audio audio; /* audio stuff */
2399 struct notifier_block acpi_nb;
2400 /* only one userspace can use Hyperz features or CMASK at a time */
2401 struct drm_file *hyperz_filp;
2402 struct drm_file *cmask_filp;
2403 /* i2c buses */
2404 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2405 /* debugfs */
2406 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2407 unsigned debugfs_count;
2408 /* virtual memory */
2409 struct radeon_vm_manager vm_manager;
2410 struct mutex gpu_clock_mutex;
2411 /* memory stats */
2412 atomic64_t vram_usage;
2413 atomic64_t gtt_usage;
2414 atomic64_t num_bytes_moved;
2415 /* ACPI interface */
2416 struct radeon_atif atif;
2417 struct radeon_atcs atcs;
2418 /* srbm instance registers */
2419 struct mutex srbm_mutex;
2420 /* GRBM index mutex. Protects concurrents access to GRBM index */
2421 struct mutex grbm_idx_mutex;
2422 /* clock, powergating flags */
2423 u32 cg_flags;
2424 u32 pg_flags;
2425
2426 struct dev_pm_domain vga_pm_domain;
2427 bool have_disp_power_ref;
2428 u32 px_quirk_flags;
2429
2430 /* tracking pinned memory */
2431 u64 vram_pin_size;
2432 u64 gart_pin_size;
2433
2434 /* amdkfd interface */
2435 struct kfd_dev *kfd;
2436 struct radeon_sa_manager kfd_bo;
2437
2438 struct mutex mn_lock;
2439 DECLARE_HASHTABLE(mn_hash, 7);
2440 };
2441
2442 bool radeon_is_px(struct drm_device *dev);
2443 int radeon_device_init(struct radeon_device *rdev,
2444 struct drm_device *ddev,
2445 struct pci_dev *pdev,
2446 uint32_t flags);
2447 void radeon_device_fini(struct radeon_device *rdev);
2448 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2449
2450 #define RADEON_MIN_MMIO_SIZE 0x10000
2451
2452 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2453 bool always_indirect)
2454 {
2455 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2456 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2457 return readl(((void __iomem *)rdev->rmmio) + reg);
2458 else {
2459 unsigned long flags;
2460 uint32_t ret;
2461
2462 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2463 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2464 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2465 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2466
2467 return ret;
2468 }
2469 }
2470
2471 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2472 bool always_indirect)
2473 {
2474 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2475 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2476 else {
2477 unsigned long flags;
2478
2479 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2480 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2481 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2482 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2483 }
2484 }
2485
2486 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2487 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2488
2489 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2490 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2491
2492 /*
2493 * Cast helper
2494 */
2495 extern const struct fence_ops radeon_fence_ops;
2496
2497 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2498 {
2499 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2500
2501 if (__f->base.ops == &radeon_fence_ops)
2502 return __f;
2503
2504 return NULL;
2505 }
2506
2507 /*
2508 * Registers read & write functions.
2509 */
2510 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2511 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2512 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2513 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2514 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2515 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2516 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2517 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2518 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2519 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2520 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2521 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2522 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2523 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2524 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2525 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2526 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2527 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2528 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2529 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2530 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2531 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2532 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2533 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2534 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2535 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2536 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2537 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2538 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2539 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2540 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2541 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2542 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2543 #define WREG32_P(reg, val, mask) \
2544 do { \
2545 uint32_t tmp_ = RREG32(reg); \
2546 tmp_ &= (mask); \
2547 tmp_ |= ((val) & ~(mask)); \
2548 WREG32(reg, tmp_); \
2549 } while (0)
2550 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2551 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2552 #define WREG32_PLL_P(reg, val, mask) \
2553 do { \
2554 uint32_t tmp_ = RREG32_PLL(reg); \
2555 tmp_ &= (mask); \
2556 tmp_ |= ((val) & ~(mask)); \
2557 WREG32_PLL(reg, tmp_); \
2558 } while (0)
2559 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2560 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2561 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2562
2563 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2564 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2565
2566 /*
2567 * Indirect registers accessor
2568 */
2569 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2570 {
2571 unsigned long flags;
2572 uint32_t r;
2573
2574 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2575 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2576 r = RREG32(RADEON_PCIE_DATA);
2577 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2578 return r;
2579 }
2580
2581 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2582 {
2583 unsigned long flags;
2584
2585 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2586 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2587 WREG32(RADEON_PCIE_DATA, (v));
2588 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2589 }
2590
2591 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2592 {
2593 unsigned long flags;
2594 u32 r;
2595
2596 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2597 WREG32(TN_SMC_IND_INDEX_0, (reg));
2598 r = RREG32(TN_SMC_IND_DATA_0);
2599 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2600 return r;
2601 }
2602
2603 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2604 {
2605 unsigned long flags;
2606
2607 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2608 WREG32(TN_SMC_IND_INDEX_0, (reg));
2609 WREG32(TN_SMC_IND_DATA_0, (v));
2610 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2611 }
2612
2613 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2614 {
2615 unsigned long flags;
2616 u32 r;
2617
2618 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2619 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2620 r = RREG32(R600_RCU_DATA);
2621 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2622 return r;
2623 }
2624
2625 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2626 {
2627 unsigned long flags;
2628
2629 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2630 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2631 WREG32(R600_RCU_DATA, (v));
2632 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2633 }
2634
2635 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2636 {
2637 unsigned long flags;
2638 u32 r;
2639
2640 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2641 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2642 r = RREG32(EVERGREEN_CG_IND_DATA);
2643 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2644 return r;
2645 }
2646
2647 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2648 {
2649 unsigned long flags;
2650
2651 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2652 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2653 WREG32(EVERGREEN_CG_IND_DATA, (v));
2654 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2655 }
2656
2657 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2658 {
2659 unsigned long flags;
2660 u32 r;
2661
2662 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2663 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2664 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2665 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2666 return r;
2667 }
2668
2669 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2670 {
2671 unsigned long flags;
2672
2673 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2674 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2675 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2676 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2677 }
2678
2679 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2680 {
2681 unsigned long flags;
2682 u32 r;
2683
2684 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2685 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2686 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2687 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2688 return r;
2689 }
2690
2691 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2692 {
2693 unsigned long flags;
2694
2695 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2696 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2697 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2698 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2699 }
2700
2701 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2702 {
2703 unsigned long flags;
2704 u32 r;
2705
2706 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2707 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2708 r = RREG32(R600_UVD_CTX_DATA);
2709 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2710 return r;
2711 }
2712
2713 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2714 {
2715 unsigned long flags;
2716
2717 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2718 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2719 WREG32(R600_UVD_CTX_DATA, (v));
2720 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2721 }
2722
2723
2724 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2725 {
2726 unsigned long flags;
2727 u32 r;
2728
2729 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2730 WREG32(CIK_DIDT_IND_INDEX, (reg));
2731 r = RREG32(CIK_DIDT_IND_DATA);
2732 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2733 return r;
2734 }
2735
2736 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2737 {
2738 unsigned long flags;
2739
2740 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2741 WREG32(CIK_DIDT_IND_INDEX, (reg));
2742 WREG32(CIK_DIDT_IND_DATA, (v));
2743 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2744 }
2745
2746 void r100_pll_errata_after_index(struct radeon_device *rdev);
2747
2748
2749 /*
2750 * ASICs helpers.
2751 */
2752 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2753 (rdev->pdev->device == 0x5969))
2754 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2755 (rdev->family == CHIP_RV200) || \
2756 (rdev->family == CHIP_RS100) || \
2757 (rdev->family == CHIP_RS200) || \
2758 (rdev->family == CHIP_RV250) || \
2759 (rdev->family == CHIP_RV280) || \
2760 (rdev->family == CHIP_RS300))
2761 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2762 (rdev->family == CHIP_RV350) || \
2763 (rdev->family == CHIP_R350) || \
2764 (rdev->family == CHIP_RV380) || \
2765 (rdev->family == CHIP_R420) || \
2766 (rdev->family == CHIP_R423) || \
2767 (rdev->family == CHIP_RV410) || \
2768 (rdev->family == CHIP_RS400) || \
2769 (rdev->family == CHIP_RS480))
2770 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2771 (rdev->ddev->pdev->device == 0x9443) || \
2772 (rdev->ddev->pdev->device == 0x944B) || \
2773 (rdev->ddev->pdev->device == 0x9506) || \
2774 (rdev->ddev->pdev->device == 0x9509) || \
2775 (rdev->ddev->pdev->device == 0x950F) || \
2776 (rdev->ddev->pdev->device == 0x689C) || \
2777 (rdev->ddev->pdev->device == 0x689D))
2778 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2779 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2780 (rdev->family == CHIP_RS690) || \
2781 (rdev->family == CHIP_RS740) || \
2782 (rdev->family >= CHIP_R600))
2783 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2784 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2785 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2786 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2787 (rdev->flags & RADEON_IS_IGP))
2788 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2789 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2790 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2791 (rdev->flags & RADEON_IS_IGP))
2792 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2793 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2794 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2795 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2796 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2797 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2798 (rdev->family == CHIP_MULLINS))
2799
2800 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2801 (rdev->ddev->pdev->device == 0x6850) || \
2802 (rdev->ddev->pdev->device == 0x6858) || \
2803 (rdev->ddev->pdev->device == 0x6859) || \
2804 (rdev->ddev->pdev->device == 0x6840) || \
2805 (rdev->ddev->pdev->device == 0x6841) || \
2806 (rdev->ddev->pdev->device == 0x6842) || \
2807 (rdev->ddev->pdev->device == 0x6843))
2808
2809 /*
2810 * BIOS helpers.
2811 */
2812 #define RBIOS8(i) (rdev->bios[i])
2813 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2814 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2815
2816 int radeon_combios_init(struct radeon_device *rdev);
2817 void radeon_combios_fini(struct radeon_device *rdev);
2818 int radeon_atombios_init(struct radeon_device *rdev);
2819 void radeon_atombios_fini(struct radeon_device *rdev);
2820
2821
2822 /*
2823 * RING helpers.
2824 */
2825
2826 /**
2827 * radeon_ring_write - write a value to the ring
2828 *
2829 * @ring: radeon_ring structure holding ring information
2830 * @v: dword (dw) value to write
2831 *
2832 * Write a value to the requested ring buffer (all asics).
2833 */
2834 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2835 {
2836 if (ring->count_dw <= 0)
2837 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2838
2839 ring->ring[ring->wptr++] = v;
2840 ring->wptr &= ring->ptr_mask;
2841 ring->count_dw--;
2842 ring->ring_free_dw--;
2843 }
2844
2845 /*
2846 * ASICs macro.
2847 */
2848 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2849 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2850 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2851 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2852 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2853 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2854 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2855 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2856 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2857 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2858 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2859 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2860 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2861 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2862 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2863 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2864 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2865 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2866 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2867 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2868 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2869 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2870 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2871 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2872 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2873 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2874 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2875 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2876 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2877 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2878 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2879 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2880 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2881 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2882 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2883 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2884 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2885 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2886 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2887 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2888 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2889 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2890 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2891 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2892 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2893 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2894 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2895 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2896 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2897 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2898 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2899 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2900 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2901 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2902 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2903 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2904 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2905 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2906 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2907 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2908 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2909 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2910 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2911 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2912 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2913 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2914 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2915 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2916 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2917 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2918 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2919 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2920 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2921 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2922 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2923 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2924 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2925 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2926 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2927 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2928 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2929 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2930 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2931 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2932 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2933 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2934 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2935
2936 /* Common functions */
2937 /* AGP */
2938 extern int radeon_gpu_reset(struct radeon_device *rdev);
2939 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2940 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2941 extern void radeon_agp_disable(struct radeon_device *rdev);
2942 extern int radeon_modeset_init(struct radeon_device *rdev);
2943 extern void radeon_modeset_fini(struct radeon_device *rdev);
2944 extern bool radeon_card_posted(struct radeon_device *rdev);
2945 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2946 extern void radeon_update_display_priority(struct radeon_device *rdev);
2947 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2948 extern void radeon_scratch_init(struct radeon_device *rdev);
2949 extern void radeon_wb_fini(struct radeon_device *rdev);
2950 extern int radeon_wb_init(struct radeon_device *rdev);
2951 extern void radeon_wb_disable(struct radeon_device *rdev);
2952 extern void radeon_surface_init(struct radeon_device *rdev);
2953 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2954 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2955 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2956 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2957 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2958 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2959 uint32_t flags);
2960 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2961 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2962 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2963 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2964 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2965 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2966 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2967 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2968 const u32 *registers,
2969 const u32 array_size);
2970
2971 /*
2972 * vm
2973 */
2974 int radeon_vm_manager_init(struct radeon_device *rdev);
2975 void radeon_vm_manager_fini(struct radeon_device *rdev);
2976 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2977 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2978 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2979 struct radeon_vm *vm,
2980 struct list_head *head);
2981 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2982 struct radeon_vm *vm, int ring);
2983 void radeon_vm_flush(struct radeon_device *rdev,
2984 struct radeon_vm *vm,
2985 int ring, struct radeon_fence *fence);
2986 void radeon_vm_fence(struct radeon_device *rdev,
2987 struct radeon_vm *vm,
2988 struct radeon_fence *fence);
2989 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2990 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2991 struct radeon_vm *vm);
2992 int radeon_vm_clear_freed(struct radeon_device *rdev,
2993 struct radeon_vm *vm);
2994 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2995 struct radeon_vm *vm);
2996 int radeon_vm_bo_update(struct radeon_device *rdev,
2997 struct radeon_bo_va *bo_va,
2998 struct ttm_mem_reg *mem);
2999 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
3000 struct radeon_bo *bo);
3001 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
3002 struct radeon_bo *bo);
3003 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
3004 struct radeon_vm *vm,
3005 struct radeon_bo *bo);
3006 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3007 struct radeon_bo_va *bo_va,
3008 uint64_t offset,
3009 uint32_t flags);
3010 void radeon_vm_bo_rmv(struct radeon_device *rdev,
3011 struct radeon_bo_va *bo_va);
3012
3013 /* audio */
3014 void r600_audio_update_hdmi(struct work_struct *work);
3015 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3016 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
3017 void r600_audio_enable(struct radeon_device *rdev,
3018 struct r600_audio_pin *pin,
3019 u8 enable_mask);
3020 void dce6_audio_enable(struct radeon_device *rdev,
3021 struct r600_audio_pin *pin,
3022 u8 enable_mask);
3023
3024 /*
3025 * R600 vram scratch functions
3026 */
3027 int r600_vram_scratch_init(struct radeon_device *rdev);
3028 void r600_vram_scratch_fini(struct radeon_device *rdev);
3029
3030 /*
3031 * r600 cs checking helper
3032 */
3033 unsigned r600_mip_minify(unsigned size, unsigned level);
3034 bool r600_fmt_is_valid_color(u32 format);
3035 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3036 int r600_fmt_get_blocksize(u32 format);
3037 int r600_fmt_get_nblocksx(u32 format, u32 w);
3038 int r600_fmt_get_nblocksy(u32 format, u32 h);
3039
3040 /*
3041 * r600 functions used by radeon_encoder.c
3042 */
3043 struct radeon_hdmi_acr {
3044 u32 clock;
3045
3046 int n_32khz;
3047 int cts_32khz;
3048
3049 int n_44_1khz;
3050 int cts_44_1khz;
3051
3052 int n_48khz;
3053 int cts_48khz;
3054
3055 };
3056
3057 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3058
3059 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3060 u32 tiling_pipe_num,
3061 u32 max_rb_num,
3062 u32 total_max_rb_num,
3063 u32 enabled_rb_mask);
3064
3065 /*
3066 * evergreen functions used by radeon_encoder.c
3067 */
3068
3069 extern int ni_init_microcode(struct radeon_device *rdev);
3070 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3071
3072 /* radeon_acpi.c */
3073 #if defined(CONFIG_ACPI)
3074 extern int radeon_acpi_init(struct radeon_device *rdev);
3075 extern void radeon_acpi_fini(struct radeon_device *rdev);
3076 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3077 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3078 u8 perf_req, bool advertise);
3079 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3080 #else
3081 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3082 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3083 #endif
3084
3085 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3086 struct radeon_cs_packet *pkt,
3087 unsigned idx);
3088 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3089 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3090 struct radeon_cs_packet *pkt);
3091 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3092 struct radeon_bo_list **cs_reloc,
3093 int nomm);
3094 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3095 uint32_t *vline_start_end,
3096 uint32_t *vline_status);
3097
3098 #include "radeon_object.h"
3099
3100 #endif
Linux kernel - Deliverables
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