2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb
;
81 extern int radeon_modeset
;
82 extern int radeon_dynclks
;
83 extern int radeon_r4xx_atom
;
84 extern int radeon_agpmode
;
85 extern int radeon_vram_limit
;
86 extern int radeon_gart_size
;
87 extern int radeon_benchmarking
;
88 extern int radeon_testing
;
89 extern int radeon_connector_table
;
91 extern int radeon_new_pll
;
92 extern int radeon_dynpm
;
93 extern int radeon_audio
;
94 extern int radeon_disp_priority
;
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 /* RADEON_IB_POOL_SIZE must be a power of 2 */
102 #define RADEON_IB_POOL_SIZE 16
103 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
104 #define RADEONFB_CONN_LIMIT 4
105 #define RADEON_BIOS_NUM_SCRATCH 8
108 * Errata workarounds.
110 enum radeon_pll_errata
{
111 CHIP_ERRATA_R300_CG
= 0x00000001,
112 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
113 CHIP_ERRATA_PLL_DELAY
= 0x00000004
117 struct radeon_device
;
123 #define ATRM_BIOS_PAGE 4096
125 #if defined(CONFIG_VGA_SWITCHEROO)
126 bool radeon_atrm_supported(struct pci_dev
*pdev
);
127 int radeon_atrm_get_bios_chunk(uint8_t *bios
, int offset
, int len
);
129 static inline bool radeon_atrm_supported(struct pci_dev
*pdev
)
134 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios
, int offset
, int len
){
138 bool radeon_get_bios(struct radeon_device
*rdev
);
144 struct radeon_dummy_page
{
148 int radeon_dummy_page_init(struct radeon_device
*rdev
);
149 void radeon_dummy_page_fini(struct radeon_device
*rdev
);
155 struct radeon_clock
{
156 struct radeon_pll p1pll
;
157 struct radeon_pll p2pll
;
158 struct radeon_pll dcpll
;
159 struct radeon_pll spll
;
160 struct radeon_pll mpll
;
162 uint32_t default_mclk
;
163 uint32_t default_sclk
;
164 uint32_t default_dispclk
;
171 int radeon_pm_init(struct radeon_device
*rdev
);
172 void radeon_pm_fini(struct radeon_device
*rdev
);
173 void radeon_pm_compute_clocks(struct radeon_device
*rdev
);
174 void radeon_combios_get_power_modes(struct radeon_device
*rdev
);
175 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
);
180 struct radeon_fence_driver
{
181 uint32_t scratch_reg
;
184 unsigned long count_timeout
;
185 wait_queue_head_t queue
;
187 struct list_head created
;
188 struct list_head emited
;
189 struct list_head signaled
;
193 struct radeon_fence
{
194 struct radeon_device
*rdev
;
196 struct list_head list
;
197 /* protected by radeon_fence.lock */
199 unsigned long timeout
;
204 int radeon_fence_driver_init(struct radeon_device
*rdev
);
205 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
206 int radeon_fence_create(struct radeon_device
*rdev
, struct radeon_fence
**fence
);
207 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
208 void radeon_fence_process(struct radeon_device
*rdev
);
209 bool radeon_fence_signaled(struct radeon_fence
*fence
);
210 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
211 int radeon_fence_wait_next(struct radeon_device
*rdev
);
212 int radeon_fence_wait_last(struct radeon_device
*rdev
);
213 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
214 void radeon_fence_unref(struct radeon_fence
**fence
);
219 struct radeon_surface_reg
{
220 struct radeon_bo
*bo
;
223 #define RADEON_GEM_MAX_SURFACES 8
229 struct ttm_bo_global_ref bo_global_ref
;
230 struct ttm_global_reference mem_global_ref
;
231 struct ttm_bo_device bdev
;
232 bool mem_global_referenced
;
237 /* Protected by gem.mutex */
238 struct list_head list
;
239 /* Protected by tbo.reserved */
241 struct ttm_placement placement
;
242 struct ttm_buffer_object tbo
;
243 struct ttm_bo_kmap_obj kmap
;
249 /* Constant after initialization */
250 struct radeon_device
*rdev
;
251 struct drm_gem_object
*gobj
;
254 struct radeon_bo_list
{
255 struct list_head list
;
256 struct radeon_bo
*bo
;
268 struct list_head objects
;
271 int radeon_gem_init(struct radeon_device
*rdev
);
272 void radeon_gem_fini(struct radeon_device
*rdev
);
273 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
274 int alignment
, int initial_domain
,
275 bool discardable
, bool kernel
,
276 struct drm_gem_object
**obj
);
277 int radeon_gem_object_pin(struct drm_gem_object
*obj
, uint32_t pin_domain
,
279 void radeon_gem_object_unpin(struct drm_gem_object
*obj
);
283 * GART structures, functions & helpers
287 struct radeon_gart_table_ram
{
288 volatile uint32_t *ptr
;
291 struct radeon_gart_table_vram
{
292 struct radeon_bo
*robj
;
293 volatile uint32_t *ptr
;
296 union radeon_gart_table
{
297 struct radeon_gart_table_ram ram
;
298 struct radeon_gart_table_vram vram
;
301 #define RADEON_GPU_PAGE_SIZE 4096
302 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
305 dma_addr_t table_addr
;
306 unsigned num_gpu_pages
;
307 unsigned num_cpu_pages
;
309 union radeon_gart_table table
;
311 dma_addr_t
*pages_addr
;
315 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
316 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
317 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
318 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
319 int radeon_gart_init(struct radeon_device
*rdev
);
320 void radeon_gart_fini(struct radeon_device
*rdev
);
321 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
323 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
324 int pages
, struct page
**pagelist
);
328 * GPU MC structures, functions & helpers
331 resource_size_t aper_size
;
332 resource_size_t aper_base
;
333 resource_size_t agp_base
;
334 /* for some chips with <= 32MB we need to lie
335 * about vram size near mc fb location */
337 u64 visible_vram_size
;
347 bool igp_sideport_enabled
;
350 bool radeon_combios_sideport_present(struct radeon_device
*rdev
);
351 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
);
354 * GPU scratch registers structures, functions & helpers
356 struct radeon_scratch
{
362 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
363 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
372 /* FIXME: use a define max crtc rather than hardcode it */
373 bool crtc_vblank_int
[2];
374 wait_queue_head_t vblank_queue
;
375 /* FIXME: use defines for max hpd/dacs */
381 int radeon_irq_kms_init(struct radeon_device
*rdev
);
382 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
383 void radeon_irq_kms_sw_irq_get(struct radeon_device
*rdev
);
384 void radeon_irq_kms_sw_irq_put(struct radeon_device
*rdev
);
390 struct list_head list
;
393 struct radeon_fence
*fence
;
401 * mutex protects scheduled_ibs, ready, alloc_bm
403 struct radeon_ib_pool
{
405 struct radeon_bo
*robj
;
406 struct list_head bogus_ib
;
407 struct radeon_ib ibs
[RADEON_IB_POOL_SIZE
];
413 struct radeon_bo
*ring_obj
;
414 volatile uint32_t *ring
;
419 unsigned ring_free_dw
;
432 struct radeon_bo
*ring_obj
;
433 volatile uint32_t *ring
;
446 struct radeon_bo
*shader_obj
;
448 u32 vs_offset
, ps_offset
;
451 u32 vb_used
, vb_total
;
452 struct radeon_ib
*vb_ib
;
455 int radeon_ib_get(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
456 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
457 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
458 int radeon_ib_pool_init(struct radeon_device
*rdev
);
459 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
460 int radeon_ib_test(struct radeon_device
*rdev
);
461 extern void radeon_ib_bogus_add(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
462 /* Ring access between begin & end cannot sleep */
463 void radeon_ring_free_size(struct radeon_device
*rdev
);
464 int radeon_ring_lock(struct radeon_device
*rdev
, unsigned ndw
);
465 void radeon_ring_unlock_commit(struct radeon_device
*rdev
);
466 void radeon_ring_unlock_undo(struct radeon_device
*rdev
);
467 int radeon_ring_test(struct radeon_device
*rdev
);
468 int radeon_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
469 void radeon_ring_fini(struct radeon_device
*rdev
);
475 struct radeon_cs_reloc
{
476 struct drm_gem_object
*gobj
;
477 struct radeon_bo
*robj
;
478 struct radeon_bo_list lobj
;
483 struct radeon_cs_chunk
{
489 void __user
*user_ptr
;
490 int last_copied_page
;
494 struct radeon_cs_parser
{
496 struct radeon_device
*rdev
;
497 struct drm_file
*filp
;
500 struct radeon_cs_chunk
*chunks
;
501 uint64_t *chunks_array
;
506 struct radeon_cs_reloc
*relocs
;
507 struct radeon_cs_reloc
**relocs_ptr
;
508 struct list_head validated
;
509 /* indices of various chunks */
511 int chunk_relocs_idx
;
512 struct radeon_ib
*ib
;
518 extern int radeon_cs_update_pages(struct radeon_cs_parser
*p
, int pg_idx
);
519 extern int radeon_cs_finish_pages(struct radeon_cs_parser
*p
);
522 static inline u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
)
524 struct radeon_cs_chunk
*ibc
= &p
->chunks
[p
->chunk_ib_idx
];
525 u32 pg_idx
, pg_offset
;
529 pg_idx
= (idx
* 4) / PAGE_SIZE
;
530 pg_offset
= (idx
* 4) % PAGE_SIZE
;
532 if (ibc
->kpage_idx
[0] == pg_idx
)
533 return ibc
->kpage
[0][pg_offset
/4];
534 if (ibc
->kpage_idx
[1] == pg_idx
)
535 return ibc
->kpage
[1][pg_offset
/4];
537 new_page
= radeon_cs_update_pages(p
, pg_idx
);
539 p
->parser_error
= new_page
;
543 idx_value
= ibc
->kpage
[new_page
][pg_offset
/4];
547 struct radeon_cs_packet
{
556 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
557 struct radeon_cs_packet
*pkt
,
558 unsigned idx
, unsigned reg
);
559 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
560 struct radeon_cs_packet
*pkt
);
566 int radeon_agp_init(struct radeon_device
*rdev
);
567 void radeon_agp_resume(struct radeon_device
*rdev
);
568 void radeon_agp_fini(struct radeon_device
*rdev
);
575 struct radeon_bo
*wb_obj
;
576 volatile uint32_t *wb
;
581 * struct radeon_pm - power management datas
582 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
583 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
584 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
585 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
586 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
587 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
588 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
589 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
590 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
591 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
592 * @needed_bandwidth: current bandwidth needs
594 * It keeps track of various data needed to take powermanagement decision.
595 * Bandwith need is used to determine minimun clock of the GPU and memory.
596 * Equation between gpu/memory clock and available bandwidth is hw dependent
597 * (type of memory, bus size, efficiency, ...)
599 enum radeon_pm_state
{
605 enum radeon_pm_action
{
612 enum radeon_voltage_type
{
619 enum radeon_pm_state_type
{
620 POWER_STATE_TYPE_DEFAULT
,
621 POWER_STATE_TYPE_POWERSAVE
,
622 POWER_STATE_TYPE_BATTERY
,
623 POWER_STATE_TYPE_BALANCED
,
624 POWER_STATE_TYPE_PERFORMANCE
,
627 enum radeon_pm_clock_mode_type
{
628 POWER_MODE_TYPE_DEFAULT
,
631 POWER_MODE_TYPE_HIGH
,
634 struct radeon_voltage
{
635 enum radeon_voltage_type type
;
637 struct radeon_gpio_rec gpio
;
638 u32 delay
; /* delay in usec from voltage drop to sclk change */
639 bool active_high
; /* voltage drop is active when bit is high */
641 u8 vddc_id
; /* index into vddc voltage table */
642 u8 vddci_id
; /* index into vddci voltage table */
648 struct radeon_pm_non_clock_info
{
651 /* standardized non-clock flags */
655 struct radeon_pm_clock_info
{
661 struct radeon_voltage voltage
;
662 /* standardized clock flags - not sure we'll need these */
666 struct radeon_power_state
{
667 enum radeon_pm_state_type type
;
668 /* XXX: use a define for num clock modes */
669 struct radeon_pm_clock_info clock_info
[8];
670 /* number of valid clock modes in this power state */
672 struct radeon_pm_clock_info
*default_clock_mode
;
673 /* non clock info about this state */
674 struct radeon_pm_non_clock_info non_clock_info
;
675 bool voltage_drop_active
;
679 * Some modes are overclocked by very low value, accept them
681 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
685 struct delayed_work idle_work
;
686 enum radeon_pm_state state
;
687 enum radeon_pm_action planned_action
;
688 unsigned long action_timeout
;
693 fixed20_12 max_bandwidth
;
694 fixed20_12 igp_sideport_mclk
;
695 fixed20_12 igp_system_mclk
;
696 fixed20_12 igp_ht_link_clk
;
697 fixed20_12 igp_ht_link_width
;
698 fixed20_12 k8_bandwidth
;
699 fixed20_12 sideport_bandwidth
;
700 fixed20_12 ht_bandwidth
;
701 fixed20_12 core_bandwidth
;
704 fixed20_12 needed_bandwidth
;
705 /* XXX: use a define for num power modes */
706 struct radeon_power_state power_state
[8];
707 /* number of valid power states */
708 int num_power_states
;
709 struct radeon_power_state
*current_power_state
;
710 struct radeon_pm_clock_info
*current_clock_mode
;
711 struct radeon_power_state
*requested_power_state
;
712 struct radeon_pm_clock_info
*requested_clock_mode
;
713 struct radeon_power_state
*default_power_state
;
714 struct radeon_i2c_chan
*i2c_bus
;
721 void radeon_benchmark(struct radeon_device
*rdev
);
727 void radeon_test_moves(struct radeon_device
*rdev
);
733 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
734 struct drm_info_list
*files
,
736 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
740 * ASIC specific functions.
743 int (*init
)(struct radeon_device
*rdev
);
744 void (*fini
)(struct radeon_device
*rdev
);
745 int (*resume
)(struct radeon_device
*rdev
);
746 int (*suspend
)(struct radeon_device
*rdev
);
747 void (*vga_set_state
)(struct radeon_device
*rdev
, bool state
);
748 int (*gpu_reset
)(struct radeon_device
*rdev
);
749 void (*gart_tlb_flush
)(struct radeon_device
*rdev
);
750 int (*gart_set_page
)(struct radeon_device
*rdev
, int i
, uint64_t addr
);
751 int (*cp_init
)(struct radeon_device
*rdev
, unsigned ring_size
);
752 void (*cp_fini
)(struct radeon_device
*rdev
);
753 void (*cp_disable
)(struct radeon_device
*rdev
);
754 void (*cp_commit
)(struct radeon_device
*rdev
);
755 void (*ring_start
)(struct radeon_device
*rdev
);
756 int (*ring_test
)(struct radeon_device
*rdev
);
757 void (*ring_ib_execute
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
758 int (*irq_set
)(struct radeon_device
*rdev
);
759 int (*irq_process
)(struct radeon_device
*rdev
);
760 u32 (*get_vblank_counter
)(struct radeon_device
*rdev
, int crtc
);
761 void (*fence_ring_emit
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
762 int (*cs_parse
)(struct radeon_cs_parser
*p
);
763 int (*copy_blit
)(struct radeon_device
*rdev
,
767 struct radeon_fence
*fence
);
768 int (*copy_dma
)(struct radeon_device
*rdev
,
772 struct radeon_fence
*fence
);
773 int (*copy
)(struct radeon_device
*rdev
,
777 struct radeon_fence
*fence
);
778 uint32_t (*get_engine_clock
)(struct radeon_device
*rdev
);
779 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
780 uint32_t (*get_memory_clock
)(struct radeon_device
*rdev
);
781 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
782 int (*get_pcie_lanes
)(struct radeon_device
*rdev
);
783 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
784 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
785 int (*set_surface_reg
)(struct radeon_device
*rdev
, int reg
,
786 uint32_t tiling_flags
, uint32_t pitch
,
787 uint32_t offset
, uint32_t obj_size
);
788 void (*clear_surface_reg
)(struct radeon_device
*rdev
, int reg
);
789 void (*bandwidth_update
)(struct radeon_device
*rdev
);
790 void (*hpd_init
)(struct radeon_device
*rdev
);
791 void (*hpd_fini
)(struct radeon_device
*rdev
);
792 bool (*hpd_sense
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
793 void (*hpd_set_polarity
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
794 /* ioctl hw specific callback. Some hw might want to perform special
795 * operation on specific ioctl. For instance on wait idle some hw
796 * might want to perform and HDP flush through MMIO as it seems that
797 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
800 void (*ioctl_wait_idle
)(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
807 const unsigned *reg_safe_bm
;
808 unsigned reg_safe_bm_size
;
813 const unsigned *reg_safe_bm
;
814 unsigned reg_safe_bm_size
;
821 unsigned max_tile_pipes
;
823 unsigned max_backends
;
825 unsigned max_threads
;
826 unsigned max_stack_entries
;
827 unsigned max_hw_contexts
;
828 unsigned max_gs_threads
;
829 unsigned sx_max_export_size
;
830 unsigned sx_max_export_pos_size
;
831 unsigned sx_max_export_smx_size
;
832 unsigned sq_num_cf_insts
;
833 unsigned tiling_nbanks
;
834 unsigned tiling_npipes
;
835 unsigned tiling_group_size
;
840 unsigned max_tile_pipes
;
842 unsigned max_backends
;
844 unsigned max_threads
;
845 unsigned max_stack_entries
;
846 unsigned max_hw_contexts
;
847 unsigned max_gs_threads
;
848 unsigned sx_max_export_size
;
849 unsigned sx_max_export_pos_size
;
850 unsigned sx_max_export_smx_size
;
851 unsigned sq_num_cf_insts
;
852 unsigned sx_num_of_sets
;
853 unsigned sc_prim_fifo_size
;
854 unsigned sc_hiz_tile_fifo_size
;
855 unsigned sc_earlyz_tile_fifo_fize
;
856 unsigned tiling_nbanks
;
857 unsigned tiling_npipes
;
858 unsigned tiling_group_size
;
861 union radeon_asic_config
{
862 struct r300_asic r300
;
863 struct r100_asic r100
;
864 struct r600_asic r600
;
865 struct rv770_asic rv770
;
869 * asic initizalization from radeon_asic.c
871 void radeon_agp_disable(struct radeon_device
*rdev
);
872 int radeon_asic_init(struct radeon_device
*rdev
);
878 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
879 struct drm_file
*filp
);
880 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
881 struct drm_file
*filp
);
882 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
883 struct drm_file
*file_priv
);
884 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
885 struct drm_file
*file_priv
);
886 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
887 struct drm_file
*file_priv
);
888 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
889 struct drm_file
*file_priv
);
890 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
891 struct drm_file
*filp
);
892 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
893 struct drm_file
*filp
);
894 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
895 struct drm_file
*filp
);
896 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
897 struct drm_file
*filp
);
898 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
899 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
900 struct drm_file
*filp
);
901 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
902 struct drm_file
*filp
);
906 * Core structure, functions and helpers.
908 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
909 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
911 struct radeon_device
{
913 struct drm_device
*ddev
;
914 struct pci_dev
*pdev
;
916 union radeon_asic_config config
;
917 enum radeon_family family
;
920 enum radeon_pll_errata pll_errata
;
927 uint16_t bios_header_start
;
928 struct radeon_bo
*stollen_vga_memory
;
929 struct fb_info
*fbdev_info
;
930 struct radeon_bo
*fbdev_rbo
;
931 struct radeon_framebuffer
*fbdev_rfb
;
933 resource_size_t rmmio_base
;
934 resource_size_t rmmio_size
;
936 radeon_rreg_t mc_rreg
;
937 radeon_wreg_t mc_wreg
;
938 radeon_rreg_t pll_rreg
;
939 radeon_wreg_t pll_wreg
;
940 uint32_t pcie_reg_mask
;
941 radeon_rreg_t pciep_rreg
;
942 radeon_wreg_t pciep_wreg
;
943 struct radeon_clock clock
;
945 struct radeon_gart gart
;
946 struct radeon_mode_info mode_info
;
947 struct radeon_scratch scratch
;
948 struct radeon_mman mman
;
949 struct radeon_fence_driver fence_drv
;
951 struct radeon_ib_pool ib_pool
;
952 struct radeon_irq irq
;
953 struct radeon_asic
*asic
;
954 struct radeon_gem gem
;
956 uint32_t bios_scratch
[RADEON_BIOS_NUM_SCRATCH
];
957 struct mutex cs_mutex
;
959 struct radeon_dummy_page dummy_page
;
965 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
966 const struct firmware
*me_fw
; /* all family ME firmware */
967 const struct firmware
*pfp_fw
; /* r6/700 PFP firmware */
968 const struct firmware
*rlc_fw
; /* r6/700 RLC firmware */
969 struct r600_blit r600_blit
;
970 int msi_enabled
; /* msi enabled */
971 struct r600_ih ih
; /* r6/700 interrupt ring */
972 struct workqueue_struct
*wq
;
973 struct work_struct hotplug_work
;
974 int num_crtc
; /* number of crtcs */
975 struct mutex dc_hw_i2c_mutex
; /* display controller hw i2c mutex */
978 struct timer_list audio_timer
;
981 int audio_bits_per_sample
;
982 uint8_t audio_status_bits
;
983 uint8_t audio_category_code
;
988 int radeon_device_init(struct radeon_device
*rdev
,
989 struct drm_device
*ddev
,
990 struct pci_dev
*pdev
,
992 void radeon_device_fini(struct radeon_device
*rdev
);
993 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
996 int r600_blit_prepare_copy(struct radeon_device
*rdev
, int size_bytes
);
997 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
998 void r600_kms_blit_copy(struct radeon_device
*rdev
,
999 u64 src_gpu_addr
, u64 dst_gpu_addr
,
1002 static inline uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1004 if (reg
< rdev
->rmmio_size
)
1005 return readl(((void __iomem
*)rdev
->rmmio
) + reg
);
1007 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
1008 return readl(((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
1012 static inline void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1014 if (reg
< rdev
->rmmio_size
)
1015 writel(v
, ((void __iomem
*)rdev
->rmmio
) + reg
);
1017 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
1018 writel(v
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
1025 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1028 * Registers read & write functions.
1030 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1031 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1032 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1033 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1034 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1035 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1036 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1037 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1038 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1039 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1040 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1041 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1042 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1043 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1044 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1045 #define WREG32_P(reg, val, mask) \
1047 uint32_t tmp_ = RREG32(reg); \
1049 tmp_ |= ((val) & ~(mask)); \
1050 WREG32(reg, tmp_); \
1052 #define WREG32_PLL_P(reg, val, mask) \
1054 uint32_t tmp_ = RREG32_PLL(reg); \
1056 tmp_ |= ((val) & ~(mask)); \
1057 WREG32_PLL(reg, tmp_); \
1059 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1062 * Indirect registers accessor
1064 static inline uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1068 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1069 r
= RREG32(RADEON_PCIE_DATA
);
1073 static inline void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1075 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1076 WREG32(RADEON_PCIE_DATA
, (v
));
1079 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
1085 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1086 (rdev->pdev->device == 0x5969))
1087 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1088 (rdev->family == CHIP_RV200) || \
1089 (rdev->family == CHIP_RS100) || \
1090 (rdev->family == CHIP_RS200) || \
1091 (rdev->family == CHIP_RV250) || \
1092 (rdev->family == CHIP_RV280) || \
1093 (rdev->family == CHIP_RS300))
1094 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1095 (rdev->family == CHIP_RV350) || \
1096 (rdev->family == CHIP_R350) || \
1097 (rdev->family == CHIP_RV380) || \
1098 (rdev->family == CHIP_R420) || \
1099 (rdev->family == CHIP_R423) || \
1100 (rdev->family == CHIP_RV410) || \
1101 (rdev->family == CHIP_RS400) || \
1102 (rdev->family == CHIP_RS480))
1103 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1104 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1105 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1106 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1111 #define RBIOS8(i) (rdev->bios[i])
1112 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1113 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1115 int radeon_combios_init(struct radeon_device
*rdev
);
1116 void radeon_combios_fini(struct radeon_device
*rdev
);
1117 int radeon_atombios_init(struct radeon_device
*rdev
);
1118 void radeon_atombios_fini(struct radeon_device
*rdev
);
1124 static inline void radeon_ring_write(struct radeon_device
*rdev
, uint32_t v
)
1127 if (rdev
->cp
.count_dw
<= 0) {
1128 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1131 rdev
->cp
.ring
[rdev
->cp
.wptr
++] = v
;
1132 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
1133 rdev
->cp
.count_dw
--;
1134 rdev
->cp
.ring_free_dw
--;
1141 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1142 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1143 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1144 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1145 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1146 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1147 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1148 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1149 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1150 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1151 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1152 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1153 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1154 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1155 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1156 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1157 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1158 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1159 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1160 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1161 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1162 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1163 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1164 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1165 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1166 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1167 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1168 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1169 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1170 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1171 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1172 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1173 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1174 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1176 /* Common functions */
1178 extern void radeon_agp_disable(struct radeon_device
*rdev
);
1179 extern int radeon_gart_table_vram_pin(struct radeon_device
*rdev
);
1180 extern void radeon_gart_restore(struct radeon_device
*rdev
);
1181 extern int radeon_modeset_init(struct radeon_device
*rdev
);
1182 extern void radeon_modeset_fini(struct radeon_device
*rdev
);
1183 extern bool radeon_card_posted(struct radeon_device
*rdev
);
1184 extern void radeon_update_bandwidth_info(struct radeon_device
*rdev
);
1185 extern void radeon_update_display_priority(struct radeon_device
*rdev
);
1186 extern bool radeon_boot_test_post_card(struct radeon_device
*rdev
);
1187 extern int radeon_clocks_init(struct radeon_device
*rdev
);
1188 extern void radeon_clocks_fini(struct radeon_device
*rdev
);
1189 extern void radeon_scratch_init(struct radeon_device
*rdev
);
1190 extern void radeon_surface_init(struct radeon_device
*rdev
);
1191 extern int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
);
1192 extern void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1193 extern void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1194 extern void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
);
1195 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
);
1196 extern void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
);
1197 extern void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
1198 extern int radeon_resume_kms(struct drm_device
*dev
);
1199 extern int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
);
1201 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1203 /* rv200,rv250,rv280 */
1204 extern void r200_set_safe_registers(struct radeon_device
*rdev
);
1206 /* r300,r350,rv350,rv370,rv380 */
1207 extern void r300_set_reg_safe(struct radeon_device
*rdev
);
1208 extern void r300_mc_program(struct radeon_device
*rdev
);
1209 extern void r300_mc_init(struct radeon_device
*rdev
);
1210 extern void r300_clock_startup(struct radeon_device
*rdev
);
1211 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
1212 extern int rv370_pcie_gart_init(struct radeon_device
*rdev
);
1213 extern void rv370_pcie_gart_fini(struct radeon_device
*rdev
);
1214 extern int rv370_pcie_gart_enable(struct radeon_device
*rdev
);
1215 extern void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
1217 /* r420,r423,rv410 */
1218 extern u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
);
1219 extern void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
1220 extern int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
);
1221 extern void r420_pipes_init(struct radeon_device
*rdev
);
1224 struct rv515_mc_save
{
1227 u32 vga_render_control
;
1228 u32 vga_hdp_control
;
1232 extern void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
);
1233 extern void rv515_vga_render_disable(struct radeon_device
*rdev
);
1234 extern void rv515_set_safe_registers(struct radeon_device
*rdev
);
1235 extern void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1236 extern void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1237 extern void rv515_clock_startup(struct radeon_device
*rdev
);
1238 extern void rv515_debugfs(struct radeon_device
*rdev
);
1239 extern int rv515_suspend(struct radeon_device
*rdev
);
1242 extern int rs400_gart_init(struct radeon_device
*rdev
);
1243 extern int rs400_gart_enable(struct radeon_device
*rdev
);
1244 extern void rs400_gart_adjust_size(struct radeon_device
*rdev
);
1245 extern void rs400_gart_disable(struct radeon_device
*rdev
);
1246 extern void rs400_gart_fini(struct radeon_device
*rdev
);
1249 extern void rs600_set_safe_registers(struct radeon_device
*rdev
);
1250 extern int rs600_irq_set(struct radeon_device
*rdev
);
1251 extern void rs600_irq_disable(struct radeon_device
*rdev
);
1254 extern void rs690_line_buffer_adjust(struct radeon_device
*rdev
,
1255 struct drm_display_mode
*mode1
,
1256 struct drm_display_mode
*mode2
);
1258 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1259 extern void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
1260 extern bool r600_card_posted(struct radeon_device
*rdev
);
1261 extern void r600_cp_stop(struct radeon_device
*rdev
);
1262 extern void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1263 extern int r600_cp_resume(struct radeon_device
*rdev
);
1264 extern void r600_cp_fini(struct radeon_device
*rdev
);
1265 extern int r600_count_pipe_bits(uint32_t val
);
1266 extern int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
1267 extern int r600_pcie_gart_init(struct radeon_device
*rdev
);
1268 extern void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
1269 extern int r600_ib_test(struct radeon_device
*rdev
);
1270 extern int r600_ring_test(struct radeon_device
*rdev
);
1271 extern void r600_wb_fini(struct radeon_device
*rdev
);
1272 extern int r600_wb_enable(struct radeon_device
*rdev
);
1273 extern void r600_wb_disable(struct radeon_device
*rdev
);
1274 extern void r600_scratch_init(struct radeon_device
*rdev
);
1275 extern int r600_blit_init(struct radeon_device
*rdev
);
1276 extern void r600_blit_fini(struct radeon_device
*rdev
);
1277 extern int r600_init_microcode(struct radeon_device
*rdev
);
1278 extern int r600_gpu_reset(struct radeon_device
*rdev
);
1280 extern int r600_irq_init(struct radeon_device
*rdev
);
1281 extern void r600_irq_fini(struct radeon_device
*rdev
);
1282 extern void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1283 extern int r600_irq_set(struct radeon_device
*rdev
);
1284 extern void r600_irq_suspend(struct radeon_device
*rdev
);
1286 extern int r600_audio_init(struct radeon_device
*rdev
);
1287 extern int r600_audio_tmds_index(struct drm_encoder
*encoder
);
1288 extern void r600_audio_set_clock(struct drm_encoder
*encoder
, int clock
);
1289 extern void r600_audio_fini(struct radeon_device
*rdev
);
1290 extern void r600_hdmi_init(struct drm_encoder
*encoder
);
1291 extern void r600_hdmi_enable(struct drm_encoder
*encoder
);
1292 extern void r600_hdmi_disable(struct drm_encoder
*encoder
);
1293 extern void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
1294 extern int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
);
1295 extern void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
,
1299 uint8_t status_bits
,
1300 uint8_t category_code
);
1303 struct evergreen_mc_save
{
1305 u32 vga_render_control
;
1306 u32 vga_hdp_control
;
1307 u32 crtc_control
[6];
1310 #include "radeon_object.h"