drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97 extern int radeon_lockup_timeout;
  98
  99 /*
 100  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 101  * symbol;
 102  */
 103 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 104 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 106 #define RADEON_IB_POOL_SIZE                     16
 107 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 108 #define RADEONFB_CONN_LIMIT                     4
 109 #define RADEON_BIOS_NUM_SCRATCH                 8
 110
 111 /* max number of rings */
 112 #define RADEON_NUM_RINGS                        3
 113
 114 /* fence seq are set to this number when signaled */
 115 #define RADEON_FENCE_SIGNALED_SEQ               0LL
 116
 117 /* internal ring indices */
 118 /* r1xx+ has gfx CP ring */
 119 #define RADEON_RING_TYPE_GFX_INDEX              0
 120
 121 /* cayman has 2 compute CP rings */
 122 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 123 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 124
 125 /* hardcode those limit for now */
 126 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 127 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 128
 129 /*
 130  * Errata workarounds.
 131  */
 132 enum radeon_pll_errata {
 133         CHIP_ERRATA_R300_CG             = 0x00000001,
 134         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 135         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 136 };
 137
 138
 139 struct radeon_device;
 140
 141
 142 /*
 143  * BIOS.
 144  */
 145 bool radeon_get_bios(struct radeon_device *rdev);
 146
 147 /*
 148  * Dummy page
 149  */
 150 struct radeon_dummy_page {
 151         struct page     *page;
 152         dma_addr_t      addr;
 153 };
 154 int radeon_dummy_page_init(struct radeon_device *rdev);
 155 void radeon_dummy_page_fini(struct radeon_device *rdev);
 156
 157
 158 /*
 159  * Clocks
 160  */
 161 struct radeon_clock {
 162         struct radeon_pll p1pll;
 163         struct radeon_pll p2pll;
 164         struct radeon_pll dcpll;
 165         struct radeon_pll spll;
 166         struct radeon_pll mpll;
 167         /* 10 Khz units */
 168         uint32_t default_mclk;
 169         uint32_t default_sclk;
 170         uint32_t default_dispclk;
 171         uint32_t dp_extclk;
 172         uint32_t max_pixel_clock;
 173 };
 174
 175 /*
 176  * Power management
 177  */
 178 int radeon_pm_init(struct radeon_device *rdev);
 179 void radeon_pm_fini(struct radeon_device *rdev);
 180 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 181 void radeon_pm_suspend(struct radeon_device *rdev);
 182 void radeon_pm_resume(struct radeon_device *rdev);
 183 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 184 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 185 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 186 void rs690_pm_info(struct radeon_device *rdev);
 187 extern int rv6xx_get_temp(struct radeon_device *rdev);
 188 extern int rv770_get_temp(struct radeon_device *rdev);
 189 extern int evergreen_get_temp(struct radeon_device *rdev);
 190 extern int sumo_get_temp(struct radeon_device *rdev);
 191 extern int si_get_temp(struct radeon_device *rdev);
 192 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 193                                     unsigned *bankh, unsigned *mtaspect,
 194                                     unsigned *tile_split);
 195
 196 /*
 197  * Fences.
 198  */
 199 struct radeon_fence_driver {
 200         uint32_t                        scratch_reg;
 201         uint64_t                        gpu_addr;
 202         volatile uint32_t               *cpu_addr;
 203         /* sync_seq is protected by ring emission lock */
 204         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 205         atomic64_t                      last_seq;
 206         unsigned long                   last_activity;
 207         bool                            initialized;
 208 };
 209
 210 struct radeon_fence {
 211         struct radeon_device            *rdev;
 212         struct kref                     kref;
 213         /* protected by radeon_fence.lock */
 214         uint64_t                        seq;
 215         /* RB, DMA, etc. */
 216         unsigned                        ring;
 217 };
 218
 219 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 220 int radeon_fence_driver_init(struct radeon_device *rdev);
 221 void radeon_fence_driver_fini(struct radeon_device *rdev);
 222 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 223 void radeon_fence_process(struct radeon_device *rdev, int ring);
 224 bool radeon_fence_signaled(struct radeon_fence *fence);
 225 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 226 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
 227 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
 228 int radeon_fence_wait_any(struct radeon_device *rdev,
 229                           struct radeon_fence **fences,
 230                           bool intr);
 231 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 232 void radeon_fence_unref(struct radeon_fence **fence);
 233 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 234 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 235 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 236 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 237                                                       struct radeon_fence *b)
 238 {
 239         if (!a) {
 240                 return b;
 241         }
 242
 243         if (!b) {
 244                 return a;
 245         }
 246
 247         BUG_ON(a->ring != b->ring);
 248
 249         if (a->seq > b->seq) {
 250                 return a;
 251         } else {
 252                 return b;
 253         }
 254 }
 255
 256 /*
 257  * Tiling registers
 258  */
 259 struct radeon_surface_reg {
 260         struct radeon_bo *bo;
 261 };
 262
 263 #define RADEON_GEM_MAX_SURFACES 8
 264
 265 /*
 266  * TTM.
 267  */
 268 struct radeon_mman {
 269         struct ttm_bo_global_ref        bo_global_ref;
 270         struct drm_global_reference     mem_global_ref;
 271         struct ttm_bo_device            bdev;
 272         bool                            mem_global_referenced;
 273         bool                            initialized;
 274 };
 275
 276 /* bo virtual address in a specific vm */
 277 struct radeon_bo_va {
 278         /* bo list is protected by bo being reserved */
 279         struct list_head                bo_list;
 280         /* vm list is protected by vm mutex */
 281         struct list_head                vm_list;
 282         /* constant after initialization */
 283         struct radeon_vm                *vm;
 284         struct radeon_bo                *bo;
 285         uint64_t                        soffset;
 286         uint64_t                        eoffset;
 287         uint32_t                        flags;
 288         struct radeon_fence             *fence;
 289         bool                            valid;
 290 };
 291
 292 struct radeon_bo {
 293         /* Protected by gem.mutex */
 294         struct list_head                list;
 295         /* Protected by tbo.reserved */
 296         u32                             placements[3];
 297         struct ttm_placement            placement;
 298         struct ttm_buffer_object        tbo;
 299         struct ttm_bo_kmap_obj          kmap;
 300         unsigned                        pin_count;
 301         void                            *kptr;
 302         u32                             tiling_flags;
 303         u32                             pitch;
 304         int                             surface_reg;
 305         /* list of all virtual address to which this bo
 306          * is associated to
 307          */
 308         struct list_head                va;
 309         /* Constant after initialization */
 310         struct radeon_device            *rdev;
 311         struct drm_gem_object           gem_base;
 312
 313         struct ttm_bo_kmap_obj dma_buf_vmap;
 314         int vmapping_count;
 315 };
 316 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 317
 318 struct radeon_bo_list {
 319         struct ttm_validate_buffer tv;
 320         struct radeon_bo        *bo;
 321         uint64_t                gpu_offset;
 322         unsigned                rdomain;
 323         unsigned                wdomain;
 324         u32                     tiling_flags;
 325 };
 326
 327 /* sub-allocation manager, it has to be protected by another lock.
 328  * By conception this is an helper for other part of the driver
 329  * like the indirect buffer or semaphore, which both have their
 330  * locking.
 331  *
 332  * Principe is simple, we keep a list of sub allocation in offset
 333  * order (first entry has offset == 0, last entry has the highest
 334  * offset).
 335  *
 336  * When allocating new object we first check if there is room at
 337  * the end total_size - (last_object_offset + last_object_size) >=
 338  * alloc_size. If so we allocate new object there.
 339  *
 340  * When there is not enough room at the end, we start waiting for
 341  * each sub object until we reach object_offset+object_size >=
 342  * alloc_size, this object then become the sub object we return.
 343  *
 344  * Alignment can't be bigger than page size.
 345  *
 346  * Hole are not considered for allocation to keep things simple.
 347  * Assumption is that there won't be hole (all object on same
 348  * alignment).
 349  */
 350 struct radeon_sa_manager {
 351         wait_queue_head_t       wq;
 352         struct radeon_bo        *bo;
 353         struct list_head        *hole;
 354         struct list_head        flist[RADEON_NUM_RINGS];
 355         struct list_head        olist;
 356         unsigned                size;
 357         uint64_t                gpu_addr;
 358         void                    *cpu_ptr;
 359         uint32_t                domain;
 360 };
 361
 362 struct radeon_sa_bo;
 363
 364 /* sub-allocation buffer */
 365 struct radeon_sa_bo {
 366         struct list_head                olist;
 367         struct list_head                flist;
 368         struct radeon_sa_manager        *manager;
 369         unsigned                        soffset;
 370         unsigned                        eoffset;
 371         struct radeon_fence             *fence;
 372 };
 373
 374 /*
 375  * GEM objects.
 376  */
 377 struct radeon_gem {
 378         struct mutex            mutex;
 379         struct list_head        objects;
 380 };
 381
 382 int radeon_gem_init(struct radeon_device *rdev);
 383 void radeon_gem_fini(struct radeon_device *rdev);
 384 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 385                                 int alignment, int initial_domain,
 386                                 bool discardable, bool kernel,
 387                                 struct drm_gem_object **obj);
 388
 389 int radeon_mode_dumb_create(struct drm_file *file_priv,
 390                             struct drm_device *dev,
 391                             struct drm_mode_create_dumb *args);
 392 int radeon_mode_dumb_mmap(struct drm_file *filp,
 393                           struct drm_device *dev,
 394                           uint32_t handle, uint64_t *offset_p);
 395 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 396                              struct drm_device *dev,
 397                              uint32_t handle);
 398
 399 /*
 400  * Semaphores.
 401  */
 402 /* everything here is constant */
 403 struct radeon_semaphore {
 404         struct radeon_sa_bo             *sa_bo;
 405         signed                          waiters;
 406         uint64_t                        gpu_addr;
 407 };
 408
 409 int radeon_semaphore_create(struct radeon_device *rdev,
 410                             struct radeon_semaphore **semaphore);
 411 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 412                                   struct radeon_semaphore *semaphore);
 413 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 414                                 struct radeon_semaphore *semaphore);
 415 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
 416                                 struct radeon_semaphore *semaphore,
 417                                 int signaler, int waiter);
 418 void radeon_semaphore_free(struct radeon_device *rdev,
 419                            struct radeon_semaphore **semaphore,
 420                            struct radeon_fence *fence);
 421
 422 /*
 423  * GART structures, functions & helpers
 424  */
 425 struct radeon_mc;
 426
 427 #define RADEON_GPU_PAGE_SIZE 4096
 428 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 429 #define RADEON_GPU_PAGE_SHIFT 12
 430 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 431
 432 struct radeon_gart {
 433         dma_addr_t                      table_addr;
 434         struct radeon_bo                *robj;
 435         void                            *ptr;
 436         unsigned                        num_gpu_pages;
 437         unsigned                        num_cpu_pages;
 438         unsigned                        table_size;
 439         struct page                     **pages;
 440         dma_addr_t                      *pages_addr;
 441         bool                            ready;
 442 };
 443
 444 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 445 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 446 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 447 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 448 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 449 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 450 int radeon_gart_init(struct radeon_device *rdev);
 451 void radeon_gart_fini(struct radeon_device *rdev);
 452 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 453                         int pages);
 454 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 455                      int pages, struct page **pagelist,
 456                      dma_addr_t *dma_addr);
 457 void radeon_gart_restore(struct radeon_device *rdev);
 458
 459
 460 /*
 461  * GPU MC structures, functions & helpers
 462  */
 463 struct radeon_mc {
 464         resource_size_t         aper_size;
 465         resource_size_t         aper_base;
 466         resource_size_t         agp_base;
 467         /* for some chips with <= 32MB we need to lie
 468          * about vram size near mc fb location */
 469         u64                     mc_vram_size;
 470         u64                     visible_vram_size;
 471         u64                     gtt_size;
 472         u64                     gtt_start;
 473         u64                     gtt_end;
 474         u64                     vram_start;
 475         u64                     vram_end;
 476         unsigned                vram_width;
 477         u64                     real_vram_size;
 478         int                     vram_mtrr;
 479         bool                    vram_is_ddr;
 480         bool                    igp_sideport_enabled;
 481         u64                     gtt_base_align;
 482 };
 483
 484 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 485 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 486
 487 /*
 488  * GPU scratch registers structures, functions & helpers
 489  */
 490 struct radeon_scratch {
 491         unsigned                num_reg;
 492         uint32_t                reg_base;
 493         bool                    free[32];
 494         uint32_t                reg[32];
 495 };
 496
 497 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 498 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 499
 500
 501 /*
 502  * IRQS.
 503  */
 504
 505 struct radeon_unpin_work {
 506         struct work_struct work;
 507         struct radeon_device *rdev;
 508         int crtc_id;
 509         struct radeon_fence *fence;
 510         struct drm_pending_vblank_event *event;
 511         struct radeon_bo *old_rbo;
 512         u64 new_crtc_base;
 513 };
 514
 515 struct r500_irq_stat_regs {
 516         u32 disp_int;
 517         u32 hdmi0_status;
 518 };
 519
 520 struct r600_irq_stat_regs {
 521         u32 disp_int;
 522         u32 disp_int_cont;
 523         u32 disp_int_cont2;
 524         u32 d1grph_int;
 525         u32 d2grph_int;
 526         u32 hdmi0_status;
 527         u32 hdmi1_status;
 528 };
 529
 530 struct evergreen_irq_stat_regs {
 531         u32 disp_int;
 532         u32 disp_int_cont;
 533         u32 disp_int_cont2;
 534         u32 disp_int_cont3;
 535         u32 disp_int_cont4;
 536         u32 disp_int_cont5;
 537         u32 d1grph_int;
 538         u32 d2grph_int;
 539         u32 d3grph_int;
 540         u32 d4grph_int;
 541         u32 d5grph_int;
 542         u32 d6grph_int;
 543         u32 afmt_status1;
 544         u32 afmt_status2;
 545         u32 afmt_status3;
 546         u32 afmt_status4;
 547         u32 afmt_status5;
 548         u32 afmt_status6;
 549 };
 550
 551 union radeon_irq_stat_regs {
 552         struct r500_irq_stat_regs r500;
 553         struct r600_irq_stat_regs r600;
 554         struct evergreen_irq_stat_regs evergreen;
 555 };
 556
 557 #define RADEON_MAX_HPD_PINS 6
 558 #define RADEON_MAX_CRTCS 6
 559 #define RADEON_MAX_AFMT_BLOCKS 6
 560
 561 struct radeon_irq {
 562         bool                            installed;
 563         spinlock_t                      lock;
 564         atomic_t                        ring_int[RADEON_NUM_RINGS];
 565         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 566         atomic_t                        pflip[RADEON_MAX_CRTCS];
 567         wait_queue_head_t               vblank_queue;
 568         bool                            hpd[RADEON_MAX_HPD_PINS];
 569         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 570         union radeon_irq_stat_regs      stat_regs;
 571 };
 572
 573 int radeon_irq_kms_init(struct radeon_device *rdev);
 574 void radeon_irq_kms_fini(struct radeon_device *rdev);
 575 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 576 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 577 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 578 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 579 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 580 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 581 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 582 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 583
 584 /*
 585  * CP & rings.
 586  */
 587
 588 struct radeon_ib {
 589         struct radeon_sa_bo             *sa_bo;
 590         uint32_t                        length_dw;
 591         uint64_t                        gpu_addr;
 592         uint32_t                        *ptr;
 593         int                             ring;
 594         struct radeon_fence             *fence;
 595         struct radeon_vm                *vm;
 596         bool                            is_const_ib;
 597         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
 598         struct radeon_semaphore         *semaphore;
 599 };
 600
 601 struct radeon_ring {
 602         struct radeon_bo        *ring_obj;
 603         volatile uint32_t       *ring;
 604         unsigned                rptr;
 605         unsigned                rptr_offs;
 606         unsigned                rptr_reg;
 607         unsigned                rptr_save_reg;
 608         u64                     next_rptr_gpu_addr;
 609         volatile u32            *next_rptr_cpu_addr;
 610         unsigned                wptr;
 611         unsigned                wptr_old;
 612         unsigned                wptr_reg;
 613         unsigned                ring_size;
 614         unsigned                ring_free_dw;
 615         int                     count_dw;
 616         unsigned long           last_activity;
 617         unsigned                last_rptr;
 618         uint64_t                gpu_addr;
 619         uint32_t                align_mask;
 620         uint32_t                ptr_mask;
 621         bool                    ready;
 622         u32                     ptr_reg_shift;
 623         u32                     ptr_reg_mask;
 624         u32                     nop;
 625         u32                     idx;
 626 };
 627
 628 /*
 629  * VM
 630  */
 631 struct radeon_vm {
 632         struct list_head                list;
 633         struct list_head                va;
 634         int                             id;
 635         unsigned                        last_pfn;
 636         u64                             pt_gpu_addr;
 637         u64                             *pt;
 638         struct radeon_sa_bo             *sa_bo;
 639         struct mutex                    mutex;
 640         /* last fence for cs using this vm */
 641         struct radeon_fence             *fence;
 642 };
 643
 644 struct radeon_vm_manager {
 645         struct mutex                    lock;
 646         struct list_head                lru_vm;
 647         uint32_t                        use_bitmap;
 648         struct radeon_sa_manager        sa_manager;
 649         uint32_t                        max_pfn;
 650         /* number of VMIDs */
 651         unsigned                        nvm;
 652         /* vram base address for page table entry  */
 653         u64                             vram_base_offset;
 654         /* is vm enabled? */
 655         bool                            enabled;
 656 };
 657
 658 /*
 659  * file private structure
 660  */
 661 struct radeon_fpriv {
 662         struct radeon_vm                vm;
 663 };
 664
 665 /*
 666  * R6xx+ IH ring
 667  */
 668 struct r600_ih {
 669         struct radeon_bo        *ring_obj;
 670         volatile uint32_t       *ring;
 671         unsigned                rptr;
 672         unsigned                ring_size;
 673         uint64_t                gpu_addr;
 674         uint32_t                ptr_mask;
 675         atomic_t                lock;
 676         bool                    enabled;
 677 };
 678
 679 struct r600_blit_cp_primitives {
 680         void (*set_render_target)(struct radeon_device *rdev, int format,
 681                                   int w, int h, u64 gpu_addr);
 682         void (*cp_set_surface_sync)(struct radeon_device *rdev,
 683                                     u32 sync_type, u32 size,
 684                                     u64 mc_addr);
 685         void (*set_shaders)(struct radeon_device *rdev);
 686         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
 687         void (*set_tex_resource)(struct radeon_device *rdev,
 688                                  int format, int w, int h, int pitch,
 689                                  u64 gpu_addr, u32 size);
 690         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
 691                              int x2, int y2);
 692         void (*draw_auto)(struct radeon_device *rdev);
 693         void (*set_default_state)(struct radeon_device *rdev);
 694 };
 695
 696 struct r600_blit {
 697         struct radeon_bo        *shader_obj;
 698         struct r600_blit_cp_primitives primitives;
 699         int max_dim;
 700         int ring_size_common;
 701         int ring_size_per_loop;
 702         u64 shader_gpu_addr;
 703         u32 vs_offset, ps_offset;
 704         u32 state_offset;
 705         u32 state_len;
 706 };
 707
 708 /*
 709  * SI RLC stuff
 710  */
 711 struct si_rlc {
 712         /* for power gating */
 713         struct radeon_bo        *save_restore_obj;
 714         uint64_t                save_restore_gpu_addr;
 715         /* for clear state */
 716         struct radeon_bo        *clear_state_obj;
 717         uint64_t                clear_state_gpu_addr;
 718 };
 719
 720 int radeon_ib_get(struct radeon_device *rdev, int ring,
 721                   struct radeon_ib *ib, struct radeon_vm *vm,
 722                   unsigned size);
 723 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
 724 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
 725                        struct radeon_ib *const_ib);
 726 int radeon_ib_pool_init(struct radeon_device *rdev);
 727 void radeon_ib_pool_fini(struct radeon_device *rdev);
 728 int radeon_ib_ring_tests(struct radeon_device *rdev);
 729 /* Ring access between begin & end cannot sleep */
 730 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
 731                                       struct radeon_ring *ring);
 732 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 733 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 734 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 735 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 736 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 737 void radeon_ring_undo(struct radeon_ring *ring);
 738 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 739 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 740 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
 741 void radeon_ring_lockup_update(struct radeon_ring *ring);
 742 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 743 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
 744                             uint32_t **data);
 745 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
 746                         unsigned size, uint32_t *data);
 747 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 748                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 749                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
 750 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 751
 752
 753 /*
 754  * CS.
 755  */
 756 struct radeon_cs_reloc {
 757         struct drm_gem_object           *gobj;
 758         struct radeon_bo                *robj;
 759         struct radeon_bo_list           lobj;
 760         uint32_t                        handle;
 761         uint32_t                        flags;
 762 };
 763
 764 struct radeon_cs_chunk {
 765         uint32_t                chunk_id;
 766         uint32_t                length_dw;
 767         int                     kpage_idx[2];
 768         uint32_t                *kpage[2];
 769         uint32_t                *kdata;
 770         void __user             *user_ptr;
 771         int                     last_copied_page;
 772         int                     last_page_index;
 773 };
 774
 775 struct radeon_cs_parser {
 776         struct device           *dev;
 777         struct radeon_device    *rdev;
 778         struct drm_file         *filp;
 779         /* chunks */
 780         unsigned                nchunks;
 781         struct radeon_cs_chunk  *chunks;
 782         uint64_t                *chunks_array;
 783         /* IB */
 784         unsigned                idx;
 785         /* relocations */
 786         unsigned                nrelocs;
 787         struct radeon_cs_reloc  *relocs;
 788         struct radeon_cs_reloc  **relocs_ptr;
 789         struct list_head        validated;
 790         /* indices of various chunks */
 791         int                     chunk_ib_idx;
 792         int                     chunk_relocs_idx;
 793         int                     chunk_flags_idx;
 794         int                     chunk_const_ib_idx;
 795         struct radeon_ib        ib;
 796         struct radeon_ib        const_ib;
 797         void                    *track;
 798         unsigned                family;
 799         int                     parser_error;
 800         u32                     cs_flags;
 801         u32                     ring;
 802         s32                     priority;
 803 };
 804
 805 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 806 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 807
 808 struct radeon_cs_packet {
 809         unsigned        idx;
 810         unsigned        type;
 811         unsigned        reg;
 812         unsigned        opcode;
 813         int             count;
 814         unsigned        one_reg_wr;
 815 };
 816
 817 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 818                                       struct radeon_cs_packet *pkt,
 819                                       unsigned idx, unsigned reg);
 820 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 821                                       struct radeon_cs_packet *pkt);
 822
 823
 824 /*
 825  * AGP
 826  */
 827 int radeon_agp_init(struct radeon_device *rdev);
 828 void radeon_agp_resume(struct radeon_device *rdev);
 829 void radeon_agp_suspend(struct radeon_device *rdev);
 830 void radeon_agp_fini(struct radeon_device *rdev);
 831
 832
 833 /*
 834  * Writeback
 835  */
 836 struct radeon_wb {
 837         struct radeon_bo        *wb_obj;
 838         volatile uint32_t       *wb;
 839         uint64_t                gpu_addr;
 840         bool                    enabled;
 841         bool                    use_event;
 842 };
 843
 844 #define RADEON_WB_SCRATCH_OFFSET 0
 845 #define RADEON_WB_RING0_NEXT_RPTR 256
 846 #define RADEON_WB_CP_RPTR_OFFSET 1024
 847 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 848 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 849 #define R600_WB_IH_WPTR_OFFSET   2048
 850 #define R600_WB_EVENT_OFFSET     3072
 851
 852 /**
 853  * struct radeon_pm - power management datas
 854  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 855  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 856  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 857  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 858  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 859  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 860  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 861  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 862  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 863  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 864  * @needed_bandwidth:   current bandwidth needs
 865  *
 866  * It keeps track of various data needed to take powermanagement decision.
 867  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 868  * Equation between gpu/memory clock and available bandwidth is hw dependent
 869  * (type of memory, bus size, efficiency, ...)
 870  */
 871
 872 enum radeon_pm_method {
 873         PM_METHOD_PROFILE,
 874         PM_METHOD_DYNPM,
 875 };
 876
 877 enum radeon_dynpm_state {
 878         DYNPM_STATE_DISABLED,
 879         DYNPM_STATE_MINIMUM,
 880         DYNPM_STATE_PAUSED,
 881         DYNPM_STATE_ACTIVE,
 882         DYNPM_STATE_SUSPENDED,
 883 };
 884 enum radeon_dynpm_action {
 885         DYNPM_ACTION_NONE,
 886         DYNPM_ACTION_MINIMUM,
 887         DYNPM_ACTION_DOWNCLOCK,
 888         DYNPM_ACTION_UPCLOCK,
 889         DYNPM_ACTION_DEFAULT
 890 };
 891
 892 enum radeon_voltage_type {
 893         VOLTAGE_NONE = 0,
 894         VOLTAGE_GPIO,
 895         VOLTAGE_VDDC,
 896         VOLTAGE_SW
 897 };
 898
 899 enum radeon_pm_state_type {
 900         POWER_STATE_TYPE_DEFAULT,
 901         POWER_STATE_TYPE_POWERSAVE,
 902         POWER_STATE_TYPE_BATTERY,
 903         POWER_STATE_TYPE_BALANCED,
 904         POWER_STATE_TYPE_PERFORMANCE,
 905 };
 906
 907 enum radeon_pm_profile_type {
 908         PM_PROFILE_DEFAULT,
 909         PM_PROFILE_AUTO,
 910         PM_PROFILE_LOW,
 911         PM_PROFILE_MID,
 912         PM_PROFILE_HIGH,
 913 };
 914
 915 #define PM_PROFILE_DEFAULT_IDX 0
 916 #define PM_PROFILE_LOW_SH_IDX  1
 917 #define PM_PROFILE_MID_SH_IDX  2
 918 #define PM_PROFILE_HIGH_SH_IDX 3
 919 #define PM_PROFILE_LOW_MH_IDX  4
 920 #define PM_PROFILE_MID_MH_IDX  5
 921 #define PM_PROFILE_HIGH_MH_IDX 6
 922 #define PM_PROFILE_MAX         7
 923
 924 struct radeon_pm_profile {
 925         int dpms_off_ps_idx;
 926         int dpms_on_ps_idx;
 927         int dpms_off_cm_idx;
 928         int dpms_on_cm_idx;
 929 };
 930
 931 enum radeon_int_thermal_type {
 932         THERMAL_TYPE_NONE,
 933         THERMAL_TYPE_RV6XX,
 934         THERMAL_TYPE_RV770,
 935         THERMAL_TYPE_EVERGREEN,
 936         THERMAL_TYPE_SUMO,
 937         THERMAL_TYPE_NI,
 938         THERMAL_TYPE_SI,
 939 };
 940
 941 struct radeon_voltage {
 942         enum radeon_voltage_type type;
 943         /* gpio voltage */
 944         struct radeon_gpio_rec gpio;
 945         u32 delay; /* delay in usec from voltage drop to sclk change */
 946         bool active_high; /* voltage drop is active when bit is high */
 947         /* VDDC voltage */
 948         u8 vddc_id; /* index into vddc voltage table */
 949         u8 vddci_id; /* index into vddci voltage table */
 950         bool vddci_enabled;
 951         /* r6xx+ sw */
 952         u16 voltage;
 953         /* evergreen+ vddci */
 954         u16 vddci;
 955 };
 956
 957 /* clock mode flags */
 958 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 959
 960 struct radeon_pm_clock_info {
 961         /* memory clock */
 962         u32 mclk;
 963         /* engine clock */
 964         u32 sclk;
 965         /* voltage info */
 966         struct radeon_voltage voltage;
 967         /* standardized clock flags */
 968         u32 flags;
 969 };
 970
 971 /* state flags */
 972 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 973
 974 struct radeon_power_state {
 975         enum radeon_pm_state_type type;
 976         struct radeon_pm_clock_info *clock_info;
 977         /* number of valid clock modes in this power state */
 978         int num_clock_modes;
 979         struct radeon_pm_clock_info *default_clock_mode;
 980         /* standardized state flags */
 981         u32 flags;
 982         u32 misc; /* vbios specific flags */
 983         u32 misc2; /* vbios specific flags */
 984         int pcie_lanes; /* pcie lanes */
 985 };
 986
 987 /*
 988  * Some modes are overclocked by very low value, accept them
 989  */
 990 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 991
 992 struct radeon_pm {
 993         struct mutex            mutex;
 994         /* write locked while reprogramming mclk */
 995         struct rw_semaphore     mclk_lock;
 996         u32                     active_crtcs;
 997         int                     active_crtc_count;
 998         int                     req_vblank;
 999         bool                    vblank_sync;
1000         fixed20_12              max_bandwidth;
1001         fixed20_12              igp_sideport_mclk;
1002         fixed20_12              igp_system_mclk;
1003         fixed20_12              igp_ht_link_clk;
1004         fixed20_12              igp_ht_link_width;
1005         fixed20_12              k8_bandwidth;
1006         fixed20_12              sideport_bandwidth;
1007         fixed20_12              ht_bandwidth;
1008         fixed20_12              core_bandwidth;
1009         fixed20_12              sclk;
1010         fixed20_12              mclk;
1011         fixed20_12              needed_bandwidth;
1012         struct radeon_power_state *power_state;
1013         /* number of valid power states */
1014         int                     num_power_states;
1015         int                     current_power_state_index;
1016         int                     current_clock_mode_index;
1017         int                     requested_power_state_index;
1018         int                     requested_clock_mode_index;
1019         int                     default_power_state_index;
1020         u32                     current_sclk;
1021         u32                     current_mclk;
1022         u16                     current_vddc;
1023         u16                     current_vddci;
1024         u32                     default_sclk;
1025         u32                     default_mclk;
1026         u16                     default_vddc;
1027         u16                     default_vddci;
1028         struct radeon_i2c_chan *i2c_bus;
1029         /* selected pm method */
1030         enum radeon_pm_method     pm_method;
1031         /* dynpm power management */
1032         struct delayed_work     dynpm_idle_work;
1033         enum radeon_dynpm_state dynpm_state;
1034         enum radeon_dynpm_action        dynpm_planned_action;
1035         unsigned long           dynpm_action_timeout;
1036         bool                    dynpm_can_upclock;
1037         bool                    dynpm_can_downclock;
1038         /* profile-based power management */
1039         enum radeon_pm_profile_type profile;
1040         int                     profile_index;
1041         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1042         /* internal thermal controller on rv6xx+ */
1043         enum radeon_int_thermal_type int_thermal_type;
1044         struct device           *int_hwmon_dev;
1045 };
1046
1047 int radeon_pm_get_type_index(struct radeon_device *rdev,
1048                              enum radeon_pm_state_type ps_type,
1049                              int instance);
1050
1051 struct r600_audio {
1052         int                     channels;
1053         int                     rate;
1054         int                     bits_per_sample;
1055         u8                      status_bits;
1056         u8                      category_code;
1057 };
1058
1059 /*
1060  * Benchmarking
1061  */
1062 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1063
1064
1065 /*
1066  * Testing
1067  */
1068 void radeon_test_moves(struct radeon_device *rdev);
1069 void radeon_test_ring_sync(struct radeon_device *rdev,
1070                            struct radeon_ring *cpA,
1071                            struct radeon_ring *cpB);
1072 void radeon_test_syncing(struct radeon_device *rdev);
1073
1074
1075 /*
1076  * Debugfs
1077  */
1078 struct radeon_debugfs {
1079         struct drm_info_list    *files;
1080         unsigned                num_files;
1081 };
1082
1083 int radeon_debugfs_add_files(struct radeon_device *rdev,
1084                              struct drm_info_list *files,
1085                              unsigned nfiles);
1086 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1087
1088
1089 /*
1090  * ASIC specific functions.
1091  */
1092 struct radeon_asic {
1093         int (*init)(struct radeon_device *rdev);
1094         void (*fini)(struct radeon_device *rdev);
1095         int (*resume)(struct radeon_device *rdev);
1096         int (*suspend)(struct radeon_device *rdev);
1097         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1098         int (*asic_reset)(struct radeon_device *rdev);
1099         /* ioctl hw specific callback. Some hw might want to perform special
1100          * operation on specific ioctl. For instance on wait idle some hw
1101          * might want to perform and HDP flush through MMIO as it seems that
1102          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1103          * through ring.
1104          */
1105         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1106         /* check if 3D engine is idle */
1107         bool (*gui_idle)(struct radeon_device *rdev);
1108         /* wait for mc_idle */
1109         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1110         /* gart */
1111         struct {
1112                 void (*tlb_flush)(struct radeon_device *rdev);
1113                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1114         } gart;
1115         struct {
1116                 int (*init)(struct radeon_device *rdev);
1117                 void (*fini)(struct radeon_device *rdev);
1118                 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
1119                 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
1120                 uint32_t (*page_flags)(struct radeon_device *rdev,
1121                                        struct radeon_vm *vm,
1122                                        uint32_t flags);
1123                 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
1124                                  unsigned pfn, uint64_t addr, uint32_t flags);
1125         } vm;
1126         /* ring specific callbacks */
1127         struct {
1128                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1129                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1130                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1131                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1132                                        struct radeon_semaphore *semaphore, bool emit_wait);
1133                 int (*cs_parse)(struct radeon_cs_parser *p);
1134                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1135                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1136                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1137                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1138         } ring[RADEON_NUM_RINGS];
1139         /* irqs */
1140         struct {
1141                 int (*set)(struct radeon_device *rdev);
1142                 int (*process)(struct radeon_device *rdev);
1143         } irq;
1144         /* displays */
1145         struct {
1146                 /* display watermarks */
1147                 void (*bandwidth_update)(struct radeon_device *rdev);
1148                 /* get frame count */
1149                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1150                 /* wait for vblank */
1151                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1152                 /* set backlight level */
1153                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1154         } display;
1155         /* copy functions for bo handling */
1156         struct {
1157                 int (*blit)(struct radeon_device *rdev,
1158                             uint64_t src_offset,
1159                             uint64_t dst_offset,
1160                             unsigned num_gpu_pages,
1161                             struct radeon_fence **fence);
1162                 u32 blit_ring_index;
1163                 int (*dma)(struct radeon_device *rdev,
1164                            uint64_t src_offset,
1165                            uint64_t dst_offset,
1166                            unsigned num_gpu_pages,
1167                            struct radeon_fence **fence);
1168                 u32 dma_ring_index;
1169                 /* method used for bo copy */
1170                 int (*copy)(struct radeon_device *rdev,
1171                             uint64_t src_offset,
1172                             uint64_t dst_offset,
1173                             unsigned num_gpu_pages,
1174                             struct radeon_fence **fence);
1175                 /* ring used for bo copies */
1176                 u32 copy_ring_index;
1177         } copy;
1178         /* surfaces */
1179         struct {
1180                 int (*set_reg)(struct radeon_device *rdev, int reg,
1181                                        uint32_t tiling_flags, uint32_t pitch,
1182                                        uint32_t offset, uint32_t obj_size);
1183                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1184         } surface;
1185         /* hotplug detect */
1186         struct {
1187                 void (*init)(struct radeon_device *rdev);
1188                 void (*fini)(struct radeon_device *rdev);
1189                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1190                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1191         } hpd;
1192         /* power management */
1193         struct {
1194                 void (*misc)(struct radeon_device *rdev);
1195                 void (*prepare)(struct radeon_device *rdev);
1196                 void (*finish)(struct radeon_device *rdev);
1197                 void (*init_profile)(struct radeon_device *rdev);
1198                 void (*get_dynpm_state)(struct radeon_device *rdev);
1199                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1200                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1201                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1202                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1203                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1204                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1205                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1206         } pm;
1207         /* pageflipping */
1208         struct {
1209                 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1210                 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1211                 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1212         } pflip;
1213 };
1214
1215 /*
1216  * Asic structures
1217  */
1218 struct r100_asic {
1219         const unsigned          *reg_safe_bm;
1220         unsigned                reg_safe_bm_size;
1221         u32                     hdp_cntl;
1222 };
1223
1224 struct r300_asic {
1225         const unsigned          *reg_safe_bm;
1226         unsigned                reg_safe_bm_size;
1227         u32                     resync_scratch;
1228         u32                     hdp_cntl;
1229 };
1230
1231 struct r600_asic {
1232         unsigned                max_pipes;
1233         unsigned                max_tile_pipes;
1234         unsigned                max_simds;
1235         unsigned                max_backends;
1236         unsigned                max_gprs;
1237         unsigned                max_threads;
1238         unsigned                max_stack_entries;
1239         unsigned                max_hw_contexts;
1240         unsigned                max_gs_threads;
1241         unsigned                sx_max_export_size;
1242         unsigned                sx_max_export_pos_size;
1243         unsigned                sx_max_export_smx_size;
1244         unsigned                sq_num_cf_insts;
1245         unsigned                tiling_nbanks;
1246         unsigned                tiling_npipes;
1247         unsigned                tiling_group_size;
1248         unsigned                tile_config;
1249         unsigned                backend_map;
1250 };
1251
1252 struct rv770_asic {
1253         unsigned                max_pipes;
1254         unsigned                max_tile_pipes;
1255         unsigned                max_simds;
1256         unsigned                max_backends;
1257         unsigned                max_gprs;
1258         unsigned                max_threads;
1259         unsigned                max_stack_entries;
1260         unsigned                max_hw_contexts;
1261         unsigned                max_gs_threads;
1262         unsigned                sx_max_export_size;
1263         unsigned                sx_max_export_pos_size;
1264         unsigned                sx_max_export_smx_size;
1265         unsigned                sq_num_cf_insts;
1266         unsigned                sx_num_of_sets;
1267         unsigned                sc_prim_fifo_size;
1268         unsigned                sc_hiz_tile_fifo_size;
1269         unsigned                sc_earlyz_tile_fifo_fize;
1270         unsigned                tiling_nbanks;
1271         unsigned                tiling_npipes;
1272         unsigned                tiling_group_size;
1273         unsigned                tile_config;
1274         unsigned                backend_map;
1275 };
1276
1277 struct evergreen_asic {
1278         unsigned num_ses;
1279         unsigned max_pipes;
1280         unsigned max_tile_pipes;
1281         unsigned max_simds;
1282         unsigned max_backends;
1283         unsigned max_gprs;
1284         unsigned max_threads;
1285         unsigned max_stack_entries;
1286         unsigned max_hw_contexts;
1287         unsigned max_gs_threads;
1288         unsigned sx_max_export_size;
1289         unsigned sx_max_export_pos_size;
1290         unsigned sx_max_export_smx_size;
1291         unsigned sq_num_cf_insts;
1292         unsigned sx_num_of_sets;
1293         unsigned sc_prim_fifo_size;
1294         unsigned sc_hiz_tile_fifo_size;
1295         unsigned sc_earlyz_tile_fifo_size;
1296         unsigned tiling_nbanks;
1297         unsigned tiling_npipes;
1298         unsigned tiling_group_size;
1299         unsigned tile_config;
1300         unsigned backend_map;
1301 };
1302
1303 struct cayman_asic {
1304         unsigned max_shader_engines;
1305         unsigned max_pipes_per_simd;
1306         unsigned max_tile_pipes;
1307         unsigned max_simds_per_se;
1308         unsigned max_backends_per_se;
1309         unsigned max_texture_channel_caches;
1310         unsigned max_gprs;
1311         unsigned max_threads;
1312         unsigned max_gs_threads;
1313         unsigned max_stack_entries;
1314         unsigned sx_num_of_sets;
1315         unsigned sx_max_export_size;
1316         unsigned sx_max_export_pos_size;
1317         unsigned sx_max_export_smx_size;
1318         unsigned max_hw_contexts;
1319         unsigned sq_num_cf_insts;
1320         unsigned sc_prim_fifo_size;
1321         unsigned sc_hiz_tile_fifo_size;
1322         unsigned sc_earlyz_tile_fifo_size;
1323
1324         unsigned num_shader_engines;
1325         unsigned num_shader_pipes_per_simd;
1326         unsigned num_tile_pipes;
1327         unsigned num_simds_per_se;
1328         unsigned num_backends_per_se;
1329         unsigned backend_disable_mask_per_asic;
1330         unsigned backend_map;
1331         unsigned num_texture_channel_caches;
1332         unsigned mem_max_burst_length_bytes;
1333         unsigned mem_row_size_in_kb;
1334         unsigned shader_engine_tile_size;
1335         unsigned num_gpus;
1336         unsigned multi_gpu_tile_size;
1337
1338         unsigned tile_config;
1339 };
1340
1341 struct si_asic {
1342         unsigned max_shader_engines;
1343         unsigned max_tile_pipes;
1344         unsigned max_cu_per_sh;
1345         unsigned max_sh_per_se;
1346         unsigned max_backends_per_se;
1347         unsigned max_texture_channel_caches;
1348         unsigned max_gprs;
1349         unsigned max_gs_threads;
1350         unsigned max_hw_contexts;
1351         unsigned sc_prim_fifo_size_frontend;
1352         unsigned sc_prim_fifo_size_backend;
1353         unsigned sc_hiz_tile_fifo_size;
1354         unsigned sc_earlyz_tile_fifo_size;
1355
1356         unsigned num_tile_pipes;
1357         unsigned num_backends_per_se;
1358         unsigned backend_disable_mask_per_asic;
1359         unsigned backend_map;
1360         unsigned num_texture_channel_caches;
1361         unsigned mem_max_burst_length_bytes;
1362         unsigned mem_row_size_in_kb;
1363         unsigned shader_engine_tile_size;
1364         unsigned num_gpus;
1365         unsigned multi_gpu_tile_size;
1366
1367         unsigned tile_config;
1368 };
1369
1370 union radeon_asic_config {
1371         struct r300_asic        r300;
1372         struct r100_asic        r100;
1373         struct r600_asic        r600;
1374         struct rv770_asic       rv770;
1375         struct evergreen_asic   evergreen;
1376         struct cayman_asic      cayman;
1377         struct si_asic          si;
1378 };
1379
1380 /*
1381  * asic initizalization from radeon_asic.c
1382  */
1383 void radeon_agp_disable(struct radeon_device *rdev);
1384 int radeon_asic_init(struct radeon_device *rdev);
1385
1386
1387 /*
1388  * IOCTL.
1389  */
1390 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1391                           struct drm_file *filp);
1392 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1393                             struct drm_file *filp);
1394 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1395                          struct drm_file *file_priv);
1396 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1397                            struct drm_file *file_priv);
1398 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1399                             struct drm_file *file_priv);
1400 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1401                            struct drm_file *file_priv);
1402 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1403                                 struct drm_file *filp);
1404 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1405                           struct drm_file *filp);
1406 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1407                           struct drm_file *filp);
1408 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1409                               struct drm_file *filp);
1410 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1411                           struct drm_file *filp);
1412 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1413 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1414                                 struct drm_file *filp);
1415 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1416                                 struct drm_file *filp);
1417
1418 /* VRAM scratch page for HDP bug, default vram page */
1419 struct r600_vram_scratch {
1420         struct radeon_bo                *robj;
1421         volatile uint32_t               *ptr;
1422         u64                             gpu_addr;
1423 };
1424
1425 /*
1426  * ACPI
1427  */
1428 struct radeon_atif_notification_cfg {
1429         bool enabled;
1430         int command_code;
1431 };
1432
1433 struct radeon_atif_notifications {
1434         bool display_switch;
1435         bool expansion_mode_change;
1436         bool thermal_state;
1437         bool forced_power_state;
1438         bool system_power_state;
1439         bool display_conf_change;
1440         bool px_gfx_switch;
1441         bool brightness_change;
1442         bool dgpu_display_event;
1443 };
1444
1445 struct radeon_atif_functions {
1446         bool system_params;
1447         bool sbios_requests;
1448         bool select_active_disp;
1449         bool lid_state;
1450         bool get_tv_standard;
1451         bool set_tv_standard;
1452         bool get_panel_expansion_mode;
1453         bool set_panel_expansion_mode;
1454         bool temperature_change;
1455         bool graphics_device_types;
1456 };
1457
1458 struct radeon_atif {
1459         struct radeon_atif_notifications notifications;
1460         struct radeon_atif_functions functions;
1461         struct radeon_atif_notification_cfg notification_cfg;
1462         struct radeon_encoder *encoder_for_bl;
1463 };
1464
1465 struct radeon_atcs_functions {
1466         bool get_ext_state;
1467         bool pcie_perf_req;
1468         bool pcie_dev_rdy;
1469         bool pcie_bus_width;
1470 };
1471
1472 struct radeon_atcs {
1473         struct radeon_atcs_functions functions;
1474 };
1475
1476 /*
1477  * Core structure, functions and helpers.
1478  */
1479 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1480 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1481
1482 struct radeon_device {
1483         struct device                   *dev;
1484         struct drm_device               *ddev;
1485         struct pci_dev                  *pdev;
1486         struct rw_semaphore             exclusive_lock;
1487         /* ASIC */
1488         union radeon_asic_config        config;
1489         enum radeon_family              family;
1490         unsigned long                   flags;
1491         int                             usec_timeout;
1492         enum radeon_pll_errata          pll_errata;
1493         int                             num_gb_pipes;
1494         int                             num_z_pipes;
1495         int                             disp_priority;
1496         /* BIOS */
1497         uint8_t                         *bios;
1498         bool                            is_atom_bios;
1499         uint16_t                        bios_header_start;
1500         struct radeon_bo                *stollen_vga_memory;
1501         /* Register mmio */
1502         resource_size_t                 rmmio_base;
1503         resource_size_t                 rmmio_size;
1504         void __iomem                    *rmmio;
1505         radeon_rreg_t                   mc_rreg;
1506         radeon_wreg_t                   mc_wreg;
1507         radeon_rreg_t                   pll_rreg;
1508         radeon_wreg_t                   pll_wreg;
1509         uint32_t                        pcie_reg_mask;
1510         radeon_rreg_t                   pciep_rreg;
1511         radeon_wreg_t                   pciep_wreg;
1512         /* io port */
1513         void __iomem                    *rio_mem;
1514         resource_size_t                 rio_mem_size;
1515         struct radeon_clock             clock;
1516         struct radeon_mc                mc;
1517         struct radeon_gart              gart;
1518         struct radeon_mode_info         mode_info;
1519         struct radeon_scratch           scratch;
1520         struct radeon_mman              mman;
1521         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
1522         wait_queue_head_t               fence_queue;
1523         struct mutex                    ring_lock;
1524         struct radeon_ring              ring[RADEON_NUM_RINGS];
1525         bool                            ib_pool_ready;
1526         struct radeon_sa_manager        ring_tmp_bo;
1527         struct radeon_irq               irq;
1528         struct radeon_asic              *asic;
1529         struct radeon_gem               gem;
1530         struct radeon_pm                pm;
1531         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1532         struct radeon_wb                wb;
1533         struct radeon_dummy_page        dummy_page;
1534         bool                            shutdown;
1535         bool                            suspend;
1536         bool                            need_dma32;
1537         bool                            accel_working;
1538         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1539         const struct firmware *me_fw;   /* all family ME firmware */
1540         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1541         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1542         const struct firmware *mc_fw;   /* NI MC firmware */
1543         const struct firmware *ce_fw;   /* SI CE firmware */
1544         struct r600_blit r600_blit;
1545         struct r600_vram_scratch vram_scratch;
1546         int msi_enabled; /* msi enabled */
1547         struct r600_ih ih; /* r6/700 interrupt ring */
1548         struct si_rlc rlc;
1549         struct work_struct hotplug_work;
1550         struct work_struct audio_work;
1551         int num_crtc; /* number of crtcs */
1552         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1553         bool audio_enabled;
1554         struct r600_audio audio_status; /* audio stuff */
1555         struct notifier_block acpi_nb;
1556         /* only one userspace can use Hyperz features or CMASK at a time */
1557         struct drm_file *hyperz_filp;
1558         struct drm_file *cmask_filp;
1559         /* i2c buses */
1560         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1561         /* debugfs */
1562         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1563         unsigned                debugfs_count;
1564         /* virtual memory */
1565         struct radeon_vm_manager        vm_manager;
1566         struct mutex                    gpu_clock_mutex;
1567         /* ACPI interface */
1568         struct radeon_atif              atif;
1569         struct radeon_atcs              atcs;
1570 };
1571
1572 int radeon_device_init(struct radeon_device *rdev,
1573                        struct drm_device *ddev,
1574                        struct pci_dev *pdev,
1575                        uint32_t flags);
1576 void radeon_device_fini(struct radeon_device *rdev);
1577 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1578
1579 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1580 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1581 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1582 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1583
1584 /*
1585  * Cast helper
1586  */
1587 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1588
1589 /*
1590  * Registers read & write functions.
1591  */
1592 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1593 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1594 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1595 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1596 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1597 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1598 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1599 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1600 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1601 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1602 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1603 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1604 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1605 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1606 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1607 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1608 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1609 #define WREG32_P(reg, val, mask)                                \
1610         do {                                                    \
1611                 uint32_t tmp_ = RREG32(reg);                    \
1612                 tmp_ &= (mask);                                 \
1613                 tmp_ |= ((val) & ~(mask));                      \
1614                 WREG32(reg, tmp_);                              \
1615         } while (0)
1616 #define WREG32_PLL_P(reg, val, mask)                            \
1617         do {                                                    \
1618                 uint32_t tmp_ = RREG32_PLL(reg);                \
1619                 tmp_ &= (mask);                                 \
1620                 tmp_ |= ((val) & ~(mask));                      \
1621                 WREG32_PLL(reg, tmp_);                          \
1622         } while (0)
1623 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1624 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1625 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1626
1627 /*
1628  * Indirect registers accessor
1629  */
1630 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1631 {
1632         uint32_t r;
1633
1634         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1635         r = RREG32(RADEON_PCIE_DATA);
1636         return r;
1637 }
1638
1639 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1640 {
1641         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1642         WREG32(RADEON_PCIE_DATA, (v));
1643 }
1644
1645 void r100_pll_errata_after_index(struct radeon_device *rdev);
1646
1647
1648 /*
1649  * ASICs helpers.
1650  */
1651 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1652                             (rdev->pdev->device == 0x5969))
1653 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1654                 (rdev->family == CHIP_RV200) || \
1655                 (rdev->family == CHIP_RS100) || \
1656                 (rdev->family == CHIP_RS200) || \
1657                 (rdev->family == CHIP_RV250) || \
1658                 (rdev->family == CHIP_RV280) || \
1659                 (rdev->family == CHIP_RS300))
1660 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1661                 (rdev->family == CHIP_RV350) ||                 \
1662                 (rdev->family == CHIP_R350)  ||                 \
1663                 (rdev->family == CHIP_RV380) ||                 \
1664                 (rdev->family == CHIP_R420)  ||                 \
1665                 (rdev->family == CHIP_R423)  ||                 \
1666                 (rdev->family == CHIP_RV410) ||                 \
1667                 (rdev->family == CHIP_RS400) ||                 \
1668                 (rdev->family == CHIP_RS480))
1669 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1670                 (rdev->ddev->pdev->device == 0x9443) || \
1671                 (rdev->ddev->pdev->device == 0x944B) || \
1672                 (rdev->ddev->pdev->device == 0x9506) || \
1673                 (rdev->ddev->pdev->device == 0x9509) || \
1674                 (rdev->ddev->pdev->device == 0x950F) || \
1675                 (rdev->ddev->pdev->device == 0x689C) || \
1676                 (rdev->ddev->pdev->device == 0x689D))
1677 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1678 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1679                             (rdev->family == CHIP_RS690)  ||    \
1680                             (rdev->family == CHIP_RS740)  ||    \
1681                             (rdev->family >= CHIP_R600))
1682 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1683 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1684 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1685 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1686                              (rdev->flags & RADEON_IS_IGP))
1687 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1688 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1689 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1690                              (rdev->flags & RADEON_IS_IGP))
1691
1692 /*
1693  * BIOS helpers.
1694  */
1695 #define RBIOS8(i) (rdev->bios[i])
1696 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1697 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1698
1699 int radeon_combios_init(struct radeon_device *rdev);
1700 void radeon_combios_fini(struct radeon_device *rdev);
1701 int radeon_atombios_init(struct radeon_device *rdev);
1702 void radeon_atombios_fini(struct radeon_device *rdev);
1703
1704
1705 /*
1706  * RING helpers.
1707  */
1708 #if DRM_DEBUG_CODE == 0
1709 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1710 {
1711         ring->ring[ring->wptr++] = v;
1712         ring->wptr &= ring->ptr_mask;
1713         ring->count_dw--;
1714         ring->ring_free_dw--;
1715 }
1716 #else
1717 /* With debugging this is just too big to inline */
1718 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1719 #endif
1720
1721 /*
1722  * ASICs macro.
1723  */
1724 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1725 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1726 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1727 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1728 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1729 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1730 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1731 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1732 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1733 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1734 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1735 #define radeon_asic_vm_bind(rdev, v, id) (rdev)->asic->vm.bind((rdev), (v), (id))
1736 #define radeon_asic_vm_tlb_flush(rdev, v) (rdev)->asic->vm.tlb_flush((rdev), (v))
1737 #define radeon_asic_vm_page_flags(rdev, v, flags) (rdev)->asic->vm.page_flags((rdev), (v), (flags))
1738 #define radeon_asic_vm_set_page(rdev, v, pfn, addr, flags) (rdev)->asic->vm.set_page((rdev), (v), (pfn), (addr), (flags))
1739 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1740 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1741 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1742 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1743 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1744 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1745 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1746 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1747 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1748 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1749 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1750 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1751 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1752 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1753 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1754 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1755 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1756 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1757 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1758 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1759 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1760 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1761 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1762 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1763 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1764 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1765 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1766 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1767 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1768 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1769 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1770 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1771 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1772 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1773 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1774 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1775 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1776 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1777 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1778 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1779 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1780 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1781 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1782
1783 /* Common functions */
1784 /* AGP */
1785 extern int radeon_gpu_reset(struct radeon_device *rdev);
1786 extern void radeon_agp_disable(struct radeon_device *rdev);
1787 extern int radeon_modeset_init(struct radeon_device *rdev);
1788 extern void radeon_modeset_fini(struct radeon_device *rdev);
1789 extern bool radeon_card_posted(struct radeon_device *rdev);
1790 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1791 extern void radeon_update_display_priority(struct radeon_device *rdev);
1792 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1793 extern void radeon_scratch_init(struct radeon_device *rdev);
1794 extern void radeon_wb_fini(struct radeon_device *rdev);
1795 extern int radeon_wb_init(struct radeon_device *rdev);
1796 extern void radeon_wb_disable(struct radeon_device *rdev);
1797 extern void radeon_surface_init(struct radeon_device *rdev);
1798 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1799 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1800 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1801 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1802 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1803 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1804 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1805 extern int radeon_resume_kms(struct drm_device *dev);
1806 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1807 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1808
1809 /*
1810  * vm
1811  */
1812 int radeon_vm_manager_init(struct radeon_device *rdev);
1813 void radeon_vm_manager_fini(struct radeon_device *rdev);
1814 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1815 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1816 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1817 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1818 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1819                             struct radeon_vm *vm,
1820                             struct radeon_bo *bo,
1821                             struct ttm_mem_reg *mem);
1822 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1823                              struct radeon_bo *bo);
1824 int radeon_vm_bo_add(struct radeon_device *rdev,
1825                      struct radeon_vm *vm,
1826                      struct radeon_bo *bo,
1827                      uint64_t offset,
1828                      uint32_t flags);
1829 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1830                      struct radeon_vm *vm,
1831                      struct radeon_bo *bo);
1832
1833 /* audio */
1834 void r600_audio_update_hdmi(struct work_struct *work);
1835
1836 /*
1837  * R600 vram scratch functions
1838  */
1839 int r600_vram_scratch_init(struct radeon_device *rdev);
1840 void r600_vram_scratch_fini(struct radeon_device *rdev);
1841
1842 /*
1843  * r600 cs checking helper
1844  */
1845 unsigned r600_mip_minify(unsigned size, unsigned level);
1846 bool r600_fmt_is_valid_color(u32 format);
1847 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1848 int r600_fmt_get_blocksize(u32 format);
1849 int r600_fmt_get_nblocksx(u32 format, u32 w);
1850 int r600_fmt_get_nblocksy(u32 format, u32 h);
1851
1852 /*
1853  * r600 functions used by radeon_encoder.c
1854  */
1855 struct radeon_hdmi_acr {
1856         u32 clock;
1857
1858         int n_32khz;
1859         int cts_32khz;
1860
1861         int n_44_1khz;
1862         int cts_44_1khz;
1863
1864         int n_48khz;
1865         int cts_48khz;
1866
1867 };
1868
1869 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1870
1871 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1872 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1873 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1874 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1875                                      u32 tiling_pipe_num,
1876                                      u32 max_rb_num,
1877                                      u32 total_max_rb_num,
1878                                      u32 enabled_rb_mask);
1879
1880 /*
1881  * evergreen functions used by radeon_encoder.c
1882  */
1883
1884 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1885
1886 extern int ni_init_microcode(struct radeon_device *rdev);
1887 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1888
1889 /* radeon_acpi.c */
1890 #if defined(CONFIG_ACPI)
1891 extern int radeon_acpi_init(struct radeon_device *rdev);
1892 extern void radeon_acpi_fini(struct radeon_device *rdev);
1893 #else
1894 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1895 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1896 #endif
1897
1898 #include "radeon_object.h"
1899
1900 #endif