2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb
;
81 extern int radeon_modeset
;
82 extern int radeon_dynclks
;
83 extern int radeon_r4xx_atom
;
84 extern int radeon_agpmode
;
85 extern int radeon_vram_limit
;
86 extern int radeon_gart_size
;
87 extern int radeon_benchmarking
;
88 extern int radeon_testing
;
89 extern int radeon_connector_table
;
91 extern int radeon_new_pll
;
92 extern int radeon_audio
;
95 * Copy from radeon_drv.h so we don't have to include both and have conflicting
98 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
99 #define RADEON_IB_POOL_SIZE 16
100 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
101 #define RADEONFB_CONN_LIMIT 4
102 #define RADEON_BIOS_NUM_SCRATCH 8
105 * Errata workarounds.
107 enum radeon_pll_errata
{
108 CHIP_ERRATA_R300_CG
= 0x00000001,
109 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
110 CHIP_ERRATA_PLL_DELAY
= 0x00000004
114 struct radeon_device
;
120 bool radeon_get_bios(struct radeon_device
*rdev
);
126 struct radeon_dummy_page
{
130 int radeon_dummy_page_init(struct radeon_device
*rdev
);
131 void radeon_dummy_page_fini(struct radeon_device
*rdev
);
137 struct radeon_clock
{
138 struct radeon_pll p1pll
;
139 struct radeon_pll p2pll
;
140 struct radeon_pll spll
;
141 struct radeon_pll mpll
;
143 uint32_t default_mclk
;
144 uint32_t default_sclk
;
150 int radeon_pm_init(struct radeon_device
*rdev
);
155 struct radeon_fence_driver
{
156 uint32_t scratch_reg
;
159 unsigned long count_timeout
;
160 wait_queue_head_t queue
;
162 struct list_head created
;
163 struct list_head emited
;
164 struct list_head signaled
;
168 struct radeon_fence
{
169 struct radeon_device
*rdev
;
171 struct list_head list
;
172 /* protected by radeon_fence.lock */
174 unsigned long timeout
;
179 int radeon_fence_driver_init(struct radeon_device
*rdev
);
180 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
181 int radeon_fence_create(struct radeon_device
*rdev
, struct radeon_fence
**fence
);
182 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
183 void radeon_fence_process(struct radeon_device
*rdev
);
184 bool radeon_fence_signaled(struct radeon_fence
*fence
);
185 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
186 int radeon_fence_wait_next(struct radeon_device
*rdev
);
187 int radeon_fence_wait_last(struct radeon_device
*rdev
);
188 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
189 void radeon_fence_unref(struct radeon_fence
**fence
);
194 struct radeon_surface_reg
{
195 struct radeon_bo
*bo
;
198 #define RADEON_GEM_MAX_SURFACES 8
204 struct ttm_bo_global_ref bo_global_ref
;
205 struct ttm_global_reference mem_global_ref
;
206 struct ttm_bo_device bdev
;
207 bool mem_global_referenced
;
212 /* Protected by gem.mutex */
213 struct list_head list
;
214 /* Protected by tbo.reserved */
216 struct ttm_placement placement
;
217 struct ttm_buffer_object tbo
;
218 struct ttm_bo_kmap_obj kmap
;
224 /* Constant after initialization */
225 struct radeon_device
*rdev
;
226 struct drm_gem_object
*gobj
;
229 struct radeon_bo_list
{
230 struct list_head list
;
231 struct radeon_bo
*bo
;
243 struct list_head objects
;
246 int radeon_gem_init(struct radeon_device
*rdev
);
247 void radeon_gem_fini(struct radeon_device
*rdev
);
248 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
249 int alignment
, int initial_domain
,
250 bool discardable
, bool kernel
,
251 struct drm_gem_object
**obj
);
252 int radeon_gem_object_pin(struct drm_gem_object
*obj
, uint32_t pin_domain
,
254 void radeon_gem_object_unpin(struct drm_gem_object
*obj
);
258 * GART structures, functions & helpers
262 struct radeon_gart_table_ram
{
263 volatile uint32_t *ptr
;
266 struct radeon_gart_table_vram
{
267 struct radeon_bo
*robj
;
268 volatile uint32_t *ptr
;
271 union radeon_gart_table
{
272 struct radeon_gart_table_ram ram
;
273 struct radeon_gart_table_vram vram
;
276 #define RADEON_GPU_PAGE_SIZE 4096
279 dma_addr_t table_addr
;
280 unsigned num_gpu_pages
;
281 unsigned num_cpu_pages
;
283 union radeon_gart_table table
;
285 dma_addr_t
*pages_addr
;
289 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
290 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
291 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
292 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
293 int radeon_gart_init(struct radeon_device
*rdev
);
294 void radeon_gart_fini(struct radeon_device
*rdev
);
295 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
297 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
298 int pages
, struct page
**pagelist
);
302 * GPU MC structures, functions & helpers
305 resource_size_t aper_size
;
306 resource_size_t aper_base
;
307 resource_size_t agp_base
;
308 /* for some chips with <= 32MB we need to lie
309 * about vram size near mc fb location */
322 bool igp_sideport_enabled
;
325 int radeon_mc_setup(struct radeon_device
*rdev
);
326 bool radeon_combios_sideport_present(struct radeon_device
*rdev
);
327 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
);
330 * GPU scratch registers structures, functions & helpers
332 struct radeon_scratch
{
338 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
339 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
348 /* FIXME: use a define max crtc rather than hardcode it */
349 bool crtc_vblank_int
[2];
350 /* FIXME: use defines for max hpd/dacs */
356 int radeon_irq_kms_init(struct radeon_device
*rdev
);
357 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
358 void radeon_irq_kms_sw_irq_get(struct radeon_device
*rdev
);
359 void radeon_irq_kms_sw_irq_put(struct radeon_device
*rdev
);
365 struct list_head list
;
368 struct radeon_fence
*fence
;
375 * mutex protects scheduled_ibs, ready, alloc_bm
377 struct radeon_ib_pool
{
379 struct radeon_bo
*robj
;
380 struct list_head scheduled_ibs
;
381 struct radeon_ib ibs
[RADEON_IB_POOL_SIZE
];
383 DECLARE_BITMAP(alloc_bm
, RADEON_IB_POOL_SIZE
);
387 struct radeon_bo
*ring_obj
;
388 volatile uint32_t *ring
;
393 unsigned ring_free_dw
;
406 struct radeon_bo
*ring_obj
;
407 volatile uint32_t *ring
;
420 struct radeon_bo
*shader_obj
;
422 u32 vs_offset
, ps_offset
;
425 u32 vb_used
, vb_total
;
426 struct radeon_ib
*vb_ib
;
429 int radeon_ib_get(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
430 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
431 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
432 int radeon_ib_pool_init(struct radeon_device
*rdev
);
433 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
434 int radeon_ib_test(struct radeon_device
*rdev
);
435 /* Ring access between begin & end cannot sleep */
436 void radeon_ring_free_size(struct radeon_device
*rdev
);
437 int radeon_ring_lock(struct radeon_device
*rdev
, unsigned ndw
);
438 void radeon_ring_unlock_commit(struct radeon_device
*rdev
);
439 void radeon_ring_unlock_undo(struct radeon_device
*rdev
);
440 int radeon_ring_test(struct radeon_device
*rdev
);
441 int radeon_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
442 void radeon_ring_fini(struct radeon_device
*rdev
);
448 struct radeon_cs_reloc
{
449 struct drm_gem_object
*gobj
;
450 struct radeon_bo
*robj
;
451 struct radeon_bo_list lobj
;
456 struct radeon_cs_chunk
{
462 void __user
*user_ptr
;
463 int last_copied_page
;
467 struct radeon_cs_parser
{
469 struct radeon_device
*rdev
;
470 struct drm_file
*filp
;
473 struct radeon_cs_chunk
*chunks
;
474 uint64_t *chunks_array
;
479 struct radeon_cs_reloc
*relocs
;
480 struct radeon_cs_reloc
**relocs_ptr
;
481 struct list_head validated
;
482 /* indices of various chunks */
484 int chunk_relocs_idx
;
485 struct radeon_ib
*ib
;
491 extern int radeon_cs_update_pages(struct radeon_cs_parser
*p
, int pg_idx
);
492 extern int radeon_cs_finish_pages(struct radeon_cs_parser
*p
);
495 static inline u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
)
497 struct radeon_cs_chunk
*ibc
= &p
->chunks
[p
->chunk_ib_idx
];
498 u32 pg_idx
, pg_offset
;
502 pg_idx
= (idx
* 4) / PAGE_SIZE
;
503 pg_offset
= (idx
* 4) % PAGE_SIZE
;
505 if (ibc
->kpage_idx
[0] == pg_idx
)
506 return ibc
->kpage
[0][pg_offset
/4];
507 if (ibc
->kpage_idx
[1] == pg_idx
)
508 return ibc
->kpage
[1][pg_offset
/4];
510 new_page
= radeon_cs_update_pages(p
, pg_idx
);
512 p
->parser_error
= new_page
;
516 idx_value
= ibc
->kpage
[new_page
][pg_offset
/4];
520 struct radeon_cs_packet
{
529 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
530 struct radeon_cs_packet
*pkt
,
531 unsigned idx
, unsigned reg
);
532 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
533 struct radeon_cs_packet
*pkt
);
539 int radeon_agp_init(struct radeon_device
*rdev
);
540 void radeon_agp_resume(struct radeon_device
*rdev
);
541 void radeon_agp_fini(struct radeon_device
*rdev
);
548 struct radeon_bo
*wb_obj
;
549 volatile uint32_t *wb
;
554 * struct radeon_pm - power management datas
555 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
556 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
557 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
558 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
560 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
561 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
562 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
563 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
564 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
565 * @needed_bandwidth: current bandwidth needs
567 * It keeps track of various data needed to take powermanagement decision.
568 * Bandwith need is used to determine minimun clock of the GPU and memory.
569 * Equation between gpu/memory clock and available bandwidth is hw dependent
570 * (type of memory, bus size, efficiency, ...)
573 fixed20_12 max_bandwidth
;
574 fixed20_12 igp_sideport_mclk
;
575 fixed20_12 igp_system_mclk
;
576 fixed20_12 igp_ht_link_clk
;
577 fixed20_12 igp_ht_link_width
;
578 fixed20_12 k8_bandwidth
;
579 fixed20_12 sideport_bandwidth
;
580 fixed20_12 ht_bandwidth
;
581 fixed20_12 core_bandwidth
;
583 fixed20_12 needed_bandwidth
;
590 void radeon_benchmark(struct radeon_device
*rdev
);
596 void radeon_test_moves(struct radeon_device
*rdev
);
602 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
603 struct drm_info_list
*files
,
605 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
606 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
);
607 int r100_debugfs_cp_init(struct radeon_device
*rdev
);
611 * ASIC specific functions.
614 int (*init
)(struct radeon_device
*rdev
);
615 void (*fini
)(struct radeon_device
*rdev
);
616 int (*resume
)(struct radeon_device
*rdev
);
617 int (*suspend
)(struct radeon_device
*rdev
);
618 void (*vga_set_state
)(struct radeon_device
*rdev
, bool state
);
619 int (*gpu_reset
)(struct radeon_device
*rdev
);
620 void (*gart_tlb_flush
)(struct radeon_device
*rdev
);
621 int (*gart_set_page
)(struct radeon_device
*rdev
, int i
, uint64_t addr
);
622 int (*cp_init
)(struct radeon_device
*rdev
, unsigned ring_size
);
623 void (*cp_fini
)(struct radeon_device
*rdev
);
624 void (*cp_disable
)(struct radeon_device
*rdev
);
625 void (*cp_commit
)(struct radeon_device
*rdev
);
626 void (*ring_start
)(struct radeon_device
*rdev
);
627 int (*ring_test
)(struct radeon_device
*rdev
);
628 void (*ring_ib_execute
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
629 int (*irq_set
)(struct radeon_device
*rdev
);
630 int (*irq_process
)(struct radeon_device
*rdev
);
631 u32 (*get_vblank_counter
)(struct radeon_device
*rdev
, int crtc
);
632 void (*fence_ring_emit
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
633 int (*cs_parse
)(struct radeon_cs_parser
*p
);
634 int (*copy_blit
)(struct radeon_device
*rdev
,
638 struct radeon_fence
*fence
);
639 int (*copy_dma
)(struct radeon_device
*rdev
,
643 struct radeon_fence
*fence
);
644 int (*copy
)(struct radeon_device
*rdev
,
648 struct radeon_fence
*fence
);
649 uint32_t (*get_engine_clock
)(struct radeon_device
*rdev
);
650 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
651 uint32_t (*get_memory_clock
)(struct radeon_device
*rdev
);
652 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
653 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
654 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
655 int (*set_surface_reg
)(struct radeon_device
*rdev
, int reg
,
656 uint32_t tiling_flags
, uint32_t pitch
,
657 uint32_t offset
, uint32_t obj_size
);
658 int (*clear_surface_reg
)(struct radeon_device
*rdev
, int reg
);
659 void (*bandwidth_update
)(struct radeon_device
*rdev
);
660 void (*hpd_init
)(struct radeon_device
*rdev
);
661 void (*hpd_fini
)(struct radeon_device
*rdev
);
662 bool (*hpd_sense
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
663 void (*hpd_set_polarity
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
664 /* ioctl hw specific callback. Some hw might want to perform special
665 * operation on specific ioctl. For instance on wait idle some hw
666 * might want to perform and HDP flush through MMIO as it seems that
667 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
670 void (*ioctl_wait_idle
)(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
677 const unsigned *reg_safe_bm
;
678 unsigned reg_safe_bm_size
;
683 const unsigned *reg_safe_bm
;
684 unsigned reg_safe_bm_size
;
691 unsigned max_tile_pipes
;
693 unsigned max_backends
;
695 unsigned max_threads
;
696 unsigned max_stack_entries
;
697 unsigned max_hw_contexts
;
698 unsigned max_gs_threads
;
699 unsigned sx_max_export_size
;
700 unsigned sx_max_export_pos_size
;
701 unsigned sx_max_export_smx_size
;
702 unsigned sq_num_cf_insts
;
707 unsigned max_tile_pipes
;
709 unsigned max_backends
;
711 unsigned max_threads
;
712 unsigned max_stack_entries
;
713 unsigned max_hw_contexts
;
714 unsigned max_gs_threads
;
715 unsigned sx_max_export_size
;
716 unsigned sx_max_export_pos_size
;
717 unsigned sx_max_export_smx_size
;
718 unsigned sq_num_cf_insts
;
719 unsigned sx_num_of_sets
;
720 unsigned sc_prim_fifo_size
;
721 unsigned sc_hiz_tile_fifo_size
;
722 unsigned sc_earlyz_tile_fifo_fize
;
725 union radeon_asic_config
{
726 struct r300_asic r300
;
727 struct r100_asic r100
;
728 struct r600_asic r600
;
729 struct rv770_asic rv770
;
736 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
737 struct drm_file
*filp
);
738 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
739 struct drm_file
*filp
);
740 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
741 struct drm_file
*file_priv
);
742 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
743 struct drm_file
*file_priv
);
744 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
745 struct drm_file
*file_priv
);
746 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
747 struct drm_file
*file_priv
);
748 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
749 struct drm_file
*filp
);
750 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
751 struct drm_file
*filp
);
752 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
753 struct drm_file
*filp
);
754 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
755 struct drm_file
*filp
);
756 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
757 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
758 struct drm_file
*filp
);
759 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
760 struct drm_file
*filp
);
764 * Core structure, functions and helpers.
766 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
767 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
769 struct radeon_device
{
771 struct drm_device
*ddev
;
772 struct pci_dev
*pdev
;
774 union radeon_asic_config config
;
775 enum radeon_family family
;
778 enum radeon_pll_errata pll_errata
;
785 uint16_t bios_header_start
;
786 struct radeon_bo
*stollen_vga_memory
;
787 struct fb_info
*fbdev_info
;
788 struct radeon_bo
*fbdev_rbo
;
789 struct radeon_framebuffer
*fbdev_rfb
;
791 resource_size_t rmmio_base
;
792 resource_size_t rmmio_size
;
794 radeon_rreg_t mc_rreg
;
795 radeon_wreg_t mc_wreg
;
796 radeon_rreg_t pll_rreg
;
797 radeon_wreg_t pll_wreg
;
798 uint32_t pcie_reg_mask
;
799 radeon_rreg_t pciep_rreg
;
800 radeon_wreg_t pciep_wreg
;
801 struct radeon_clock clock
;
803 struct radeon_gart gart
;
804 struct radeon_mode_info mode_info
;
805 struct radeon_scratch scratch
;
806 struct radeon_mman mman
;
807 struct radeon_fence_driver fence_drv
;
809 struct radeon_ib_pool ib_pool
;
810 struct radeon_irq irq
;
811 struct radeon_asic
*asic
;
812 struct radeon_gem gem
;
814 uint32_t bios_scratch
[RADEON_BIOS_NUM_SCRATCH
];
815 struct mutex cs_mutex
;
817 struct radeon_dummy_page dummy_page
;
823 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
824 const struct firmware
*me_fw
; /* all family ME firmware */
825 const struct firmware
*pfp_fw
; /* r6/700 PFP firmware */
826 const struct firmware
*rlc_fw
; /* r6/700 RLC firmware */
827 struct r600_blit r600_blit
;
828 int msi_enabled
; /* msi enabled */
829 struct r600_ih ih
; /* r6/700 interrupt ring */
830 struct workqueue_struct
*wq
;
831 struct work_struct hotplug_work
;
832 int num_crtc
; /* number of crtcs */
833 struct mutex dc_hw_i2c_mutex
; /* display controller hw i2c mutex */
836 struct timer_list audio_timer
;
839 int audio_bits_per_sample
;
840 uint8_t audio_status_bits
;
841 uint8_t audio_category_code
;
844 int radeon_device_init(struct radeon_device
*rdev
,
845 struct drm_device
*ddev
,
846 struct pci_dev
*pdev
,
848 void radeon_device_fini(struct radeon_device
*rdev
);
849 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
852 int r600_blit_prepare_copy(struct radeon_device
*rdev
, int size_bytes
);
853 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
854 void r600_kms_blit_copy(struct radeon_device
*rdev
,
855 u64 src_gpu_addr
, u64 dst_gpu_addr
,
858 static inline uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
)
860 if (reg
< rdev
->rmmio_size
)
861 return readl(((void __iomem
*)rdev
->rmmio
) + reg
);
863 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
864 return readl(((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
868 static inline void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
870 if (reg
< rdev
->rmmio_size
)
871 writel(v
, ((void __iomem
*)rdev
->rmmio
) + reg
);
873 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
874 writel(v
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
881 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
884 * Registers read & write functions.
886 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
887 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
888 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
889 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
890 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
891 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
892 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
893 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
894 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
895 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
896 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
897 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
898 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
899 #define WREG32_P(reg, val, mask) \
901 uint32_t tmp_ = RREG32(reg); \
903 tmp_ |= ((val) & ~(mask)); \
906 #define WREG32_PLL_P(reg, val, mask) \
908 uint32_t tmp_ = RREG32_PLL(reg); \
910 tmp_ |= ((val) & ~(mask)); \
911 WREG32_PLL(reg, tmp_); \
913 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
916 * Indirect registers accessor
918 static inline uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
)
922 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
923 r
= RREG32(RADEON_PCIE_DATA
);
927 static inline void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
929 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
930 WREG32(RADEON_PCIE_DATA
, (v
));
933 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
939 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
940 (rdev->pdev->device == 0x5969))
941 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
942 (rdev->family == CHIP_RV200) || \
943 (rdev->family == CHIP_RS100) || \
944 (rdev->family == CHIP_RS200) || \
945 (rdev->family == CHIP_RV250) || \
946 (rdev->family == CHIP_RV280) || \
947 (rdev->family == CHIP_RS300))
948 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
949 (rdev->family == CHIP_RV350) || \
950 (rdev->family == CHIP_R350) || \
951 (rdev->family == CHIP_RV380) || \
952 (rdev->family == CHIP_R420) || \
953 (rdev->family == CHIP_R423) || \
954 (rdev->family == CHIP_RV410) || \
955 (rdev->family == CHIP_RS400) || \
956 (rdev->family == CHIP_RS480))
957 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
958 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
959 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
965 #define RBIOS8(i) (rdev->bios[i])
966 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
967 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
969 int radeon_combios_init(struct radeon_device
*rdev
);
970 void radeon_combios_fini(struct radeon_device
*rdev
);
971 int radeon_atombios_init(struct radeon_device
*rdev
);
972 void radeon_atombios_fini(struct radeon_device
*rdev
);
978 static inline void radeon_ring_write(struct radeon_device
*rdev
, uint32_t v
)
981 if (rdev
->cp
.count_dw
<= 0) {
982 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
985 rdev
->cp
.ring
[rdev
->cp
.wptr
++] = v
;
986 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
988 rdev
->cp
.ring_free_dw
--;
995 #define radeon_init(rdev) (rdev)->asic->init((rdev))
996 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
997 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
998 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
999 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1000 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1001 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1002 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1003 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1004 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1005 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1006 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1007 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1008 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1009 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1010 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1011 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1012 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1013 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1014 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1015 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1016 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1017 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1018 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1019 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1020 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1021 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1022 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1023 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1024 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1025 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1026 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1027 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1029 /* Common functions */
1031 extern void radeon_agp_disable(struct radeon_device
*rdev
);
1032 extern int radeon_gart_table_vram_pin(struct radeon_device
*rdev
);
1033 extern int radeon_modeset_init(struct radeon_device
*rdev
);
1034 extern void radeon_modeset_fini(struct radeon_device
*rdev
);
1035 extern bool radeon_card_posted(struct radeon_device
*rdev
);
1036 extern bool radeon_boot_test_post_card(struct radeon_device
*rdev
);
1037 extern int radeon_clocks_init(struct radeon_device
*rdev
);
1038 extern void radeon_clocks_fini(struct radeon_device
*rdev
);
1039 extern void radeon_scratch_init(struct radeon_device
*rdev
);
1040 extern void radeon_surface_init(struct radeon_device
*rdev
);
1041 extern int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
);
1042 extern void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1043 extern void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1044 extern void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
);
1045 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
);
1047 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1048 struct r100_mc_save
{
1056 extern void r100_cp_disable(struct radeon_device
*rdev
);
1057 extern int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
1058 extern void r100_cp_fini(struct radeon_device
*rdev
);
1059 extern void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
1060 extern int r100_pci_gart_init(struct radeon_device
*rdev
);
1061 extern void r100_pci_gart_fini(struct radeon_device
*rdev
);
1062 extern int r100_pci_gart_enable(struct radeon_device
*rdev
);
1063 extern void r100_pci_gart_disable(struct radeon_device
*rdev
);
1064 extern int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
1065 extern int r100_debugfs_mc_info_init(struct radeon_device
*rdev
);
1066 extern int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
1067 extern void r100_ib_fini(struct radeon_device
*rdev
);
1068 extern int r100_ib_init(struct radeon_device
*rdev
);
1069 extern void r100_irq_disable(struct radeon_device
*rdev
);
1070 extern int r100_irq_set(struct radeon_device
*rdev
);
1071 extern void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
1072 extern void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
1073 extern void r100_vram_init_sizes(struct radeon_device
*rdev
);
1074 extern void r100_wb_disable(struct radeon_device
*rdev
);
1075 extern void r100_wb_fini(struct radeon_device
*rdev
);
1076 extern int r100_wb_init(struct radeon_device
*rdev
);
1077 extern void r100_hdp_reset(struct radeon_device
*rdev
);
1078 extern int r100_rb2d_reset(struct radeon_device
*rdev
);
1079 extern int r100_cp_reset(struct radeon_device
*rdev
);
1080 extern void r100_vga_render_disable(struct radeon_device
*rdev
);
1081 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1082 struct radeon_cs_packet
*pkt
,
1083 struct radeon_bo
*robj
);
1084 extern int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
1085 struct radeon_cs_packet
*pkt
,
1086 const unsigned *auth
, unsigned n
,
1087 radeon_packet0_check_t check
);
1088 extern int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
1089 struct radeon_cs_packet
*pkt
,
1091 extern void r100_enable_bm(struct radeon_device
*rdev
);
1092 extern void r100_set_common_regs(struct radeon_device
*rdev
);
1094 /* rv200,rv250,rv280 */
1095 extern void r200_set_safe_registers(struct radeon_device
*rdev
);
1097 /* r300,r350,rv350,rv370,rv380 */
1098 extern void r300_set_reg_safe(struct radeon_device
*rdev
);
1099 extern void r300_mc_program(struct radeon_device
*rdev
);
1100 extern void r300_vram_info(struct radeon_device
*rdev
);
1101 extern void r300_clock_startup(struct radeon_device
*rdev
);
1102 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
1103 extern int rv370_pcie_gart_init(struct radeon_device
*rdev
);
1104 extern void rv370_pcie_gart_fini(struct radeon_device
*rdev
);
1105 extern int rv370_pcie_gart_enable(struct radeon_device
*rdev
);
1106 extern void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
1108 /* r420,r423,rv410 */
1109 extern int r420_mc_init(struct radeon_device
*rdev
);
1110 extern u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
);
1111 extern void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
1112 extern int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
);
1113 extern void r420_pipes_init(struct radeon_device
*rdev
);
1116 struct rv515_mc_save
{
1119 u32 vga_render_control
;
1120 u32 vga_hdp_control
;
1124 extern void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
);
1125 extern void rv515_vga_render_disable(struct radeon_device
*rdev
);
1126 extern void rv515_set_safe_registers(struct radeon_device
*rdev
);
1127 extern void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1128 extern void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1129 extern void rv515_clock_startup(struct radeon_device
*rdev
);
1130 extern void rv515_debugfs(struct radeon_device
*rdev
);
1131 extern int rv515_suspend(struct radeon_device
*rdev
);
1134 extern int rs400_gart_init(struct radeon_device
*rdev
);
1135 extern int rs400_gart_enable(struct radeon_device
*rdev
);
1136 extern void rs400_gart_adjust_size(struct radeon_device
*rdev
);
1137 extern void rs400_gart_disable(struct radeon_device
*rdev
);
1138 extern void rs400_gart_fini(struct radeon_device
*rdev
);
1141 extern void rs600_set_safe_registers(struct radeon_device
*rdev
);
1142 extern int rs600_irq_set(struct radeon_device
*rdev
);
1143 extern void rs600_irq_disable(struct radeon_device
*rdev
);
1146 extern void rs690_line_buffer_adjust(struct radeon_device
*rdev
,
1147 struct drm_display_mode
*mode1
,
1148 struct drm_display_mode
*mode2
);
1150 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1151 extern bool r600_card_posted(struct radeon_device
*rdev
);
1152 extern void r600_cp_stop(struct radeon_device
*rdev
);
1153 extern void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1154 extern int r600_cp_resume(struct radeon_device
*rdev
);
1155 extern void r600_cp_fini(struct radeon_device
*rdev
);
1156 extern int r600_count_pipe_bits(uint32_t val
);
1157 extern int r600_gart_clear_page(struct radeon_device
*rdev
, int i
);
1158 extern int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
1159 extern int r600_pcie_gart_init(struct radeon_device
*rdev
);
1160 extern void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
1161 extern int r600_ib_test(struct radeon_device
*rdev
);
1162 extern int r600_ring_test(struct radeon_device
*rdev
);
1163 extern void r600_wb_fini(struct radeon_device
*rdev
);
1164 extern int r600_wb_enable(struct radeon_device
*rdev
);
1165 extern void r600_wb_disable(struct radeon_device
*rdev
);
1166 extern void r600_scratch_init(struct radeon_device
*rdev
);
1167 extern int r600_blit_init(struct radeon_device
*rdev
);
1168 extern void r600_blit_fini(struct radeon_device
*rdev
);
1169 extern int r600_init_microcode(struct radeon_device
*rdev
);
1170 extern int r600_gpu_reset(struct radeon_device
*rdev
);
1172 extern int r600_irq_init(struct radeon_device
*rdev
);
1173 extern void r600_irq_fini(struct radeon_device
*rdev
);
1174 extern void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1175 extern int r600_irq_set(struct radeon_device
*rdev
);
1176 extern void r600_irq_suspend(struct radeon_device
*rdev
);
1178 extern int r600_audio_init(struct radeon_device
*rdev
);
1179 extern int r600_audio_tmds_index(struct drm_encoder
*encoder
);
1180 extern void r600_audio_set_clock(struct drm_encoder
*encoder
, int clock
);
1181 extern void r600_audio_fini(struct radeon_device
*rdev
);
1182 extern void r600_hdmi_init(struct drm_encoder
*encoder
);
1183 extern void r600_hdmi_enable(struct drm_encoder
*encoder
, int enable
);
1184 extern void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
1185 extern int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
);
1186 extern void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
,
1190 uint8_t status_bits
,
1191 uint8_t category_code
);
1193 #include "radeon_object.h"