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drm/radeon/kms: add support for gui idle interrupts (v4)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
94 extern int radeon_disp_priority;
95 extern int radeon_hw_i2c;
96
97 /*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
104 #define RADEON_IB_POOL_SIZE 16
105 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
106 #define RADEONFB_CONN_LIMIT 4
107 #define RADEON_BIOS_NUM_SCRATCH 8
108
109 /*
110 * Errata workarounds.
111 */
112 enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116 };
117
118
119 struct radeon_device;
120
121
122 /*
123 * BIOS.
124 */
125 #define ATRM_BIOS_PAGE 4096
126
127 #if defined(CONFIG_VGA_SWITCHEROO)
128 bool radeon_atrm_supported(struct pci_dev *pdev);
129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130 #else
131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132 {
133 return false;
134 }
135
136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138 }
139 #endif
140 bool radeon_get_bios(struct radeon_device *rdev);
141
142
143 /*
144 * Dummy page
145 */
146 struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149 };
150 int radeon_dummy_page_init(struct radeon_device *rdev);
151 void radeon_dummy_page_fini(struct radeon_device *rdev);
152
153
154 /*
155 * Clocks
156 */
157 struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
168 };
169
170 /*
171 * Power management
172 */
173 int radeon_pm_init(struct radeon_device *rdev);
174 void radeon_pm_fini(struct radeon_device *rdev);
175 void radeon_pm_compute_clocks(struct radeon_device *rdev);
176 void radeon_combios_get_power_modes(struct radeon_device *rdev);
177 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
178
179 /*
180 * Fences.
181 */
182 struct radeon_fence_driver {
183 uint32_t scratch_reg;
184 atomic_t seq;
185 uint32_t last_seq;
186 unsigned long last_jiffies;
187 unsigned long last_timeout;
188 wait_queue_head_t queue;
189 rwlock_t lock;
190 struct list_head created;
191 struct list_head emited;
192 struct list_head signaled;
193 bool initialized;
194 };
195
196 struct radeon_fence {
197 struct radeon_device *rdev;
198 struct kref kref;
199 struct list_head list;
200 /* protected by radeon_fence.lock */
201 uint32_t seq;
202 bool emited;
203 bool signaled;
204 };
205
206 int radeon_fence_driver_init(struct radeon_device *rdev);
207 void radeon_fence_driver_fini(struct radeon_device *rdev);
208 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
209 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
210 void radeon_fence_process(struct radeon_device *rdev);
211 bool radeon_fence_signaled(struct radeon_fence *fence);
212 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
213 int radeon_fence_wait_next(struct radeon_device *rdev);
214 int radeon_fence_wait_last(struct radeon_device *rdev);
215 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
216 void radeon_fence_unref(struct radeon_fence **fence);
217
218 /*
219 * Tiling registers
220 */
221 struct radeon_surface_reg {
222 struct radeon_bo *bo;
223 };
224
225 #define RADEON_GEM_MAX_SURFACES 8
226
227 /*
228 * TTM.
229 */
230 struct radeon_mman {
231 struct ttm_bo_global_ref bo_global_ref;
232 struct ttm_global_reference mem_global_ref;
233 struct ttm_bo_device bdev;
234 bool mem_global_referenced;
235 bool initialized;
236 };
237
238 struct radeon_bo {
239 /* Protected by gem.mutex */
240 struct list_head list;
241 /* Protected by tbo.reserved */
242 u32 placements[3];
243 struct ttm_placement placement;
244 struct ttm_buffer_object tbo;
245 struct ttm_bo_kmap_obj kmap;
246 unsigned pin_count;
247 void *kptr;
248 u32 tiling_flags;
249 u32 pitch;
250 int surface_reg;
251 /* Constant after initialization */
252 struct radeon_device *rdev;
253 struct drm_gem_object *gobj;
254 };
255
256 struct radeon_bo_list {
257 struct list_head list;
258 struct radeon_bo *bo;
259 uint64_t gpu_offset;
260 unsigned rdomain;
261 unsigned wdomain;
262 u32 tiling_flags;
263 };
264
265 /*
266 * GEM objects.
267 */
268 struct radeon_gem {
269 struct mutex mutex;
270 struct list_head objects;
271 };
272
273 int radeon_gem_init(struct radeon_device *rdev);
274 void radeon_gem_fini(struct radeon_device *rdev);
275 int radeon_gem_object_create(struct radeon_device *rdev, int size,
276 int alignment, int initial_domain,
277 bool discardable, bool kernel,
278 struct drm_gem_object **obj);
279 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
280 uint64_t *gpu_addr);
281 void radeon_gem_object_unpin(struct drm_gem_object *obj);
282
283
284 /*
285 * GART structures, functions & helpers
286 */
287 struct radeon_mc;
288
289 struct radeon_gart_table_ram {
290 volatile uint32_t *ptr;
291 };
292
293 struct radeon_gart_table_vram {
294 struct radeon_bo *robj;
295 volatile uint32_t *ptr;
296 };
297
298 union radeon_gart_table {
299 struct radeon_gart_table_ram ram;
300 struct radeon_gart_table_vram vram;
301 };
302
303 #define RADEON_GPU_PAGE_SIZE 4096
304 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
305
306 struct radeon_gart {
307 dma_addr_t table_addr;
308 unsigned num_gpu_pages;
309 unsigned num_cpu_pages;
310 unsigned table_size;
311 union radeon_gart_table table;
312 struct page **pages;
313 dma_addr_t *pages_addr;
314 bool ready;
315 };
316
317 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
318 void radeon_gart_table_ram_free(struct radeon_device *rdev);
319 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
320 void radeon_gart_table_vram_free(struct radeon_device *rdev);
321 int radeon_gart_init(struct radeon_device *rdev);
322 void radeon_gart_fini(struct radeon_device *rdev);
323 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
324 int pages);
325 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
326 int pages, struct page **pagelist);
327
328
329 /*
330 * GPU MC structures, functions & helpers
331 */
332 struct radeon_mc {
333 resource_size_t aper_size;
334 resource_size_t aper_base;
335 resource_size_t agp_base;
336 /* for some chips with <= 32MB we need to lie
337 * about vram size near mc fb location */
338 u64 mc_vram_size;
339 u64 visible_vram_size;
340 u64 gtt_size;
341 u64 gtt_start;
342 u64 gtt_end;
343 u64 vram_start;
344 u64 vram_end;
345 unsigned vram_width;
346 u64 real_vram_size;
347 int vram_mtrr;
348 bool vram_is_ddr;
349 bool igp_sideport_enabled;
350 };
351
352 bool radeon_combios_sideport_present(struct radeon_device *rdev);
353 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
354
355 /*
356 * GPU scratch registers structures, functions & helpers
357 */
358 struct radeon_scratch {
359 unsigned num_reg;
360 bool free[32];
361 uint32_t reg[32];
362 };
363
364 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
365 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
366
367
368 /*
369 * IRQS.
370 */
371 struct radeon_irq {
372 bool installed;
373 bool sw_int;
374 /* FIXME: use a define max crtc rather than hardcode it */
375 bool crtc_vblank_int[6];
376 wait_queue_head_t vblank_queue;
377 /* FIXME: use defines for max hpd/dacs */
378 bool hpd[6];
379 bool gui_idle;
380 bool gui_idle_acked;
381 wait_queue_head_t idle_queue;
382 /* FIXME: use defines for max HDMI blocks */
383 bool hdmi[2];
384 spinlock_t sw_lock;
385 int sw_refcount;
386 };
387
388 int radeon_irq_kms_init(struct radeon_device *rdev);
389 void radeon_irq_kms_fini(struct radeon_device *rdev);
390 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
391 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
392
393 /*
394 * CP & ring.
395 */
396 struct radeon_ib {
397 struct list_head list;
398 unsigned idx;
399 uint64_t gpu_addr;
400 struct radeon_fence *fence;
401 uint32_t *ptr;
402 uint32_t length_dw;
403 bool free;
404 };
405
406 /*
407 * locking -
408 * mutex protects scheduled_ibs, ready, alloc_bm
409 */
410 struct radeon_ib_pool {
411 struct mutex mutex;
412 struct radeon_bo *robj;
413 struct list_head bogus_ib;
414 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
415 bool ready;
416 unsigned head_id;
417 };
418
419 struct radeon_cp {
420 struct radeon_bo *ring_obj;
421 volatile uint32_t *ring;
422 unsigned rptr;
423 unsigned wptr;
424 unsigned wptr_old;
425 unsigned ring_size;
426 unsigned ring_free_dw;
427 int count_dw;
428 uint64_t gpu_addr;
429 uint32_t align_mask;
430 uint32_t ptr_mask;
431 struct mutex mutex;
432 bool ready;
433 };
434
435 /*
436 * R6xx+ IH ring
437 */
438 struct r600_ih {
439 struct radeon_bo *ring_obj;
440 volatile uint32_t *ring;
441 unsigned rptr;
442 unsigned wptr;
443 unsigned wptr_old;
444 unsigned ring_size;
445 uint64_t gpu_addr;
446 uint32_t ptr_mask;
447 spinlock_t lock;
448 bool enabled;
449 };
450
451 struct r600_blit {
452 struct mutex mutex;
453 struct radeon_bo *shader_obj;
454 u64 shader_gpu_addr;
455 u32 vs_offset, ps_offset;
456 u32 state_offset;
457 u32 state_len;
458 u32 vb_used, vb_total;
459 struct radeon_ib *vb_ib;
460 };
461
462 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
463 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
464 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
465 int radeon_ib_pool_init(struct radeon_device *rdev);
466 void radeon_ib_pool_fini(struct radeon_device *rdev);
467 int radeon_ib_test(struct radeon_device *rdev);
468 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
469 /* Ring access between begin & end cannot sleep */
470 void radeon_ring_free_size(struct radeon_device *rdev);
471 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
472 void radeon_ring_unlock_commit(struct radeon_device *rdev);
473 void radeon_ring_unlock_undo(struct radeon_device *rdev);
474 int radeon_ring_test(struct radeon_device *rdev);
475 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
476 void radeon_ring_fini(struct radeon_device *rdev);
477
478
479 /*
480 * CS.
481 */
482 struct radeon_cs_reloc {
483 struct drm_gem_object *gobj;
484 struct radeon_bo *robj;
485 struct radeon_bo_list lobj;
486 uint32_t handle;
487 uint32_t flags;
488 };
489
490 struct radeon_cs_chunk {
491 uint32_t chunk_id;
492 uint32_t length_dw;
493 int kpage_idx[2];
494 uint32_t *kpage[2];
495 uint32_t *kdata;
496 void __user *user_ptr;
497 int last_copied_page;
498 int last_page_index;
499 };
500
501 struct radeon_cs_parser {
502 struct device *dev;
503 struct radeon_device *rdev;
504 struct drm_file *filp;
505 /* chunks */
506 unsigned nchunks;
507 struct radeon_cs_chunk *chunks;
508 uint64_t *chunks_array;
509 /* IB */
510 unsigned idx;
511 /* relocations */
512 unsigned nrelocs;
513 struct radeon_cs_reloc *relocs;
514 struct radeon_cs_reloc **relocs_ptr;
515 struct list_head validated;
516 /* indices of various chunks */
517 int chunk_ib_idx;
518 int chunk_relocs_idx;
519 struct radeon_ib *ib;
520 void *track;
521 unsigned family;
522 int parser_error;
523 };
524
525 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
526 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
527
528
529 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
530 {
531 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
532 u32 pg_idx, pg_offset;
533 u32 idx_value = 0;
534 int new_page;
535
536 pg_idx = (idx * 4) / PAGE_SIZE;
537 pg_offset = (idx * 4) % PAGE_SIZE;
538
539 if (ibc->kpage_idx[0] == pg_idx)
540 return ibc->kpage[0][pg_offset/4];
541 if (ibc->kpage_idx[1] == pg_idx)
542 return ibc->kpage[1][pg_offset/4];
543
544 new_page = radeon_cs_update_pages(p, pg_idx);
545 if (new_page < 0) {
546 p->parser_error = new_page;
547 return 0;
548 }
549
550 idx_value = ibc->kpage[new_page][pg_offset/4];
551 return idx_value;
552 }
553
554 struct radeon_cs_packet {
555 unsigned idx;
556 unsigned type;
557 unsigned reg;
558 unsigned opcode;
559 int count;
560 unsigned one_reg_wr;
561 };
562
563 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
564 struct radeon_cs_packet *pkt,
565 unsigned idx, unsigned reg);
566 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
567 struct radeon_cs_packet *pkt);
568
569
570 /*
571 * AGP
572 */
573 int radeon_agp_init(struct radeon_device *rdev);
574 void radeon_agp_resume(struct radeon_device *rdev);
575 void radeon_agp_fini(struct radeon_device *rdev);
576
577
578 /*
579 * Writeback
580 */
581 struct radeon_wb {
582 struct radeon_bo *wb_obj;
583 volatile uint32_t *wb;
584 uint64_t gpu_addr;
585 };
586
587 /**
588 * struct radeon_pm - power management datas
589 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
590 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
591 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
592 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
593 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
594 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
595 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
596 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
597 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
598 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
599 * @needed_bandwidth: current bandwidth needs
600 *
601 * It keeps track of various data needed to take powermanagement decision.
602 * Bandwith need is used to determine minimun clock of the GPU and memory.
603 * Equation between gpu/memory clock and available bandwidth is hw dependent
604 * (type of memory, bus size, efficiency, ...)
605 */
606 enum radeon_pm_state {
607 PM_STATE_DISABLED,
608 PM_STATE_MINIMUM,
609 PM_STATE_PAUSED,
610 PM_STATE_ACTIVE
611 };
612 enum radeon_pm_action {
613 PM_ACTION_NONE,
614 PM_ACTION_MINIMUM,
615 PM_ACTION_DOWNCLOCK,
616 PM_ACTION_UPCLOCK
617 };
618
619 enum radeon_voltage_type {
620 VOLTAGE_NONE = 0,
621 VOLTAGE_GPIO,
622 VOLTAGE_VDDC,
623 VOLTAGE_SW
624 };
625
626 enum radeon_pm_state_type {
627 POWER_STATE_TYPE_DEFAULT,
628 POWER_STATE_TYPE_POWERSAVE,
629 POWER_STATE_TYPE_BATTERY,
630 POWER_STATE_TYPE_BALANCED,
631 POWER_STATE_TYPE_PERFORMANCE,
632 };
633
634 enum radeon_pm_clock_mode_type {
635 POWER_MODE_TYPE_DEFAULT,
636 POWER_MODE_TYPE_LOW,
637 POWER_MODE_TYPE_MID,
638 POWER_MODE_TYPE_HIGH,
639 };
640
641 struct radeon_voltage {
642 enum radeon_voltage_type type;
643 /* gpio voltage */
644 struct radeon_gpio_rec gpio;
645 u32 delay; /* delay in usec from voltage drop to sclk change */
646 bool active_high; /* voltage drop is active when bit is high */
647 /* VDDC voltage */
648 u8 vddc_id; /* index into vddc voltage table */
649 u8 vddci_id; /* index into vddci voltage table */
650 bool vddci_enabled;
651 /* r6xx+ sw */
652 u32 voltage;
653 };
654
655 struct radeon_pm_non_clock_info {
656 /* pcie lanes */
657 int pcie_lanes;
658 /* standardized non-clock flags */
659 u32 flags;
660 };
661
662 struct radeon_pm_clock_info {
663 /* memory clock */
664 u32 mclk;
665 /* engine clock */
666 u32 sclk;
667 /* voltage info */
668 struct radeon_voltage voltage;
669 /* standardized clock flags - not sure we'll need these */
670 u32 flags;
671 };
672
673 struct radeon_power_state {
674 enum radeon_pm_state_type type;
675 /* XXX: use a define for num clock modes */
676 struct radeon_pm_clock_info clock_info[8];
677 /* number of valid clock modes in this power state */
678 int num_clock_modes;
679 struct radeon_pm_clock_info *default_clock_mode;
680 /* non clock info about this state */
681 struct radeon_pm_non_clock_info non_clock_info;
682 bool voltage_drop_active;
683 };
684
685 /*
686 * Some modes are overclocked by very low value, accept them
687 */
688 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
689
690 struct radeon_pm {
691 struct mutex mutex;
692 struct delayed_work idle_work;
693 enum radeon_pm_state state;
694 enum radeon_pm_action planned_action;
695 unsigned long action_timeout;
696 bool downclocked;
697 int active_crtcs;
698 int req_vblank;
699 bool vblank_sync;
700 bool gui_idle;
701 fixed20_12 max_bandwidth;
702 fixed20_12 igp_sideport_mclk;
703 fixed20_12 igp_system_mclk;
704 fixed20_12 igp_ht_link_clk;
705 fixed20_12 igp_ht_link_width;
706 fixed20_12 k8_bandwidth;
707 fixed20_12 sideport_bandwidth;
708 fixed20_12 ht_bandwidth;
709 fixed20_12 core_bandwidth;
710 fixed20_12 sclk;
711 fixed20_12 mclk;
712 fixed20_12 needed_bandwidth;
713 /* XXX: use a define for num power modes */
714 struct radeon_power_state power_state[8];
715 /* number of valid power states */
716 int num_power_states;
717 struct radeon_power_state *current_power_state;
718 struct radeon_pm_clock_info *current_clock_mode;
719 struct radeon_power_state *requested_power_state;
720 struct radeon_pm_clock_info *requested_clock_mode;
721 struct radeon_power_state *default_power_state;
722 struct radeon_i2c_chan *i2c_bus;
723 };
724
725
726 /*
727 * Benchmarking
728 */
729 void radeon_benchmark(struct radeon_device *rdev);
730
731
732 /*
733 * Testing
734 */
735 void radeon_test_moves(struct radeon_device *rdev);
736
737
738 /*
739 * Debugfs
740 */
741 int radeon_debugfs_add_files(struct radeon_device *rdev,
742 struct drm_info_list *files,
743 unsigned nfiles);
744 int radeon_debugfs_fence_init(struct radeon_device *rdev);
745
746
747 /*
748 * ASIC specific functions.
749 */
750 struct radeon_asic {
751 int (*init)(struct radeon_device *rdev);
752 void (*fini)(struct radeon_device *rdev);
753 int (*resume)(struct radeon_device *rdev);
754 int (*suspend)(struct radeon_device *rdev);
755 void (*vga_set_state)(struct radeon_device *rdev, bool state);
756 bool (*gpu_is_lockup)(struct radeon_device *rdev);
757 int (*asic_reset)(struct radeon_device *rdev);
758 void (*gart_tlb_flush)(struct radeon_device *rdev);
759 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
760 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
761 void (*cp_fini)(struct radeon_device *rdev);
762 void (*cp_disable)(struct radeon_device *rdev);
763 void (*cp_commit)(struct radeon_device *rdev);
764 void (*ring_start)(struct radeon_device *rdev);
765 int (*ring_test)(struct radeon_device *rdev);
766 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
767 int (*irq_set)(struct radeon_device *rdev);
768 int (*irq_process)(struct radeon_device *rdev);
769 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
770 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
771 int (*cs_parse)(struct radeon_cs_parser *p);
772 int (*copy_blit)(struct radeon_device *rdev,
773 uint64_t src_offset,
774 uint64_t dst_offset,
775 unsigned num_pages,
776 struct radeon_fence *fence);
777 int (*copy_dma)(struct radeon_device *rdev,
778 uint64_t src_offset,
779 uint64_t dst_offset,
780 unsigned num_pages,
781 struct radeon_fence *fence);
782 int (*copy)(struct radeon_device *rdev,
783 uint64_t src_offset,
784 uint64_t dst_offset,
785 unsigned num_pages,
786 struct radeon_fence *fence);
787 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
788 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
789 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
790 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
791 int (*get_pcie_lanes)(struct radeon_device *rdev);
792 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
793 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
794 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
795 uint32_t tiling_flags, uint32_t pitch,
796 uint32_t offset, uint32_t obj_size);
797 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
798 void (*bandwidth_update)(struct radeon_device *rdev);
799 void (*hpd_init)(struct radeon_device *rdev);
800 void (*hpd_fini)(struct radeon_device *rdev);
801 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
802 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
803 /* ioctl hw specific callback. Some hw might want to perform special
804 * operation on specific ioctl. For instance on wait idle some hw
805 * might want to perform and HDP flush through MMIO as it seems that
806 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
807 * through ring.
808 */
809 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
810 bool (*gui_idle)(struct radeon_device *rdev);
811 };
812
813 /*
814 * Asic structures
815 */
816 struct r100_gpu_lockup {
817 unsigned long last_jiffies;
818 u32 last_cp_rptr;
819 };
820
821 struct r100_asic {
822 const unsigned *reg_safe_bm;
823 unsigned reg_safe_bm_size;
824 u32 hdp_cntl;
825 struct r100_gpu_lockup lockup;
826 };
827
828 struct r300_asic {
829 const unsigned *reg_safe_bm;
830 unsigned reg_safe_bm_size;
831 u32 resync_scratch;
832 u32 hdp_cntl;
833 struct r100_gpu_lockup lockup;
834 };
835
836 struct r600_asic {
837 unsigned max_pipes;
838 unsigned max_tile_pipes;
839 unsigned max_simds;
840 unsigned max_backends;
841 unsigned max_gprs;
842 unsigned max_threads;
843 unsigned max_stack_entries;
844 unsigned max_hw_contexts;
845 unsigned max_gs_threads;
846 unsigned sx_max_export_size;
847 unsigned sx_max_export_pos_size;
848 unsigned sx_max_export_smx_size;
849 unsigned sq_num_cf_insts;
850 unsigned tiling_nbanks;
851 unsigned tiling_npipes;
852 unsigned tiling_group_size;
853 struct r100_gpu_lockup lockup;
854 };
855
856 struct rv770_asic {
857 unsigned max_pipes;
858 unsigned max_tile_pipes;
859 unsigned max_simds;
860 unsigned max_backends;
861 unsigned max_gprs;
862 unsigned max_threads;
863 unsigned max_stack_entries;
864 unsigned max_hw_contexts;
865 unsigned max_gs_threads;
866 unsigned sx_max_export_size;
867 unsigned sx_max_export_pos_size;
868 unsigned sx_max_export_smx_size;
869 unsigned sq_num_cf_insts;
870 unsigned sx_num_of_sets;
871 unsigned sc_prim_fifo_size;
872 unsigned sc_hiz_tile_fifo_size;
873 unsigned sc_earlyz_tile_fifo_fize;
874 unsigned tiling_nbanks;
875 unsigned tiling_npipes;
876 unsigned tiling_group_size;
877 struct r100_gpu_lockup lockup;
878 };
879
880 struct evergreen_asic {
881 unsigned num_ses;
882 unsigned max_pipes;
883 unsigned max_tile_pipes;
884 unsigned max_simds;
885 unsigned max_backends;
886 unsigned max_gprs;
887 unsigned max_threads;
888 unsigned max_stack_entries;
889 unsigned max_hw_contexts;
890 unsigned max_gs_threads;
891 unsigned sx_max_export_size;
892 unsigned sx_max_export_pos_size;
893 unsigned sx_max_export_smx_size;
894 unsigned sq_num_cf_insts;
895 unsigned sx_num_of_sets;
896 unsigned sc_prim_fifo_size;
897 unsigned sc_hiz_tile_fifo_size;
898 unsigned sc_earlyz_tile_fifo_size;
899 unsigned tiling_nbanks;
900 unsigned tiling_npipes;
901 unsigned tiling_group_size;
902 };
903
904 union radeon_asic_config {
905 struct r300_asic r300;
906 struct r100_asic r100;
907 struct r600_asic r600;
908 struct rv770_asic rv770;
909 struct evergreen_asic evergreen;
910 };
911
912 /*
913 * asic initizalization from radeon_asic.c
914 */
915 void radeon_agp_disable(struct radeon_device *rdev);
916 int radeon_asic_init(struct radeon_device *rdev);
917
918
919 /*
920 * IOCTL.
921 */
922 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
923 struct drm_file *filp);
924 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
925 struct drm_file *filp);
926 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
927 struct drm_file *file_priv);
928 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
929 struct drm_file *file_priv);
930 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
931 struct drm_file *file_priv);
932 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
933 struct drm_file *file_priv);
934 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
935 struct drm_file *filp);
936 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
937 struct drm_file *filp);
938 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
939 struct drm_file *filp);
940 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *filp);
942 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
943 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
944 struct drm_file *filp);
945 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *filp);
947
948
949 /*
950 * Core structure, functions and helpers.
951 */
952 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
953 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
954
955 struct radeon_device {
956 struct device *dev;
957 struct drm_device *ddev;
958 struct pci_dev *pdev;
959 /* ASIC */
960 union radeon_asic_config config;
961 enum radeon_family family;
962 unsigned long flags;
963 int usec_timeout;
964 enum radeon_pll_errata pll_errata;
965 int num_gb_pipes;
966 int num_z_pipes;
967 int disp_priority;
968 /* BIOS */
969 uint8_t *bios;
970 bool is_atom_bios;
971 uint16_t bios_header_start;
972 struct radeon_bo *stollen_vga_memory;
973 /* Register mmio */
974 resource_size_t rmmio_base;
975 resource_size_t rmmio_size;
976 void *rmmio;
977 radeon_rreg_t mc_rreg;
978 radeon_wreg_t mc_wreg;
979 radeon_rreg_t pll_rreg;
980 radeon_wreg_t pll_wreg;
981 uint32_t pcie_reg_mask;
982 radeon_rreg_t pciep_rreg;
983 radeon_wreg_t pciep_wreg;
984 struct radeon_clock clock;
985 struct radeon_mc mc;
986 struct radeon_gart gart;
987 struct radeon_mode_info mode_info;
988 struct radeon_scratch scratch;
989 struct radeon_mman mman;
990 struct radeon_fence_driver fence_drv;
991 struct radeon_cp cp;
992 struct radeon_ib_pool ib_pool;
993 struct radeon_irq irq;
994 struct radeon_asic *asic;
995 struct radeon_gem gem;
996 struct radeon_pm pm;
997 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
998 struct mutex cs_mutex;
999 struct radeon_wb wb;
1000 struct radeon_dummy_page dummy_page;
1001 bool gpu_lockup;
1002 bool shutdown;
1003 bool suspend;
1004 bool need_dma32;
1005 bool accel_working;
1006 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1007 const struct firmware *me_fw; /* all family ME firmware */
1008 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1009 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1010 struct r600_blit r600_blit;
1011 int msi_enabled; /* msi enabled */
1012 struct r600_ih ih; /* r6/700 interrupt ring */
1013 struct workqueue_struct *wq;
1014 struct work_struct hotplug_work;
1015 int num_crtc; /* number of crtcs */
1016 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1017
1018 /* audio stuff */
1019 struct timer_list audio_timer;
1020 int audio_channels;
1021 int audio_rate;
1022 int audio_bits_per_sample;
1023 uint8_t audio_status_bits;
1024 uint8_t audio_category_code;
1025
1026 bool powered_down;
1027 };
1028
1029 int radeon_device_init(struct radeon_device *rdev,
1030 struct drm_device *ddev,
1031 struct pci_dev *pdev,
1032 uint32_t flags);
1033 void radeon_device_fini(struct radeon_device *rdev);
1034 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1035
1036 /* r600 blit */
1037 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1038 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1039 void r600_kms_blit_copy(struct radeon_device *rdev,
1040 u64 src_gpu_addr, u64 dst_gpu_addr,
1041 int size_bytes);
1042
1043 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1044 {
1045 if (reg < rdev->rmmio_size)
1046 return readl(((void __iomem *)rdev->rmmio) + reg);
1047 else {
1048 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1049 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1050 }
1051 }
1052
1053 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1054 {
1055 if (reg < rdev->rmmio_size)
1056 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1057 else {
1058 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1059 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1060 }
1061 }
1062
1063 /*
1064 * Cast helper
1065 */
1066 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1067
1068 /*
1069 * Registers read & write functions.
1070 */
1071 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1072 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1073 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1074 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1075 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1076 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1077 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1078 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1079 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1080 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1081 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1082 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1083 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1084 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1085 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1086 #define WREG32_P(reg, val, mask) \
1087 do { \
1088 uint32_t tmp_ = RREG32(reg); \
1089 tmp_ &= (mask); \
1090 tmp_ |= ((val) & ~(mask)); \
1091 WREG32(reg, tmp_); \
1092 } while (0)
1093 #define WREG32_PLL_P(reg, val, mask) \
1094 do { \
1095 uint32_t tmp_ = RREG32_PLL(reg); \
1096 tmp_ &= (mask); \
1097 tmp_ |= ((val) & ~(mask)); \
1098 WREG32_PLL(reg, tmp_); \
1099 } while (0)
1100 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1101
1102 /*
1103 * Indirect registers accessor
1104 */
1105 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1106 {
1107 uint32_t r;
1108
1109 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1110 r = RREG32(RADEON_PCIE_DATA);
1111 return r;
1112 }
1113
1114 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1115 {
1116 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1117 WREG32(RADEON_PCIE_DATA, (v));
1118 }
1119
1120 void r100_pll_errata_after_index(struct radeon_device *rdev);
1121
1122
1123 /*
1124 * ASICs helpers.
1125 */
1126 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1127 (rdev->pdev->device == 0x5969))
1128 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1129 (rdev->family == CHIP_RV200) || \
1130 (rdev->family == CHIP_RS100) || \
1131 (rdev->family == CHIP_RS200) || \
1132 (rdev->family == CHIP_RV250) || \
1133 (rdev->family == CHIP_RV280) || \
1134 (rdev->family == CHIP_RS300))
1135 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1136 (rdev->family == CHIP_RV350) || \
1137 (rdev->family == CHIP_R350) || \
1138 (rdev->family == CHIP_RV380) || \
1139 (rdev->family == CHIP_R420) || \
1140 (rdev->family == CHIP_R423) || \
1141 (rdev->family == CHIP_RV410) || \
1142 (rdev->family == CHIP_RS400) || \
1143 (rdev->family == CHIP_RS480))
1144 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1145 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1146 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1147 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1148
1149 /*
1150 * BIOS helpers.
1151 */
1152 #define RBIOS8(i) (rdev->bios[i])
1153 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1154 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1155
1156 int radeon_combios_init(struct radeon_device *rdev);
1157 void radeon_combios_fini(struct radeon_device *rdev);
1158 int radeon_atombios_init(struct radeon_device *rdev);
1159 void radeon_atombios_fini(struct radeon_device *rdev);
1160
1161
1162 /*
1163 * RING helpers.
1164 */
1165 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1166 {
1167 #if DRM_DEBUG_CODE
1168 if (rdev->cp.count_dw <= 0) {
1169 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1170 }
1171 #endif
1172 rdev->cp.ring[rdev->cp.wptr++] = v;
1173 rdev->cp.wptr &= rdev->cp.ptr_mask;
1174 rdev->cp.count_dw--;
1175 rdev->cp.ring_free_dw--;
1176 }
1177
1178
1179 /*
1180 * ASICs macro.
1181 */
1182 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1183 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1184 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1185 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1186 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1187 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1188 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1189 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1190 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1191 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1192 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1193 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1194 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1195 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1196 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1197 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1198 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1199 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1200 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1201 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1202 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1203 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1204 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1205 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1206 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1207 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1208 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1209 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1210 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1211 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1212 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1213 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1214 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1215 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1216 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1217 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1218
1219 /* Common functions */
1220 /* AGP */
1221 extern int radeon_gpu_reset(struct radeon_device *rdev);
1222 extern void radeon_agp_disable(struct radeon_device *rdev);
1223 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1224 extern void radeon_gart_restore(struct radeon_device *rdev);
1225 extern int radeon_modeset_init(struct radeon_device *rdev);
1226 extern void radeon_modeset_fini(struct radeon_device *rdev);
1227 extern bool radeon_card_posted(struct radeon_device *rdev);
1228 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1229 extern void radeon_update_display_priority(struct radeon_device *rdev);
1230 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1231 extern int radeon_clocks_init(struct radeon_device *rdev);
1232 extern void radeon_clocks_fini(struct radeon_device *rdev);
1233 extern void radeon_scratch_init(struct radeon_device *rdev);
1234 extern void radeon_surface_init(struct radeon_device *rdev);
1235 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1236 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1237 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1238 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1239 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1240 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1241 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1242 extern int radeon_resume_kms(struct drm_device *dev);
1243 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1244
1245 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1246 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1247 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1248
1249 /* rv200,rv250,rv280 */
1250 extern void r200_set_safe_registers(struct radeon_device *rdev);
1251
1252 /* r300,r350,rv350,rv370,rv380 */
1253 extern void r300_set_reg_safe(struct radeon_device *rdev);
1254 extern void r300_mc_program(struct radeon_device *rdev);
1255 extern void r300_mc_init(struct radeon_device *rdev);
1256 extern void r300_clock_startup(struct radeon_device *rdev);
1257 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1258 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1259 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1260 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1261 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1262
1263 /* r420,r423,rv410 */
1264 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1265 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1266 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1267 extern void r420_pipes_init(struct radeon_device *rdev);
1268
1269 /* rv515 */
1270 struct rv515_mc_save {
1271 u32 d1vga_control;
1272 u32 d2vga_control;
1273 u32 vga_render_control;
1274 u32 vga_hdp_control;
1275 u32 d1crtc_control;
1276 u32 d2crtc_control;
1277 };
1278 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1279 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1280 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1281 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1282 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1283 extern void rv515_clock_startup(struct radeon_device *rdev);
1284 extern void rv515_debugfs(struct radeon_device *rdev);
1285 extern int rv515_suspend(struct radeon_device *rdev);
1286
1287 /* rs400 */
1288 extern int rs400_gart_init(struct radeon_device *rdev);
1289 extern int rs400_gart_enable(struct radeon_device *rdev);
1290 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1291 extern void rs400_gart_disable(struct radeon_device *rdev);
1292 extern void rs400_gart_fini(struct radeon_device *rdev);
1293
1294 /* rs600 */
1295 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1296 extern int rs600_irq_set(struct radeon_device *rdev);
1297 extern void rs600_irq_disable(struct radeon_device *rdev);
1298
1299 /* rs690, rs740 */
1300 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1301 struct drm_display_mode *mode1,
1302 struct drm_display_mode *mode2);
1303
1304 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1305 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1306 extern bool r600_card_posted(struct radeon_device *rdev);
1307 extern void r600_cp_stop(struct radeon_device *rdev);
1308 extern int r600_cp_start(struct radeon_device *rdev);
1309 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1310 extern int r600_cp_resume(struct radeon_device *rdev);
1311 extern void r600_cp_fini(struct radeon_device *rdev);
1312 extern int r600_count_pipe_bits(uint32_t val);
1313 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1314 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1315 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1316 extern int r600_ib_test(struct radeon_device *rdev);
1317 extern int r600_ring_test(struct radeon_device *rdev);
1318 extern void r600_wb_fini(struct radeon_device *rdev);
1319 extern int r600_wb_enable(struct radeon_device *rdev);
1320 extern void r600_wb_disable(struct radeon_device *rdev);
1321 extern void r600_scratch_init(struct radeon_device *rdev);
1322 extern int r600_blit_init(struct radeon_device *rdev);
1323 extern void r600_blit_fini(struct radeon_device *rdev);
1324 extern int r600_init_microcode(struct radeon_device *rdev);
1325 extern int r600_asic_reset(struct radeon_device *rdev);
1326 /* r600 irq */
1327 extern int r600_irq_init(struct radeon_device *rdev);
1328 extern void r600_irq_fini(struct radeon_device *rdev);
1329 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1330 extern int r600_irq_set(struct radeon_device *rdev);
1331 extern void r600_irq_suspend(struct radeon_device *rdev);
1332 extern void r600_disable_interrupts(struct radeon_device *rdev);
1333 extern void r600_rlc_stop(struct radeon_device *rdev);
1334 /* r600 audio */
1335 extern int r600_audio_init(struct radeon_device *rdev);
1336 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1337 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1338 extern int r600_audio_channels(struct radeon_device *rdev);
1339 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1340 extern int r600_audio_rate(struct radeon_device *rdev);
1341 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1342 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1343 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1344 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1345 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1346 extern void r600_audio_fini(struct radeon_device *rdev);
1347 extern void r600_hdmi_init(struct drm_encoder *encoder);
1348 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1349 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1350 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1351 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1352 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1353
1354 extern void r700_cp_stop(struct radeon_device *rdev);
1355 extern void r700_cp_fini(struct radeon_device *rdev);
1356 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1357 extern int evergreen_irq_set(struct radeon_device *rdev);
1358
1359 /* evergreen */
1360 struct evergreen_mc_save {
1361 u32 vga_control[6];
1362 u32 vga_render_control;
1363 u32 vga_hdp_control;
1364 u32 crtc_control[6];
1365 };
1366
1367 #include "radeon_object.h"
1368
1369 #endif
Linux kernel - Deliverables
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