drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97 extern int radeon_lockup_timeout;
  98
  99 /*
 100  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 101  * symbol;
 102  */
 103 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 104 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 106 #define RADEON_IB_POOL_SIZE                     16
 107 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 108 #define RADEONFB_CONN_LIMIT                     4
 109 #define RADEON_BIOS_NUM_SCRATCH                 8
 110
 111 /* max number of rings */
 112 #define RADEON_NUM_RINGS                        3
 113
 114 /* fence seq are set to this number when signaled */
 115 #define RADEON_FENCE_SIGNALED_SEQ               0LL
 116
 117 /* internal ring indices */
 118 /* r1xx+ has gfx CP ring */
 119 #define RADEON_RING_TYPE_GFX_INDEX              0
 120
 121 /* cayman has 2 compute CP rings */
 122 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 123 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 124
 125 /* hardcode those limit for now */
 126 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 127 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 128
 129 /*
 130  * Errata workarounds.
 131  */
 132 enum radeon_pll_errata {
 133         CHIP_ERRATA_R300_CG             = 0x00000001,
 134         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 135         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 136 };
 137
 138
 139 struct radeon_device;
 140
 141
 142 /*
 143  * BIOS.
 144  */
 145 #define ATRM_BIOS_PAGE 4096
 146
 147 #if defined(CONFIG_VGA_SWITCHEROO)
 148 bool radeon_atrm_supported(struct pci_dev *pdev);
 149 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 150 #else
 151 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 152 {
 153         return false;
 154 }
 155
 156 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 157         return -EINVAL;
 158 }
 159 #endif
 160 bool radeon_get_bios(struct radeon_device *rdev);
 161
 162
 163 /*
 164  * Mutex which allows recursive locking from the same process.
 165  */
 166 struct radeon_mutex {
 167         struct mutex            mutex;
 168         struct task_struct      *owner;
 169         int                     level;
 170 };
 171
 172 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
 173 {
 174         mutex_init(&mutex->mutex);
 175         mutex->owner = NULL;
 176         mutex->level = 0;
 177 }
 178
 179 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
 180 {
 181         if (mutex_trylock(&mutex->mutex)) {
 182                 /* The mutex was unlocked before, so it's ours now */
 183                 mutex->owner = current;
 184         } else if (mutex->owner != current) {
 185                 /* Another process locked the mutex, take it */
 186                 mutex_lock(&mutex->mutex);
 187                 mutex->owner = current;
 188         }
 189         /* Otherwise the mutex was already locked by this process */
 190
 191         mutex->level++;
 192 }
 193
 194 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
 195 {
 196         if (--mutex->level > 0)
 197                 return;
 198
 199         mutex->owner = NULL;
 200         mutex_unlock(&mutex->mutex);
 201 }
 202
 203
 204 /*
 205  * Dummy page
 206  */
 207 struct radeon_dummy_page {
 208         struct page     *page;
 209         dma_addr_t      addr;
 210 };
 211 int radeon_dummy_page_init(struct radeon_device *rdev);
 212 void radeon_dummy_page_fini(struct radeon_device *rdev);
 213
 214
 215 /*
 216  * Clocks
 217  */
 218 struct radeon_clock {
 219         struct radeon_pll p1pll;
 220         struct radeon_pll p2pll;
 221         struct radeon_pll dcpll;
 222         struct radeon_pll spll;
 223         struct radeon_pll mpll;
 224         /* 10 Khz units */
 225         uint32_t default_mclk;
 226         uint32_t default_sclk;
 227         uint32_t default_dispclk;
 228         uint32_t dp_extclk;
 229         uint32_t max_pixel_clock;
 230 };
 231
 232 /*
 233  * Power management
 234  */
 235 int radeon_pm_init(struct radeon_device *rdev);
 236 void radeon_pm_fini(struct radeon_device *rdev);
 237 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 238 void radeon_pm_suspend(struct radeon_device *rdev);
 239 void radeon_pm_resume(struct radeon_device *rdev);
 240 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 241 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 242 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 243 void rs690_pm_info(struct radeon_device *rdev);
 244 extern int rv6xx_get_temp(struct radeon_device *rdev);
 245 extern int rv770_get_temp(struct radeon_device *rdev);
 246 extern int evergreen_get_temp(struct radeon_device *rdev);
 247 extern int sumo_get_temp(struct radeon_device *rdev);
 248 extern int si_get_temp(struct radeon_device *rdev);
 249 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 250                                     unsigned *bankh, unsigned *mtaspect,
 251                                     unsigned *tile_split);
 252
 253 /*
 254  * Fences.
 255  */
 256 struct radeon_fence_driver {
 257         uint32_t                        scratch_reg;
 258         uint64_t                        gpu_addr;
 259         volatile uint32_t               *cpu_addr;
 260         /* sync_seq is protected by ring emission lock */
 261         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 262         atomic64_t                      last_seq;
 263         unsigned long                   last_activity;
 264         bool                            initialized;
 265 };
 266
 267 struct radeon_fence {
 268         struct radeon_device            *rdev;
 269         struct kref                     kref;
 270         /* protected by radeon_fence.lock */
 271         uint64_t                        seq;
 272         /* RB, DMA, etc. */
 273         unsigned                        ring;
 274 };
 275
 276 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 277 int radeon_fence_driver_init(struct radeon_device *rdev);
 278 void radeon_fence_driver_fini(struct radeon_device *rdev);
 279 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 280 void radeon_fence_process(struct radeon_device *rdev, int ring);
 281 bool radeon_fence_signaled(struct radeon_fence *fence);
 282 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 283 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
 284 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
 285 int radeon_fence_wait_any(struct radeon_device *rdev,
 286                           struct radeon_fence **fences,
 287                           bool intr);
 288 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 289 void radeon_fence_unref(struct radeon_fence **fence);
 290 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 291 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 292 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 293 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 294                                                       struct radeon_fence *b)
 295 {
 296         if (!a) {
 297                 return b;
 298         }
 299
 300         if (!b) {
 301                 return a;
 302         }
 303
 304         BUG_ON(a->ring != b->ring);
 305
 306         if (a->seq > b->seq) {
 307                 return a;
 308         } else {
 309                 return b;
 310         }
 311 }
 312
 313 /*
 314  * Tiling registers
 315  */
 316 struct radeon_surface_reg {
 317         struct radeon_bo *bo;
 318 };
 319
 320 #define RADEON_GEM_MAX_SURFACES 8
 321
 322 /*
 323  * TTM.
 324  */
 325 struct radeon_mman {
 326         struct ttm_bo_global_ref        bo_global_ref;
 327         struct drm_global_reference     mem_global_ref;
 328         struct ttm_bo_device            bdev;
 329         bool                            mem_global_referenced;
 330         bool                            initialized;
 331 };
 332
 333 /* bo virtual address in a specific vm */
 334 struct radeon_bo_va {
 335         /* bo list is protected by bo being reserved */
 336         struct list_head                bo_list;
 337         /* vm list is protected by vm mutex */
 338         struct list_head                vm_list;
 339         /* constant after initialization */
 340         struct radeon_vm                *vm;
 341         struct radeon_bo                *bo;
 342         uint64_t                        soffset;
 343         uint64_t                        eoffset;
 344         uint32_t                        flags;
 345         bool                            valid;
 346 };
 347
 348 struct radeon_bo {
 349         /* Protected by gem.mutex */
 350         struct list_head                list;
 351         /* Protected by tbo.reserved */
 352         u32                             placements[3];
 353         struct ttm_placement            placement;
 354         struct ttm_buffer_object        tbo;
 355         struct ttm_bo_kmap_obj          kmap;
 356         unsigned                        pin_count;
 357         void                            *kptr;
 358         u32                             tiling_flags;
 359         u32                             pitch;
 360         int                             surface_reg;
 361         /* list of all virtual address to which this bo
 362          * is associated to
 363          */
 364         struct list_head                va;
 365         /* Constant after initialization */
 366         struct radeon_device            *rdev;
 367         struct drm_gem_object           gem_base;
 368
 369         struct ttm_bo_kmap_obj dma_buf_vmap;
 370         int vmapping_count;
 371 };
 372 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 373
 374 struct radeon_bo_list {
 375         struct ttm_validate_buffer tv;
 376         struct radeon_bo        *bo;
 377         uint64_t                gpu_offset;
 378         unsigned                rdomain;
 379         unsigned                wdomain;
 380         u32                     tiling_flags;
 381 };
 382
 383 /* sub-allocation manager, it has to be protected by another lock.
 384  * By conception this is an helper for other part of the driver
 385  * like the indirect buffer or semaphore, which both have their
 386  * locking.
 387  *
 388  * Principe is simple, we keep a list of sub allocation in offset
 389  * order (first entry has offset == 0, last entry has the highest
 390  * offset).
 391  *
 392  * When allocating new object we first check if there is room at
 393  * the end total_size - (last_object_offset + last_object_size) >=
 394  * alloc_size. If so we allocate new object there.
 395  *
 396  * When there is not enough room at the end, we start waiting for
 397  * each sub object until we reach object_offset+object_size >=
 398  * alloc_size, this object then become the sub object we return.
 399  *
 400  * Alignment can't be bigger than page size.
 401  *
 402  * Hole are not considered for allocation to keep things simple.
 403  * Assumption is that there won't be hole (all object on same
 404  * alignment).
 405  */
 406 struct radeon_sa_manager {
 407         spinlock_t              lock;
 408         struct radeon_bo        *bo;
 409         struct list_head        *hole;
 410         struct list_head        flist[RADEON_NUM_RINGS];
 411         struct list_head        olist;
 412         unsigned                size;
 413         uint64_t                gpu_addr;
 414         void                    *cpu_ptr;
 415         uint32_t                domain;
 416 };
 417
 418 struct radeon_sa_bo;
 419
 420 /* sub-allocation buffer */
 421 struct radeon_sa_bo {
 422         struct list_head                olist;
 423         struct list_head                flist;
 424         struct radeon_sa_manager        *manager;
 425         unsigned                        soffset;
 426         unsigned                        eoffset;
 427         struct radeon_fence             *fence;
 428 };
 429
 430 /*
 431  * GEM objects.
 432  */
 433 struct radeon_gem {
 434         struct mutex            mutex;
 435         struct list_head        objects;
 436 };
 437
 438 int radeon_gem_init(struct radeon_device *rdev);
 439 void radeon_gem_fini(struct radeon_device *rdev);
 440 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 441                                 int alignment, int initial_domain,
 442                                 bool discardable, bool kernel,
 443                                 struct drm_gem_object **obj);
 444
 445 int radeon_mode_dumb_create(struct drm_file *file_priv,
 446                             struct drm_device *dev,
 447                             struct drm_mode_create_dumb *args);
 448 int radeon_mode_dumb_mmap(struct drm_file *filp,
 449                           struct drm_device *dev,
 450                           uint32_t handle, uint64_t *offset_p);
 451 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 452                              struct drm_device *dev,
 453                              uint32_t handle);
 454
 455 /*
 456  * Semaphores.
 457  */
 458 /* everything here is constant */
 459 struct radeon_semaphore {
 460         struct radeon_sa_bo             *sa_bo;
 461         signed                          waiters;
 462         uint64_t                        gpu_addr;
 463 };
 464
 465 int radeon_semaphore_create(struct radeon_device *rdev,
 466                             struct radeon_semaphore **semaphore);
 467 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 468                                   struct radeon_semaphore *semaphore);
 469 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 470                                 struct radeon_semaphore *semaphore);
 471 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
 472                                 struct radeon_semaphore *semaphore,
 473                                 int signaler, int waiter);
 474 void radeon_semaphore_free(struct radeon_device *rdev,
 475                            struct radeon_semaphore **semaphore,
 476                            struct radeon_fence *fence);
 477
 478 /*
 479  * GART structures, functions & helpers
 480  */
 481 struct radeon_mc;
 482
 483 #define RADEON_GPU_PAGE_SIZE 4096
 484 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 485 #define RADEON_GPU_PAGE_SHIFT 12
 486 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 487
 488 struct radeon_gart {
 489         dma_addr_t                      table_addr;
 490         struct radeon_bo                *robj;
 491         void                            *ptr;
 492         unsigned                        num_gpu_pages;
 493         unsigned                        num_cpu_pages;
 494         unsigned                        table_size;
 495         struct page                     **pages;
 496         dma_addr_t                      *pages_addr;
 497         bool                            ready;
 498 };
 499
 500 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 501 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 502 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 503 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 504 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 505 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 506 int radeon_gart_init(struct radeon_device *rdev);
 507 void radeon_gart_fini(struct radeon_device *rdev);
 508 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 509                         int pages);
 510 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 511                      int pages, struct page **pagelist,
 512                      dma_addr_t *dma_addr);
 513 void radeon_gart_restore(struct radeon_device *rdev);
 514
 515
 516 /*
 517  * GPU MC structures, functions & helpers
 518  */
 519 struct radeon_mc {
 520         resource_size_t         aper_size;
 521         resource_size_t         aper_base;
 522         resource_size_t         agp_base;
 523         /* for some chips with <= 32MB we need to lie
 524          * about vram size near mc fb location */
 525         u64                     mc_vram_size;
 526         u64                     visible_vram_size;
 527         u64                     gtt_size;
 528         u64                     gtt_start;
 529         u64                     gtt_end;
 530         u64                     vram_start;
 531         u64                     vram_end;
 532         unsigned                vram_width;
 533         u64                     real_vram_size;
 534         int                     vram_mtrr;
 535         bool                    vram_is_ddr;
 536         bool                    igp_sideport_enabled;
 537         u64                     gtt_base_align;
 538 };
 539
 540 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 541 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 542
 543 /*
 544  * GPU scratch registers structures, functions & helpers
 545  */
 546 struct radeon_scratch {
 547         unsigned                num_reg;
 548         uint32_t                reg_base;
 549         bool                    free[32];
 550         uint32_t                reg[32];
 551 };
 552
 553 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 554 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 555
 556
 557 /*
 558  * IRQS.
 559  */
 560
 561 struct radeon_unpin_work {
 562         struct work_struct work;
 563         struct radeon_device *rdev;
 564         int crtc_id;
 565         struct radeon_fence *fence;
 566         struct drm_pending_vblank_event *event;
 567         struct radeon_bo *old_rbo;
 568         u64 new_crtc_base;
 569 };
 570
 571 struct r500_irq_stat_regs {
 572         u32 disp_int;
 573         u32 hdmi0_status;
 574 };
 575
 576 struct r600_irq_stat_regs {
 577         u32 disp_int;
 578         u32 disp_int_cont;
 579         u32 disp_int_cont2;
 580         u32 d1grph_int;
 581         u32 d2grph_int;
 582         u32 hdmi0_status;
 583         u32 hdmi1_status;
 584 };
 585
 586 struct evergreen_irq_stat_regs {
 587         u32 disp_int;
 588         u32 disp_int_cont;
 589         u32 disp_int_cont2;
 590         u32 disp_int_cont3;
 591         u32 disp_int_cont4;
 592         u32 disp_int_cont5;
 593         u32 d1grph_int;
 594         u32 d2grph_int;
 595         u32 d3grph_int;
 596         u32 d4grph_int;
 597         u32 d5grph_int;
 598         u32 d6grph_int;
 599         u32 afmt_status1;
 600         u32 afmt_status2;
 601         u32 afmt_status3;
 602         u32 afmt_status4;
 603         u32 afmt_status5;
 604         u32 afmt_status6;
 605 };
 606
 607 union radeon_irq_stat_regs {
 608         struct r500_irq_stat_regs r500;
 609         struct r600_irq_stat_regs r600;
 610         struct evergreen_irq_stat_regs evergreen;
 611 };
 612
 613 #define RADEON_MAX_HPD_PINS 6
 614 #define RADEON_MAX_CRTCS 6
 615 #define RADEON_MAX_AFMT_BLOCKS 6
 616
 617 struct radeon_irq {
 618         bool            installed;
 619         bool            sw_int[RADEON_NUM_RINGS];
 620         bool            crtc_vblank_int[RADEON_MAX_CRTCS];
 621         bool            pflip[RADEON_MAX_CRTCS];
 622         wait_queue_head_t       vblank_queue;
 623         bool            hpd[RADEON_MAX_HPD_PINS];
 624         bool            gui_idle;
 625         bool            gui_idle_acked;
 626         wait_queue_head_t       idle_queue;
 627         bool            afmt[RADEON_MAX_AFMT_BLOCKS];
 628         spinlock_t sw_lock;
 629         int sw_refcount[RADEON_NUM_RINGS];
 630         union radeon_irq_stat_regs stat_regs;
 631         spinlock_t pflip_lock[RADEON_MAX_CRTCS];
 632         int pflip_refcount[RADEON_MAX_CRTCS];
 633 };
 634
 635 int radeon_irq_kms_init(struct radeon_device *rdev);
 636 void radeon_irq_kms_fini(struct radeon_device *rdev);
 637 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 638 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 639 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 640 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 641
 642 /*
 643  * CP & rings.
 644  */
 645
 646 struct radeon_ib {
 647         struct radeon_sa_bo             *sa_bo;
 648         uint32_t                        length_dw;
 649         uint64_t                        gpu_addr;
 650         uint32_t                        *ptr;
 651         int                             ring;
 652         struct radeon_fence             *fence;
 653         unsigned                        vm_id;
 654         bool                            is_const_ib;
 655         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
 656         struct radeon_semaphore         *semaphore;
 657 };
 658
 659 struct radeon_ring {
 660         struct radeon_bo        *ring_obj;
 661         volatile uint32_t       *ring;
 662         unsigned                rptr;
 663         unsigned                rptr_offs;
 664         unsigned                rptr_reg;
 665         unsigned                wptr;
 666         unsigned                wptr_old;
 667         unsigned                wptr_reg;
 668         unsigned                ring_size;
 669         unsigned                ring_free_dw;
 670         int                     count_dw;
 671         unsigned long           last_activity;
 672         unsigned                last_rptr;
 673         uint64_t                gpu_addr;
 674         uint32_t                align_mask;
 675         uint32_t                ptr_mask;
 676         bool                    ready;
 677         u32                     ptr_reg_shift;
 678         u32                     ptr_reg_mask;
 679         u32                     nop;
 680 };
 681
 682 /*
 683  * VM
 684  */
 685 struct radeon_vm {
 686         struct list_head                list;
 687         struct list_head                va;
 688         int                             id;
 689         unsigned                        last_pfn;
 690         u64                             pt_gpu_addr;
 691         u64                             *pt;
 692         struct radeon_sa_bo             *sa_bo;
 693         struct mutex                    mutex;
 694         /* last fence for cs using this vm */
 695         struct radeon_fence             *fence;
 696 };
 697
 698 struct radeon_vm_funcs {
 699         int (*init)(struct radeon_device *rdev);
 700         void (*fini)(struct radeon_device *rdev);
 701         /* cs mutex must be lock for schedule_ib */
 702         int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 703         void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
 704         void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
 705         uint32_t (*page_flags)(struct radeon_device *rdev,
 706                                struct radeon_vm *vm,
 707                                uint32_t flags);
 708         void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
 709                         unsigned pfn, uint64_t addr, uint32_t flags);
 710 };
 711
 712 struct radeon_vm_manager {
 713         struct list_head                lru_vm;
 714         uint32_t                        use_bitmap;
 715         struct radeon_sa_manager        sa_manager;
 716         uint32_t                        max_pfn;
 717         /* fields constant after init */
 718         const struct radeon_vm_funcs    *funcs;
 719         /* number of VMIDs */
 720         unsigned                        nvm;
 721         /* vram base address for page table entry  */
 722         u64                             vram_base_offset;
 723         /* is vm enabled? */
 724         bool                            enabled;
 725 };
 726
 727 /*
 728  * file private structure
 729  */
 730 struct radeon_fpriv {
 731         struct radeon_vm                vm;
 732 };
 733
 734 /*
 735  * R6xx+ IH ring
 736  */
 737 struct r600_ih {
 738         struct radeon_bo        *ring_obj;
 739         volatile uint32_t       *ring;
 740         unsigned                rptr;
 741         unsigned                rptr_offs;
 742         unsigned                wptr;
 743         unsigned                wptr_old;
 744         unsigned                ring_size;
 745         uint64_t                gpu_addr;
 746         uint32_t                ptr_mask;
 747         spinlock_t              lock;
 748         bool                    enabled;
 749 };
 750
 751 struct r600_blit_cp_primitives {
 752         void (*set_render_target)(struct radeon_device *rdev, int format,
 753                                   int w, int h, u64 gpu_addr);
 754         void (*cp_set_surface_sync)(struct radeon_device *rdev,
 755                                     u32 sync_type, u32 size,
 756                                     u64 mc_addr);
 757         void (*set_shaders)(struct radeon_device *rdev);
 758         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
 759         void (*set_tex_resource)(struct radeon_device *rdev,
 760                                  int format, int w, int h, int pitch,
 761                                  u64 gpu_addr, u32 size);
 762         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
 763                              int x2, int y2);
 764         void (*draw_auto)(struct radeon_device *rdev);
 765         void (*set_default_state)(struct radeon_device *rdev);
 766 };
 767
 768 struct r600_blit {
 769         struct radeon_bo        *shader_obj;
 770         struct r600_blit_cp_primitives primitives;
 771         int max_dim;
 772         int ring_size_common;
 773         int ring_size_per_loop;
 774         u64 shader_gpu_addr;
 775         u32 vs_offset, ps_offset;
 776         u32 state_offset;
 777         u32 state_len;
 778 };
 779
 780 void r600_blit_suspend(struct radeon_device *rdev);
 781
 782 /*
 783  * SI RLC stuff
 784  */
 785 struct si_rlc {
 786         /* for power gating */
 787         struct radeon_bo        *save_restore_obj;
 788         uint64_t                save_restore_gpu_addr;
 789         /* for clear state */
 790         struct radeon_bo        *clear_state_obj;
 791         uint64_t                clear_state_gpu_addr;
 792 };
 793
 794 int radeon_ib_get(struct radeon_device *rdev, int ring,
 795                   struct radeon_ib *ib, unsigned size);
 796 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
 797 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 798 int radeon_ib_pool_init(struct radeon_device *rdev);
 799 void radeon_ib_pool_fini(struct radeon_device *rdev);
 800 int radeon_ib_pool_start(struct radeon_device *rdev);
 801 int radeon_ib_pool_suspend(struct radeon_device *rdev);
 802 int radeon_ib_ring_tests(struct radeon_device *rdev);
 803 /* Ring access between begin & end cannot sleep */
 804 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
 805 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 806 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 807 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 808 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 809 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 810 void radeon_ring_undo(struct radeon_ring *ring);
 811 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 812 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 813 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
 814 void radeon_ring_lockup_update(struct radeon_ring *ring);
 815 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 816 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 817                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 818                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
 819 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 820
 821
 822 /*
 823  * CS.
 824  */
 825 struct radeon_cs_reloc {
 826         struct drm_gem_object           *gobj;
 827         struct radeon_bo                *robj;
 828         struct radeon_bo_list           lobj;
 829         uint32_t                        handle;
 830         uint32_t                        flags;
 831 };
 832
 833 struct radeon_cs_chunk {
 834         uint32_t                chunk_id;
 835         uint32_t                length_dw;
 836         int                     kpage_idx[2];
 837         uint32_t                *kpage[2];
 838         uint32_t                *kdata;
 839         void __user             *user_ptr;
 840         int                     last_copied_page;
 841         int                     last_page_index;
 842 };
 843
 844 struct radeon_cs_parser {
 845         struct device           *dev;
 846         struct radeon_device    *rdev;
 847         struct drm_file         *filp;
 848         /* chunks */
 849         unsigned                nchunks;
 850         struct radeon_cs_chunk  *chunks;
 851         uint64_t                *chunks_array;
 852         /* IB */
 853         unsigned                idx;
 854         /* relocations */
 855         unsigned                nrelocs;
 856         struct radeon_cs_reloc  *relocs;
 857         struct radeon_cs_reloc  **relocs_ptr;
 858         struct list_head        validated;
 859         /* indices of various chunks */
 860         int                     chunk_ib_idx;
 861         int                     chunk_relocs_idx;
 862         int                     chunk_flags_idx;
 863         int                     chunk_const_ib_idx;
 864         struct radeon_ib        ib;
 865         struct radeon_ib        const_ib;
 866         void                    *track;
 867         unsigned                family;
 868         int                     parser_error;
 869         u32                     cs_flags;
 870         u32                     ring;
 871         s32                     priority;
 872 };
 873
 874 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 875 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 876
 877 struct radeon_cs_packet {
 878         unsigned        idx;
 879         unsigned        type;
 880         unsigned        reg;
 881         unsigned        opcode;
 882         int             count;
 883         unsigned        one_reg_wr;
 884 };
 885
 886 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 887                                       struct radeon_cs_packet *pkt,
 888                                       unsigned idx, unsigned reg);
 889 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 890                                       struct radeon_cs_packet *pkt);
 891
 892
 893 /*
 894  * AGP
 895  */
 896 int radeon_agp_init(struct radeon_device *rdev);
 897 void radeon_agp_resume(struct radeon_device *rdev);
 898 void radeon_agp_suspend(struct radeon_device *rdev);
 899 void radeon_agp_fini(struct radeon_device *rdev);
 900
 901
 902 /*
 903  * Writeback
 904  */
 905 struct radeon_wb {
 906         struct radeon_bo        *wb_obj;
 907         volatile uint32_t       *wb;
 908         uint64_t                gpu_addr;
 909         bool                    enabled;
 910         bool                    use_event;
 911 };
 912
 913 #define RADEON_WB_SCRATCH_OFFSET 0
 914 #define RADEON_WB_CP_RPTR_OFFSET 1024
 915 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 916 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 917 #define R600_WB_IH_WPTR_OFFSET   2048
 918 #define R600_WB_EVENT_OFFSET     3072
 919
 920 /**
 921  * struct radeon_pm - power management datas
 922  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 923  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 924  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 925  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 926  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 927  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 928  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 929  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 930  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 931  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 932  * @needed_bandwidth:   current bandwidth needs
 933  *
 934  * It keeps track of various data needed to take powermanagement decision.
 935  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 936  * Equation between gpu/memory clock and available bandwidth is hw dependent
 937  * (type of memory, bus size, efficiency, ...)
 938  */
 939
 940 enum radeon_pm_method {
 941         PM_METHOD_PROFILE,
 942         PM_METHOD_DYNPM,
 943 };
 944
 945 enum radeon_dynpm_state {
 946         DYNPM_STATE_DISABLED,
 947         DYNPM_STATE_MINIMUM,
 948         DYNPM_STATE_PAUSED,
 949         DYNPM_STATE_ACTIVE,
 950         DYNPM_STATE_SUSPENDED,
 951 };
 952 enum radeon_dynpm_action {
 953         DYNPM_ACTION_NONE,
 954         DYNPM_ACTION_MINIMUM,
 955         DYNPM_ACTION_DOWNCLOCK,
 956         DYNPM_ACTION_UPCLOCK,
 957         DYNPM_ACTION_DEFAULT
 958 };
 959
 960 enum radeon_voltage_type {
 961         VOLTAGE_NONE = 0,
 962         VOLTAGE_GPIO,
 963         VOLTAGE_VDDC,
 964         VOLTAGE_SW
 965 };
 966
 967 enum radeon_pm_state_type {
 968         POWER_STATE_TYPE_DEFAULT,
 969         POWER_STATE_TYPE_POWERSAVE,
 970         POWER_STATE_TYPE_BATTERY,
 971         POWER_STATE_TYPE_BALANCED,
 972         POWER_STATE_TYPE_PERFORMANCE,
 973 };
 974
 975 enum radeon_pm_profile_type {
 976         PM_PROFILE_DEFAULT,
 977         PM_PROFILE_AUTO,
 978         PM_PROFILE_LOW,
 979         PM_PROFILE_MID,
 980         PM_PROFILE_HIGH,
 981 };
 982
 983 #define PM_PROFILE_DEFAULT_IDX 0
 984 #define PM_PROFILE_LOW_SH_IDX  1
 985 #define PM_PROFILE_MID_SH_IDX  2
 986 #define PM_PROFILE_HIGH_SH_IDX 3
 987 #define PM_PROFILE_LOW_MH_IDX  4
 988 #define PM_PROFILE_MID_MH_IDX  5
 989 #define PM_PROFILE_HIGH_MH_IDX 6
 990 #define PM_PROFILE_MAX         7
 991
 992 struct radeon_pm_profile {
 993         int dpms_off_ps_idx;
 994         int dpms_on_ps_idx;
 995         int dpms_off_cm_idx;
 996         int dpms_on_cm_idx;
 997 };
 998
 999 enum radeon_int_thermal_type {
1000         THERMAL_TYPE_NONE,
1001         THERMAL_TYPE_RV6XX,
1002         THERMAL_TYPE_RV770,
1003         THERMAL_TYPE_EVERGREEN,
1004         THERMAL_TYPE_SUMO,
1005         THERMAL_TYPE_NI,
1006         THERMAL_TYPE_SI,
1007 };
1008
1009 struct radeon_voltage {
1010         enum radeon_voltage_type type;
1011         /* gpio voltage */
1012         struct radeon_gpio_rec gpio;
1013         u32 delay; /* delay in usec from voltage drop to sclk change */
1014         bool active_high; /* voltage drop is active when bit is high */
1015         /* VDDC voltage */
1016         u8 vddc_id; /* index into vddc voltage table */
1017         u8 vddci_id; /* index into vddci voltage table */
1018         bool vddci_enabled;
1019         /* r6xx+ sw */
1020         u16 voltage;
1021         /* evergreen+ vddci */
1022         u16 vddci;
1023 };
1024
1025 /* clock mode flags */
1026 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1027
1028 struct radeon_pm_clock_info {
1029         /* memory clock */
1030         u32 mclk;
1031         /* engine clock */
1032         u32 sclk;
1033         /* voltage info */
1034         struct radeon_voltage voltage;
1035         /* standardized clock flags */
1036         u32 flags;
1037 };
1038
1039 /* state flags */
1040 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1041
1042 struct radeon_power_state {
1043         enum radeon_pm_state_type type;
1044         struct radeon_pm_clock_info *clock_info;
1045         /* number of valid clock modes in this power state */
1046         int num_clock_modes;
1047         struct radeon_pm_clock_info *default_clock_mode;
1048         /* standardized state flags */
1049         u32 flags;
1050         u32 misc; /* vbios specific flags */
1051         u32 misc2; /* vbios specific flags */
1052         int pcie_lanes; /* pcie lanes */
1053 };
1054
1055 /*
1056  * Some modes are overclocked by very low value, accept them
1057  */
1058 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1059
1060 struct radeon_pm {
1061         struct mutex            mutex;
1062         u32                     active_crtcs;
1063         int                     active_crtc_count;
1064         int                     req_vblank;
1065         bool                    vblank_sync;
1066         bool                    gui_idle;
1067         fixed20_12              max_bandwidth;
1068         fixed20_12              igp_sideport_mclk;
1069         fixed20_12              igp_system_mclk;
1070         fixed20_12              igp_ht_link_clk;
1071         fixed20_12              igp_ht_link_width;
1072         fixed20_12              k8_bandwidth;
1073         fixed20_12              sideport_bandwidth;
1074         fixed20_12              ht_bandwidth;
1075         fixed20_12              core_bandwidth;
1076         fixed20_12              sclk;
1077         fixed20_12              mclk;
1078         fixed20_12              needed_bandwidth;
1079         struct radeon_power_state *power_state;
1080         /* number of valid power states */
1081         int                     num_power_states;
1082         int                     current_power_state_index;
1083         int                     current_clock_mode_index;
1084         int                     requested_power_state_index;
1085         int                     requested_clock_mode_index;
1086         int                     default_power_state_index;
1087         u32                     current_sclk;
1088         u32                     current_mclk;
1089         u16                     current_vddc;
1090         u16                     current_vddci;
1091         u32                     default_sclk;
1092         u32                     default_mclk;
1093         u16                     default_vddc;
1094         u16                     default_vddci;
1095         struct radeon_i2c_chan *i2c_bus;
1096         /* selected pm method */
1097         enum radeon_pm_method     pm_method;
1098         /* dynpm power management */
1099         struct delayed_work     dynpm_idle_work;
1100         enum radeon_dynpm_state dynpm_state;
1101         enum radeon_dynpm_action        dynpm_planned_action;
1102         unsigned long           dynpm_action_timeout;
1103         bool                    dynpm_can_upclock;
1104         bool                    dynpm_can_downclock;
1105         /* profile-based power management */
1106         enum radeon_pm_profile_type profile;
1107         int                     profile_index;
1108         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1109         /* internal thermal controller on rv6xx+ */
1110         enum radeon_int_thermal_type int_thermal_type;
1111         struct device           *int_hwmon_dev;
1112 };
1113
1114 int radeon_pm_get_type_index(struct radeon_device *rdev,
1115                              enum radeon_pm_state_type ps_type,
1116                              int instance);
1117
1118 struct r600_audio {
1119         int                     channels;
1120         int                     rate;
1121         int                     bits_per_sample;
1122         u8                      status_bits;
1123         u8                      category_code;
1124 };
1125
1126 /*
1127  * Benchmarking
1128  */
1129 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1130
1131
1132 /*
1133  * Testing
1134  */
1135 void radeon_test_moves(struct radeon_device *rdev);
1136 void radeon_test_ring_sync(struct radeon_device *rdev,
1137                            struct radeon_ring *cpA,
1138                            struct radeon_ring *cpB);
1139 void radeon_test_syncing(struct radeon_device *rdev);
1140
1141
1142 /*
1143  * Debugfs
1144  */
1145 struct radeon_debugfs {
1146         struct drm_info_list    *files;
1147         unsigned                num_files;
1148 };
1149
1150 int radeon_debugfs_add_files(struct radeon_device *rdev,
1151                              struct drm_info_list *files,
1152                              unsigned nfiles);
1153 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1154
1155
1156 /*
1157  * ASIC specific functions.
1158  */
1159 struct radeon_asic {
1160         int (*init)(struct radeon_device *rdev);
1161         void (*fini)(struct radeon_device *rdev);
1162         int (*resume)(struct radeon_device *rdev);
1163         int (*suspend)(struct radeon_device *rdev);
1164         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1165         int (*asic_reset)(struct radeon_device *rdev);
1166         /* ioctl hw specific callback. Some hw might want to perform special
1167          * operation on specific ioctl. For instance on wait idle some hw
1168          * might want to perform and HDP flush through MMIO as it seems that
1169          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1170          * through ring.
1171          */
1172         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1173         /* check if 3D engine is idle */
1174         bool (*gui_idle)(struct radeon_device *rdev);
1175         /* wait for mc_idle */
1176         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1177         /* gart */
1178         struct {
1179                 void (*tlb_flush)(struct radeon_device *rdev);
1180                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1181         } gart;
1182         /* ring specific callbacks */
1183         struct {
1184                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1185                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1186                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1187                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1188                                        struct radeon_semaphore *semaphore, bool emit_wait);
1189                 int (*cs_parse)(struct radeon_cs_parser *p);
1190                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1191                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1192                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1193                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1194         } ring[RADEON_NUM_RINGS];
1195         /* irqs */
1196         struct {
1197                 int (*set)(struct radeon_device *rdev);
1198                 int (*process)(struct radeon_device *rdev);
1199         } irq;
1200         /* displays */
1201         struct {
1202                 /* display watermarks */
1203                 void (*bandwidth_update)(struct radeon_device *rdev);
1204                 /* get frame count */
1205                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1206                 /* wait for vblank */
1207                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1208         } display;
1209         /* copy functions for bo handling */
1210         struct {
1211                 int (*blit)(struct radeon_device *rdev,
1212                             uint64_t src_offset,
1213                             uint64_t dst_offset,
1214                             unsigned num_gpu_pages,
1215                             struct radeon_fence **fence);
1216                 u32 blit_ring_index;
1217                 int (*dma)(struct radeon_device *rdev,
1218                            uint64_t src_offset,
1219                            uint64_t dst_offset,
1220                            unsigned num_gpu_pages,
1221                            struct radeon_fence **fence);
1222                 u32 dma_ring_index;
1223                 /* method used for bo copy */
1224                 int (*copy)(struct radeon_device *rdev,
1225                             uint64_t src_offset,
1226                             uint64_t dst_offset,
1227                             unsigned num_gpu_pages,
1228                             struct radeon_fence **fence);
1229                 /* ring used for bo copies */
1230                 u32 copy_ring_index;
1231         } copy;
1232         /* surfaces */
1233         struct {
1234                 int (*set_reg)(struct radeon_device *rdev, int reg,
1235                                        uint32_t tiling_flags, uint32_t pitch,
1236                                        uint32_t offset, uint32_t obj_size);
1237                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1238         } surface;
1239         /* hotplug detect */
1240         struct {
1241                 void (*init)(struct radeon_device *rdev);
1242                 void (*fini)(struct radeon_device *rdev);
1243                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1244                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1245         } hpd;
1246         /* power management */
1247         struct {
1248                 void (*misc)(struct radeon_device *rdev);
1249                 void (*prepare)(struct radeon_device *rdev);
1250                 void (*finish)(struct radeon_device *rdev);
1251                 void (*init_profile)(struct radeon_device *rdev);
1252                 void (*get_dynpm_state)(struct radeon_device *rdev);
1253                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1254                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1255                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1256                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1257                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1258                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1259                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1260         } pm;
1261         /* pageflipping */
1262         struct {
1263                 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1264                 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1265                 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1266         } pflip;
1267 };
1268
1269 /*
1270  * Asic structures
1271  */
1272 struct r100_asic {
1273         const unsigned          *reg_safe_bm;
1274         unsigned                reg_safe_bm_size;
1275         u32                     hdp_cntl;
1276 };
1277
1278 struct r300_asic {
1279         const unsigned          *reg_safe_bm;
1280         unsigned                reg_safe_bm_size;
1281         u32                     resync_scratch;
1282         u32                     hdp_cntl;
1283 };
1284
1285 struct r600_asic {
1286         unsigned                max_pipes;
1287         unsigned                max_tile_pipes;
1288         unsigned                max_simds;
1289         unsigned                max_backends;
1290         unsigned                max_gprs;
1291         unsigned                max_threads;
1292         unsigned                max_stack_entries;
1293         unsigned                max_hw_contexts;
1294         unsigned                max_gs_threads;
1295         unsigned                sx_max_export_size;
1296         unsigned                sx_max_export_pos_size;
1297         unsigned                sx_max_export_smx_size;
1298         unsigned                sq_num_cf_insts;
1299         unsigned                tiling_nbanks;
1300         unsigned                tiling_npipes;
1301         unsigned                tiling_group_size;
1302         unsigned                tile_config;
1303         unsigned                backend_map;
1304 };
1305
1306 struct rv770_asic {
1307         unsigned                max_pipes;
1308         unsigned                max_tile_pipes;
1309         unsigned                max_simds;
1310         unsigned                max_backends;
1311         unsigned                max_gprs;
1312         unsigned                max_threads;
1313         unsigned                max_stack_entries;
1314         unsigned                max_hw_contexts;
1315         unsigned                max_gs_threads;
1316         unsigned                sx_max_export_size;
1317         unsigned                sx_max_export_pos_size;
1318         unsigned                sx_max_export_smx_size;
1319         unsigned                sq_num_cf_insts;
1320         unsigned                sx_num_of_sets;
1321         unsigned                sc_prim_fifo_size;
1322         unsigned                sc_hiz_tile_fifo_size;
1323         unsigned                sc_earlyz_tile_fifo_fize;
1324         unsigned                tiling_nbanks;
1325         unsigned                tiling_npipes;
1326         unsigned                tiling_group_size;
1327         unsigned                tile_config;
1328         unsigned                backend_map;
1329 };
1330
1331 struct evergreen_asic {
1332         unsigned num_ses;
1333         unsigned max_pipes;
1334         unsigned max_tile_pipes;
1335         unsigned max_simds;
1336         unsigned max_backends;
1337         unsigned max_gprs;
1338         unsigned max_threads;
1339         unsigned max_stack_entries;
1340         unsigned max_hw_contexts;
1341         unsigned max_gs_threads;
1342         unsigned sx_max_export_size;
1343         unsigned sx_max_export_pos_size;
1344         unsigned sx_max_export_smx_size;
1345         unsigned sq_num_cf_insts;
1346         unsigned sx_num_of_sets;
1347         unsigned sc_prim_fifo_size;
1348         unsigned sc_hiz_tile_fifo_size;
1349         unsigned sc_earlyz_tile_fifo_size;
1350         unsigned tiling_nbanks;
1351         unsigned tiling_npipes;
1352         unsigned tiling_group_size;
1353         unsigned tile_config;
1354         unsigned backend_map;
1355 };
1356
1357 struct cayman_asic {
1358         unsigned max_shader_engines;
1359         unsigned max_pipes_per_simd;
1360         unsigned max_tile_pipes;
1361         unsigned max_simds_per_se;
1362         unsigned max_backends_per_se;
1363         unsigned max_texture_channel_caches;
1364         unsigned max_gprs;
1365         unsigned max_threads;
1366         unsigned max_gs_threads;
1367         unsigned max_stack_entries;
1368         unsigned sx_num_of_sets;
1369         unsigned sx_max_export_size;
1370         unsigned sx_max_export_pos_size;
1371         unsigned sx_max_export_smx_size;
1372         unsigned max_hw_contexts;
1373         unsigned sq_num_cf_insts;
1374         unsigned sc_prim_fifo_size;
1375         unsigned sc_hiz_tile_fifo_size;
1376         unsigned sc_earlyz_tile_fifo_size;
1377
1378         unsigned num_shader_engines;
1379         unsigned num_shader_pipes_per_simd;
1380         unsigned num_tile_pipes;
1381         unsigned num_simds_per_se;
1382         unsigned num_backends_per_se;
1383         unsigned backend_disable_mask_per_asic;
1384         unsigned backend_map;
1385         unsigned num_texture_channel_caches;
1386         unsigned mem_max_burst_length_bytes;
1387         unsigned mem_row_size_in_kb;
1388         unsigned shader_engine_tile_size;
1389         unsigned num_gpus;
1390         unsigned multi_gpu_tile_size;
1391
1392         unsigned tile_config;
1393 };
1394
1395 struct si_asic {
1396         unsigned max_shader_engines;
1397         unsigned max_tile_pipes;
1398         unsigned max_cu_per_sh;
1399         unsigned max_sh_per_se;
1400         unsigned max_backends_per_se;
1401         unsigned max_texture_channel_caches;
1402         unsigned max_gprs;
1403         unsigned max_gs_threads;
1404         unsigned max_hw_contexts;
1405         unsigned sc_prim_fifo_size_frontend;
1406         unsigned sc_prim_fifo_size_backend;
1407         unsigned sc_hiz_tile_fifo_size;
1408         unsigned sc_earlyz_tile_fifo_size;
1409
1410         unsigned num_tile_pipes;
1411         unsigned num_backends_per_se;
1412         unsigned backend_disable_mask_per_asic;
1413         unsigned backend_map;
1414         unsigned num_texture_channel_caches;
1415         unsigned mem_max_burst_length_bytes;
1416         unsigned mem_row_size_in_kb;
1417         unsigned shader_engine_tile_size;
1418         unsigned num_gpus;
1419         unsigned multi_gpu_tile_size;
1420
1421         unsigned tile_config;
1422 };
1423
1424 union radeon_asic_config {
1425         struct r300_asic        r300;
1426         struct r100_asic        r100;
1427         struct r600_asic        r600;
1428         struct rv770_asic       rv770;
1429         struct evergreen_asic   evergreen;
1430         struct cayman_asic      cayman;
1431         struct si_asic          si;
1432 };
1433
1434 /*
1435  * asic initizalization from radeon_asic.c
1436  */
1437 void radeon_agp_disable(struct radeon_device *rdev);
1438 int radeon_asic_init(struct radeon_device *rdev);
1439
1440
1441 /*
1442  * IOCTL.
1443  */
1444 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1445                           struct drm_file *filp);
1446 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1447                             struct drm_file *filp);
1448 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1449                          struct drm_file *file_priv);
1450 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1451                            struct drm_file *file_priv);
1452 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1453                             struct drm_file *file_priv);
1454 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1455                            struct drm_file *file_priv);
1456 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1457                                 struct drm_file *filp);
1458 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1459                           struct drm_file *filp);
1460 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1461                           struct drm_file *filp);
1462 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1463                               struct drm_file *filp);
1464 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1465                           struct drm_file *filp);
1466 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1467 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1468                                 struct drm_file *filp);
1469 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1470                                 struct drm_file *filp);
1471
1472 /* VRAM scratch page for HDP bug, default vram page */
1473 struct r600_vram_scratch {
1474         struct radeon_bo                *robj;
1475         volatile uint32_t               *ptr;
1476         u64                             gpu_addr;
1477 };
1478
1479
1480 /*
1481  * Core structure, functions and helpers.
1482  */
1483 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1484 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1485
1486 struct radeon_device {
1487         struct device                   *dev;
1488         struct drm_device               *ddev;
1489         struct pci_dev                  *pdev;
1490         /* ASIC */
1491         union radeon_asic_config        config;
1492         enum radeon_family              family;
1493         unsigned long                   flags;
1494         int                             usec_timeout;
1495         enum radeon_pll_errata          pll_errata;
1496         int                             num_gb_pipes;
1497         int                             num_z_pipes;
1498         int                             disp_priority;
1499         /* BIOS */
1500         uint8_t                         *bios;
1501         bool                            is_atom_bios;
1502         uint16_t                        bios_header_start;
1503         struct radeon_bo                *stollen_vga_memory;
1504         /* Register mmio */
1505         resource_size_t                 rmmio_base;
1506         resource_size_t                 rmmio_size;
1507         void __iomem                    *rmmio;
1508         radeon_rreg_t                   mc_rreg;
1509         radeon_wreg_t                   mc_wreg;
1510         radeon_rreg_t                   pll_rreg;
1511         radeon_wreg_t                   pll_wreg;
1512         uint32_t                        pcie_reg_mask;
1513         radeon_rreg_t                   pciep_rreg;
1514         radeon_wreg_t                   pciep_wreg;
1515         /* io port */
1516         void __iomem                    *rio_mem;
1517         resource_size_t                 rio_mem_size;
1518         struct radeon_clock             clock;
1519         struct radeon_mc                mc;
1520         struct radeon_gart              gart;
1521         struct radeon_mode_info         mode_info;
1522         struct radeon_scratch           scratch;
1523         struct radeon_mman              mman;
1524         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
1525         wait_queue_head_t               fence_queue;
1526         struct mutex                    ring_lock;
1527         struct radeon_ring              ring[RADEON_NUM_RINGS];
1528         bool                            ib_pool_ready;
1529         struct radeon_sa_manager        ring_tmp_bo;
1530         struct radeon_irq               irq;
1531         struct radeon_asic              *asic;
1532         struct radeon_gem               gem;
1533         struct radeon_pm                pm;
1534         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1535         struct radeon_mutex             cs_mutex;
1536         struct radeon_wb                wb;
1537         struct radeon_dummy_page        dummy_page;
1538         bool                            shutdown;
1539         bool                            suspend;
1540         bool                            need_dma32;
1541         bool                            accel_working;
1542         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1543         const struct firmware *me_fw;   /* all family ME firmware */
1544         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1545         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1546         const struct firmware *mc_fw;   /* NI MC firmware */
1547         const struct firmware *ce_fw;   /* SI CE firmware */
1548         struct r600_blit r600_blit;
1549         struct r600_vram_scratch vram_scratch;
1550         int msi_enabled; /* msi enabled */
1551         struct r600_ih ih; /* r6/700 interrupt ring */
1552         struct si_rlc rlc;
1553         struct work_struct hotplug_work;
1554         struct work_struct audio_work;
1555         int num_crtc; /* number of crtcs */
1556         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1557         struct mutex vram_mutex;
1558         bool audio_enabled;
1559         struct r600_audio audio_status; /* audio stuff */
1560         struct notifier_block acpi_nb;
1561         /* only one userspace can use Hyperz features or CMASK at a time */
1562         struct drm_file *hyperz_filp;
1563         struct drm_file *cmask_filp;
1564         /* i2c buses */
1565         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1566         /* debugfs */
1567         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1568         unsigned                debugfs_count;
1569         /* virtual memory */
1570         struct radeon_vm_manager        vm_manager;
1571 };
1572
1573 int radeon_device_init(struct radeon_device *rdev,
1574                        struct drm_device *ddev,
1575                        struct pci_dev *pdev,
1576                        uint32_t flags);
1577 void radeon_device_fini(struct radeon_device *rdev);
1578 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1579
1580 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1581 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1582 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1583 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1584
1585 /*
1586  * Cast helper
1587  */
1588 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1589
1590 /*
1591  * Registers read & write functions.
1592  */
1593 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1594 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1595 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1596 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1597 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1598 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1599 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1600 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1601 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1602 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1603 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1604 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1605 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1606 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1607 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1608 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1609 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1610 #define WREG32_P(reg, val, mask)                                \
1611         do {                                                    \
1612                 uint32_t tmp_ = RREG32(reg);                    \
1613                 tmp_ &= (mask);                                 \
1614                 tmp_ |= ((val) & ~(mask));                      \
1615                 WREG32(reg, tmp_);                              \
1616         } while (0)
1617 #define WREG32_PLL_P(reg, val, mask)                            \
1618         do {                                                    \
1619                 uint32_t tmp_ = RREG32_PLL(reg);                \
1620                 tmp_ &= (mask);                                 \
1621                 tmp_ |= ((val) & ~(mask));                      \
1622                 WREG32_PLL(reg, tmp_);                          \
1623         } while (0)
1624 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1625 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1626 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1627
1628 /*
1629  * Indirect registers accessor
1630  */
1631 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1632 {
1633         uint32_t r;
1634
1635         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1636         r = RREG32(RADEON_PCIE_DATA);
1637         return r;
1638 }
1639
1640 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1641 {
1642         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1643         WREG32(RADEON_PCIE_DATA, (v));
1644 }
1645
1646 void r100_pll_errata_after_index(struct radeon_device *rdev);
1647
1648
1649 /*
1650  * ASICs helpers.
1651  */
1652 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1653                             (rdev->pdev->device == 0x5969))
1654 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1655                 (rdev->family == CHIP_RV200) || \
1656                 (rdev->family == CHIP_RS100) || \
1657                 (rdev->family == CHIP_RS200) || \
1658                 (rdev->family == CHIP_RV250) || \
1659                 (rdev->family == CHIP_RV280) || \
1660                 (rdev->family == CHIP_RS300))
1661 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1662                 (rdev->family == CHIP_RV350) ||                 \
1663                 (rdev->family == CHIP_R350)  ||                 \
1664                 (rdev->family == CHIP_RV380) ||                 \
1665                 (rdev->family == CHIP_R420)  ||                 \
1666                 (rdev->family == CHIP_R423)  ||                 \
1667                 (rdev->family == CHIP_RV410) ||                 \
1668                 (rdev->family == CHIP_RS400) ||                 \
1669                 (rdev->family == CHIP_RS480))
1670 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1671                 (rdev->ddev->pdev->device == 0x9443) || \
1672                 (rdev->ddev->pdev->device == 0x944B) || \
1673                 (rdev->ddev->pdev->device == 0x9506) || \
1674                 (rdev->ddev->pdev->device == 0x9509) || \
1675                 (rdev->ddev->pdev->device == 0x950F) || \
1676                 (rdev->ddev->pdev->device == 0x689C) || \
1677                 (rdev->ddev->pdev->device == 0x689D))
1678 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1679 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1680                             (rdev->family == CHIP_RS690)  ||    \
1681                             (rdev->family == CHIP_RS740)  ||    \
1682                             (rdev->family >= CHIP_R600))
1683 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1684 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1685 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1686 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1687                              (rdev->flags & RADEON_IS_IGP))
1688 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1689 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1690 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1691                              (rdev->flags & RADEON_IS_IGP))
1692
1693 /*
1694  * BIOS helpers.
1695  */
1696 #define RBIOS8(i) (rdev->bios[i])
1697 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1698 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1699
1700 int radeon_combios_init(struct radeon_device *rdev);
1701 void radeon_combios_fini(struct radeon_device *rdev);
1702 int radeon_atombios_init(struct radeon_device *rdev);
1703 void radeon_atombios_fini(struct radeon_device *rdev);
1704
1705
1706 /*
1707  * RING helpers.
1708  */
1709 #if DRM_DEBUG_CODE == 0
1710 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1711 {
1712         ring->ring[ring->wptr++] = v;
1713         ring->wptr &= ring->ptr_mask;
1714         ring->count_dw--;
1715         ring->ring_free_dw--;
1716 }
1717 #else
1718 /* With debugging this is just too big to inline */
1719 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1720 #endif
1721
1722 /*
1723  * ASICs macro.
1724  */
1725 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1726 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1727 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1728 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1729 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1730 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1731 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1732 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1733 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1734 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1735 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1736 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1737 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1738 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1739 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1740 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1741 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1742 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1743 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1744 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1745 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1746 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1747 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1748 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1749 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1750 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1751 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1752 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1753 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1754 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1755 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1756 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1757 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1758 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1759 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1760 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1761 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1762 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1763 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1764 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1765 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1766 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1767 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1768 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1769 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1770 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1771 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1772 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1773 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1774 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1775 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1776
1777 /* Common functions */
1778 /* AGP */
1779 extern int radeon_gpu_reset(struct radeon_device *rdev);
1780 extern void radeon_agp_disable(struct radeon_device *rdev);
1781 extern int radeon_modeset_init(struct radeon_device *rdev);
1782 extern void radeon_modeset_fini(struct radeon_device *rdev);
1783 extern bool radeon_card_posted(struct radeon_device *rdev);
1784 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1785 extern void radeon_update_display_priority(struct radeon_device *rdev);
1786 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1787 extern void radeon_scratch_init(struct radeon_device *rdev);
1788 extern void radeon_wb_fini(struct radeon_device *rdev);
1789 extern int radeon_wb_init(struct radeon_device *rdev);
1790 extern void radeon_wb_disable(struct radeon_device *rdev);
1791 extern void radeon_surface_init(struct radeon_device *rdev);
1792 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1793 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1794 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1795 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1796 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1797 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1798 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1799 extern int radeon_resume_kms(struct drm_device *dev);
1800 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1801 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1802
1803 /*
1804  * vm
1805  */
1806 int radeon_vm_manager_init(struct radeon_device *rdev);
1807 void radeon_vm_manager_fini(struct radeon_device *rdev);
1808 int radeon_vm_manager_start(struct radeon_device *rdev);
1809 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1810 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1811 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1812 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1813 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1814 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1815                             struct radeon_vm *vm,
1816                             struct radeon_bo *bo,
1817                             struct ttm_mem_reg *mem);
1818 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1819                              struct radeon_bo *bo);
1820 int radeon_vm_bo_add(struct radeon_device *rdev,
1821                      struct radeon_vm *vm,
1822                      struct radeon_bo *bo,
1823                      uint64_t offset,
1824                      uint32_t flags);
1825 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1826                      struct radeon_vm *vm,
1827                      struct radeon_bo *bo);
1828
1829 /* audio */
1830 void r600_audio_update_hdmi(struct work_struct *work);
1831
1832 /*
1833  * R600 vram scratch functions
1834  */
1835 int r600_vram_scratch_init(struct radeon_device *rdev);
1836 void r600_vram_scratch_fini(struct radeon_device *rdev);
1837
1838 /*
1839  * r600 cs checking helper
1840  */
1841 unsigned r600_mip_minify(unsigned size, unsigned level);
1842 bool r600_fmt_is_valid_color(u32 format);
1843 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1844 int r600_fmt_get_blocksize(u32 format);
1845 int r600_fmt_get_nblocksx(u32 format, u32 w);
1846 int r600_fmt_get_nblocksy(u32 format, u32 h);
1847
1848 /*
1849  * r600 functions used by radeon_encoder.c
1850  */
1851 struct radeon_hdmi_acr {
1852         u32 clock;
1853
1854         int n_32khz;
1855         int cts_32khz;
1856
1857         int n_44_1khz;
1858         int cts_44_1khz;
1859
1860         int n_48khz;
1861         int cts_48khz;
1862
1863 };
1864
1865 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1866
1867 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1868 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1869 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1870 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1871                                      u32 tiling_pipe_num,
1872                                      u32 max_rb_num,
1873                                      u32 total_max_rb_num,
1874                                      u32 enabled_rb_mask);
1875
1876 /*
1877  * evergreen functions used by radeon_encoder.c
1878  */
1879
1880 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1881
1882 extern int ni_init_microcode(struct radeon_device *rdev);
1883 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1884
1885 /* radeon_acpi.c */
1886 #if defined(CONFIG_ACPI)
1887 extern int radeon_acpi_init(struct radeon_device *rdev);
1888 #else
1889 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1890 #endif
1891
1892 #include "radeon_object.h"
1893
1894 #endif