drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97 extern int radeon_lockup_timeout;
  98
  99 /*
 100  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 101  * symbol;
 102  */
 103 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 104 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 106 #define RADEON_IB_POOL_SIZE                     16
 107 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 108 #define RADEONFB_CONN_LIMIT                     4
 109 #define RADEON_BIOS_NUM_SCRATCH                 8
 110
 111 /* max number of rings */
 112 #define RADEON_NUM_RINGS                        3
 113
 114 /* fence seq are set to this number when signaled */
 115 #define RADEON_FENCE_SIGNALED_SEQ               0LL
 116
 117 /* internal ring indices */
 118 /* r1xx+ has gfx CP ring */
 119 #define RADEON_RING_TYPE_GFX_INDEX              0
 120
 121 /* cayman has 2 compute CP rings */
 122 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 123 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 124
 125 /* hardcode those limit for now */
 126 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 127 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 128
 129 /*
 130  * Errata workarounds.
 131  */
 132 enum radeon_pll_errata {
 133         CHIP_ERRATA_R300_CG             = 0x00000001,
 134         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 135         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 136 };
 137
 138
 139 struct radeon_device;
 140
 141
 142 /*
 143  * BIOS.
 144  */
 145 #define ATRM_BIOS_PAGE 4096
 146
 147 #if defined(CONFIG_VGA_SWITCHEROO)
 148 bool radeon_atrm_supported(struct pci_dev *pdev);
 149 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 150 #else
 151 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 152 {
 153         return false;
 154 }
 155
 156 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 157         return -EINVAL;
 158 }
 159 #endif
 160 bool radeon_get_bios(struct radeon_device *rdev);
 161
 162 /*
 163  * Dummy page
 164  */
 165 struct radeon_dummy_page {
 166         struct page     *page;
 167         dma_addr_t      addr;
 168 };
 169 int radeon_dummy_page_init(struct radeon_device *rdev);
 170 void radeon_dummy_page_fini(struct radeon_device *rdev);
 171
 172
 173 /*
 174  * Clocks
 175  */
 176 struct radeon_clock {
 177         struct radeon_pll p1pll;
 178         struct radeon_pll p2pll;
 179         struct radeon_pll dcpll;
 180         struct radeon_pll spll;
 181         struct radeon_pll mpll;
 182         /* 10 Khz units */
 183         uint32_t default_mclk;
 184         uint32_t default_sclk;
 185         uint32_t default_dispclk;
 186         uint32_t dp_extclk;
 187         uint32_t max_pixel_clock;
 188 };
 189
 190 /*
 191  * Power management
 192  */
 193 int radeon_pm_init(struct radeon_device *rdev);
 194 void radeon_pm_fini(struct radeon_device *rdev);
 195 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 196 void radeon_pm_suspend(struct radeon_device *rdev);
 197 void radeon_pm_resume(struct radeon_device *rdev);
 198 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 199 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 200 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 201 void rs690_pm_info(struct radeon_device *rdev);
 202 extern int rv6xx_get_temp(struct radeon_device *rdev);
 203 extern int rv770_get_temp(struct radeon_device *rdev);
 204 extern int evergreen_get_temp(struct radeon_device *rdev);
 205 extern int sumo_get_temp(struct radeon_device *rdev);
 206 extern int si_get_temp(struct radeon_device *rdev);
 207 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 208                                     unsigned *bankh, unsigned *mtaspect,
 209                                     unsigned *tile_split);
 210
 211 /*
 212  * Fences.
 213  */
 214 struct radeon_fence_driver {
 215         uint32_t                        scratch_reg;
 216         uint64_t                        gpu_addr;
 217         volatile uint32_t               *cpu_addr;
 218         /* sync_seq is protected by ring emission lock */
 219         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 220         atomic64_t                      last_seq;
 221         unsigned long                   last_activity;
 222         bool                            initialized;
 223 };
 224
 225 struct radeon_fence {
 226         struct radeon_device            *rdev;
 227         struct kref                     kref;
 228         /* protected by radeon_fence.lock */
 229         uint64_t                        seq;
 230         /* RB, DMA, etc. */
 231         unsigned                        ring;
 232 };
 233
 234 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 235 int radeon_fence_driver_init(struct radeon_device *rdev);
 236 void radeon_fence_driver_fini(struct radeon_device *rdev);
 237 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 238 void radeon_fence_process(struct radeon_device *rdev, int ring);
 239 bool radeon_fence_signaled(struct radeon_fence *fence);
 240 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 241 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
 242 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
 243 int radeon_fence_wait_any(struct radeon_device *rdev,
 244                           struct radeon_fence **fences,
 245                           bool intr);
 246 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 247 void radeon_fence_unref(struct radeon_fence **fence);
 248 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 249 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 250 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 251 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 252                                                       struct radeon_fence *b)
 253 {
 254         if (!a) {
 255                 return b;
 256         }
 257
 258         if (!b) {
 259                 return a;
 260         }
 261
 262         BUG_ON(a->ring != b->ring);
 263
 264         if (a->seq > b->seq) {
 265                 return a;
 266         } else {
 267                 return b;
 268         }
 269 }
 270
 271 /*
 272  * Tiling registers
 273  */
 274 struct radeon_surface_reg {
 275         struct radeon_bo *bo;
 276 };
 277
 278 #define RADEON_GEM_MAX_SURFACES 8
 279
 280 /*
 281  * TTM.
 282  */
 283 struct radeon_mman {
 284         struct ttm_bo_global_ref        bo_global_ref;
 285         struct drm_global_reference     mem_global_ref;
 286         struct ttm_bo_device            bdev;
 287         bool                            mem_global_referenced;
 288         bool                            initialized;
 289 };
 290
 291 /* bo virtual address in a specific vm */
 292 struct radeon_bo_va {
 293         /* bo list is protected by bo being reserved */
 294         struct list_head                bo_list;
 295         /* vm list is protected by vm mutex */
 296         struct list_head                vm_list;
 297         /* constant after initialization */
 298         struct radeon_vm                *vm;
 299         struct radeon_bo                *bo;
 300         uint64_t                        soffset;
 301         uint64_t                        eoffset;
 302         uint32_t                        flags;
 303         bool                            valid;
 304 };
 305
 306 struct radeon_bo {
 307         /* Protected by gem.mutex */
 308         struct list_head                list;
 309         /* Protected by tbo.reserved */
 310         u32                             placements[3];
 311         struct ttm_placement            placement;
 312         struct ttm_buffer_object        tbo;
 313         struct ttm_bo_kmap_obj          kmap;
 314         unsigned                        pin_count;
 315         void                            *kptr;
 316         u32                             tiling_flags;
 317         u32                             pitch;
 318         int                             surface_reg;
 319         /* list of all virtual address to which this bo
 320          * is associated to
 321          */
 322         struct list_head                va;
 323         /* Constant after initialization */
 324         struct radeon_device            *rdev;
 325         struct drm_gem_object           gem_base;
 326
 327         struct ttm_bo_kmap_obj dma_buf_vmap;
 328         int vmapping_count;
 329 };
 330 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 331
 332 struct radeon_bo_list {
 333         struct ttm_validate_buffer tv;
 334         struct radeon_bo        *bo;
 335         uint64_t                gpu_offset;
 336         unsigned                rdomain;
 337         unsigned                wdomain;
 338         u32                     tiling_flags;
 339 };
 340
 341 /* sub-allocation manager, it has to be protected by another lock.
 342  * By conception this is an helper for other part of the driver
 343  * like the indirect buffer or semaphore, which both have their
 344  * locking.
 345  *
 346  * Principe is simple, we keep a list of sub allocation in offset
 347  * order (first entry has offset == 0, last entry has the highest
 348  * offset).
 349  *
 350  * When allocating new object we first check if there is room at
 351  * the end total_size - (last_object_offset + last_object_size) >=
 352  * alloc_size. If so we allocate new object there.
 353  *
 354  * When there is not enough room at the end, we start waiting for
 355  * each sub object until we reach object_offset+object_size >=
 356  * alloc_size, this object then become the sub object we return.
 357  *
 358  * Alignment can't be bigger than page size.
 359  *
 360  * Hole are not considered for allocation to keep things simple.
 361  * Assumption is that there won't be hole (all object on same
 362  * alignment).
 363  */
 364 struct radeon_sa_manager {
 365         wait_queue_head_t       wq;
 366         struct radeon_bo        *bo;
 367         struct list_head        *hole;
 368         struct list_head        flist[RADEON_NUM_RINGS];
 369         struct list_head        olist;
 370         unsigned                size;
 371         uint64_t                gpu_addr;
 372         void                    *cpu_ptr;
 373         uint32_t                domain;
 374 };
 375
 376 struct radeon_sa_bo;
 377
 378 /* sub-allocation buffer */
 379 struct radeon_sa_bo {
 380         struct list_head                olist;
 381         struct list_head                flist;
 382         struct radeon_sa_manager        *manager;
 383         unsigned                        soffset;
 384         unsigned                        eoffset;
 385         struct radeon_fence             *fence;
 386 };
 387
 388 /*
 389  * GEM objects.
 390  */
 391 struct radeon_gem {
 392         struct mutex            mutex;
 393         struct list_head        objects;
 394 };
 395
 396 int radeon_gem_init(struct radeon_device *rdev);
 397 void radeon_gem_fini(struct radeon_device *rdev);
 398 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 399                                 int alignment, int initial_domain,
 400                                 bool discardable, bool kernel,
 401                                 struct drm_gem_object **obj);
 402
 403 int radeon_mode_dumb_create(struct drm_file *file_priv,
 404                             struct drm_device *dev,
 405                             struct drm_mode_create_dumb *args);
 406 int radeon_mode_dumb_mmap(struct drm_file *filp,
 407                           struct drm_device *dev,
 408                           uint32_t handle, uint64_t *offset_p);
 409 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 410                              struct drm_device *dev,
 411                              uint32_t handle);
 412
 413 /*
 414  * Semaphores.
 415  */
 416 /* everything here is constant */
 417 struct radeon_semaphore {
 418         struct radeon_sa_bo             *sa_bo;
 419         signed                          waiters;
 420         uint64_t                        gpu_addr;
 421 };
 422
 423 int radeon_semaphore_create(struct radeon_device *rdev,
 424                             struct radeon_semaphore **semaphore);
 425 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 426                                   struct radeon_semaphore *semaphore);
 427 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 428                                 struct radeon_semaphore *semaphore);
 429 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
 430                                 struct radeon_semaphore *semaphore,
 431                                 int signaler, int waiter);
 432 void radeon_semaphore_free(struct radeon_device *rdev,
 433                            struct radeon_semaphore **semaphore,
 434                            struct radeon_fence *fence);
 435
 436 /*
 437  * GART structures, functions & helpers
 438  */
 439 struct radeon_mc;
 440
 441 #define RADEON_GPU_PAGE_SIZE 4096
 442 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 443 #define RADEON_GPU_PAGE_SHIFT 12
 444 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 445
 446 struct radeon_gart {
 447         dma_addr_t                      table_addr;
 448         struct radeon_bo                *robj;
 449         void                            *ptr;
 450         unsigned                        num_gpu_pages;
 451         unsigned                        num_cpu_pages;
 452         unsigned                        table_size;
 453         struct page                     **pages;
 454         dma_addr_t                      *pages_addr;
 455         bool                            ready;
 456 };
 457
 458 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 459 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 460 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 461 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 462 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 463 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 464 int radeon_gart_init(struct radeon_device *rdev);
 465 void radeon_gart_fini(struct radeon_device *rdev);
 466 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 467                         int pages);
 468 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 469                      int pages, struct page **pagelist,
 470                      dma_addr_t *dma_addr);
 471 void radeon_gart_restore(struct radeon_device *rdev);
 472
 473
 474 /*
 475  * GPU MC structures, functions & helpers
 476  */
 477 struct radeon_mc {
 478         resource_size_t         aper_size;
 479         resource_size_t         aper_base;
 480         resource_size_t         agp_base;
 481         /* for some chips with <= 32MB we need to lie
 482          * about vram size near mc fb location */
 483         u64                     mc_vram_size;
 484         u64                     visible_vram_size;
 485         u64                     gtt_size;
 486         u64                     gtt_start;
 487         u64                     gtt_end;
 488         u64                     vram_start;
 489         u64                     vram_end;
 490         unsigned                vram_width;
 491         u64                     real_vram_size;
 492         int                     vram_mtrr;
 493         bool                    vram_is_ddr;
 494         bool                    igp_sideport_enabled;
 495         u64                     gtt_base_align;
 496 };
 497
 498 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 499 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 500
 501 /*
 502  * GPU scratch registers structures, functions & helpers
 503  */
 504 struct radeon_scratch {
 505         unsigned                num_reg;
 506         uint32_t                reg_base;
 507         bool                    free[32];
 508         uint32_t                reg[32];
 509 };
 510
 511 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 512 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 513
 514
 515 /*
 516  * IRQS.
 517  */
 518
 519 struct radeon_unpin_work {
 520         struct work_struct work;
 521         struct radeon_device *rdev;
 522         int crtc_id;
 523         struct radeon_fence *fence;
 524         struct drm_pending_vblank_event *event;
 525         struct radeon_bo *old_rbo;
 526         u64 new_crtc_base;
 527 };
 528
 529 struct r500_irq_stat_regs {
 530         u32 disp_int;
 531         u32 hdmi0_status;
 532 };
 533
 534 struct r600_irq_stat_regs {
 535         u32 disp_int;
 536         u32 disp_int_cont;
 537         u32 disp_int_cont2;
 538         u32 d1grph_int;
 539         u32 d2grph_int;
 540         u32 hdmi0_status;
 541         u32 hdmi1_status;
 542 };
 543
 544 struct evergreen_irq_stat_regs {
 545         u32 disp_int;
 546         u32 disp_int_cont;
 547         u32 disp_int_cont2;
 548         u32 disp_int_cont3;
 549         u32 disp_int_cont4;
 550         u32 disp_int_cont5;
 551         u32 d1grph_int;
 552         u32 d2grph_int;
 553         u32 d3grph_int;
 554         u32 d4grph_int;
 555         u32 d5grph_int;
 556         u32 d6grph_int;
 557         u32 afmt_status1;
 558         u32 afmt_status2;
 559         u32 afmt_status3;
 560         u32 afmt_status4;
 561         u32 afmt_status5;
 562         u32 afmt_status6;
 563 };
 564
 565 union radeon_irq_stat_regs {
 566         struct r500_irq_stat_regs r500;
 567         struct r600_irq_stat_regs r600;
 568         struct evergreen_irq_stat_regs evergreen;
 569 };
 570
 571 #define RADEON_MAX_HPD_PINS 6
 572 #define RADEON_MAX_CRTCS 6
 573 #define RADEON_MAX_AFMT_BLOCKS 6
 574
 575 struct radeon_irq {
 576         bool                            installed;
 577         spinlock_t                      lock;
 578         atomic_t                        ring_int[RADEON_NUM_RINGS];
 579         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 580         atomic_t                        pflip[RADEON_MAX_CRTCS];
 581         wait_queue_head_t               vblank_queue;
 582         bool                            hpd[RADEON_MAX_HPD_PINS];
 583         bool                            gui_idle;
 584         bool                            gui_idle_acked;
 585         wait_queue_head_t               idle_queue;
 586         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 587         union radeon_irq_stat_regs      stat_regs;
 588 };
 589
 590 int radeon_irq_kms_init(struct radeon_device *rdev);
 591 void radeon_irq_kms_fini(struct radeon_device *rdev);
 592 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 593 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 594 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 595 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 596 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 597 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 598 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 599 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 600 int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev);
 601
 602 /*
 603  * CP & rings.
 604  */
 605
 606 struct radeon_ib {
 607         struct radeon_sa_bo             *sa_bo;
 608         uint32_t                        length_dw;
 609         uint64_t                        gpu_addr;
 610         uint32_t                        *ptr;
 611         int                             ring;
 612         struct radeon_fence             *fence;
 613         unsigned                        vm_id;
 614         bool                            is_const_ib;
 615         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
 616         struct radeon_semaphore         *semaphore;
 617 };
 618
 619 struct radeon_ring {
 620         struct radeon_bo        *ring_obj;
 621         volatile uint32_t       *ring;
 622         unsigned                rptr;
 623         unsigned                rptr_offs;
 624         unsigned                rptr_reg;
 625         unsigned                rptr_save_reg;
 626         u64                     next_rptr_gpu_addr;
 627         volatile u32            *next_rptr_cpu_addr;
 628         unsigned                wptr;
 629         unsigned                wptr_old;
 630         unsigned                wptr_reg;
 631         unsigned                ring_size;
 632         unsigned                ring_free_dw;
 633         int                     count_dw;
 634         unsigned long           last_activity;
 635         unsigned                last_rptr;
 636         uint64_t                gpu_addr;
 637         uint32_t                align_mask;
 638         uint32_t                ptr_mask;
 639         bool                    ready;
 640         u32                     ptr_reg_shift;
 641         u32                     ptr_reg_mask;
 642         u32                     nop;
 643         u32                     idx;
 644 };
 645
 646 /*
 647  * VM
 648  */
 649 struct radeon_vm {
 650         struct list_head                list;
 651         struct list_head                va;
 652         int                             id;
 653         unsigned                        last_pfn;
 654         u64                             pt_gpu_addr;
 655         u64                             *pt;
 656         struct radeon_sa_bo             *sa_bo;
 657         struct mutex                    mutex;
 658         /* last fence for cs using this vm */
 659         struct radeon_fence             *fence;
 660 };
 661
 662 struct radeon_vm_funcs {
 663         int (*init)(struct radeon_device *rdev);
 664         void (*fini)(struct radeon_device *rdev);
 665         /* cs mutex must be lock for schedule_ib */
 666         int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 667         void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
 668         void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
 669         uint32_t (*page_flags)(struct radeon_device *rdev,
 670                                struct radeon_vm *vm,
 671                                uint32_t flags);
 672         void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
 673                         unsigned pfn, uint64_t addr, uint32_t flags);
 674 };
 675
 676 struct radeon_vm_manager {
 677         struct mutex                    lock;
 678         struct list_head                lru_vm;
 679         uint32_t                        use_bitmap;
 680         struct radeon_sa_manager        sa_manager;
 681         uint32_t                        max_pfn;
 682         /* fields constant after init */
 683         const struct radeon_vm_funcs    *funcs;
 684         /* number of VMIDs */
 685         unsigned                        nvm;
 686         /* vram base address for page table entry  */
 687         u64                             vram_base_offset;
 688         /* is vm enabled? */
 689         bool                            enabled;
 690 };
 691
 692 /*
 693  * file private structure
 694  */
 695 struct radeon_fpriv {
 696         struct radeon_vm                vm;
 697 };
 698
 699 /*
 700  * R6xx+ IH ring
 701  */
 702 struct r600_ih {
 703         struct radeon_bo        *ring_obj;
 704         volatile uint32_t       *ring;
 705         unsigned                rptr;
 706         unsigned                ring_size;
 707         uint64_t                gpu_addr;
 708         uint32_t                ptr_mask;
 709         atomic_t                lock;
 710         bool                    enabled;
 711 };
 712
 713 struct r600_blit_cp_primitives {
 714         void (*set_render_target)(struct radeon_device *rdev, int format,
 715                                   int w, int h, u64 gpu_addr);
 716         void (*cp_set_surface_sync)(struct radeon_device *rdev,
 717                                     u32 sync_type, u32 size,
 718                                     u64 mc_addr);
 719         void (*set_shaders)(struct radeon_device *rdev);
 720         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
 721         void (*set_tex_resource)(struct radeon_device *rdev,
 722                                  int format, int w, int h, int pitch,
 723                                  u64 gpu_addr, u32 size);
 724         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
 725                              int x2, int y2);
 726         void (*draw_auto)(struct radeon_device *rdev);
 727         void (*set_default_state)(struct radeon_device *rdev);
 728 };
 729
 730 struct r600_blit {
 731         struct radeon_bo        *shader_obj;
 732         struct r600_blit_cp_primitives primitives;
 733         int max_dim;
 734         int ring_size_common;
 735         int ring_size_per_loop;
 736         u64 shader_gpu_addr;
 737         u32 vs_offset, ps_offset;
 738         u32 state_offset;
 739         u32 state_len;
 740 };
 741
 742 /*
 743  * SI RLC stuff
 744  */
 745 struct si_rlc {
 746         /* for power gating */
 747         struct radeon_bo        *save_restore_obj;
 748         uint64_t                save_restore_gpu_addr;
 749         /* for clear state */
 750         struct radeon_bo        *clear_state_obj;
 751         uint64_t                clear_state_gpu_addr;
 752 };
 753
 754 int radeon_ib_get(struct radeon_device *rdev, int ring,
 755                   struct radeon_ib *ib, unsigned size);
 756 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
 757 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
 758                        struct radeon_ib *const_ib);
 759 int radeon_ib_pool_init(struct radeon_device *rdev);
 760 void radeon_ib_pool_fini(struct radeon_device *rdev);
 761 int radeon_ib_ring_tests(struct radeon_device *rdev);
 762 /* Ring access between begin & end cannot sleep */
 763 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
 764                                       struct radeon_ring *ring);
 765 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 766 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 767 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 768 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 769 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 770 void radeon_ring_undo(struct radeon_ring *ring);
 771 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 772 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 773 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
 774 void radeon_ring_lockup_update(struct radeon_ring *ring);
 775 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 776 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
 777                             uint32_t **data);
 778 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
 779                         unsigned size, uint32_t *data);
 780 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 781                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 782                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
 783 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 784
 785
 786 /*
 787  * CS.
 788  */
 789 struct radeon_cs_reloc {
 790         struct drm_gem_object           *gobj;
 791         struct radeon_bo                *robj;
 792         struct radeon_bo_list           lobj;
 793         uint32_t                        handle;
 794         uint32_t                        flags;
 795 };
 796
 797 struct radeon_cs_chunk {
 798         uint32_t                chunk_id;
 799         uint32_t                length_dw;
 800         int                     kpage_idx[2];
 801         uint32_t                *kpage[2];
 802         uint32_t                *kdata;
 803         void __user             *user_ptr;
 804         int                     last_copied_page;
 805         int                     last_page_index;
 806 };
 807
 808 struct radeon_cs_parser {
 809         struct device           *dev;
 810         struct radeon_device    *rdev;
 811         struct drm_file         *filp;
 812         /* chunks */
 813         unsigned                nchunks;
 814         struct radeon_cs_chunk  *chunks;
 815         uint64_t                *chunks_array;
 816         /* IB */
 817         unsigned                idx;
 818         /* relocations */
 819         unsigned                nrelocs;
 820         struct radeon_cs_reloc  *relocs;
 821         struct radeon_cs_reloc  **relocs_ptr;
 822         struct list_head        validated;
 823         /* indices of various chunks */
 824         int                     chunk_ib_idx;
 825         int                     chunk_relocs_idx;
 826         int                     chunk_flags_idx;
 827         int                     chunk_const_ib_idx;
 828         struct radeon_ib        ib;
 829         struct radeon_ib        const_ib;
 830         void                    *track;
 831         unsigned                family;
 832         int                     parser_error;
 833         u32                     cs_flags;
 834         u32                     ring;
 835         s32                     priority;
 836 };
 837
 838 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 839 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 840
 841 struct radeon_cs_packet {
 842         unsigned        idx;
 843         unsigned        type;
 844         unsigned        reg;
 845         unsigned        opcode;
 846         int             count;
 847         unsigned        one_reg_wr;
 848 };
 849
 850 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 851                                       struct radeon_cs_packet *pkt,
 852                                       unsigned idx, unsigned reg);
 853 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 854                                       struct radeon_cs_packet *pkt);
 855
 856
 857 /*
 858  * AGP
 859  */
 860 int radeon_agp_init(struct radeon_device *rdev);
 861 void radeon_agp_resume(struct radeon_device *rdev);
 862 void radeon_agp_suspend(struct radeon_device *rdev);
 863 void radeon_agp_fini(struct radeon_device *rdev);
 864
 865
 866 /*
 867  * Writeback
 868  */
 869 struct radeon_wb {
 870         struct radeon_bo        *wb_obj;
 871         volatile uint32_t       *wb;
 872         uint64_t                gpu_addr;
 873         bool                    enabled;
 874         bool                    use_event;
 875 };
 876
 877 #define RADEON_WB_SCRATCH_OFFSET 0
 878 #define RADEON_WB_RING0_NEXT_RPTR 256
 879 #define RADEON_WB_CP_RPTR_OFFSET 1024
 880 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 881 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 882 #define R600_WB_IH_WPTR_OFFSET   2048
 883 #define R600_WB_EVENT_OFFSET     3072
 884
 885 /**
 886  * struct radeon_pm - power management datas
 887  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 888  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 889  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 890  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 891  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 892  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 893  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 894  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 895  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 896  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 897  * @needed_bandwidth:   current bandwidth needs
 898  *
 899  * It keeps track of various data needed to take powermanagement decision.
 900  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 901  * Equation between gpu/memory clock and available bandwidth is hw dependent
 902  * (type of memory, bus size, efficiency, ...)
 903  */
 904
 905 enum radeon_pm_method {
 906         PM_METHOD_PROFILE,
 907         PM_METHOD_DYNPM,
 908 };
 909
 910 enum radeon_dynpm_state {
 911         DYNPM_STATE_DISABLED,
 912         DYNPM_STATE_MINIMUM,
 913         DYNPM_STATE_PAUSED,
 914         DYNPM_STATE_ACTIVE,
 915         DYNPM_STATE_SUSPENDED,
 916 };
 917 enum radeon_dynpm_action {
 918         DYNPM_ACTION_NONE,
 919         DYNPM_ACTION_MINIMUM,
 920         DYNPM_ACTION_DOWNCLOCK,
 921         DYNPM_ACTION_UPCLOCK,
 922         DYNPM_ACTION_DEFAULT
 923 };
 924
 925 enum radeon_voltage_type {
 926         VOLTAGE_NONE = 0,
 927         VOLTAGE_GPIO,
 928         VOLTAGE_VDDC,
 929         VOLTAGE_SW
 930 };
 931
 932 enum radeon_pm_state_type {
 933         POWER_STATE_TYPE_DEFAULT,
 934         POWER_STATE_TYPE_POWERSAVE,
 935         POWER_STATE_TYPE_BATTERY,
 936         POWER_STATE_TYPE_BALANCED,
 937         POWER_STATE_TYPE_PERFORMANCE,
 938 };
 939
 940 enum radeon_pm_profile_type {
 941         PM_PROFILE_DEFAULT,
 942         PM_PROFILE_AUTO,
 943         PM_PROFILE_LOW,
 944         PM_PROFILE_MID,
 945         PM_PROFILE_HIGH,
 946 };
 947
 948 #define PM_PROFILE_DEFAULT_IDX 0
 949 #define PM_PROFILE_LOW_SH_IDX  1
 950 #define PM_PROFILE_MID_SH_IDX  2
 951 #define PM_PROFILE_HIGH_SH_IDX 3
 952 #define PM_PROFILE_LOW_MH_IDX  4
 953 #define PM_PROFILE_MID_MH_IDX  5
 954 #define PM_PROFILE_HIGH_MH_IDX 6
 955 #define PM_PROFILE_MAX         7
 956
 957 struct radeon_pm_profile {
 958         int dpms_off_ps_idx;
 959         int dpms_on_ps_idx;
 960         int dpms_off_cm_idx;
 961         int dpms_on_cm_idx;
 962 };
 963
 964 enum radeon_int_thermal_type {
 965         THERMAL_TYPE_NONE,
 966         THERMAL_TYPE_RV6XX,
 967         THERMAL_TYPE_RV770,
 968         THERMAL_TYPE_EVERGREEN,
 969         THERMAL_TYPE_SUMO,
 970         THERMAL_TYPE_NI,
 971         THERMAL_TYPE_SI,
 972 };
 973
 974 struct radeon_voltage {
 975         enum radeon_voltage_type type;
 976         /* gpio voltage */
 977         struct radeon_gpio_rec gpio;
 978         u32 delay; /* delay in usec from voltage drop to sclk change */
 979         bool active_high; /* voltage drop is active when bit is high */
 980         /* VDDC voltage */
 981         u8 vddc_id; /* index into vddc voltage table */
 982         u8 vddci_id; /* index into vddci voltage table */
 983         bool vddci_enabled;
 984         /* r6xx+ sw */
 985         u16 voltage;
 986         /* evergreen+ vddci */
 987         u16 vddci;
 988 };
 989
 990 /* clock mode flags */
 991 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 992
 993 struct radeon_pm_clock_info {
 994         /* memory clock */
 995         u32 mclk;
 996         /* engine clock */
 997         u32 sclk;
 998         /* voltage info */
 999         struct radeon_voltage voltage;
1000         /* standardized clock flags */
1001         u32 flags;
1002 };
1003
1004 /* state flags */
1005 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1006
1007 struct radeon_power_state {
1008         enum radeon_pm_state_type type;
1009         struct radeon_pm_clock_info *clock_info;
1010         /* number of valid clock modes in this power state */
1011         int num_clock_modes;
1012         struct radeon_pm_clock_info *default_clock_mode;
1013         /* standardized state flags */
1014         u32 flags;
1015         u32 misc; /* vbios specific flags */
1016         u32 misc2; /* vbios specific flags */
1017         int pcie_lanes; /* pcie lanes */
1018 };
1019
1020 /*
1021  * Some modes are overclocked by very low value, accept them
1022  */
1023 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1024
1025 struct radeon_pm {
1026         struct mutex            mutex;
1027         /* write locked while reprogramming mclk */
1028         struct rw_semaphore     mclk_lock;
1029         u32                     active_crtcs;
1030         int                     active_crtc_count;
1031         int                     req_vblank;
1032         bool                    vblank_sync;
1033         fixed20_12              max_bandwidth;
1034         fixed20_12              igp_sideport_mclk;
1035         fixed20_12              igp_system_mclk;
1036         fixed20_12              igp_ht_link_clk;
1037         fixed20_12              igp_ht_link_width;
1038         fixed20_12              k8_bandwidth;
1039         fixed20_12              sideport_bandwidth;
1040         fixed20_12              ht_bandwidth;
1041         fixed20_12              core_bandwidth;
1042         fixed20_12              sclk;
1043         fixed20_12              mclk;
1044         fixed20_12              needed_bandwidth;
1045         struct radeon_power_state *power_state;
1046         /* number of valid power states */
1047         int                     num_power_states;
1048         int                     current_power_state_index;
1049         int                     current_clock_mode_index;
1050         int                     requested_power_state_index;
1051         int                     requested_clock_mode_index;
1052         int                     default_power_state_index;
1053         u32                     current_sclk;
1054         u32                     current_mclk;
1055         u16                     current_vddc;
1056         u16                     current_vddci;
1057         u32                     default_sclk;
1058         u32                     default_mclk;
1059         u16                     default_vddc;
1060         u16                     default_vddci;
1061         struct radeon_i2c_chan *i2c_bus;
1062         /* selected pm method */
1063         enum radeon_pm_method     pm_method;
1064         /* dynpm power management */
1065         struct delayed_work     dynpm_idle_work;
1066         enum radeon_dynpm_state dynpm_state;
1067         enum radeon_dynpm_action        dynpm_planned_action;
1068         unsigned long           dynpm_action_timeout;
1069         bool                    dynpm_can_upclock;
1070         bool                    dynpm_can_downclock;
1071         /* profile-based power management */
1072         enum radeon_pm_profile_type profile;
1073         int                     profile_index;
1074         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1075         /* internal thermal controller on rv6xx+ */
1076         enum radeon_int_thermal_type int_thermal_type;
1077         struct device           *int_hwmon_dev;
1078 };
1079
1080 int radeon_pm_get_type_index(struct radeon_device *rdev,
1081                              enum radeon_pm_state_type ps_type,
1082                              int instance);
1083
1084 struct r600_audio {
1085         int                     channels;
1086         int                     rate;
1087         int                     bits_per_sample;
1088         u8                      status_bits;
1089         u8                      category_code;
1090 };
1091
1092 /*
1093  * Benchmarking
1094  */
1095 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1096
1097
1098 /*
1099  * Testing
1100  */
1101 void radeon_test_moves(struct radeon_device *rdev);
1102 void radeon_test_ring_sync(struct radeon_device *rdev,
1103                            struct radeon_ring *cpA,
1104                            struct radeon_ring *cpB);
1105 void radeon_test_syncing(struct radeon_device *rdev);
1106
1107
1108 /*
1109  * Debugfs
1110  */
1111 struct radeon_debugfs {
1112         struct drm_info_list    *files;
1113         unsigned                num_files;
1114 };
1115
1116 int radeon_debugfs_add_files(struct radeon_device *rdev,
1117                              struct drm_info_list *files,
1118                              unsigned nfiles);
1119 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1120
1121
1122 /*
1123  * ASIC specific functions.
1124  */
1125 struct radeon_asic {
1126         int (*init)(struct radeon_device *rdev);
1127         void (*fini)(struct radeon_device *rdev);
1128         int (*resume)(struct radeon_device *rdev);
1129         int (*suspend)(struct radeon_device *rdev);
1130         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1131         int (*asic_reset)(struct radeon_device *rdev);
1132         /* ioctl hw specific callback. Some hw might want to perform special
1133          * operation on specific ioctl. For instance on wait idle some hw
1134          * might want to perform and HDP flush through MMIO as it seems that
1135          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1136          * through ring.
1137          */
1138         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1139         /* check if 3D engine is idle */
1140         bool (*gui_idle)(struct radeon_device *rdev);
1141         /* wait for mc_idle */
1142         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1143         /* gart */
1144         struct {
1145                 void (*tlb_flush)(struct radeon_device *rdev);
1146                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1147         } gart;
1148         /* ring specific callbacks */
1149         struct {
1150                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1151                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1152                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1153                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1154                                        struct radeon_semaphore *semaphore, bool emit_wait);
1155                 int (*cs_parse)(struct radeon_cs_parser *p);
1156                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1157                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1158                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1159                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1160         } ring[RADEON_NUM_RINGS];
1161         /* irqs */
1162         struct {
1163                 int (*set)(struct radeon_device *rdev);
1164                 int (*process)(struct radeon_device *rdev);
1165         } irq;
1166         /* displays */
1167         struct {
1168                 /* display watermarks */
1169                 void (*bandwidth_update)(struct radeon_device *rdev);
1170                 /* get frame count */
1171                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1172                 /* wait for vblank */
1173                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1174         } display;
1175         /* copy functions for bo handling */
1176         struct {
1177                 int (*blit)(struct radeon_device *rdev,
1178                             uint64_t src_offset,
1179                             uint64_t dst_offset,
1180                             unsigned num_gpu_pages,
1181                             struct radeon_fence **fence);
1182                 u32 blit_ring_index;
1183                 int (*dma)(struct radeon_device *rdev,
1184                            uint64_t src_offset,
1185                            uint64_t dst_offset,
1186                            unsigned num_gpu_pages,
1187                            struct radeon_fence **fence);
1188                 u32 dma_ring_index;
1189                 /* method used for bo copy */
1190                 int (*copy)(struct radeon_device *rdev,
1191                             uint64_t src_offset,
1192                             uint64_t dst_offset,
1193                             unsigned num_gpu_pages,
1194                             struct radeon_fence **fence);
1195                 /* ring used for bo copies */
1196                 u32 copy_ring_index;
1197         } copy;
1198         /* surfaces */
1199         struct {
1200                 int (*set_reg)(struct radeon_device *rdev, int reg,
1201                                        uint32_t tiling_flags, uint32_t pitch,
1202                                        uint32_t offset, uint32_t obj_size);
1203                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1204         } surface;
1205         /* hotplug detect */
1206         struct {
1207                 void (*init)(struct radeon_device *rdev);
1208                 void (*fini)(struct radeon_device *rdev);
1209                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1210                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1211         } hpd;
1212         /* power management */
1213         struct {
1214                 void (*misc)(struct radeon_device *rdev);
1215                 void (*prepare)(struct radeon_device *rdev);
1216                 void (*finish)(struct radeon_device *rdev);
1217                 void (*init_profile)(struct radeon_device *rdev);
1218                 void (*get_dynpm_state)(struct radeon_device *rdev);
1219                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1220                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1221                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1222                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1223                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1224                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1225                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1226         } pm;
1227         /* pageflipping */
1228         struct {
1229                 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1230                 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1231                 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1232         } pflip;
1233 };
1234
1235 /*
1236  * Asic structures
1237  */
1238 struct r100_asic {
1239         const unsigned          *reg_safe_bm;
1240         unsigned                reg_safe_bm_size;
1241         u32                     hdp_cntl;
1242 };
1243
1244 struct r300_asic {
1245         const unsigned          *reg_safe_bm;
1246         unsigned                reg_safe_bm_size;
1247         u32                     resync_scratch;
1248         u32                     hdp_cntl;
1249 };
1250
1251 struct r600_asic {
1252         unsigned                max_pipes;
1253         unsigned                max_tile_pipes;
1254         unsigned                max_simds;
1255         unsigned                max_backends;
1256         unsigned                max_gprs;
1257         unsigned                max_threads;
1258         unsigned                max_stack_entries;
1259         unsigned                max_hw_contexts;
1260         unsigned                max_gs_threads;
1261         unsigned                sx_max_export_size;
1262         unsigned                sx_max_export_pos_size;
1263         unsigned                sx_max_export_smx_size;
1264         unsigned                sq_num_cf_insts;
1265         unsigned                tiling_nbanks;
1266         unsigned                tiling_npipes;
1267         unsigned                tiling_group_size;
1268         unsigned                tile_config;
1269         unsigned                backend_map;
1270 };
1271
1272 struct rv770_asic {
1273         unsigned                max_pipes;
1274         unsigned                max_tile_pipes;
1275         unsigned                max_simds;
1276         unsigned                max_backends;
1277         unsigned                max_gprs;
1278         unsigned                max_threads;
1279         unsigned                max_stack_entries;
1280         unsigned                max_hw_contexts;
1281         unsigned                max_gs_threads;
1282         unsigned                sx_max_export_size;
1283         unsigned                sx_max_export_pos_size;
1284         unsigned                sx_max_export_smx_size;
1285         unsigned                sq_num_cf_insts;
1286         unsigned                sx_num_of_sets;
1287         unsigned                sc_prim_fifo_size;
1288         unsigned                sc_hiz_tile_fifo_size;
1289         unsigned                sc_earlyz_tile_fifo_fize;
1290         unsigned                tiling_nbanks;
1291         unsigned                tiling_npipes;
1292         unsigned                tiling_group_size;
1293         unsigned                tile_config;
1294         unsigned                backend_map;
1295 };
1296
1297 struct evergreen_asic {
1298         unsigned num_ses;
1299         unsigned max_pipes;
1300         unsigned max_tile_pipes;
1301         unsigned max_simds;
1302         unsigned max_backends;
1303         unsigned max_gprs;
1304         unsigned max_threads;
1305         unsigned max_stack_entries;
1306         unsigned max_hw_contexts;
1307         unsigned max_gs_threads;
1308         unsigned sx_max_export_size;
1309         unsigned sx_max_export_pos_size;
1310         unsigned sx_max_export_smx_size;
1311         unsigned sq_num_cf_insts;
1312         unsigned sx_num_of_sets;
1313         unsigned sc_prim_fifo_size;
1314         unsigned sc_hiz_tile_fifo_size;
1315         unsigned sc_earlyz_tile_fifo_size;
1316         unsigned tiling_nbanks;
1317         unsigned tiling_npipes;
1318         unsigned tiling_group_size;
1319         unsigned tile_config;
1320         unsigned backend_map;
1321 };
1322
1323 struct cayman_asic {
1324         unsigned max_shader_engines;
1325         unsigned max_pipes_per_simd;
1326         unsigned max_tile_pipes;
1327         unsigned max_simds_per_se;
1328         unsigned max_backends_per_se;
1329         unsigned max_texture_channel_caches;
1330         unsigned max_gprs;
1331         unsigned max_threads;
1332         unsigned max_gs_threads;
1333         unsigned max_stack_entries;
1334         unsigned sx_num_of_sets;
1335         unsigned sx_max_export_size;
1336         unsigned sx_max_export_pos_size;
1337         unsigned sx_max_export_smx_size;
1338         unsigned max_hw_contexts;
1339         unsigned sq_num_cf_insts;
1340         unsigned sc_prim_fifo_size;
1341         unsigned sc_hiz_tile_fifo_size;
1342         unsigned sc_earlyz_tile_fifo_size;
1343
1344         unsigned num_shader_engines;
1345         unsigned num_shader_pipes_per_simd;
1346         unsigned num_tile_pipes;
1347         unsigned num_simds_per_se;
1348         unsigned num_backends_per_se;
1349         unsigned backend_disable_mask_per_asic;
1350         unsigned backend_map;
1351         unsigned num_texture_channel_caches;
1352         unsigned mem_max_burst_length_bytes;
1353         unsigned mem_row_size_in_kb;
1354         unsigned shader_engine_tile_size;
1355         unsigned num_gpus;
1356         unsigned multi_gpu_tile_size;
1357
1358         unsigned tile_config;
1359 };
1360
1361 struct si_asic {
1362         unsigned max_shader_engines;
1363         unsigned max_tile_pipes;
1364         unsigned max_cu_per_sh;
1365         unsigned max_sh_per_se;
1366         unsigned max_backends_per_se;
1367         unsigned max_texture_channel_caches;
1368         unsigned max_gprs;
1369         unsigned max_gs_threads;
1370         unsigned max_hw_contexts;
1371         unsigned sc_prim_fifo_size_frontend;
1372         unsigned sc_prim_fifo_size_backend;
1373         unsigned sc_hiz_tile_fifo_size;
1374         unsigned sc_earlyz_tile_fifo_size;
1375
1376         unsigned num_tile_pipes;
1377         unsigned num_backends_per_se;
1378         unsigned backend_disable_mask_per_asic;
1379         unsigned backend_map;
1380         unsigned num_texture_channel_caches;
1381         unsigned mem_max_burst_length_bytes;
1382         unsigned mem_row_size_in_kb;
1383         unsigned shader_engine_tile_size;
1384         unsigned num_gpus;
1385         unsigned multi_gpu_tile_size;
1386
1387         unsigned tile_config;
1388 };
1389
1390 union radeon_asic_config {
1391         struct r300_asic        r300;
1392         struct r100_asic        r100;
1393         struct r600_asic        r600;
1394         struct rv770_asic       rv770;
1395         struct evergreen_asic   evergreen;
1396         struct cayman_asic      cayman;
1397         struct si_asic          si;
1398 };
1399
1400 /*
1401  * asic initizalization from radeon_asic.c
1402  */
1403 void radeon_agp_disable(struct radeon_device *rdev);
1404 int radeon_asic_init(struct radeon_device *rdev);
1405
1406
1407 /*
1408  * IOCTL.
1409  */
1410 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1411                           struct drm_file *filp);
1412 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1413                             struct drm_file *filp);
1414 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1415                          struct drm_file *file_priv);
1416 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1417                            struct drm_file *file_priv);
1418 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1419                             struct drm_file *file_priv);
1420 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1421                            struct drm_file *file_priv);
1422 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1423                                 struct drm_file *filp);
1424 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1425                           struct drm_file *filp);
1426 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1427                           struct drm_file *filp);
1428 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1429                               struct drm_file *filp);
1430 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1431                           struct drm_file *filp);
1432 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1433 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1434                                 struct drm_file *filp);
1435 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1436                                 struct drm_file *filp);
1437
1438 /* VRAM scratch page for HDP bug, default vram page */
1439 struct r600_vram_scratch {
1440         struct radeon_bo                *robj;
1441         volatile uint32_t               *ptr;
1442         u64                             gpu_addr;
1443 };
1444
1445
1446 /*
1447  * Core structure, functions and helpers.
1448  */
1449 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1450 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1451
1452 struct radeon_device {
1453         struct device                   *dev;
1454         struct drm_device               *ddev;
1455         struct pci_dev                  *pdev;
1456         struct rw_semaphore             exclusive_lock;
1457         /* ASIC */
1458         union radeon_asic_config        config;
1459         enum radeon_family              family;
1460         unsigned long                   flags;
1461         int                             usec_timeout;
1462         enum radeon_pll_errata          pll_errata;
1463         int                             num_gb_pipes;
1464         int                             num_z_pipes;
1465         int                             disp_priority;
1466         /* BIOS */
1467         uint8_t                         *bios;
1468         bool                            is_atom_bios;
1469         uint16_t                        bios_header_start;
1470         struct radeon_bo                *stollen_vga_memory;
1471         /* Register mmio */
1472         resource_size_t                 rmmio_base;
1473         resource_size_t                 rmmio_size;
1474         void __iomem                    *rmmio;
1475         radeon_rreg_t                   mc_rreg;
1476         radeon_wreg_t                   mc_wreg;
1477         radeon_rreg_t                   pll_rreg;
1478         radeon_wreg_t                   pll_wreg;
1479         uint32_t                        pcie_reg_mask;
1480         radeon_rreg_t                   pciep_rreg;
1481         radeon_wreg_t                   pciep_wreg;
1482         /* io port */
1483         void __iomem                    *rio_mem;
1484         resource_size_t                 rio_mem_size;
1485         struct radeon_clock             clock;
1486         struct radeon_mc                mc;
1487         struct radeon_gart              gart;
1488         struct radeon_mode_info         mode_info;
1489         struct radeon_scratch           scratch;
1490         struct radeon_mman              mman;
1491         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
1492         wait_queue_head_t               fence_queue;
1493         struct mutex                    ring_lock;
1494         struct radeon_ring              ring[RADEON_NUM_RINGS];
1495         bool                            ib_pool_ready;
1496         struct radeon_sa_manager        ring_tmp_bo;
1497         struct radeon_irq               irq;
1498         struct radeon_asic              *asic;
1499         struct radeon_gem               gem;
1500         struct radeon_pm                pm;
1501         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1502         struct radeon_wb                wb;
1503         struct radeon_dummy_page        dummy_page;
1504         bool                            shutdown;
1505         bool                            suspend;
1506         bool                            need_dma32;
1507         bool                            accel_working;
1508         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1509         const struct firmware *me_fw;   /* all family ME firmware */
1510         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1511         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1512         const struct firmware *mc_fw;   /* NI MC firmware */
1513         const struct firmware *ce_fw;   /* SI CE firmware */
1514         struct r600_blit r600_blit;
1515         struct r600_vram_scratch vram_scratch;
1516         int msi_enabled; /* msi enabled */
1517         struct r600_ih ih; /* r6/700 interrupt ring */
1518         struct si_rlc rlc;
1519         struct work_struct hotplug_work;
1520         struct work_struct audio_work;
1521         int num_crtc; /* number of crtcs */
1522         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1523         bool audio_enabled;
1524         struct r600_audio audio_status; /* audio stuff */
1525         struct notifier_block acpi_nb;
1526         /* only one userspace can use Hyperz features or CMASK at a time */
1527         struct drm_file *hyperz_filp;
1528         struct drm_file *cmask_filp;
1529         /* i2c buses */
1530         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1531         /* debugfs */
1532         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1533         unsigned                debugfs_count;
1534         /* virtual memory */
1535         struct radeon_vm_manager        vm_manager;
1536 };
1537
1538 int radeon_device_init(struct radeon_device *rdev,
1539                        struct drm_device *ddev,
1540                        struct pci_dev *pdev,
1541                        uint32_t flags);
1542 void radeon_device_fini(struct radeon_device *rdev);
1543 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1544
1545 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1546 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1547 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1548 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1549
1550 /*
1551  * Cast helper
1552  */
1553 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1554
1555 /*
1556  * Registers read & write functions.
1557  */
1558 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1559 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1560 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1561 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1562 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1563 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1564 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1565 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1566 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1567 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1568 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1569 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1570 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1571 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1572 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1573 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1574 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1575 #define WREG32_P(reg, val, mask)                                \
1576         do {                                                    \
1577                 uint32_t tmp_ = RREG32(reg);                    \
1578                 tmp_ &= (mask);                                 \
1579                 tmp_ |= ((val) & ~(mask));                      \
1580                 WREG32(reg, tmp_);                              \
1581         } while (0)
1582 #define WREG32_PLL_P(reg, val, mask)                            \
1583         do {                                                    \
1584                 uint32_t tmp_ = RREG32_PLL(reg);                \
1585                 tmp_ &= (mask);                                 \
1586                 tmp_ |= ((val) & ~(mask));                      \
1587                 WREG32_PLL(reg, tmp_);                          \
1588         } while (0)
1589 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1590 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1591 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1592
1593 /*
1594  * Indirect registers accessor
1595  */
1596 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1597 {
1598         uint32_t r;
1599
1600         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1601         r = RREG32(RADEON_PCIE_DATA);
1602         return r;
1603 }
1604
1605 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1606 {
1607         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1608         WREG32(RADEON_PCIE_DATA, (v));
1609 }
1610
1611 void r100_pll_errata_after_index(struct radeon_device *rdev);
1612
1613
1614 /*
1615  * ASICs helpers.
1616  */
1617 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1618                             (rdev->pdev->device == 0x5969))
1619 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1620                 (rdev->family == CHIP_RV200) || \
1621                 (rdev->family == CHIP_RS100) || \
1622                 (rdev->family == CHIP_RS200) || \
1623                 (rdev->family == CHIP_RV250) || \
1624                 (rdev->family == CHIP_RV280) || \
1625                 (rdev->family == CHIP_RS300))
1626 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1627                 (rdev->family == CHIP_RV350) ||                 \
1628                 (rdev->family == CHIP_R350)  ||                 \
1629                 (rdev->family == CHIP_RV380) ||                 \
1630                 (rdev->family == CHIP_R420)  ||                 \
1631                 (rdev->family == CHIP_R423)  ||                 \
1632                 (rdev->family == CHIP_RV410) ||                 \
1633                 (rdev->family == CHIP_RS400) ||                 \
1634                 (rdev->family == CHIP_RS480))
1635 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1636                 (rdev->ddev->pdev->device == 0x9443) || \
1637                 (rdev->ddev->pdev->device == 0x944B) || \
1638                 (rdev->ddev->pdev->device == 0x9506) || \
1639                 (rdev->ddev->pdev->device == 0x9509) || \
1640                 (rdev->ddev->pdev->device == 0x950F) || \
1641                 (rdev->ddev->pdev->device == 0x689C) || \
1642                 (rdev->ddev->pdev->device == 0x689D))
1643 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1644 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1645                             (rdev->family == CHIP_RS690)  ||    \
1646                             (rdev->family == CHIP_RS740)  ||    \
1647                             (rdev->family >= CHIP_R600))
1648 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1649 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1650 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1651 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1652                              (rdev->flags & RADEON_IS_IGP))
1653 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1654 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1655 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1656                              (rdev->flags & RADEON_IS_IGP))
1657
1658 /*
1659  * BIOS helpers.
1660  */
1661 #define RBIOS8(i) (rdev->bios[i])
1662 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1663 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1664
1665 int radeon_combios_init(struct radeon_device *rdev);
1666 void radeon_combios_fini(struct radeon_device *rdev);
1667 int radeon_atombios_init(struct radeon_device *rdev);
1668 void radeon_atombios_fini(struct radeon_device *rdev);
1669
1670
1671 /*
1672  * RING helpers.
1673  */
1674 #if DRM_DEBUG_CODE == 0
1675 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1676 {
1677         ring->ring[ring->wptr++] = v;
1678         ring->wptr &= ring->ptr_mask;
1679         ring->count_dw--;
1680         ring->ring_free_dw--;
1681 }
1682 #else
1683 /* With debugging this is just too big to inline */
1684 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1685 #endif
1686
1687 /*
1688  * ASICs macro.
1689  */
1690 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1691 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1692 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1693 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1694 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1695 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1696 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1697 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1698 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1699 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1700 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1701 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1702 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1703 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1704 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1705 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1706 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1707 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1708 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1709 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1710 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1711 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1712 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1713 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1714 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1715 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1716 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1717 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1718 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1719 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1720 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1721 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1722 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1723 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1724 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1725 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1726 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1727 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1728 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1729 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1730 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1731 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1732 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1733 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1734 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1735 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1736 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1737 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1738 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1739 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1740 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1741
1742 /* Common functions */
1743 /* AGP */
1744 extern int radeon_gpu_reset(struct radeon_device *rdev);
1745 extern void radeon_agp_disable(struct radeon_device *rdev);
1746 extern int radeon_modeset_init(struct radeon_device *rdev);
1747 extern void radeon_modeset_fini(struct radeon_device *rdev);
1748 extern bool radeon_card_posted(struct radeon_device *rdev);
1749 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1750 extern void radeon_update_display_priority(struct radeon_device *rdev);
1751 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1752 extern void radeon_scratch_init(struct radeon_device *rdev);
1753 extern void radeon_wb_fini(struct radeon_device *rdev);
1754 extern int radeon_wb_init(struct radeon_device *rdev);
1755 extern void radeon_wb_disable(struct radeon_device *rdev);
1756 extern void radeon_surface_init(struct radeon_device *rdev);
1757 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1758 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1759 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1760 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1761 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1762 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1763 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1764 extern int radeon_resume_kms(struct drm_device *dev);
1765 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1766 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1767
1768 /*
1769  * vm
1770  */
1771 int radeon_vm_manager_init(struct radeon_device *rdev);
1772 void radeon_vm_manager_fini(struct radeon_device *rdev);
1773 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1774 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1775 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1776 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1777 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1778                             struct radeon_vm *vm,
1779                             struct radeon_bo *bo,
1780                             struct ttm_mem_reg *mem);
1781 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1782                              struct radeon_bo *bo);
1783 int radeon_vm_bo_add(struct radeon_device *rdev,
1784                      struct radeon_vm *vm,
1785                      struct radeon_bo *bo,
1786                      uint64_t offset,
1787                      uint32_t flags);
1788 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1789                      struct radeon_vm *vm,
1790                      struct radeon_bo *bo);
1791
1792 /* audio */
1793 void r600_audio_update_hdmi(struct work_struct *work);
1794
1795 /*
1796  * R600 vram scratch functions
1797  */
1798 int r600_vram_scratch_init(struct radeon_device *rdev);
1799 void r600_vram_scratch_fini(struct radeon_device *rdev);
1800
1801 /*
1802  * r600 cs checking helper
1803  */
1804 unsigned r600_mip_minify(unsigned size, unsigned level);
1805 bool r600_fmt_is_valid_color(u32 format);
1806 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1807 int r600_fmt_get_blocksize(u32 format);
1808 int r600_fmt_get_nblocksx(u32 format, u32 w);
1809 int r600_fmt_get_nblocksy(u32 format, u32 h);
1810
1811 /*
1812  * r600 functions used by radeon_encoder.c
1813  */
1814 struct radeon_hdmi_acr {
1815         u32 clock;
1816
1817         int n_32khz;
1818         int cts_32khz;
1819
1820         int n_44_1khz;
1821         int cts_44_1khz;
1822
1823         int n_48khz;
1824         int cts_48khz;
1825
1826 };
1827
1828 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1829
1830 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1831 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1832 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1833 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1834                                      u32 tiling_pipe_num,
1835                                      u32 max_rb_num,
1836                                      u32 total_max_rb_num,
1837                                      u32 enabled_rb_mask);
1838
1839 /*
1840  * evergreen functions used by radeon_encoder.c
1841  */
1842
1843 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1844
1845 extern int ni_init_microcode(struct radeon_device *rdev);
1846 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1847
1848 /* radeon_acpi.c */
1849 #if defined(CONFIG_ACPI)
1850 extern int radeon_acpi_init(struct radeon_device *rdev);
1851 #else
1852 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1853 #endif
1854
1855 #include "radeon_object.h"
1856
1857 #endif