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drm/radeon: precompute fence cpu/gpu addr once v3
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /*
111 * Errata workarounds.
112 */
113 enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
117 };
118
119
120 struct radeon_device;
121
122
123 /*
124 * BIOS.
125 */
126 #define ATRM_BIOS_PAGE 4096
127
128 #if defined(CONFIG_VGA_SWITCHEROO)
129 bool radeon_atrm_supported(struct pci_dev *pdev);
130 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
131 #else
132 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133 {
134 return false;
135 }
136
137 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
138 return -EINVAL;
139 }
140 #endif
141 bool radeon_get_bios(struct radeon_device *rdev);
142
143
144 /*
145 * Dummy page
146 */
147 struct radeon_dummy_page {
148 struct page *page;
149 dma_addr_t addr;
150 };
151 int radeon_dummy_page_init(struct radeon_device *rdev);
152 void radeon_dummy_page_fini(struct radeon_device *rdev);
153
154
155 /*
156 * Clocks
157 */
158 struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll dcpll;
162 struct radeon_pll spll;
163 struct radeon_pll mpll;
164 /* 10 Khz units */
165 uint32_t default_mclk;
166 uint32_t default_sclk;
167 uint32_t default_dispclk;
168 uint32_t dp_extclk;
169 uint32_t max_pixel_clock;
170 };
171
172 /*
173 * Power management
174 */
175 int radeon_pm_init(struct radeon_device *rdev);
176 void radeon_pm_fini(struct radeon_device *rdev);
177 void radeon_pm_compute_clocks(struct radeon_device *rdev);
178 void radeon_pm_suspend(struct radeon_device *rdev);
179 void radeon_pm_resume(struct radeon_device *rdev);
180 void radeon_combios_get_power_modes(struct radeon_device *rdev);
181 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
182 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
183 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
184 void rs690_pm_info(struct radeon_device *rdev);
185 extern int rv6xx_get_temp(struct radeon_device *rdev);
186 extern int rv770_get_temp(struct radeon_device *rdev);
187 extern int evergreen_get_temp(struct radeon_device *rdev);
188 extern int sumo_get_temp(struct radeon_device *rdev);
189
190 /*
191 * Fences.
192 */
193 struct radeon_fence_driver {
194 uint32_t scratch_reg;
195 uint64_t gpu_addr;
196 volatile uint32_t *cpu_addr;
197 atomic_t seq;
198 uint32_t last_seq;
199 unsigned long last_jiffies;
200 unsigned long last_timeout;
201 wait_queue_head_t queue;
202 struct list_head created;
203 struct list_head emitted;
204 struct list_head signaled;
205 bool initialized;
206 };
207
208 struct radeon_fence {
209 struct radeon_device *rdev;
210 struct kref kref;
211 struct list_head list;
212 /* protected by radeon_fence.lock */
213 uint32_t seq;
214 bool emitted;
215 bool signaled;
216 /* RB, DMA, etc. */
217 int ring;
218 };
219
220 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
221 int radeon_fence_driver_init(struct radeon_device *rdev);
222 void radeon_fence_driver_fini(struct radeon_device *rdev);
223 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
224 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
225 void radeon_fence_process(struct radeon_device *rdev, int ring);
226 bool radeon_fence_signaled(struct radeon_fence *fence);
227 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
228 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
229 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
230 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
231 void radeon_fence_unref(struct radeon_fence **fence);
232 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
233
234 /*
235 * Semaphores.
236 */
237 struct radeon_ring;
238
239 struct radeon_semaphore_driver {
240 rwlock_t lock;
241 struct list_head free;
242 };
243
244 struct radeon_semaphore {
245 struct radeon_bo *robj;
246 struct list_head list;
247 uint64_t gpu_addr;
248 };
249
250 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
251 int radeon_semaphore_create(struct radeon_device *rdev,
252 struct radeon_semaphore **semaphore);
253 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
254 struct radeon_semaphore *semaphore);
255 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
256 struct radeon_semaphore *semaphore);
257 void radeon_semaphore_free(struct radeon_device *rdev,
258 struct radeon_semaphore *semaphore);
259
260 /*
261 * Tiling registers
262 */
263 struct radeon_surface_reg {
264 struct radeon_bo *bo;
265 };
266
267 #define RADEON_GEM_MAX_SURFACES 8
268
269 /*
270 * TTM.
271 */
272 struct radeon_mman {
273 struct ttm_bo_global_ref bo_global_ref;
274 struct drm_global_reference mem_global_ref;
275 struct ttm_bo_device bdev;
276 bool mem_global_referenced;
277 bool initialized;
278 };
279
280 struct radeon_bo {
281 /* Protected by gem.mutex */
282 struct list_head list;
283 /* Protected by tbo.reserved */
284 u32 placements[3];
285 struct ttm_placement placement;
286 struct ttm_buffer_object tbo;
287 struct ttm_bo_kmap_obj kmap;
288 unsigned pin_count;
289 void *kptr;
290 u32 tiling_flags;
291 u32 pitch;
292 int surface_reg;
293 /* Constant after initialization */
294 struct radeon_device *rdev;
295 struct drm_gem_object gem_base;
296 };
297 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
298
299 struct radeon_bo_list {
300 struct ttm_validate_buffer tv;
301 struct radeon_bo *bo;
302 uint64_t gpu_offset;
303 unsigned rdomain;
304 unsigned wdomain;
305 u32 tiling_flags;
306 };
307
308 /*
309 * GEM objects.
310 */
311 struct radeon_gem {
312 struct mutex mutex;
313 struct list_head objects;
314 };
315
316 int radeon_gem_init(struct radeon_device *rdev);
317 void radeon_gem_fini(struct radeon_device *rdev);
318 int radeon_gem_object_create(struct radeon_device *rdev, int size,
319 int alignment, int initial_domain,
320 bool discardable, bool kernel,
321 struct drm_gem_object **obj);
322 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
323 uint64_t *gpu_addr);
324 void radeon_gem_object_unpin(struct drm_gem_object *obj);
325
326 int radeon_mode_dumb_create(struct drm_file *file_priv,
327 struct drm_device *dev,
328 struct drm_mode_create_dumb *args);
329 int radeon_mode_dumb_mmap(struct drm_file *filp,
330 struct drm_device *dev,
331 uint32_t handle, uint64_t *offset_p);
332 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
333 struct drm_device *dev,
334 uint32_t handle);
335
336 /*
337 * GART structures, functions & helpers
338 */
339 struct radeon_mc;
340
341 #define RADEON_GPU_PAGE_SIZE 4096
342 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
343 #define RADEON_GPU_PAGE_SHIFT 12
344
345 struct radeon_gart {
346 dma_addr_t table_addr;
347 struct radeon_bo *robj;
348 void *ptr;
349 unsigned num_gpu_pages;
350 unsigned num_cpu_pages;
351 unsigned table_size;
352 struct page **pages;
353 dma_addr_t *pages_addr;
354 bool ready;
355 };
356
357 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
358 void radeon_gart_table_ram_free(struct radeon_device *rdev);
359 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
360 void radeon_gart_table_vram_free(struct radeon_device *rdev);
361 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
362 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
363 int radeon_gart_init(struct radeon_device *rdev);
364 void radeon_gart_fini(struct radeon_device *rdev);
365 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
366 int pages);
367 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
368 int pages, struct page **pagelist,
369 dma_addr_t *dma_addr);
370 void radeon_gart_restore(struct radeon_device *rdev);
371
372
373 /*
374 * GPU MC structures, functions & helpers
375 */
376 struct radeon_mc {
377 resource_size_t aper_size;
378 resource_size_t aper_base;
379 resource_size_t agp_base;
380 /* for some chips with <= 32MB we need to lie
381 * about vram size near mc fb location */
382 u64 mc_vram_size;
383 u64 visible_vram_size;
384 u64 gtt_size;
385 u64 gtt_start;
386 u64 gtt_end;
387 u64 vram_start;
388 u64 vram_end;
389 unsigned vram_width;
390 u64 real_vram_size;
391 int vram_mtrr;
392 bool vram_is_ddr;
393 bool igp_sideport_enabled;
394 u64 gtt_base_align;
395 };
396
397 bool radeon_combios_sideport_present(struct radeon_device *rdev);
398 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
399
400 /*
401 * GPU scratch registers structures, functions & helpers
402 */
403 struct radeon_scratch {
404 unsigned num_reg;
405 uint32_t reg_base;
406 bool free[32];
407 uint32_t reg[32];
408 };
409
410 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
411 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
412
413
414 /*
415 * IRQS.
416 */
417
418 struct radeon_unpin_work {
419 struct work_struct work;
420 struct radeon_device *rdev;
421 int crtc_id;
422 struct radeon_fence *fence;
423 struct drm_pending_vblank_event *event;
424 struct radeon_bo *old_rbo;
425 u64 new_crtc_base;
426 };
427
428 struct r500_irq_stat_regs {
429 u32 disp_int;
430 };
431
432 struct r600_irq_stat_regs {
433 u32 disp_int;
434 u32 disp_int_cont;
435 u32 disp_int_cont2;
436 u32 d1grph_int;
437 u32 d2grph_int;
438 };
439
440 struct evergreen_irq_stat_regs {
441 u32 disp_int;
442 u32 disp_int_cont;
443 u32 disp_int_cont2;
444 u32 disp_int_cont3;
445 u32 disp_int_cont4;
446 u32 disp_int_cont5;
447 u32 d1grph_int;
448 u32 d2grph_int;
449 u32 d3grph_int;
450 u32 d4grph_int;
451 u32 d5grph_int;
452 u32 d6grph_int;
453 };
454
455 union radeon_irq_stat_regs {
456 struct r500_irq_stat_regs r500;
457 struct r600_irq_stat_regs r600;
458 struct evergreen_irq_stat_regs evergreen;
459 };
460
461 #define RADEON_MAX_HPD_PINS 6
462 #define RADEON_MAX_CRTCS 6
463 #define RADEON_MAX_HDMI_BLOCKS 2
464
465 struct radeon_irq {
466 bool installed;
467 bool sw_int;
468 bool crtc_vblank_int[RADEON_MAX_CRTCS];
469 bool pflip[RADEON_MAX_CRTCS];
470 wait_queue_head_t vblank_queue;
471 bool hpd[RADEON_MAX_HPD_PINS];
472 bool gui_idle;
473 bool gui_idle_acked;
474 wait_queue_head_t idle_queue;
475 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
476 spinlock_t sw_lock;
477 int sw_refcount;
478 union radeon_irq_stat_regs stat_regs;
479 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
480 int pflip_refcount[RADEON_MAX_CRTCS];
481 };
482
483 int radeon_irq_kms_init(struct radeon_device *rdev);
484 void radeon_irq_kms_fini(struct radeon_device *rdev);
485 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
486 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
487 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
488 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
489
490 /*
491 * CP & rings.
492 */
493
494 /* max number of rings */
495 #define RADEON_NUM_RINGS 3
496
497 /* internal ring indices */
498 /* r1xx+ has gfx CP ring */
499 #define RADEON_RING_TYPE_GFX_INDEX 0
500
501 /* cayman has 2 compute CP rings */
502 #define CAYMAN_RING_TYPE_CP1_INDEX 1
503 #define CAYMAN_RING_TYPE_CP2_INDEX 2
504
505 struct radeon_ib {
506 struct list_head list;
507 unsigned idx;
508 uint64_t gpu_addr;
509 struct radeon_fence *fence;
510 uint32_t *ptr;
511 uint32_t length_dw;
512 bool free;
513 };
514
515 /*
516 * locking -
517 * mutex protects scheduled_ibs, ready, alloc_bm
518 */
519 struct radeon_ib_pool {
520 struct mutex mutex;
521 struct radeon_bo *robj;
522 struct list_head bogus_ib;
523 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
524 bool ready;
525 unsigned head_id;
526 };
527
528 struct radeon_ring {
529 struct radeon_bo *ring_obj;
530 volatile uint32_t *ring;
531 unsigned rptr;
532 unsigned rptr_offs;
533 unsigned rptr_reg;
534 unsigned wptr;
535 unsigned wptr_old;
536 unsigned wptr_reg;
537 unsigned ring_size;
538 unsigned ring_free_dw;
539 int count_dw;
540 uint64_t gpu_addr;
541 uint32_t align_mask;
542 uint32_t ptr_mask;
543 struct mutex mutex;
544 bool ready;
545 };
546
547 /*
548 * R6xx+ IH ring
549 */
550 struct r600_ih {
551 struct radeon_bo *ring_obj;
552 volatile uint32_t *ring;
553 unsigned rptr;
554 unsigned rptr_offs;
555 unsigned wptr;
556 unsigned wptr_old;
557 unsigned ring_size;
558 uint64_t gpu_addr;
559 uint32_t ptr_mask;
560 spinlock_t lock;
561 bool enabled;
562 };
563
564 struct r600_blit_cp_primitives {
565 void (*set_render_target)(struct radeon_device *rdev, int format,
566 int w, int h, u64 gpu_addr);
567 void (*cp_set_surface_sync)(struct radeon_device *rdev,
568 u32 sync_type, u32 size,
569 u64 mc_addr);
570 void (*set_shaders)(struct radeon_device *rdev);
571 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
572 void (*set_tex_resource)(struct radeon_device *rdev,
573 int format, int w, int h, int pitch,
574 u64 gpu_addr, u32 size);
575 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
576 int x2, int y2);
577 void (*draw_auto)(struct radeon_device *rdev);
578 void (*set_default_state)(struct radeon_device *rdev);
579 };
580
581 struct r600_blit {
582 struct mutex mutex;
583 struct radeon_bo *shader_obj;
584 struct r600_blit_cp_primitives primitives;
585 int max_dim;
586 int ring_size_common;
587 int ring_size_per_loop;
588 u64 shader_gpu_addr;
589 u32 vs_offset, ps_offset;
590 u32 state_offset;
591 u32 state_len;
592 u32 vb_used, vb_total;
593 struct radeon_ib *vb_ib;
594 };
595
596 void r600_blit_suspend(struct radeon_device *rdev);
597
598 int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
599 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
600 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
601 int radeon_ib_pool_init(struct radeon_device *rdev);
602 void radeon_ib_pool_fini(struct radeon_device *rdev);
603 int radeon_ib_test(struct radeon_device *rdev);
604 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
605 /* Ring access between begin & end cannot sleep */
606 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
607 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
608 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
609 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
610 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
611 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
612 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
613 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
614 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
615 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg);
616 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
617
618
619 /*
620 * CS.
621 */
622 struct radeon_cs_reloc {
623 struct drm_gem_object *gobj;
624 struct radeon_bo *robj;
625 struct radeon_bo_list lobj;
626 uint32_t handle;
627 uint32_t flags;
628 };
629
630 struct radeon_cs_chunk {
631 uint32_t chunk_id;
632 uint32_t length_dw;
633 int kpage_idx[2];
634 uint32_t *kpage[2];
635 uint32_t *kdata;
636 void __user *user_ptr;
637 int last_copied_page;
638 int last_page_index;
639 };
640
641 struct radeon_cs_parser {
642 struct device *dev;
643 struct radeon_device *rdev;
644 struct drm_file *filp;
645 /* chunks */
646 unsigned nchunks;
647 struct radeon_cs_chunk *chunks;
648 uint64_t *chunks_array;
649 /* IB */
650 unsigned idx;
651 /* relocations */
652 unsigned nrelocs;
653 struct radeon_cs_reloc *relocs;
654 struct radeon_cs_reloc **relocs_ptr;
655 struct list_head validated;
656 /* indices of various chunks */
657 int chunk_ib_idx;
658 int chunk_relocs_idx;
659 struct radeon_ib *ib;
660 void *track;
661 unsigned family;
662 int parser_error;
663 bool keep_tiling_flags;
664 };
665
666 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
667 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
668 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
669
670 struct radeon_cs_packet {
671 unsigned idx;
672 unsigned type;
673 unsigned reg;
674 unsigned opcode;
675 int count;
676 unsigned one_reg_wr;
677 };
678
679 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
680 struct radeon_cs_packet *pkt,
681 unsigned idx, unsigned reg);
682 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
683 struct radeon_cs_packet *pkt);
684
685
686 /*
687 * AGP
688 */
689 int radeon_agp_init(struct radeon_device *rdev);
690 void radeon_agp_resume(struct radeon_device *rdev);
691 void radeon_agp_suspend(struct radeon_device *rdev);
692 void radeon_agp_fini(struct radeon_device *rdev);
693
694
695 /*
696 * Writeback
697 */
698 struct radeon_wb {
699 struct radeon_bo *wb_obj;
700 volatile uint32_t *wb;
701 uint64_t gpu_addr;
702 bool enabled;
703 bool use_event;
704 };
705
706 #define RADEON_WB_SCRATCH_OFFSET 0
707 #define RADEON_WB_CP_RPTR_OFFSET 1024
708 #define RADEON_WB_CP1_RPTR_OFFSET 1280
709 #define RADEON_WB_CP2_RPTR_OFFSET 1536
710 #define R600_WB_IH_WPTR_OFFSET 2048
711 #define R600_WB_EVENT_OFFSET 3072
712
713 /**
714 * struct radeon_pm - power management datas
715 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
716 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
717 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
718 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
719 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
720 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
721 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
722 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
723 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
724 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
725 * @needed_bandwidth: current bandwidth needs
726 *
727 * It keeps track of various data needed to take powermanagement decision.
728 * Bandwidth need is used to determine minimun clock of the GPU and memory.
729 * Equation between gpu/memory clock and available bandwidth is hw dependent
730 * (type of memory, bus size, efficiency, ...)
731 */
732
733 enum radeon_pm_method {
734 PM_METHOD_PROFILE,
735 PM_METHOD_DYNPM,
736 };
737
738 enum radeon_dynpm_state {
739 DYNPM_STATE_DISABLED,
740 DYNPM_STATE_MINIMUM,
741 DYNPM_STATE_PAUSED,
742 DYNPM_STATE_ACTIVE,
743 DYNPM_STATE_SUSPENDED,
744 };
745 enum radeon_dynpm_action {
746 DYNPM_ACTION_NONE,
747 DYNPM_ACTION_MINIMUM,
748 DYNPM_ACTION_DOWNCLOCK,
749 DYNPM_ACTION_UPCLOCK,
750 DYNPM_ACTION_DEFAULT
751 };
752
753 enum radeon_voltage_type {
754 VOLTAGE_NONE = 0,
755 VOLTAGE_GPIO,
756 VOLTAGE_VDDC,
757 VOLTAGE_SW
758 };
759
760 enum radeon_pm_state_type {
761 POWER_STATE_TYPE_DEFAULT,
762 POWER_STATE_TYPE_POWERSAVE,
763 POWER_STATE_TYPE_BATTERY,
764 POWER_STATE_TYPE_BALANCED,
765 POWER_STATE_TYPE_PERFORMANCE,
766 };
767
768 enum radeon_pm_profile_type {
769 PM_PROFILE_DEFAULT,
770 PM_PROFILE_AUTO,
771 PM_PROFILE_LOW,
772 PM_PROFILE_MID,
773 PM_PROFILE_HIGH,
774 };
775
776 #define PM_PROFILE_DEFAULT_IDX 0
777 #define PM_PROFILE_LOW_SH_IDX 1
778 #define PM_PROFILE_MID_SH_IDX 2
779 #define PM_PROFILE_HIGH_SH_IDX 3
780 #define PM_PROFILE_LOW_MH_IDX 4
781 #define PM_PROFILE_MID_MH_IDX 5
782 #define PM_PROFILE_HIGH_MH_IDX 6
783 #define PM_PROFILE_MAX 7
784
785 struct radeon_pm_profile {
786 int dpms_off_ps_idx;
787 int dpms_on_ps_idx;
788 int dpms_off_cm_idx;
789 int dpms_on_cm_idx;
790 };
791
792 enum radeon_int_thermal_type {
793 THERMAL_TYPE_NONE,
794 THERMAL_TYPE_RV6XX,
795 THERMAL_TYPE_RV770,
796 THERMAL_TYPE_EVERGREEN,
797 THERMAL_TYPE_SUMO,
798 THERMAL_TYPE_NI,
799 };
800
801 struct radeon_voltage {
802 enum radeon_voltage_type type;
803 /* gpio voltage */
804 struct radeon_gpio_rec gpio;
805 u32 delay; /* delay in usec from voltage drop to sclk change */
806 bool active_high; /* voltage drop is active when bit is high */
807 /* VDDC voltage */
808 u8 vddc_id; /* index into vddc voltage table */
809 u8 vddci_id; /* index into vddci voltage table */
810 bool vddci_enabled;
811 /* r6xx+ sw */
812 u16 voltage;
813 /* evergreen+ vddci */
814 u16 vddci;
815 };
816
817 /* clock mode flags */
818 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
819
820 struct radeon_pm_clock_info {
821 /* memory clock */
822 u32 mclk;
823 /* engine clock */
824 u32 sclk;
825 /* voltage info */
826 struct radeon_voltage voltage;
827 /* standardized clock flags */
828 u32 flags;
829 };
830
831 /* state flags */
832 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
833
834 struct radeon_power_state {
835 enum radeon_pm_state_type type;
836 struct radeon_pm_clock_info *clock_info;
837 /* number of valid clock modes in this power state */
838 int num_clock_modes;
839 struct radeon_pm_clock_info *default_clock_mode;
840 /* standardized state flags */
841 u32 flags;
842 u32 misc; /* vbios specific flags */
843 u32 misc2; /* vbios specific flags */
844 int pcie_lanes; /* pcie lanes */
845 };
846
847 /*
848 * Some modes are overclocked by very low value, accept them
849 */
850 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
851
852 struct radeon_pm {
853 struct mutex mutex;
854 u32 active_crtcs;
855 int active_crtc_count;
856 int req_vblank;
857 bool vblank_sync;
858 bool gui_idle;
859 fixed20_12 max_bandwidth;
860 fixed20_12 igp_sideport_mclk;
861 fixed20_12 igp_system_mclk;
862 fixed20_12 igp_ht_link_clk;
863 fixed20_12 igp_ht_link_width;
864 fixed20_12 k8_bandwidth;
865 fixed20_12 sideport_bandwidth;
866 fixed20_12 ht_bandwidth;
867 fixed20_12 core_bandwidth;
868 fixed20_12 sclk;
869 fixed20_12 mclk;
870 fixed20_12 needed_bandwidth;
871 struct radeon_power_state *power_state;
872 /* number of valid power states */
873 int num_power_states;
874 int current_power_state_index;
875 int current_clock_mode_index;
876 int requested_power_state_index;
877 int requested_clock_mode_index;
878 int default_power_state_index;
879 u32 current_sclk;
880 u32 current_mclk;
881 u16 current_vddc;
882 u16 current_vddci;
883 u32 default_sclk;
884 u32 default_mclk;
885 u16 default_vddc;
886 u16 default_vddci;
887 struct radeon_i2c_chan *i2c_bus;
888 /* selected pm method */
889 enum radeon_pm_method pm_method;
890 /* dynpm power management */
891 struct delayed_work dynpm_idle_work;
892 enum radeon_dynpm_state dynpm_state;
893 enum radeon_dynpm_action dynpm_planned_action;
894 unsigned long dynpm_action_timeout;
895 bool dynpm_can_upclock;
896 bool dynpm_can_downclock;
897 /* profile-based power management */
898 enum radeon_pm_profile_type profile;
899 int profile_index;
900 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
901 /* internal thermal controller on rv6xx+ */
902 enum radeon_int_thermal_type int_thermal_type;
903 struct device *int_hwmon_dev;
904 };
905
906 int radeon_pm_get_type_index(struct radeon_device *rdev,
907 enum radeon_pm_state_type ps_type,
908 int instance);
909
910 /*
911 * Benchmarking
912 */
913 void radeon_benchmark(struct radeon_device *rdev, int test_number);
914
915
916 /*
917 * Testing
918 */
919 void radeon_test_moves(struct radeon_device *rdev);
920 void radeon_test_ring_sync(struct radeon_device *rdev,
921 struct radeon_ring *cpA,
922 struct radeon_ring *cpB);
923 void radeon_test_syncing(struct radeon_device *rdev);
924
925
926 /*
927 * Debugfs
928 */
929 struct radeon_debugfs {
930 struct drm_info_list *files;
931 unsigned num_files;
932 };
933
934 int radeon_debugfs_add_files(struct radeon_device *rdev,
935 struct drm_info_list *files,
936 unsigned nfiles);
937 int radeon_debugfs_fence_init(struct radeon_device *rdev);
938
939
940 /*
941 * ASIC specific functions.
942 */
943 struct radeon_asic {
944 int (*init)(struct radeon_device *rdev);
945 void (*fini)(struct radeon_device *rdev);
946 int (*resume)(struct radeon_device *rdev);
947 int (*suspend)(struct radeon_device *rdev);
948 void (*vga_set_state)(struct radeon_device *rdev, bool state);
949 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
950 int (*asic_reset)(struct radeon_device *rdev);
951 void (*gart_tlb_flush)(struct radeon_device *rdev);
952 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
953 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
954 void (*cp_fini)(struct radeon_device *rdev);
955 void (*cp_disable)(struct radeon_device *rdev);
956 void (*ring_start)(struct radeon_device *rdev);
957
958 struct {
959 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
960 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
961 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
962 struct radeon_semaphore *semaphore, bool emit_wait);
963 } ring[RADEON_NUM_RINGS];
964
965 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
966 int (*irq_set)(struct radeon_device *rdev);
967 int (*irq_process)(struct radeon_device *rdev);
968 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
969 int (*cs_parse)(struct radeon_cs_parser *p);
970 int (*copy_blit)(struct radeon_device *rdev,
971 uint64_t src_offset,
972 uint64_t dst_offset,
973 unsigned num_gpu_pages,
974 struct radeon_fence *fence);
975 int (*copy_dma)(struct radeon_device *rdev,
976 uint64_t src_offset,
977 uint64_t dst_offset,
978 unsigned num_gpu_pages,
979 struct radeon_fence *fence);
980 int (*copy)(struct radeon_device *rdev,
981 uint64_t src_offset,
982 uint64_t dst_offset,
983 unsigned num_gpu_pages,
984 struct radeon_fence *fence);
985 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
986 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
987 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
988 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
989 int (*get_pcie_lanes)(struct radeon_device *rdev);
990 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
991 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
992 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
993 uint32_t tiling_flags, uint32_t pitch,
994 uint32_t offset, uint32_t obj_size);
995 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
996 void (*bandwidth_update)(struct radeon_device *rdev);
997 void (*hpd_init)(struct radeon_device *rdev);
998 void (*hpd_fini)(struct radeon_device *rdev);
999 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1000 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1001 /* ioctl hw specific callback. Some hw might want to perform special
1002 * operation on specific ioctl. For instance on wait idle some hw
1003 * might want to perform and HDP flush through MMIO as it seems that
1004 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1005 * through ring.
1006 */
1007 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1008 bool (*gui_idle)(struct radeon_device *rdev);
1009 /* power management */
1010 void (*pm_misc)(struct radeon_device *rdev);
1011 void (*pm_prepare)(struct radeon_device *rdev);
1012 void (*pm_finish)(struct radeon_device *rdev);
1013 void (*pm_init_profile)(struct radeon_device *rdev);
1014 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
1015 /* pageflipping */
1016 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1017 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1018 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1019 };
1020
1021 /*
1022 * Asic structures
1023 */
1024 struct r100_gpu_lockup {
1025 unsigned long last_jiffies;
1026 u32 last_cp_rptr;
1027 };
1028
1029 struct r100_asic {
1030 const unsigned *reg_safe_bm;
1031 unsigned reg_safe_bm_size;
1032 u32 hdp_cntl;
1033 struct r100_gpu_lockup lockup;
1034 };
1035
1036 struct r300_asic {
1037 const unsigned *reg_safe_bm;
1038 unsigned reg_safe_bm_size;
1039 u32 resync_scratch;
1040 u32 hdp_cntl;
1041 struct r100_gpu_lockup lockup;
1042 };
1043
1044 struct r600_asic {
1045 unsigned max_pipes;
1046 unsigned max_tile_pipes;
1047 unsigned max_simds;
1048 unsigned max_backends;
1049 unsigned max_gprs;
1050 unsigned max_threads;
1051 unsigned max_stack_entries;
1052 unsigned max_hw_contexts;
1053 unsigned max_gs_threads;
1054 unsigned sx_max_export_size;
1055 unsigned sx_max_export_pos_size;
1056 unsigned sx_max_export_smx_size;
1057 unsigned sq_num_cf_insts;
1058 unsigned tiling_nbanks;
1059 unsigned tiling_npipes;
1060 unsigned tiling_group_size;
1061 unsigned tile_config;
1062 unsigned backend_map;
1063 struct r100_gpu_lockup lockup;
1064 };
1065
1066 struct rv770_asic {
1067 unsigned max_pipes;
1068 unsigned max_tile_pipes;
1069 unsigned max_simds;
1070 unsigned max_backends;
1071 unsigned max_gprs;
1072 unsigned max_threads;
1073 unsigned max_stack_entries;
1074 unsigned max_hw_contexts;
1075 unsigned max_gs_threads;
1076 unsigned sx_max_export_size;
1077 unsigned sx_max_export_pos_size;
1078 unsigned sx_max_export_smx_size;
1079 unsigned sq_num_cf_insts;
1080 unsigned sx_num_of_sets;
1081 unsigned sc_prim_fifo_size;
1082 unsigned sc_hiz_tile_fifo_size;
1083 unsigned sc_earlyz_tile_fifo_fize;
1084 unsigned tiling_nbanks;
1085 unsigned tiling_npipes;
1086 unsigned tiling_group_size;
1087 unsigned tile_config;
1088 unsigned backend_map;
1089 struct r100_gpu_lockup lockup;
1090 };
1091
1092 struct evergreen_asic {
1093 unsigned num_ses;
1094 unsigned max_pipes;
1095 unsigned max_tile_pipes;
1096 unsigned max_simds;
1097 unsigned max_backends;
1098 unsigned max_gprs;
1099 unsigned max_threads;
1100 unsigned max_stack_entries;
1101 unsigned max_hw_contexts;
1102 unsigned max_gs_threads;
1103 unsigned sx_max_export_size;
1104 unsigned sx_max_export_pos_size;
1105 unsigned sx_max_export_smx_size;
1106 unsigned sq_num_cf_insts;
1107 unsigned sx_num_of_sets;
1108 unsigned sc_prim_fifo_size;
1109 unsigned sc_hiz_tile_fifo_size;
1110 unsigned sc_earlyz_tile_fifo_size;
1111 unsigned tiling_nbanks;
1112 unsigned tiling_npipes;
1113 unsigned tiling_group_size;
1114 unsigned tile_config;
1115 unsigned backend_map;
1116 struct r100_gpu_lockup lockup;
1117 };
1118
1119 struct cayman_asic {
1120 unsigned max_shader_engines;
1121 unsigned max_pipes_per_simd;
1122 unsigned max_tile_pipes;
1123 unsigned max_simds_per_se;
1124 unsigned max_backends_per_se;
1125 unsigned max_texture_channel_caches;
1126 unsigned max_gprs;
1127 unsigned max_threads;
1128 unsigned max_gs_threads;
1129 unsigned max_stack_entries;
1130 unsigned sx_num_of_sets;
1131 unsigned sx_max_export_size;
1132 unsigned sx_max_export_pos_size;
1133 unsigned sx_max_export_smx_size;
1134 unsigned max_hw_contexts;
1135 unsigned sq_num_cf_insts;
1136 unsigned sc_prim_fifo_size;
1137 unsigned sc_hiz_tile_fifo_size;
1138 unsigned sc_earlyz_tile_fifo_size;
1139
1140 unsigned num_shader_engines;
1141 unsigned num_shader_pipes_per_simd;
1142 unsigned num_tile_pipes;
1143 unsigned num_simds_per_se;
1144 unsigned num_backends_per_se;
1145 unsigned backend_disable_mask_per_asic;
1146 unsigned backend_map;
1147 unsigned num_texture_channel_caches;
1148 unsigned mem_max_burst_length_bytes;
1149 unsigned mem_row_size_in_kb;
1150 unsigned shader_engine_tile_size;
1151 unsigned num_gpus;
1152 unsigned multi_gpu_tile_size;
1153
1154 unsigned tile_config;
1155 struct r100_gpu_lockup lockup;
1156 };
1157
1158 union radeon_asic_config {
1159 struct r300_asic r300;
1160 struct r100_asic r100;
1161 struct r600_asic r600;
1162 struct rv770_asic rv770;
1163 struct evergreen_asic evergreen;
1164 struct cayman_asic cayman;
1165 };
1166
1167 /*
1168 * asic initizalization from radeon_asic.c
1169 */
1170 void radeon_agp_disable(struct radeon_device *rdev);
1171 int radeon_asic_init(struct radeon_device *rdev);
1172
1173
1174 /*
1175 * IOCTL.
1176 */
1177 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1178 struct drm_file *filp);
1179 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1180 struct drm_file *filp);
1181 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1182 struct drm_file *file_priv);
1183 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1184 struct drm_file *file_priv);
1185 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1186 struct drm_file *file_priv);
1187 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file_priv);
1189 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1190 struct drm_file *filp);
1191 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1192 struct drm_file *filp);
1193 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1194 struct drm_file *filp);
1195 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1196 struct drm_file *filp);
1197 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1198 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1199 struct drm_file *filp);
1200 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1201 struct drm_file *filp);
1202
1203 /* VRAM scratch page for HDP bug, default vram page */
1204 struct r600_vram_scratch {
1205 struct radeon_bo *robj;
1206 volatile uint32_t *ptr;
1207 u64 gpu_addr;
1208 };
1209
1210
1211 /*
1212 * Mutex which allows recursive locking from the same process.
1213 */
1214 struct radeon_mutex {
1215 struct mutex mutex;
1216 struct task_struct *owner;
1217 int level;
1218 };
1219
1220 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1221 {
1222 mutex_init(&mutex->mutex);
1223 mutex->owner = NULL;
1224 mutex->level = 0;
1225 }
1226
1227 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1228 {
1229 if (mutex_trylock(&mutex->mutex)) {
1230 /* The mutex was unlocked before, so it's ours now */
1231 mutex->owner = current;
1232 } else if (mutex->owner != current) {
1233 /* Another process locked the mutex, take it */
1234 mutex_lock(&mutex->mutex);
1235 mutex->owner = current;
1236 }
1237 /* Otherwise the mutex was already locked by this process */
1238
1239 mutex->level++;
1240 }
1241
1242 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1243 {
1244 if (--mutex->level > 0)
1245 return;
1246
1247 mutex->owner = NULL;
1248 mutex_unlock(&mutex->mutex);
1249 }
1250
1251
1252 /*
1253 * Core structure, functions and helpers.
1254 */
1255 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1256 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1257
1258 struct radeon_device {
1259 struct device *dev;
1260 struct drm_device *ddev;
1261 struct pci_dev *pdev;
1262 /* ASIC */
1263 union radeon_asic_config config;
1264 enum radeon_family family;
1265 unsigned long flags;
1266 int usec_timeout;
1267 enum radeon_pll_errata pll_errata;
1268 int num_gb_pipes;
1269 int num_z_pipes;
1270 int disp_priority;
1271 /* BIOS */
1272 uint8_t *bios;
1273 bool is_atom_bios;
1274 uint16_t bios_header_start;
1275 struct radeon_bo *stollen_vga_memory;
1276 /* Register mmio */
1277 resource_size_t rmmio_base;
1278 resource_size_t rmmio_size;
1279 void __iomem *rmmio;
1280 radeon_rreg_t mc_rreg;
1281 radeon_wreg_t mc_wreg;
1282 radeon_rreg_t pll_rreg;
1283 radeon_wreg_t pll_wreg;
1284 uint32_t pcie_reg_mask;
1285 radeon_rreg_t pciep_rreg;
1286 radeon_wreg_t pciep_wreg;
1287 /* io port */
1288 void __iomem *rio_mem;
1289 resource_size_t rio_mem_size;
1290 struct radeon_clock clock;
1291 struct radeon_mc mc;
1292 struct radeon_gart gart;
1293 struct radeon_mode_info mode_info;
1294 struct radeon_scratch scratch;
1295 struct radeon_mman mman;
1296 rwlock_t fence_lock;
1297 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1298 struct radeon_semaphore_driver semaphore_drv;
1299 struct radeon_ring ring[RADEON_NUM_RINGS];
1300 struct radeon_ib_pool ib_pool;
1301 struct radeon_irq irq;
1302 struct radeon_asic *asic;
1303 struct radeon_gem gem;
1304 struct radeon_pm pm;
1305 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1306 struct radeon_mutex cs_mutex;
1307 struct radeon_wb wb;
1308 struct radeon_dummy_page dummy_page;
1309 bool gpu_lockup;
1310 bool shutdown;
1311 bool suspend;
1312 bool need_dma32;
1313 bool accel_working;
1314 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1315 const struct firmware *me_fw; /* all family ME firmware */
1316 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1317 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1318 const struct firmware *mc_fw; /* NI MC firmware */
1319 struct r600_blit r600_blit;
1320 struct r600_vram_scratch vram_scratch;
1321 int msi_enabled; /* msi enabled */
1322 struct r600_ih ih; /* r6/700 interrupt ring */
1323 struct work_struct hotplug_work;
1324 int num_crtc; /* number of crtcs */
1325 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1326 struct mutex vram_mutex;
1327
1328 /* audio stuff */
1329 bool audio_enabled;
1330 struct timer_list audio_timer;
1331 int audio_channels;
1332 int audio_rate;
1333 int audio_bits_per_sample;
1334 uint8_t audio_status_bits;
1335 uint8_t audio_category_code;
1336
1337 struct notifier_block acpi_nb;
1338 /* only one userspace can use Hyperz features or CMASK at a time */
1339 struct drm_file *hyperz_filp;
1340 struct drm_file *cmask_filp;
1341 /* i2c buses */
1342 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1343 /* debugfs */
1344 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1345 unsigned debugfs_count;
1346 };
1347
1348 int radeon_device_init(struct radeon_device *rdev,
1349 struct drm_device *ddev,
1350 struct pci_dev *pdev,
1351 uint32_t flags);
1352 void radeon_device_fini(struct radeon_device *rdev);
1353 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1354
1355 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1356 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1357 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1358 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1359
1360 /*
1361 * Cast helper
1362 */
1363 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1364
1365 /*
1366 * Registers read & write functions.
1367 */
1368 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1369 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1370 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1371 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1372 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1373 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1374 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1375 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1376 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1377 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1378 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1379 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1380 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1381 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1382 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1383 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1384 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1385 #define WREG32_P(reg, val, mask) \
1386 do { \
1387 uint32_t tmp_ = RREG32(reg); \
1388 tmp_ &= (mask); \
1389 tmp_ |= ((val) & ~(mask)); \
1390 WREG32(reg, tmp_); \
1391 } while (0)
1392 #define WREG32_PLL_P(reg, val, mask) \
1393 do { \
1394 uint32_t tmp_ = RREG32_PLL(reg); \
1395 tmp_ &= (mask); \
1396 tmp_ |= ((val) & ~(mask)); \
1397 WREG32_PLL(reg, tmp_); \
1398 } while (0)
1399 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1400 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1401 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1402
1403 /*
1404 * Indirect registers accessor
1405 */
1406 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1407 {
1408 uint32_t r;
1409
1410 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1411 r = RREG32(RADEON_PCIE_DATA);
1412 return r;
1413 }
1414
1415 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1416 {
1417 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1418 WREG32(RADEON_PCIE_DATA, (v));
1419 }
1420
1421 void r100_pll_errata_after_index(struct radeon_device *rdev);
1422
1423
1424 /*
1425 * ASICs helpers.
1426 */
1427 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1428 (rdev->pdev->device == 0x5969))
1429 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1430 (rdev->family == CHIP_RV200) || \
1431 (rdev->family == CHIP_RS100) || \
1432 (rdev->family == CHIP_RS200) || \
1433 (rdev->family == CHIP_RV250) || \
1434 (rdev->family == CHIP_RV280) || \
1435 (rdev->family == CHIP_RS300))
1436 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1437 (rdev->family == CHIP_RV350) || \
1438 (rdev->family == CHIP_R350) || \
1439 (rdev->family == CHIP_RV380) || \
1440 (rdev->family == CHIP_R420) || \
1441 (rdev->family == CHIP_R423) || \
1442 (rdev->family == CHIP_RV410) || \
1443 (rdev->family == CHIP_RS400) || \
1444 (rdev->family == CHIP_RS480))
1445 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1446 (rdev->ddev->pdev->device == 0x9443) || \
1447 (rdev->ddev->pdev->device == 0x944B) || \
1448 (rdev->ddev->pdev->device == 0x9506) || \
1449 (rdev->ddev->pdev->device == 0x9509) || \
1450 (rdev->ddev->pdev->device == 0x950F) || \
1451 (rdev->ddev->pdev->device == 0x689C) || \
1452 (rdev->ddev->pdev->device == 0x689D))
1453 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1454 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1455 (rdev->family == CHIP_RS690) || \
1456 (rdev->family == CHIP_RS740) || \
1457 (rdev->family >= CHIP_R600))
1458 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1459 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1460 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1461 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1462 (rdev->flags & RADEON_IS_IGP))
1463 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1464
1465 /*
1466 * BIOS helpers.
1467 */
1468 #define RBIOS8(i) (rdev->bios[i])
1469 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1470 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1471
1472 int radeon_combios_init(struct radeon_device *rdev);
1473 void radeon_combios_fini(struct radeon_device *rdev);
1474 int radeon_atombios_init(struct radeon_device *rdev);
1475 void radeon_atombios_fini(struct radeon_device *rdev);
1476
1477
1478 /*
1479 * RING helpers.
1480 */
1481 #if DRM_DEBUG_CODE == 0
1482 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1483 {
1484 ring->ring[ring->wptr++] = v;
1485 ring->wptr &= ring->ptr_mask;
1486 ring->count_dw--;
1487 ring->ring_free_dw--;
1488 }
1489 #else
1490 /* With debugging this is just too big to inline */
1491 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1492 #endif
1493
1494 /*
1495 * ASICs macro.
1496 */
1497 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1498 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1499 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1500 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1501 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1502 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1503 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1504 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1505 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1506 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1507 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1508 #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1509 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1510 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1511 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1512 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1513 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1514 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1515 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1516 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1517 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1518 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1519 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1520 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1521 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1522 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1523 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1524 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1525 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1526 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1527 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1528 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1529 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1530 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1531 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1532 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1533 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1534 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1535 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1536 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1537 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1538 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1539 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1540 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1541
1542 /* Common functions */
1543 /* AGP */
1544 extern int radeon_gpu_reset(struct radeon_device *rdev);
1545 extern void radeon_agp_disable(struct radeon_device *rdev);
1546 extern int radeon_modeset_init(struct radeon_device *rdev);
1547 extern void radeon_modeset_fini(struct radeon_device *rdev);
1548 extern bool radeon_card_posted(struct radeon_device *rdev);
1549 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1550 extern void radeon_update_display_priority(struct radeon_device *rdev);
1551 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1552 extern void radeon_scratch_init(struct radeon_device *rdev);
1553 extern void radeon_wb_fini(struct radeon_device *rdev);
1554 extern int radeon_wb_init(struct radeon_device *rdev);
1555 extern void radeon_wb_disable(struct radeon_device *rdev);
1556 extern void radeon_surface_init(struct radeon_device *rdev);
1557 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1558 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1559 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1560 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1561 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1562 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1563 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1564 extern int radeon_resume_kms(struct drm_device *dev);
1565 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1566 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1567
1568 /*
1569 * R600 vram scratch functions
1570 */
1571 int r600_vram_scratch_init(struct radeon_device *rdev);
1572 void r600_vram_scratch_fini(struct radeon_device *rdev);
1573
1574 /*
1575 * r600 functions used by radeon_encoder.c
1576 */
1577 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1578 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1579 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1580
1581 extern int ni_init_microcode(struct radeon_device *rdev);
1582 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1583
1584 /* radeon_acpi.c */
1585 #if defined(CONFIG_ACPI)
1586 extern int radeon_acpi_init(struct radeon_device *rdev);
1587 #else
1588 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1589 #endif
1590
1591 #include "radeon_object.h"
1592
1593 #endif
Linux kernel - Deliverables
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