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drm/radeon: save/restore the PD addr on suspend/resume
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68
69 #include <ttm/ttm_bo_api.h>
70 #include <ttm/ttm_bo_driver.h>
71 #include <ttm/ttm_placement.h>
72 #include <ttm/ttm_module.h>
73 #include <ttm/ttm_execbuf_util.h>
74
75 #include "radeon_family.h"
76 #include "radeon_mode.h"
77 #include "radeon_reg.h"
78
79 /*
80 * Modules parameters.
81 */
82 extern int radeon_no_wb;
83 extern int radeon_modeset;
84 extern int radeon_dynclks;
85 extern int radeon_r4xx_atom;
86 extern int radeon_agpmode;
87 extern int radeon_vram_limit;
88 extern int radeon_gart_size;
89 extern int radeon_benchmarking;
90 extern int radeon_testing;
91 extern int radeon_connector_table;
92 extern int radeon_tv;
93 extern int radeon_audio;
94 extern int radeon_disp_priority;
95 extern int radeon_hw_i2c;
96 extern int radeon_pcie_gen2;
97 extern int radeon_msi;
98 extern int radeon_lockup_timeout;
99 extern int radeon_fastfb;
100 extern int radeon_dpm;
101 extern int radeon_aspm;
102 extern int radeon_runtime_pm;
103 extern int radeon_hard_reset;
104 extern int radeon_vm_size;
105 extern int radeon_vm_block_size;
106 extern int radeon_deep_color;
107 extern int radeon_use_pflipirq;
108 extern int radeon_bapm;
109
110 /*
111 * Copy from radeon_drv.h so we don't have to include both and have conflicting
112 * symbol;
113 */
114 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
115 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
116 /* RADEON_IB_POOL_SIZE must be a power of 2 */
117 #define RADEON_IB_POOL_SIZE 16
118 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
119 #define RADEONFB_CONN_LIMIT 4
120 #define RADEON_BIOS_NUM_SCRATCH 8
121
122 /* fence seq are set to this number when signaled */
123 #define RADEON_FENCE_SIGNALED_SEQ 0LL
124
125 /* internal ring indices */
126 /* r1xx+ has gfx CP ring */
127 #define RADEON_RING_TYPE_GFX_INDEX 0
128
129 /* cayman has 2 compute CP rings */
130 #define CAYMAN_RING_TYPE_CP1_INDEX 1
131 #define CAYMAN_RING_TYPE_CP2_INDEX 2
132
133 /* R600+ has an async dma ring */
134 #define R600_RING_TYPE_DMA_INDEX 3
135 /* cayman add a second async dma ring */
136 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
137
138 /* R600+ */
139 #define R600_RING_TYPE_UVD_INDEX 5
140
141 /* TN+ */
142 #define TN_RING_TYPE_VCE1_INDEX 6
143 #define TN_RING_TYPE_VCE2_INDEX 7
144
145 /* max number of rings */
146 #define RADEON_NUM_RINGS 8
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* number of hw syncs before falling back on blocking */
152 #define RADEON_NUM_SYNCS 4
153
154 /* hardcode those limit for now */
155 #define RADEON_VA_IB_OFFSET (1 << 20)
156 #define RADEON_VA_RESERVED_SIZE (8 << 20)
157 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
158
159 /* hard reset data */
160 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
161
162 /* reset flags */
163 #define RADEON_RESET_GFX (1 << 0)
164 #define RADEON_RESET_COMPUTE (1 << 1)
165 #define RADEON_RESET_DMA (1 << 2)
166 #define RADEON_RESET_CP (1 << 3)
167 #define RADEON_RESET_GRBM (1 << 4)
168 #define RADEON_RESET_DMA1 (1 << 5)
169 #define RADEON_RESET_RLC (1 << 6)
170 #define RADEON_RESET_SEM (1 << 7)
171 #define RADEON_RESET_IH (1 << 8)
172 #define RADEON_RESET_VMC (1 << 9)
173 #define RADEON_RESET_MC (1 << 10)
174 #define RADEON_RESET_DISPLAY (1 << 11)
175
176 /* CG block flags */
177 #define RADEON_CG_BLOCK_GFX (1 << 0)
178 #define RADEON_CG_BLOCK_MC (1 << 1)
179 #define RADEON_CG_BLOCK_SDMA (1 << 2)
180 #define RADEON_CG_BLOCK_UVD (1 << 3)
181 #define RADEON_CG_BLOCK_VCE (1 << 4)
182 #define RADEON_CG_BLOCK_HDP (1 << 5)
183 #define RADEON_CG_BLOCK_BIF (1 << 6)
184
185 /* CG flags */
186 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
187 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
188 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
189 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
190 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
191 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
192 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
193 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
194 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
195 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
196 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
197 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
198 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
199 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
200 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
201 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
202 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
203
204 /* PG flags */
205 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
206 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
207 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
208 #define RADEON_PG_SUPPORT_UVD (1 << 3)
209 #define RADEON_PG_SUPPORT_VCE (1 << 4)
210 #define RADEON_PG_SUPPORT_CP (1 << 5)
211 #define RADEON_PG_SUPPORT_GDS (1 << 6)
212 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
213 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
214 #define RADEON_PG_SUPPORT_ACP (1 << 9)
215 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
216
217 /* max cursor sizes (in pixels) */
218 #define CURSOR_WIDTH 64
219 #define CURSOR_HEIGHT 64
220
221 #define CIK_CURSOR_WIDTH 128
222 #define CIK_CURSOR_HEIGHT 128
223
224 /*
225 * Errata workarounds.
226 */
227 enum radeon_pll_errata {
228 CHIP_ERRATA_R300_CG = 0x00000001,
229 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
230 CHIP_ERRATA_PLL_DELAY = 0x00000004
231 };
232
233
234 struct radeon_device;
235
236
237 /*
238 * BIOS.
239 */
240 bool radeon_get_bios(struct radeon_device *rdev);
241
242 /*
243 * Dummy page
244 */
245 struct radeon_dummy_page {
246 struct page *page;
247 dma_addr_t addr;
248 };
249 int radeon_dummy_page_init(struct radeon_device *rdev);
250 void radeon_dummy_page_fini(struct radeon_device *rdev);
251
252
253 /*
254 * Clocks
255 */
256 struct radeon_clock {
257 struct radeon_pll p1pll;
258 struct radeon_pll p2pll;
259 struct radeon_pll dcpll;
260 struct radeon_pll spll;
261 struct radeon_pll mpll;
262 /* 10 Khz units */
263 uint32_t default_mclk;
264 uint32_t default_sclk;
265 uint32_t default_dispclk;
266 uint32_t current_dispclk;
267 uint32_t dp_extclk;
268 uint32_t max_pixel_clock;
269 };
270
271 /*
272 * Power management
273 */
274 int radeon_pm_init(struct radeon_device *rdev);
275 int radeon_pm_late_init(struct radeon_device *rdev);
276 void radeon_pm_fini(struct radeon_device *rdev);
277 void radeon_pm_compute_clocks(struct radeon_device *rdev);
278 void radeon_pm_suspend(struct radeon_device *rdev);
279 void radeon_pm_resume(struct radeon_device *rdev);
280 void radeon_combios_get_power_modes(struct radeon_device *rdev);
281 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
282 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
283 u8 clock_type,
284 u32 clock,
285 bool strobe_mode,
286 struct atom_clock_dividers *dividers);
287 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_mpll_param *mpll_param);
291 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
292 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
293 u16 voltage_level, u8 voltage_type,
294 u32 *gpio_value, u32 *gpio_mask);
295 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
296 u32 eng_clock, u32 mem_clock);
297 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
298 u8 voltage_type, u16 *voltage_step);
299 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
300 u16 voltage_id, u16 *voltage);
301 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
302 u16 *voltage,
303 u16 leakage_idx);
304 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
305 u16 *leakage_id);
306 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
307 u16 *vddc, u16 *vddci,
308 u16 virtual_voltage_id,
309 u16 vbios_voltage_id);
310 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
311 u16 virtual_voltage_id,
312 u16 *voltage);
313 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
314 u8 voltage_type,
315 u16 nominal_voltage,
316 u16 *true_voltage);
317 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
318 u8 voltage_type, u16 *min_voltage);
319 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *max_voltage);
321 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
322 u8 voltage_type, u8 voltage_mode,
323 struct atom_voltage_table *voltage_table);
324 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
325 u8 voltage_type, u8 voltage_mode);
326 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
327 u8 voltage_type,
328 u8 *svd_gpio_id, u8 *svc_gpio_id);
329 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
330 u32 mem_clock);
331 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
332 u32 mem_clock);
333 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
334 u8 module_index,
335 struct atom_mc_reg_table *reg_table);
336 int radeon_atom_get_memory_info(struct radeon_device *rdev,
337 u8 module_index, struct atom_memory_info *mem_info);
338 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
339 bool gddr5, u8 module_index,
340 struct atom_memory_clock_range_table *mclk_range_table);
341 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
342 u16 voltage_id, u16 *voltage);
343 void rs690_pm_info(struct radeon_device *rdev);
344 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
345 unsigned *bankh, unsigned *mtaspect,
346 unsigned *tile_split);
347
348 /*
349 * Fences.
350 */
351 struct radeon_fence_driver {
352 uint32_t scratch_reg;
353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
357 atomic64_t last_seq;
358 bool initialized;
359 };
360
361 struct radeon_fence {
362 struct radeon_device *rdev;
363 struct kref kref;
364 /* protected by radeon_fence.lock */
365 uint64_t seq;
366 /* RB, DMA, etc. */
367 unsigned ring;
368 };
369
370 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
371 int radeon_fence_driver_init(struct radeon_device *rdev);
372 void radeon_fence_driver_fini(struct radeon_device *rdev);
373 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
374 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
375 void radeon_fence_process(struct radeon_device *rdev, int ring);
376 bool radeon_fence_signaled(struct radeon_fence *fence);
377 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
378 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
379 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
380 int radeon_fence_wait_any(struct radeon_device *rdev,
381 struct radeon_fence **fences,
382 bool intr);
383 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
384 void radeon_fence_unref(struct radeon_fence **fence);
385 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
386 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
387 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
388 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
389 struct radeon_fence *b)
390 {
391 if (!a) {
392 return b;
393 }
394
395 if (!b) {
396 return a;
397 }
398
399 BUG_ON(a->ring != b->ring);
400
401 if (a->seq > b->seq) {
402 return a;
403 } else {
404 return b;
405 }
406 }
407
408 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
409 struct radeon_fence *b)
410 {
411 if (!a) {
412 return false;
413 }
414
415 if (!b) {
416 return true;
417 }
418
419 BUG_ON(a->ring != b->ring);
420
421 return a->seq < b->seq;
422 }
423
424 /*
425 * Tiling registers
426 */
427 struct radeon_surface_reg {
428 struct radeon_bo *bo;
429 };
430
431 #define RADEON_GEM_MAX_SURFACES 8
432
433 /*
434 * TTM.
435 */
436 struct radeon_mman {
437 struct ttm_bo_global_ref bo_global_ref;
438 struct drm_global_reference mem_global_ref;
439 struct ttm_bo_device bdev;
440 bool mem_global_referenced;
441 bool initialized;
442
443 #if defined(CONFIG_DEBUG_FS)
444 struct dentry *vram;
445 struct dentry *gtt;
446 #endif
447 };
448
449 /* bo virtual address in a specific vm */
450 struct radeon_bo_va {
451 /* protected by bo being reserved */
452 struct list_head bo_list;
453 uint32_t flags;
454 uint64_t addr;
455 unsigned ref_count;
456
457 /* protected by vm mutex */
458 struct interval_tree_node it;
459 struct list_head vm_status;
460
461 /* constant after initialization */
462 struct radeon_vm *vm;
463 struct radeon_bo *bo;
464 };
465
466 struct radeon_bo {
467 /* Protected by gem.mutex */
468 struct list_head list;
469 /* Protected by tbo.reserved */
470 u32 initial_domain;
471 u32 placements[3];
472 struct ttm_placement placement;
473 struct ttm_buffer_object tbo;
474 struct ttm_bo_kmap_obj kmap;
475 u32 flags;
476 unsigned pin_count;
477 void *kptr;
478 u32 tiling_flags;
479 u32 pitch;
480 int surface_reg;
481 /* list of all virtual address to which this bo
482 * is associated to
483 */
484 struct list_head va;
485 /* Constant after initialization */
486 struct radeon_device *rdev;
487 struct drm_gem_object gem_base;
488
489 struct ttm_bo_kmap_obj dma_buf_vmap;
490 pid_t pid;
491 };
492 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
493
494 int radeon_gem_debugfs_init(struct radeon_device *rdev);
495
496 /* sub-allocation manager, it has to be protected by another lock.
497 * By conception this is an helper for other part of the driver
498 * like the indirect buffer or semaphore, which both have their
499 * locking.
500 *
501 * Principe is simple, we keep a list of sub allocation in offset
502 * order (first entry has offset == 0, last entry has the highest
503 * offset).
504 *
505 * When allocating new object we first check if there is room at
506 * the end total_size - (last_object_offset + last_object_size) >=
507 * alloc_size. If so we allocate new object there.
508 *
509 * When there is not enough room at the end, we start waiting for
510 * each sub object until we reach object_offset+object_size >=
511 * alloc_size, this object then become the sub object we return.
512 *
513 * Alignment can't be bigger than page size.
514 *
515 * Hole are not considered for allocation to keep things simple.
516 * Assumption is that there won't be hole (all object on same
517 * alignment).
518 */
519 struct radeon_sa_manager {
520 wait_queue_head_t wq;
521 struct radeon_bo *bo;
522 struct list_head *hole;
523 struct list_head flist[RADEON_NUM_RINGS];
524 struct list_head olist;
525 unsigned size;
526 uint64_t gpu_addr;
527 void *cpu_ptr;
528 uint32_t domain;
529 uint32_t align;
530 };
531
532 struct radeon_sa_bo;
533
534 /* sub-allocation buffer */
535 struct radeon_sa_bo {
536 struct list_head olist;
537 struct list_head flist;
538 struct radeon_sa_manager *manager;
539 unsigned soffset;
540 unsigned eoffset;
541 struct radeon_fence *fence;
542 };
543
544 /*
545 * GEM objects.
546 */
547 struct radeon_gem {
548 struct mutex mutex;
549 struct list_head objects;
550 };
551
552 int radeon_gem_init(struct radeon_device *rdev);
553 void radeon_gem_fini(struct radeon_device *rdev);
554 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
555 int alignment, int initial_domain,
556 u32 flags, bool kernel,
557 struct drm_gem_object **obj);
558
559 int radeon_mode_dumb_create(struct drm_file *file_priv,
560 struct drm_device *dev,
561 struct drm_mode_create_dumb *args);
562 int radeon_mode_dumb_mmap(struct drm_file *filp,
563 struct drm_device *dev,
564 uint32_t handle, uint64_t *offset_p);
565
566 /*
567 * Semaphores.
568 */
569 struct radeon_semaphore {
570 struct radeon_sa_bo *sa_bo;
571 signed waiters;
572 uint64_t gpu_addr;
573 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
574 };
575
576 int radeon_semaphore_create(struct radeon_device *rdev,
577 struct radeon_semaphore **semaphore);
578 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
579 struct radeon_semaphore *semaphore);
580 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
581 struct radeon_semaphore *semaphore);
582 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
583 struct radeon_fence *fence);
584 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
585 struct radeon_semaphore *semaphore,
586 int waiting_ring);
587 void radeon_semaphore_free(struct radeon_device *rdev,
588 struct radeon_semaphore **semaphore,
589 struct radeon_fence *fence);
590
591 /*
592 * GART structures, functions & helpers
593 */
594 struct radeon_mc;
595
596 #define RADEON_GPU_PAGE_SIZE 4096
597 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
598 #define RADEON_GPU_PAGE_SHIFT 12
599 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
600
601 #define RADEON_GART_PAGE_DUMMY 0
602 #define RADEON_GART_PAGE_VALID (1 << 0)
603 #define RADEON_GART_PAGE_READ (1 << 1)
604 #define RADEON_GART_PAGE_WRITE (1 << 2)
605 #define RADEON_GART_PAGE_SNOOP (1 << 3)
606
607 struct radeon_gart {
608 dma_addr_t table_addr;
609 struct radeon_bo *robj;
610 void *ptr;
611 unsigned num_gpu_pages;
612 unsigned num_cpu_pages;
613 unsigned table_size;
614 struct page **pages;
615 dma_addr_t *pages_addr;
616 bool ready;
617 };
618
619 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
620 void radeon_gart_table_ram_free(struct radeon_device *rdev);
621 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
622 void radeon_gart_table_vram_free(struct radeon_device *rdev);
623 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
624 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
625 int radeon_gart_init(struct radeon_device *rdev);
626 void radeon_gart_fini(struct radeon_device *rdev);
627 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
628 int pages);
629 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
630 int pages, struct page **pagelist,
631 dma_addr_t *dma_addr, uint32_t flags);
632
633
634 /*
635 * GPU MC structures, functions & helpers
636 */
637 struct radeon_mc {
638 resource_size_t aper_size;
639 resource_size_t aper_base;
640 resource_size_t agp_base;
641 /* for some chips with <= 32MB we need to lie
642 * about vram size near mc fb location */
643 u64 mc_vram_size;
644 u64 visible_vram_size;
645 u64 gtt_size;
646 u64 gtt_start;
647 u64 gtt_end;
648 u64 vram_start;
649 u64 vram_end;
650 unsigned vram_width;
651 u64 real_vram_size;
652 int vram_mtrr;
653 bool vram_is_ddr;
654 bool igp_sideport_enabled;
655 u64 gtt_base_align;
656 u64 mc_mask;
657 };
658
659 bool radeon_combios_sideport_present(struct radeon_device *rdev);
660 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
661
662 /*
663 * GPU scratch registers structures, functions & helpers
664 */
665 struct radeon_scratch {
666 unsigned num_reg;
667 uint32_t reg_base;
668 bool free[32];
669 uint32_t reg[32];
670 };
671
672 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
673 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
674
675 /*
676 * GPU doorbell structures, functions & helpers
677 */
678 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
679
680 struct radeon_doorbell {
681 /* doorbell mmio */
682 resource_size_t base;
683 resource_size_t size;
684 u32 __iomem *ptr;
685 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
686 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
687 };
688
689 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
690 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
691
692 /*
693 * IRQS.
694 */
695
696 struct radeon_flip_work {
697 struct work_struct flip_work;
698 struct work_struct unpin_work;
699 struct radeon_device *rdev;
700 int crtc_id;
701 uint64_t base;
702 struct drm_pending_vblank_event *event;
703 struct radeon_bo *old_rbo;
704 struct radeon_fence *fence;
705 };
706
707 struct r500_irq_stat_regs {
708 u32 disp_int;
709 u32 hdmi0_status;
710 };
711
712 struct r600_irq_stat_regs {
713 u32 disp_int;
714 u32 disp_int_cont;
715 u32 disp_int_cont2;
716 u32 d1grph_int;
717 u32 d2grph_int;
718 u32 hdmi0_status;
719 u32 hdmi1_status;
720 };
721
722 struct evergreen_irq_stat_regs {
723 u32 disp_int;
724 u32 disp_int_cont;
725 u32 disp_int_cont2;
726 u32 disp_int_cont3;
727 u32 disp_int_cont4;
728 u32 disp_int_cont5;
729 u32 d1grph_int;
730 u32 d2grph_int;
731 u32 d3grph_int;
732 u32 d4grph_int;
733 u32 d5grph_int;
734 u32 d6grph_int;
735 u32 afmt_status1;
736 u32 afmt_status2;
737 u32 afmt_status3;
738 u32 afmt_status4;
739 u32 afmt_status5;
740 u32 afmt_status6;
741 };
742
743 struct cik_irq_stat_regs {
744 u32 disp_int;
745 u32 disp_int_cont;
746 u32 disp_int_cont2;
747 u32 disp_int_cont3;
748 u32 disp_int_cont4;
749 u32 disp_int_cont5;
750 u32 disp_int_cont6;
751 u32 d1grph_int;
752 u32 d2grph_int;
753 u32 d3grph_int;
754 u32 d4grph_int;
755 u32 d5grph_int;
756 u32 d6grph_int;
757 };
758
759 union radeon_irq_stat_regs {
760 struct r500_irq_stat_regs r500;
761 struct r600_irq_stat_regs r600;
762 struct evergreen_irq_stat_regs evergreen;
763 struct cik_irq_stat_regs cik;
764 };
765
766 struct radeon_irq {
767 bool installed;
768 spinlock_t lock;
769 atomic_t ring_int[RADEON_NUM_RINGS];
770 bool crtc_vblank_int[RADEON_MAX_CRTCS];
771 atomic_t pflip[RADEON_MAX_CRTCS];
772 wait_queue_head_t vblank_queue;
773 bool hpd[RADEON_MAX_HPD_PINS];
774 bool afmt[RADEON_MAX_AFMT_BLOCKS];
775 union radeon_irq_stat_regs stat_regs;
776 bool dpm_thermal;
777 };
778
779 int radeon_irq_kms_init(struct radeon_device *rdev);
780 void radeon_irq_kms_fini(struct radeon_device *rdev);
781 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
782 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
783 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
784 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
785 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
786 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
787 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
788 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
789
790 /*
791 * CP & rings.
792 */
793
794 struct radeon_ib {
795 struct radeon_sa_bo *sa_bo;
796 uint32_t length_dw;
797 uint64_t gpu_addr;
798 uint32_t *ptr;
799 int ring;
800 struct radeon_fence *fence;
801 struct radeon_vm *vm;
802 bool is_const_ib;
803 struct radeon_semaphore *semaphore;
804 };
805
806 struct radeon_ring {
807 struct radeon_bo *ring_obj;
808 volatile uint32_t *ring;
809 unsigned rptr_offs;
810 unsigned rptr_save_reg;
811 u64 next_rptr_gpu_addr;
812 volatile u32 *next_rptr_cpu_addr;
813 unsigned wptr;
814 unsigned wptr_old;
815 unsigned ring_size;
816 unsigned ring_free_dw;
817 int count_dw;
818 atomic_t last_rptr;
819 atomic64_t last_activity;
820 uint64_t gpu_addr;
821 uint32_t align_mask;
822 uint32_t ptr_mask;
823 bool ready;
824 u32 nop;
825 u32 idx;
826 u64 last_semaphore_signal_addr;
827 u64 last_semaphore_wait_addr;
828 /* for CIK queues */
829 u32 me;
830 u32 pipe;
831 u32 queue;
832 struct radeon_bo *mqd_obj;
833 u32 doorbell_index;
834 unsigned wptr_offs;
835 };
836
837 struct radeon_mec {
838 struct radeon_bo *hpd_eop_obj;
839 u64 hpd_eop_gpu_addr;
840 u32 num_pipe;
841 u32 num_mec;
842 u32 num_queue;
843 };
844
845 /*
846 * VM
847 */
848
849 /* maximum number of VMIDs */
850 #define RADEON_NUM_VM 16
851
852 /* number of entries in page table */
853 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
854
855 /* PTBs (Page Table Blocks) need to be aligned to 32K */
856 #define RADEON_VM_PTB_ALIGN_SIZE 32768
857 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
858 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
859
860 #define R600_PTE_VALID (1 << 0)
861 #define R600_PTE_SYSTEM (1 << 1)
862 #define R600_PTE_SNOOPED (1 << 2)
863 #define R600_PTE_READABLE (1 << 5)
864 #define R600_PTE_WRITEABLE (1 << 6)
865
866 /* PTE (Page Table Entry) fragment field for different page sizes */
867 #define R600_PTE_FRAG_4KB (0 << 7)
868 #define R600_PTE_FRAG_64KB (4 << 7)
869 #define R600_PTE_FRAG_256KB (6 << 7)
870
871 /* flags needed to be set so we can copy directly from the GART table */
872 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
873 R600_PTE_SYSTEM | R600_PTE_VALID )
874
875 struct radeon_vm_pt {
876 struct radeon_bo *bo;
877 uint64_t addr;
878 };
879
880 struct radeon_vm {
881 struct rb_root va;
882 unsigned id;
883
884 /* BOs moved, but not yet updated in the PT */
885 struct list_head invalidated;
886
887 /* BOs freed, but not yet updated in the PT */
888 struct list_head freed;
889
890 /* contains the page directory */
891 struct radeon_bo *page_directory;
892 uint64_t pd_gpu_addr;
893 unsigned max_pde_used;
894
895 /* array of page tables, one for each page directory entry */
896 struct radeon_vm_pt *page_tables;
897
898 struct radeon_bo_va *ib_bo_va;
899
900 struct mutex mutex;
901 /* last fence for cs using this vm */
902 struct radeon_fence *fence;
903 /* last flush or NULL if we still need to flush */
904 struct radeon_fence *last_flush;
905 /* last use of vmid */
906 struct radeon_fence *last_id_use;
907 };
908
909 struct radeon_vm_manager {
910 struct radeon_fence *active[RADEON_NUM_VM];
911 uint32_t max_pfn;
912 /* number of VMIDs */
913 unsigned nvm;
914 /* vram base address for page table entry */
915 u64 vram_base_offset;
916 /* is vm enabled? */
917 bool enabled;
918 /* for hw to save the PD addr on suspend/resume */
919 uint32_t saved_table_addr[RADEON_NUM_VM];
920 };
921
922 /*
923 * file private structure
924 */
925 struct radeon_fpriv {
926 struct radeon_vm vm;
927 };
928
929 /*
930 * R6xx+ IH ring
931 */
932 struct r600_ih {
933 struct radeon_bo *ring_obj;
934 volatile uint32_t *ring;
935 unsigned rptr;
936 unsigned ring_size;
937 uint64_t gpu_addr;
938 uint32_t ptr_mask;
939 atomic_t lock;
940 bool enabled;
941 };
942
943 /*
944 * RLC stuff
945 */
946 #include "clearstate_defs.h"
947
948 struct radeon_rlc {
949 /* for power gating */
950 struct radeon_bo *save_restore_obj;
951 uint64_t save_restore_gpu_addr;
952 volatile uint32_t *sr_ptr;
953 const u32 *reg_list;
954 u32 reg_list_size;
955 /* for clear state */
956 struct radeon_bo *clear_state_obj;
957 uint64_t clear_state_gpu_addr;
958 volatile uint32_t *cs_ptr;
959 const struct cs_section_def *cs_data;
960 u32 clear_state_size;
961 /* for cp tables */
962 struct radeon_bo *cp_table_obj;
963 uint64_t cp_table_gpu_addr;
964 volatile uint32_t *cp_table_ptr;
965 u32 cp_table_size;
966 };
967
968 int radeon_ib_get(struct radeon_device *rdev, int ring,
969 struct radeon_ib *ib, struct radeon_vm *vm,
970 unsigned size);
971 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
972 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
973 struct radeon_ib *const_ib, bool hdp_flush);
974 int radeon_ib_pool_init(struct radeon_device *rdev);
975 void radeon_ib_pool_fini(struct radeon_device *rdev);
976 int radeon_ib_ring_tests(struct radeon_device *rdev);
977 /* Ring access between begin & end cannot sleep */
978 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
979 struct radeon_ring *ring);
980 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
981 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
982 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
983 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
984 bool hdp_flush);
985 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
986 bool hdp_flush);
987 void radeon_ring_undo(struct radeon_ring *ring);
988 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
989 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
990 void radeon_ring_lockup_update(struct radeon_device *rdev,
991 struct radeon_ring *ring);
992 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
993 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
994 uint32_t **data);
995 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
996 unsigned size, uint32_t *data);
997 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
998 unsigned rptr_offs, u32 nop);
999 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1000
1001
1002 /* r600 async dma */
1003 void r600_dma_stop(struct radeon_device *rdev);
1004 int r600_dma_resume(struct radeon_device *rdev);
1005 void r600_dma_fini(struct radeon_device *rdev);
1006
1007 void cayman_dma_stop(struct radeon_device *rdev);
1008 int cayman_dma_resume(struct radeon_device *rdev);
1009 void cayman_dma_fini(struct radeon_device *rdev);
1010
1011 /*
1012 * CS.
1013 */
1014 struct radeon_cs_reloc {
1015 struct drm_gem_object *gobj;
1016 struct radeon_bo *robj;
1017 struct ttm_validate_buffer tv;
1018 uint64_t gpu_offset;
1019 unsigned prefered_domains;
1020 unsigned allowed_domains;
1021 uint32_t tiling_flags;
1022 uint32_t handle;
1023 };
1024
1025 struct radeon_cs_chunk {
1026 uint32_t chunk_id;
1027 uint32_t length_dw;
1028 uint32_t *kdata;
1029 void __user *user_ptr;
1030 };
1031
1032 struct radeon_cs_parser {
1033 struct device *dev;
1034 struct radeon_device *rdev;
1035 struct drm_file *filp;
1036 /* chunks */
1037 unsigned nchunks;
1038 struct radeon_cs_chunk *chunks;
1039 uint64_t *chunks_array;
1040 /* IB */
1041 unsigned idx;
1042 /* relocations */
1043 unsigned nrelocs;
1044 struct radeon_cs_reloc *relocs;
1045 struct radeon_cs_reloc **relocs_ptr;
1046 struct radeon_cs_reloc *vm_bos;
1047 struct list_head validated;
1048 unsigned dma_reloc_idx;
1049 /* indices of various chunks */
1050 int chunk_ib_idx;
1051 int chunk_relocs_idx;
1052 int chunk_flags_idx;
1053 int chunk_const_ib_idx;
1054 struct radeon_ib ib;
1055 struct radeon_ib const_ib;
1056 void *track;
1057 unsigned family;
1058 int parser_error;
1059 u32 cs_flags;
1060 u32 ring;
1061 s32 priority;
1062 struct ww_acquire_ctx ticket;
1063 };
1064
1065 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1066 {
1067 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1068
1069 if (ibc->kdata)
1070 return ibc->kdata[idx];
1071 return p->ib.ptr[idx];
1072 }
1073
1074
1075 struct radeon_cs_packet {
1076 unsigned idx;
1077 unsigned type;
1078 unsigned reg;
1079 unsigned opcode;
1080 int count;
1081 unsigned one_reg_wr;
1082 };
1083
1084 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1085 struct radeon_cs_packet *pkt,
1086 unsigned idx, unsigned reg);
1087 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1088 struct radeon_cs_packet *pkt);
1089
1090
1091 /*
1092 * AGP
1093 */
1094 int radeon_agp_init(struct radeon_device *rdev);
1095 void radeon_agp_resume(struct radeon_device *rdev);
1096 void radeon_agp_suspend(struct radeon_device *rdev);
1097 void radeon_agp_fini(struct radeon_device *rdev);
1098
1099
1100 /*
1101 * Writeback
1102 */
1103 struct radeon_wb {
1104 struct radeon_bo *wb_obj;
1105 volatile uint32_t *wb;
1106 uint64_t gpu_addr;
1107 bool enabled;
1108 bool use_event;
1109 };
1110
1111 #define RADEON_WB_SCRATCH_OFFSET 0
1112 #define RADEON_WB_RING0_NEXT_RPTR 256
1113 #define RADEON_WB_CP_RPTR_OFFSET 1024
1114 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1115 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1116 #define R600_WB_DMA_RPTR_OFFSET 1792
1117 #define R600_WB_IH_WPTR_OFFSET 2048
1118 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1119 #define R600_WB_EVENT_OFFSET 3072
1120 #define CIK_WB_CP1_WPTR_OFFSET 3328
1121 #define CIK_WB_CP2_WPTR_OFFSET 3584
1122
1123 /**
1124 * struct radeon_pm - power management datas
1125 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1126 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1127 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1128 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1129 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1130 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1131 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1132 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1133 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1134 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1135 * @needed_bandwidth: current bandwidth needs
1136 *
1137 * It keeps track of various data needed to take powermanagement decision.
1138 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1139 * Equation between gpu/memory clock and available bandwidth is hw dependent
1140 * (type of memory, bus size, efficiency, ...)
1141 */
1142
1143 enum radeon_pm_method {
1144 PM_METHOD_PROFILE,
1145 PM_METHOD_DYNPM,
1146 PM_METHOD_DPM,
1147 };
1148
1149 enum radeon_dynpm_state {
1150 DYNPM_STATE_DISABLED,
1151 DYNPM_STATE_MINIMUM,
1152 DYNPM_STATE_PAUSED,
1153 DYNPM_STATE_ACTIVE,
1154 DYNPM_STATE_SUSPENDED,
1155 };
1156 enum radeon_dynpm_action {
1157 DYNPM_ACTION_NONE,
1158 DYNPM_ACTION_MINIMUM,
1159 DYNPM_ACTION_DOWNCLOCK,
1160 DYNPM_ACTION_UPCLOCK,
1161 DYNPM_ACTION_DEFAULT
1162 };
1163
1164 enum radeon_voltage_type {
1165 VOLTAGE_NONE = 0,
1166 VOLTAGE_GPIO,
1167 VOLTAGE_VDDC,
1168 VOLTAGE_SW
1169 };
1170
1171 enum radeon_pm_state_type {
1172 /* not used for dpm */
1173 POWER_STATE_TYPE_DEFAULT,
1174 POWER_STATE_TYPE_POWERSAVE,
1175 /* user selectable states */
1176 POWER_STATE_TYPE_BATTERY,
1177 POWER_STATE_TYPE_BALANCED,
1178 POWER_STATE_TYPE_PERFORMANCE,
1179 /* internal states */
1180 POWER_STATE_TYPE_INTERNAL_UVD,
1181 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1182 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1183 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1184 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1185 POWER_STATE_TYPE_INTERNAL_BOOT,
1186 POWER_STATE_TYPE_INTERNAL_THERMAL,
1187 POWER_STATE_TYPE_INTERNAL_ACPI,
1188 POWER_STATE_TYPE_INTERNAL_ULV,
1189 POWER_STATE_TYPE_INTERNAL_3DPERF,
1190 };
1191
1192 enum radeon_pm_profile_type {
1193 PM_PROFILE_DEFAULT,
1194 PM_PROFILE_AUTO,
1195 PM_PROFILE_LOW,
1196 PM_PROFILE_MID,
1197 PM_PROFILE_HIGH,
1198 };
1199
1200 #define PM_PROFILE_DEFAULT_IDX 0
1201 #define PM_PROFILE_LOW_SH_IDX 1
1202 #define PM_PROFILE_MID_SH_IDX 2
1203 #define PM_PROFILE_HIGH_SH_IDX 3
1204 #define PM_PROFILE_LOW_MH_IDX 4
1205 #define PM_PROFILE_MID_MH_IDX 5
1206 #define PM_PROFILE_HIGH_MH_IDX 6
1207 #define PM_PROFILE_MAX 7
1208
1209 struct radeon_pm_profile {
1210 int dpms_off_ps_idx;
1211 int dpms_on_ps_idx;
1212 int dpms_off_cm_idx;
1213 int dpms_on_cm_idx;
1214 };
1215
1216 enum radeon_int_thermal_type {
1217 THERMAL_TYPE_NONE,
1218 THERMAL_TYPE_EXTERNAL,
1219 THERMAL_TYPE_EXTERNAL_GPIO,
1220 THERMAL_TYPE_RV6XX,
1221 THERMAL_TYPE_RV770,
1222 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1223 THERMAL_TYPE_EVERGREEN,
1224 THERMAL_TYPE_SUMO,
1225 THERMAL_TYPE_NI,
1226 THERMAL_TYPE_SI,
1227 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1228 THERMAL_TYPE_CI,
1229 THERMAL_TYPE_KV,
1230 };
1231
1232 struct radeon_voltage {
1233 enum radeon_voltage_type type;
1234 /* gpio voltage */
1235 struct radeon_gpio_rec gpio;
1236 u32 delay; /* delay in usec from voltage drop to sclk change */
1237 bool active_high; /* voltage drop is active when bit is high */
1238 /* VDDC voltage */
1239 u8 vddc_id; /* index into vddc voltage table */
1240 u8 vddci_id; /* index into vddci voltage table */
1241 bool vddci_enabled;
1242 /* r6xx+ sw */
1243 u16 voltage;
1244 /* evergreen+ vddci */
1245 u16 vddci;
1246 };
1247
1248 /* clock mode flags */
1249 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1250
1251 struct radeon_pm_clock_info {
1252 /* memory clock */
1253 u32 mclk;
1254 /* engine clock */
1255 u32 sclk;
1256 /* voltage info */
1257 struct radeon_voltage voltage;
1258 /* standardized clock flags */
1259 u32 flags;
1260 };
1261
1262 /* state flags */
1263 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1264
1265 struct radeon_power_state {
1266 enum radeon_pm_state_type type;
1267 struct radeon_pm_clock_info *clock_info;
1268 /* number of valid clock modes in this power state */
1269 int num_clock_modes;
1270 struct radeon_pm_clock_info *default_clock_mode;
1271 /* standardized state flags */
1272 u32 flags;
1273 u32 misc; /* vbios specific flags */
1274 u32 misc2; /* vbios specific flags */
1275 int pcie_lanes; /* pcie lanes */
1276 };
1277
1278 /*
1279 * Some modes are overclocked by very low value, accept them
1280 */
1281 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1282
1283 enum radeon_dpm_auto_throttle_src {
1284 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1285 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1286 };
1287
1288 enum radeon_dpm_event_src {
1289 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1290 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1291 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1292 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1293 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1294 };
1295
1296 #define RADEON_MAX_VCE_LEVELS 6
1297
1298 enum radeon_vce_level {
1299 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1300 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1301 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1302 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1303 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1304 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1305 };
1306
1307 struct radeon_ps {
1308 u32 caps; /* vbios flags */
1309 u32 class; /* vbios flags */
1310 u32 class2; /* vbios flags */
1311 /* UVD clocks */
1312 u32 vclk;
1313 u32 dclk;
1314 /* VCE clocks */
1315 u32 evclk;
1316 u32 ecclk;
1317 bool vce_active;
1318 enum radeon_vce_level vce_level;
1319 /* asic priv */
1320 void *ps_priv;
1321 };
1322
1323 struct radeon_dpm_thermal {
1324 /* thermal interrupt work */
1325 struct work_struct work;
1326 /* low temperature threshold */
1327 int min_temp;
1328 /* high temperature threshold */
1329 int max_temp;
1330 /* was interrupt low to high or high to low */
1331 bool high_to_low;
1332 };
1333
1334 enum radeon_clk_action
1335 {
1336 RADEON_SCLK_UP = 1,
1337 RADEON_SCLK_DOWN
1338 };
1339
1340 struct radeon_blacklist_clocks
1341 {
1342 u32 sclk;
1343 u32 mclk;
1344 enum radeon_clk_action action;
1345 };
1346
1347 struct radeon_clock_and_voltage_limits {
1348 u32 sclk;
1349 u32 mclk;
1350 u16 vddc;
1351 u16 vddci;
1352 };
1353
1354 struct radeon_clock_array {
1355 u32 count;
1356 u32 *values;
1357 };
1358
1359 struct radeon_clock_voltage_dependency_entry {
1360 u32 clk;
1361 u16 v;
1362 };
1363
1364 struct radeon_clock_voltage_dependency_table {
1365 u32 count;
1366 struct radeon_clock_voltage_dependency_entry *entries;
1367 };
1368
1369 union radeon_cac_leakage_entry {
1370 struct {
1371 u16 vddc;
1372 u32 leakage;
1373 };
1374 struct {
1375 u16 vddc1;
1376 u16 vddc2;
1377 u16 vddc3;
1378 };
1379 };
1380
1381 struct radeon_cac_leakage_table {
1382 u32 count;
1383 union radeon_cac_leakage_entry *entries;
1384 };
1385
1386 struct radeon_phase_shedding_limits_entry {
1387 u16 voltage;
1388 u32 sclk;
1389 u32 mclk;
1390 };
1391
1392 struct radeon_phase_shedding_limits_table {
1393 u32 count;
1394 struct radeon_phase_shedding_limits_entry *entries;
1395 };
1396
1397 struct radeon_uvd_clock_voltage_dependency_entry {
1398 u32 vclk;
1399 u32 dclk;
1400 u16 v;
1401 };
1402
1403 struct radeon_uvd_clock_voltage_dependency_table {
1404 u8 count;
1405 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1406 };
1407
1408 struct radeon_vce_clock_voltage_dependency_entry {
1409 u32 ecclk;
1410 u32 evclk;
1411 u16 v;
1412 };
1413
1414 struct radeon_vce_clock_voltage_dependency_table {
1415 u8 count;
1416 struct radeon_vce_clock_voltage_dependency_entry *entries;
1417 };
1418
1419 struct radeon_ppm_table {
1420 u8 ppm_design;
1421 u16 cpu_core_number;
1422 u32 platform_tdp;
1423 u32 small_ac_platform_tdp;
1424 u32 platform_tdc;
1425 u32 small_ac_platform_tdc;
1426 u32 apu_tdp;
1427 u32 dgpu_tdp;
1428 u32 dgpu_ulv_power;
1429 u32 tj_max;
1430 };
1431
1432 struct radeon_cac_tdp_table {
1433 u16 tdp;
1434 u16 configurable_tdp;
1435 u16 tdc;
1436 u16 battery_power_limit;
1437 u16 small_power_limit;
1438 u16 low_cac_leakage;
1439 u16 high_cac_leakage;
1440 u16 maximum_power_delivery_limit;
1441 };
1442
1443 struct radeon_dpm_dynamic_state {
1444 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1445 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1446 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1447 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1448 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1449 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1450 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1451 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1452 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1453 struct radeon_clock_array valid_sclk_values;
1454 struct radeon_clock_array valid_mclk_values;
1455 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1456 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1457 u32 mclk_sclk_ratio;
1458 u32 sclk_mclk_delta;
1459 u16 vddc_vddci_delta;
1460 u16 min_vddc_for_pcie_gen2;
1461 struct radeon_cac_leakage_table cac_leakage_table;
1462 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1463 struct radeon_ppm_table *ppm_table;
1464 struct radeon_cac_tdp_table *cac_tdp_table;
1465 };
1466
1467 struct radeon_dpm_fan {
1468 u16 t_min;
1469 u16 t_med;
1470 u16 t_high;
1471 u16 pwm_min;
1472 u16 pwm_med;
1473 u16 pwm_high;
1474 u8 t_hyst;
1475 u32 cycle_delay;
1476 u16 t_max;
1477 bool ucode_fan_control;
1478 };
1479
1480 enum radeon_pcie_gen {
1481 RADEON_PCIE_GEN1 = 0,
1482 RADEON_PCIE_GEN2 = 1,
1483 RADEON_PCIE_GEN3 = 2,
1484 RADEON_PCIE_GEN_INVALID = 0xffff
1485 };
1486
1487 enum radeon_dpm_forced_level {
1488 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1489 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1490 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1491 };
1492
1493 struct radeon_vce_state {
1494 /* vce clocks */
1495 u32 evclk;
1496 u32 ecclk;
1497 /* gpu clocks */
1498 u32 sclk;
1499 u32 mclk;
1500 u8 clk_idx;
1501 u8 pstate;
1502 };
1503
1504 struct radeon_dpm {
1505 struct radeon_ps *ps;
1506 /* number of valid power states */
1507 int num_ps;
1508 /* current power state that is active */
1509 struct radeon_ps *current_ps;
1510 /* requested power state */
1511 struct radeon_ps *requested_ps;
1512 /* boot up power state */
1513 struct radeon_ps *boot_ps;
1514 /* default uvd power state */
1515 struct radeon_ps *uvd_ps;
1516 /* vce requirements */
1517 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1518 enum radeon_vce_level vce_level;
1519 enum radeon_pm_state_type state;
1520 enum radeon_pm_state_type user_state;
1521 u32 platform_caps;
1522 u32 voltage_response_time;
1523 u32 backbias_response_time;
1524 void *priv;
1525 u32 new_active_crtcs;
1526 int new_active_crtc_count;
1527 u32 current_active_crtcs;
1528 int current_active_crtc_count;
1529 struct radeon_dpm_dynamic_state dyn_state;
1530 struct radeon_dpm_fan fan;
1531 u32 tdp_limit;
1532 u32 near_tdp_limit;
1533 u32 near_tdp_limit_adjusted;
1534 u32 sq_ramping_threshold;
1535 u32 cac_leakage;
1536 u16 tdp_od_limit;
1537 u32 tdp_adjustment;
1538 u16 load_line_slope;
1539 bool power_control;
1540 bool ac_power;
1541 /* special states active */
1542 bool thermal_active;
1543 bool uvd_active;
1544 bool vce_active;
1545 /* thermal handling */
1546 struct radeon_dpm_thermal thermal;
1547 /* forced levels */
1548 enum radeon_dpm_forced_level forced_level;
1549 /* track UVD streams */
1550 unsigned sd;
1551 unsigned hd;
1552 };
1553
1554 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1555 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1556
1557 struct radeon_pm {
1558 struct mutex mutex;
1559 /* write locked while reprogramming mclk */
1560 struct rw_semaphore mclk_lock;
1561 u32 active_crtcs;
1562 int active_crtc_count;
1563 int req_vblank;
1564 bool vblank_sync;
1565 fixed20_12 max_bandwidth;
1566 fixed20_12 igp_sideport_mclk;
1567 fixed20_12 igp_system_mclk;
1568 fixed20_12 igp_ht_link_clk;
1569 fixed20_12 igp_ht_link_width;
1570 fixed20_12 k8_bandwidth;
1571 fixed20_12 sideport_bandwidth;
1572 fixed20_12 ht_bandwidth;
1573 fixed20_12 core_bandwidth;
1574 fixed20_12 sclk;
1575 fixed20_12 mclk;
1576 fixed20_12 needed_bandwidth;
1577 struct radeon_power_state *power_state;
1578 /* number of valid power states */
1579 int num_power_states;
1580 int current_power_state_index;
1581 int current_clock_mode_index;
1582 int requested_power_state_index;
1583 int requested_clock_mode_index;
1584 int default_power_state_index;
1585 u32 current_sclk;
1586 u32 current_mclk;
1587 u16 current_vddc;
1588 u16 current_vddci;
1589 u32 default_sclk;
1590 u32 default_mclk;
1591 u16 default_vddc;
1592 u16 default_vddci;
1593 struct radeon_i2c_chan *i2c_bus;
1594 /* selected pm method */
1595 enum radeon_pm_method pm_method;
1596 /* dynpm power management */
1597 struct delayed_work dynpm_idle_work;
1598 enum radeon_dynpm_state dynpm_state;
1599 enum radeon_dynpm_action dynpm_planned_action;
1600 unsigned long dynpm_action_timeout;
1601 bool dynpm_can_upclock;
1602 bool dynpm_can_downclock;
1603 /* profile-based power management */
1604 enum radeon_pm_profile_type profile;
1605 int profile_index;
1606 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1607 /* internal thermal controller on rv6xx+ */
1608 enum radeon_int_thermal_type int_thermal_type;
1609 struct device *int_hwmon_dev;
1610 /* dpm */
1611 bool dpm_enabled;
1612 struct radeon_dpm dpm;
1613 };
1614
1615 int radeon_pm_get_type_index(struct radeon_device *rdev,
1616 enum radeon_pm_state_type ps_type,
1617 int instance);
1618 /*
1619 * UVD
1620 */
1621 #define RADEON_MAX_UVD_HANDLES 10
1622 #define RADEON_UVD_STACK_SIZE (1024*1024)
1623 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1624
1625 struct radeon_uvd {
1626 struct radeon_bo *vcpu_bo;
1627 void *cpu_addr;
1628 uint64_t gpu_addr;
1629 void *saved_bo;
1630 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1631 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1632 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1633 struct delayed_work idle_work;
1634 };
1635
1636 int radeon_uvd_init(struct radeon_device *rdev);
1637 void radeon_uvd_fini(struct radeon_device *rdev);
1638 int radeon_uvd_suspend(struct radeon_device *rdev);
1639 int radeon_uvd_resume(struct radeon_device *rdev);
1640 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1641 uint32_t handle, struct radeon_fence **fence);
1642 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1643 uint32_t handle, struct radeon_fence **fence);
1644 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1645 void radeon_uvd_free_handles(struct radeon_device *rdev,
1646 struct drm_file *filp);
1647 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1648 void radeon_uvd_note_usage(struct radeon_device *rdev);
1649 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1650 unsigned vclk, unsigned dclk,
1651 unsigned vco_min, unsigned vco_max,
1652 unsigned fb_factor, unsigned fb_mask,
1653 unsigned pd_min, unsigned pd_max,
1654 unsigned pd_even,
1655 unsigned *optimal_fb_div,
1656 unsigned *optimal_vclk_div,
1657 unsigned *optimal_dclk_div);
1658 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1659 unsigned cg_upll_func_cntl);
1660
1661 /*
1662 * VCE
1663 */
1664 #define RADEON_MAX_VCE_HANDLES 16
1665 #define RADEON_VCE_STACK_SIZE (1024*1024)
1666 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1667
1668 struct radeon_vce {
1669 struct radeon_bo *vcpu_bo;
1670 uint64_t gpu_addr;
1671 unsigned fw_version;
1672 unsigned fb_version;
1673 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1674 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1675 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1676 struct delayed_work idle_work;
1677 };
1678
1679 int radeon_vce_init(struct radeon_device *rdev);
1680 void radeon_vce_fini(struct radeon_device *rdev);
1681 int radeon_vce_suspend(struct radeon_device *rdev);
1682 int radeon_vce_resume(struct radeon_device *rdev);
1683 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1684 uint32_t handle, struct radeon_fence **fence);
1685 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1686 uint32_t handle, struct radeon_fence **fence);
1687 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1688 void radeon_vce_note_usage(struct radeon_device *rdev);
1689 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1690 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1691 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1692 struct radeon_ring *ring,
1693 struct radeon_semaphore *semaphore,
1694 bool emit_wait);
1695 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1696 void radeon_vce_fence_emit(struct radeon_device *rdev,
1697 struct radeon_fence *fence);
1698 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1699 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1700
1701 struct r600_audio_pin {
1702 int channels;
1703 int rate;
1704 int bits_per_sample;
1705 u8 status_bits;
1706 u8 category_code;
1707 u32 offset;
1708 bool connected;
1709 u32 id;
1710 };
1711
1712 struct r600_audio {
1713 bool enabled;
1714 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1715 int num_pins;
1716 };
1717
1718 /*
1719 * Benchmarking
1720 */
1721 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1722
1723
1724 /*
1725 * Testing
1726 */
1727 void radeon_test_moves(struct radeon_device *rdev);
1728 void radeon_test_ring_sync(struct radeon_device *rdev,
1729 struct radeon_ring *cpA,
1730 struct radeon_ring *cpB);
1731 void radeon_test_syncing(struct radeon_device *rdev);
1732
1733
1734 /*
1735 * Debugfs
1736 */
1737 struct radeon_debugfs {
1738 struct drm_info_list *files;
1739 unsigned num_files;
1740 };
1741
1742 int radeon_debugfs_add_files(struct radeon_device *rdev,
1743 struct drm_info_list *files,
1744 unsigned nfiles);
1745 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1746
1747 /*
1748 * ASIC ring specific functions.
1749 */
1750 struct radeon_asic_ring {
1751 /* ring read/write ptr handling */
1752 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1753 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1754 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1755
1756 /* validating and patching of IBs */
1757 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1758 int (*cs_parse)(struct radeon_cs_parser *p);
1759
1760 /* command emmit functions */
1761 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1762 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1763 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1764 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1765 struct radeon_semaphore *semaphore, bool emit_wait);
1766 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1767
1768 /* testing functions */
1769 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1770 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1771 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1772
1773 /* deprecated */
1774 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1775 };
1776
1777 /*
1778 * ASIC specific functions.
1779 */
1780 struct radeon_asic {
1781 int (*init)(struct radeon_device *rdev);
1782 void (*fini)(struct radeon_device *rdev);
1783 int (*resume)(struct radeon_device *rdev);
1784 int (*suspend)(struct radeon_device *rdev);
1785 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1786 int (*asic_reset)(struct radeon_device *rdev);
1787 /* Flush the HDP cache via MMIO */
1788 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1789 /* check if 3D engine is idle */
1790 bool (*gui_idle)(struct radeon_device *rdev);
1791 /* wait for mc_idle */
1792 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1793 /* get the reference clock */
1794 u32 (*get_xclk)(struct radeon_device *rdev);
1795 /* get the gpu clock counter */
1796 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1797 /* gart */
1798 struct {
1799 void (*tlb_flush)(struct radeon_device *rdev);
1800 void (*set_page)(struct radeon_device *rdev, unsigned i,
1801 uint64_t addr, uint32_t flags);
1802 } gart;
1803 struct {
1804 int (*init)(struct radeon_device *rdev);
1805 void (*fini)(struct radeon_device *rdev);
1806 void (*copy_pages)(struct radeon_device *rdev,
1807 struct radeon_ib *ib,
1808 uint64_t pe, uint64_t src,
1809 unsigned count);
1810 void (*write_pages)(struct radeon_device *rdev,
1811 struct radeon_ib *ib,
1812 uint64_t pe,
1813 uint64_t addr, unsigned count,
1814 uint32_t incr, uint32_t flags);
1815 void (*set_pages)(struct radeon_device *rdev,
1816 struct radeon_ib *ib,
1817 uint64_t pe,
1818 uint64_t addr, unsigned count,
1819 uint32_t incr, uint32_t flags);
1820 void (*pad_ib)(struct radeon_ib *ib);
1821 } vm;
1822 /* ring specific callbacks */
1823 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1824 /* irqs */
1825 struct {
1826 int (*set)(struct radeon_device *rdev);
1827 int (*process)(struct radeon_device *rdev);
1828 } irq;
1829 /* displays */
1830 struct {
1831 /* display watermarks */
1832 void (*bandwidth_update)(struct radeon_device *rdev);
1833 /* get frame count */
1834 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1835 /* wait for vblank */
1836 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1837 /* set backlight level */
1838 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1839 /* get backlight level */
1840 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1841 /* audio callbacks */
1842 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1843 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1844 } display;
1845 /* copy functions for bo handling */
1846 struct {
1847 int (*blit)(struct radeon_device *rdev,
1848 uint64_t src_offset,
1849 uint64_t dst_offset,
1850 unsigned num_gpu_pages,
1851 struct radeon_fence **fence);
1852 u32 blit_ring_index;
1853 int (*dma)(struct radeon_device *rdev,
1854 uint64_t src_offset,
1855 uint64_t dst_offset,
1856 unsigned num_gpu_pages,
1857 struct radeon_fence **fence);
1858 u32 dma_ring_index;
1859 /* method used for bo copy */
1860 int (*copy)(struct radeon_device *rdev,
1861 uint64_t src_offset,
1862 uint64_t dst_offset,
1863 unsigned num_gpu_pages,
1864 struct radeon_fence **fence);
1865 /* ring used for bo copies */
1866 u32 copy_ring_index;
1867 } copy;
1868 /* surfaces */
1869 struct {
1870 int (*set_reg)(struct radeon_device *rdev, int reg,
1871 uint32_t tiling_flags, uint32_t pitch,
1872 uint32_t offset, uint32_t obj_size);
1873 void (*clear_reg)(struct radeon_device *rdev, int reg);
1874 } surface;
1875 /* hotplug detect */
1876 struct {
1877 void (*init)(struct radeon_device *rdev);
1878 void (*fini)(struct radeon_device *rdev);
1879 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1880 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1881 } hpd;
1882 /* static power management */
1883 struct {
1884 void (*misc)(struct radeon_device *rdev);
1885 void (*prepare)(struct radeon_device *rdev);
1886 void (*finish)(struct radeon_device *rdev);
1887 void (*init_profile)(struct radeon_device *rdev);
1888 void (*get_dynpm_state)(struct radeon_device *rdev);
1889 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1890 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1891 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1892 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1893 int (*get_pcie_lanes)(struct radeon_device *rdev);
1894 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1895 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1896 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1897 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1898 int (*get_temperature)(struct radeon_device *rdev);
1899 } pm;
1900 /* dynamic power management */
1901 struct {
1902 int (*init)(struct radeon_device *rdev);
1903 void (*setup_asic)(struct radeon_device *rdev);
1904 int (*enable)(struct radeon_device *rdev);
1905 int (*late_enable)(struct radeon_device *rdev);
1906 void (*disable)(struct radeon_device *rdev);
1907 int (*pre_set_power_state)(struct radeon_device *rdev);
1908 int (*set_power_state)(struct radeon_device *rdev);
1909 void (*post_set_power_state)(struct radeon_device *rdev);
1910 void (*display_configuration_changed)(struct radeon_device *rdev);
1911 void (*fini)(struct radeon_device *rdev);
1912 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1913 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1914 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1915 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1916 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1917 bool (*vblank_too_short)(struct radeon_device *rdev);
1918 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1919 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1920 } dpm;
1921 /* pageflipping */
1922 struct {
1923 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1924 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1925 } pflip;
1926 };
1927
1928 /*
1929 * Asic structures
1930 */
1931 struct r100_asic {
1932 const unsigned *reg_safe_bm;
1933 unsigned reg_safe_bm_size;
1934 u32 hdp_cntl;
1935 };
1936
1937 struct r300_asic {
1938 const unsigned *reg_safe_bm;
1939 unsigned reg_safe_bm_size;
1940 u32 resync_scratch;
1941 u32 hdp_cntl;
1942 };
1943
1944 struct r600_asic {
1945 unsigned max_pipes;
1946 unsigned max_tile_pipes;
1947 unsigned max_simds;
1948 unsigned max_backends;
1949 unsigned max_gprs;
1950 unsigned max_threads;
1951 unsigned max_stack_entries;
1952 unsigned max_hw_contexts;
1953 unsigned max_gs_threads;
1954 unsigned sx_max_export_size;
1955 unsigned sx_max_export_pos_size;
1956 unsigned sx_max_export_smx_size;
1957 unsigned sq_num_cf_insts;
1958 unsigned tiling_nbanks;
1959 unsigned tiling_npipes;
1960 unsigned tiling_group_size;
1961 unsigned tile_config;
1962 unsigned backend_map;
1963 unsigned active_simds;
1964 };
1965
1966 struct rv770_asic {
1967 unsigned max_pipes;
1968 unsigned max_tile_pipes;
1969 unsigned max_simds;
1970 unsigned max_backends;
1971 unsigned max_gprs;
1972 unsigned max_threads;
1973 unsigned max_stack_entries;
1974 unsigned max_hw_contexts;
1975 unsigned max_gs_threads;
1976 unsigned sx_max_export_size;
1977 unsigned sx_max_export_pos_size;
1978 unsigned sx_max_export_smx_size;
1979 unsigned sq_num_cf_insts;
1980 unsigned sx_num_of_sets;
1981 unsigned sc_prim_fifo_size;
1982 unsigned sc_hiz_tile_fifo_size;
1983 unsigned sc_earlyz_tile_fifo_fize;
1984 unsigned tiling_nbanks;
1985 unsigned tiling_npipes;
1986 unsigned tiling_group_size;
1987 unsigned tile_config;
1988 unsigned backend_map;
1989 unsigned active_simds;
1990 };
1991
1992 struct evergreen_asic {
1993 unsigned num_ses;
1994 unsigned max_pipes;
1995 unsigned max_tile_pipes;
1996 unsigned max_simds;
1997 unsigned max_backends;
1998 unsigned max_gprs;
1999 unsigned max_threads;
2000 unsigned max_stack_entries;
2001 unsigned max_hw_contexts;
2002 unsigned max_gs_threads;
2003 unsigned sx_max_export_size;
2004 unsigned sx_max_export_pos_size;
2005 unsigned sx_max_export_smx_size;
2006 unsigned sq_num_cf_insts;
2007 unsigned sx_num_of_sets;
2008 unsigned sc_prim_fifo_size;
2009 unsigned sc_hiz_tile_fifo_size;
2010 unsigned sc_earlyz_tile_fifo_size;
2011 unsigned tiling_nbanks;
2012 unsigned tiling_npipes;
2013 unsigned tiling_group_size;
2014 unsigned tile_config;
2015 unsigned backend_map;
2016 unsigned active_simds;
2017 };
2018
2019 struct cayman_asic {
2020 unsigned max_shader_engines;
2021 unsigned max_pipes_per_simd;
2022 unsigned max_tile_pipes;
2023 unsigned max_simds_per_se;
2024 unsigned max_backends_per_se;
2025 unsigned max_texture_channel_caches;
2026 unsigned max_gprs;
2027 unsigned max_threads;
2028 unsigned max_gs_threads;
2029 unsigned max_stack_entries;
2030 unsigned sx_num_of_sets;
2031 unsigned sx_max_export_size;
2032 unsigned sx_max_export_pos_size;
2033 unsigned sx_max_export_smx_size;
2034 unsigned max_hw_contexts;
2035 unsigned sq_num_cf_insts;
2036 unsigned sc_prim_fifo_size;
2037 unsigned sc_hiz_tile_fifo_size;
2038 unsigned sc_earlyz_tile_fifo_size;
2039
2040 unsigned num_shader_engines;
2041 unsigned num_shader_pipes_per_simd;
2042 unsigned num_tile_pipes;
2043 unsigned num_simds_per_se;
2044 unsigned num_backends_per_se;
2045 unsigned backend_disable_mask_per_asic;
2046 unsigned backend_map;
2047 unsigned num_texture_channel_caches;
2048 unsigned mem_max_burst_length_bytes;
2049 unsigned mem_row_size_in_kb;
2050 unsigned shader_engine_tile_size;
2051 unsigned num_gpus;
2052 unsigned multi_gpu_tile_size;
2053
2054 unsigned tile_config;
2055 unsigned active_simds;
2056 };
2057
2058 struct si_asic {
2059 unsigned max_shader_engines;
2060 unsigned max_tile_pipes;
2061 unsigned max_cu_per_sh;
2062 unsigned max_sh_per_se;
2063 unsigned max_backends_per_se;
2064 unsigned max_texture_channel_caches;
2065 unsigned max_gprs;
2066 unsigned max_gs_threads;
2067 unsigned max_hw_contexts;
2068 unsigned sc_prim_fifo_size_frontend;
2069 unsigned sc_prim_fifo_size_backend;
2070 unsigned sc_hiz_tile_fifo_size;
2071 unsigned sc_earlyz_tile_fifo_size;
2072
2073 unsigned num_tile_pipes;
2074 unsigned backend_enable_mask;
2075 unsigned backend_disable_mask_per_asic;
2076 unsigned backend_map;
2077 unsigned num_texture_channel_caches;
2078 unsigned mem_max_burst_length_bytes;
2079 unsigned mem_row_size_in_kb;
2080 unsigned shader_engine_tile_size;
2081 unsigned num_gpus;
2082 unsigned multi_gpu_tile_size;
2083
2084 unsigned tile_config;
2085 uint32_t tile_mode_array[32];
2086 uint32_t active_cus;
2087 };
2088
2089 struct cik_asic {
2090 unsigned max_shader_engines;
2091 unsigned max_tile_pipes;
2092 unsigned max_cu_per_sh;
2093 unsigned max_sh_per_se;
2094 unsigned max_backends_per_se;
2095 unsigned max_texture_channel_caches;
2096 unsigned max_gprs;
2097 unsigned max_gs_threads;
2098 unsigned max_hw_contexts;
2099 unsigned sc_prim_fifo_size_frontend;
2100 unsigned sc_prim_fifo_size_backend;
2101 unsigned sc_hiz_tile_fifo_size;
2102 unsigned sc_earlyz_tile_fifo_size;
2103
2104 unsigned num_tile_pipes;
2105 unsigned backend_enable_mask;
2106 unsigned backend_disable_mask_per_asic;
2107 unsigned backend_map;
2108 unsigned num_texture_channel_caches;
2109 unsigned mem_max_burst_length_bytes;
2110 unsigned mem_row_size_in_kb;
2111 unsigned shader_engine_tile_size;
2112 unsigned num_gpus;
2113 unsigned multi_gpu_tile_size;
2114
2115 unsigned tile_config;
2116 uint32_t tile_mode_array[32];
2117 uint32_t macrotile_mode_array[16];
2118 uint32_t active_cus;
2119 };
2120
2121 union radeon_asic_config {
2122 struct r300_asic r300;
2123 struct r100_asic r100;
2124 struct r600_asic r600;
2125 struct rv770_asic rv770;
2126 struct evergreen_asic evergreen;
2127 struct cayman_asic cayman;
2128 struct si_asic si;
2129 struct cik_asic cik;
2130 };
2131
2132 /*
2133 * asic initizalization from radeon_asic.c
2134 */
2135 void radeon_agp_disable(struct radeon_device *rdev);
2136 int radeon_asic_init(struct radeon_device *rdev);
2137
2138
2139 /*
2140 * IOCTL.
2141 */
2142 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2143 struct drm_file *filp);
2144 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2145 struct drm_file *filp);
2146 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2147 struct drm_file *file_priv);
2148 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2149 struct drm_file *file_priv);
2150 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2151 struct drm_file *file_priv);
2152 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *file_priv);
2154 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2155 struct drm_file *filp);
2156 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2157 struct drm_file *filp);
2158 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2159 struct drm_file *filp);
2160 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2161 struct drm_file *filp);
2162 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2163 struct drm_file *filp);
2164 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2165 struct drm_file *filp);
2166 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2167 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *filp);
2169 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
2171
2172 /* VRAM scratch page for HDP bug, default vram page */
2173 struct r600_vram_scratch {
2174 struct radeon_bo *robj;
2175 volatile uint32_t *ptr;
2176 u64 gpu_addr;
2177 };
2178
2179 /*
2180 * ACPI
2181 */
2182 struct radeon_atif_notification_cfg {
2183 bool enabled;
2184 int command_code;
2185 };
2186
2187 struct radeon_atif_notifications {
2188 bool display_switch;
2189 bool expansion_mode_change;
2190 bool thermal_state;
2191 bool forced_power_state;
2192 bool system_power_state;
2193 bool display_conf_change;
2194 bool px_gfx_switch;
2195 bool brightness_change;
2196 bool dgpu_display_event;
2197 };
2198
2199 struct radeon_atif_functions {
2200 bool system_params;
2201 bool sbios_requests;
2202 bool select_active_disp;
2203 bool lid_state;
2204 bool get_tv_standard;
2205 bool set_tv_standard;
2206 bool get_panel_expansion_mode;
2207 bool set_panel_expansion_mode;
2208 bool temperature_change;
2209 bool graphics_device_types;
2210 };
2211
2212 struct radeon_atif {
2213 struct radeon_atif_notifications notifications;
2214 struct radeon_atif_functions functions;
2215 struct radeon_atif_notification_cfg notification_cfg;
2216 struct radeon_encoder *encoder_for_bl;
2217 };
2218
2219 struct radeon_atcs_functions {
2220 bool get_ext_state;
2221 bool pcie_perf_req;
2222 bool pcie_dev_rdy;
2223 bool pcie_bus_width;
2224 };
2225
2226 struct radeon_atcs {
2227 struct radeon_atcs_functions functions;
2228 };
2229
2230 /*
2231 * Core structure, functions and helpers.
2232 */
2233 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2234 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2235
2236 struct radeon_device {
2237 struct device *dev;
2238 struct drm_device *ddev;
2239 struct pci_dev *pdev;
2240 struct rw_semaphore exclusive_lock;
2241 /* ASIC */
2242 union radeon_asic_config config;
2243 enum radeon_family family;
2244 unsigned long flags;
2245 int usec_timeout;
2246 enum radeon_pll_errata pll_errata;
2247 int num_gb_pipes;
2248 int num_z_pipes;
2249 int disp_priority;
2250 /* BIOS */
2251 uint8_t *bios;
2252 bool is_atom_bios;
2253 uint16_t bios_header_start;
2254 struct radeon_bo *stollen_vga_memory;
2255 /* Register mmio */
2256 resource_size_t rmmio_base;
2257 resource_size_t rmmio_size;
2258 /* protects concurrent MM_INDEX/DATA based register access */
2259 spinlock_t mmio_idx_lock;
2260 /* protects concurrent SMC based register access */
2261 spinlock_t smc_idx_lock;
2262 /* protects concurrent PLL register access */
2263 spinlock_t pll_idx_lock;
2264 /* protects concurrent MC register access */
2265 spinlock_t mc_idx_lock;
2266 /* protects concurrent PCIE register access */
2267 spinlock_t pcie_idx_lock;
2268 /* protects concurrent PCIE_PORT register access */
2269 spinlock_t pciep_idx_lock;
2270 /* protects concurrent PIF register access */
2271 spinlock_t pif_idx_lock;
2272 /* protects concurrent CG register access */
2273 spinlock_t cg_idx_lock;
2274 /* protects concurrent UVD register access */
2275 spinlock_t uvd_idx_lock;
2276 /* protects concurrent RCU register access */
2277 spinlock_t rcu_idx_lock;
2278 /* protects concurrent DIDT register access */
2279 spinlock_t didt_idx_lock;
2280 /* protects concurrent ENDPOINT (audio) register access */
2281 spinlock_t end_idx_lock;
2282 void __iomem *rmmio;
2283 radeon_rreg_t mc_rreg;
2284 radeon_wreg_t mc_wreg;
2285 radeon_rreg_t pll_rreg;
2286 radeon_wreg_t pll_wreg;
2287 uint32_t pcie_reg_mask;
2288 radeon_rreg_t pciep_rreg;
2289 radeon_wreg_t pciep_wreg;
2290 /* io port */
2291 void __iomem *rio_mem;
2292 resource_size_t rio_mem_size;
2293 struct radeon_clock clock;
2294 struct radeon_mc mc;
2295 struct radeon_gart gart;
2296 struct radeon_mode_info mode_info;
2297 struct radeon_scratch scratch;
2298 struct radeon_doorbell doorbell;
2299 struct radeon_mman mman;
2300 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2301 wait_queue_head_t fence_queue;
2302 struct mutex ring_lock;
2303 struct radeon_ring ring[RADEON_NUM_RINGS];
2304 bool ib_pool_ready;
2305 struct radeon_sa_manager ring_tmp_bo;
2306 struct radeon_irq irq;
2307 struct radeon_asic *asic;
2308 struct radeon_gem gem;
2309 struct radeon_pm pm;
2310 struct radeon_uvd uvd;
2311 struct radeon_vce vce;
2312 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2313 struct radeon_wb wb;
2314 struct radeon_dummy_page dummy_page;
2315 bool shutdown;
2316 bool suspend;
2317 bool need_dma32;
2318 bool accel_working;
2319 bool fastfb_working; /* IGP feature*/
2320 bool needs_reset;
2321 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2322 const struct firmware *me_fw; /* all family ME firmware */
2323 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2324 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2325 const struct firmware *mc_fw; /* NI MC firmware */
2326 const struct firmware *ce_fw; /* SI CE firmware */
2327 const struct firmware *mec_fw; /* CIK MEC firmware */
2328 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2329 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2330 const struct firmware *smc_fw; /* SMC firmware */
2331 const struct firmware *uvd_fw; /* UVD firmware */
2332 const struct firmware *vce_fw; /* VCE firmware */
2333 bool new_fw;
2334 struct r600_vram_scratch vram_scratch;
2335 int msi_enabled; /* msi enabled */
2336 struct r600_ih ih; /* r6/700 interrupt ring */
2337 struct radeon_rlc rlc;
2338 struct radeon_mec mec;
2339 struct work_struct hotplug_work;
2340 struct work_struct audio_work;
2341 struct work_struct reset_work;
2342 int num_crtc; /* number of crtcs */
2343 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2344 bool has_uvd;
2345 struct r600_audio audio; /* audio stuff */
2346 struct notifier_block acpi_nb;
2347 /* only one userspace can use Hyperz features or CMASK at a time */
2348 struct drm_file *hyperz_filp;
2349 struct drm_file *cmask_filp;
2350 /* i2c buses */
2351 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2352 /* debugfs */
2353 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2354 unsigned debugfs_count;
2355 /* virtual memory */
2356 struct radeon_vm_manager vm_manager;
2357 struct mutex gpu_clock_mutex;
2358 /* memory stats */
2359 atomic64_t vram_usage;
2360 atomic64_t gtt_usage;
2361 atomic64_t num_bytes_moved;
2362 /* ACPI interface */
2363 struct radeon_atif atif;
2364 struct radeon_atcs atcs;
2365 /* srbm instance registers */
2366 struct mutex srbm_mutex;
2367 /* clock, powergating flags */
2368 u32 cg_flags;
2369 u32 pg_flags;
2370
2371 struct dev_pm_domain vga_pm_domain;
2372 bool have_disp_power_ref;
2373 u32 px_quirk_flags;
2374
2375 /* tracking pinned memory */
2376 u64 vram_pin_size;
2377 u64 gart_pin_size;
2378 };
2379
2380 bool radeon_is_px(struct drm_device *dev);
2381 int radeon_device_init(struct radeon_device *rdev,
2382 struct drm_device *ddev,
2383 struct pci_dev *pdev,
2384 uint32_t flags);
2385 void radeon_device_fini(struct radeon_device *rdev);
2386 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2387
2388 #define RADEON_MIN_MMIO_SIZE 0x10000
2389
2390 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2391 bool always_indirect)
2392 {
2393 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2394 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2395 return readl(((void __iomem *)rdev->rmmio) + reg);
2396 else {
2397 unsigned long flags;
2398 uint32_t ret;
2399
2400 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2401 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2402 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2403 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2404
2405 return ret;
2406 }
2407 }
2408
2409 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2410 bool always_indirect)
2411 {
2412 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2413 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2414 else {
2415 unsigned long flags;
2416
2417 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2418 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2419 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2420 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2421 }
2422 }
2423
2424 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2425 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2426
2427 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2428 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2429
2430 /*
2431 * Cast helper
2432 */
2433 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2434
2435 /*
2436 * Registers read & write functions.
2437 */
2438 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2439 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2440 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2441 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2442 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2443 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2444 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2445 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2446 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2447 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2448 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2449 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2450 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2451 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2452 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2453 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2454 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2455 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2456 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2457 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2458 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2459 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2460 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2461 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2462 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2463 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2464 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2465 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2466 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2467 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2468 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2469 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2470 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2471 #define WREG32_P(reg, val, mask) \
2472 do { \
2473 uint32_t tmp_ = RREG32(reg); \
2474 tmp_ &= (mask); \
2475 tmp_ |= ((val) & ~(mask)); \
2476 WREG32(reg, tmp_); \
2477 } while (0)
2478 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2479 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2480 #define WREG32_PLL_P(reg, val, mask) \
2481 do { \
2482 uint32_t tmp_ = RREG32_PLL(reg); \
2483 tmp_ &= (mask); \
2484 tmp_ |= ((val) & ~(mask)); \
2485 WREG32_PLL(reg, tmp_); \
2486 } while (0)
2487 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2488 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2489 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2490
2491 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2492 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2493
2494 /*
2495 * Indirect registers accessor
2496 */
2497 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2498 {
2499 unsigned long flags;
2500 uint32_t r;
2501
2502 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2503 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2504 r = RREG32(RADEON_PCIE_DATA);
2505 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2506 return r;
2507 }
2508
2509 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2510 {
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2514 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2515 WREG32(RADEON_PCIE_DATA, (v));
2516 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2517 }
2518
2519 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2520 {
2521 unsigned long flags;
2522 u32 r;
2523
2524 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2525 WREG32(TN_SMC_IND_INDEX_0, (reg));
2526 r = RREG32(TN_SMC_IND_DATA_0);
2527 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2528 return r;
2529 }
2530
2531 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2532 {
2533 unsigned long flags;
2534
2535 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2536 WREG32(TN_SMC_IND_INDEX_0, (reg));
2537 WREG32(TN_SMC_IND_DATA_0, (v));
2538 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2539 }
2540
2541 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2542 {
2543 unsigned long flags;
2544 u32 r;
2545
2546 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2547 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2548 r = RREG32(R600_RCU_DATA);
2549 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2550 return r;
2551 }
2552
2553 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2554 {
2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2558 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2559 WREG32(R600_RCU_DATA, (v));
2560 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2561 }
2562
2563 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2564 {
2565 unsigned long flags;
2566 u32 r;
2567
2568 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2569 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2570 r = RREG32(EVERGREEN_CG_IND_DATA);
2571 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2572 return r;
2573 }
2574
2575 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2576 {
2577 unsigned long flags;
2578
2579 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2580 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2581 WREG32(EVERGREEN_CG_IND_DATA, (v));
2582 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2583 }
2584
2585 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2586 {
2587 unsigned long flags;
2588 u32 r;
2589
2590 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2591 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2592 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2593 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2594 return r;
2595 }
2596
2597 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2598 {
2599 unsigned long flags;
2600
2601 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2602 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2603 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2604 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2605 }
2606
2607 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2608 {
2609 unsigned long flags;
2610 u32 r;
2611
2612 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2613 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2614 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2615 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2616 return r;
2617 }
2618
2619 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2620 {
2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2624 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2625 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2626 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2627 }
2628
2629 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2630 {
2631 unsigned long flags;
2632 u32 r;
2633
2634 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2635 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2636 r = RREG32(R600_UVD_CTX_DATA);
2637 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2638 return r;
2639 }
2640
2641 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2642 {
2643 unsigned long flags;
2644
2645 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2646 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2647 WREG32(R600_UVD_CTX_DATA, (v));
2648 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2649 }
2650
2651
2652 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2653 {
2654 unsigned long flags;
2655 u32 r;
2656
2657 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2658 WREG32(CIK_DIDT_IND_INDEX, (reg));
2659 r = RREG32(CIK_DIDT_IND_DATA);
2660 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2661 return r;
2662 }
2663
2664 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2665 {
2666 unsigned long flags;
2667
2668 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2669 WREG32(CIK_DIDT_IND_INDEX, (reg));
2670 WREG32(CIK_DIDT_IND_DATA, (v));
2671 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2672 }
2673
2674 void r100_pll_errata_after_index(struct radeon_device *rdev);
2675
2676
2677 /*
2678 * ASICs helpers.
2679 */
2680 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2681 (rdev->pdev->device == 0x5969))
2682 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2683 (rdev->family == CHIP_RV200) || \
2684 (rdev->family == CHIP_RS100) || \
2685 (rdev->family == CHIP_RS200) || \
2686 (rdev->family == CHIP_RV250) || \
2687 (rdev->family == CHIP_RV280) || \
2688 (rdev->family == CHIP_RS300))
2689 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2690 (rdev->family == CHIP_RV350) || \
2691 (rdev->family == CHIP_R350) || \
2692 (rdev->family == CHIP_RV380) || \
2693 (rdev->family == CHIP_R420) || \
2694 (rdev->family == CHIP_R423) || \
2695 (rdev->family == CHIP_RV410) || \
2696 (rdev->family == CHIP_RS400) || \
2697 (rdev->family == CHIP_RS480))
2698 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2699 (rdev->ddev->pdev->device == 0x9443) || \
2700 (rdev->ddev->pdev->device == 0x944B) || \
2701 (rdev->ddev->pdev->device == 0x9506) || \
2702 (rdev->ddev->pdev->device == 0x9509) || \
2703 (rdev->ddev->pdev->device == 0x950F) || \
2704 (rdev->ddev->pdev->device == 0x689C) || \
2705 (rdev->ddev->pdev->device == 0x689D))
2706 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2707 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2708 (rdev->family == CHIP_RS690) || \
2709 (rdev->family == CHIP_RS740) || \
2710 (rdev->family >= CHIP_R600))
2711 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2712 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2713 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2714 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2715 (rdev->flags & RADEON_IS_IGP))
2716 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2717 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2718 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2719 (rdev->flags & RADEON_IS_IGP))
2720 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2721 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2722 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2723 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2724 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2725 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2726 (rdev->family == CHIP_MULLINS))
2727
2728 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2729 (rdev->ddev->pdev->device == 0x6850) || \
2730 (rdev->ddev->pdev->device == 0x6858) || \
2731 (rdev->ddev->pdev->device == 0x6859) || \
2732 (rdev->ddev->pdev->device == 0x6840) || \
2733 (rdev->ddev->pdev->device == 0x6841) || \
2734 (rdev->ddev->pdev->device == 0x6842) || \
2735 (rdev->ddev->pdev->device == 0x6843))
2736
2737 /*
2738 * BIOS helpers.
2739 */
2740 #define RBIOS8(i) (rdev->bios[i])
2741 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2742 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2743
2744 int radeon_combios_init(struct radeon_device *rdev);
2745 void radeon_combios_fini(struct radeon_device *rdev);
2746 int radeon_atombios_init(struct radeon_device *rdev);
2747 void radeon_atombios_fini(struct radeon_device *rdev);
2748
2749
2750 /*
2751 * RING helpers.
2752 */
2753 #if DRM_DEBUG_CODE == 0
2754 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2755 {
2756 ring->ring[ring->wptr++] = v;
2757 ring->wptr &= ring->ptr_mask;
2758 ring->count_dw--;
2759 ring->ring_free_dw--;
2760 }
2761 #else
2762 /* With debugging this is just too big to inline */
2763 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2764 #endif
2765
2766 /*
2767 * ASICs macro.
2768 */
2769 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2770 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2771 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2772 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2773 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2774 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2775 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2776 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2777 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2778 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2779 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2780 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2781 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2782 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2783 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2784 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2785 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2786 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2787 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2788 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2789 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2790 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2791 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2792 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2793 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2794 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2795 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2796 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2797 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2798 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2799 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2800 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2801 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2802 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2803 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2804 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2805 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2806 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2807 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2808 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2809 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2810 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2811 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2812 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2813 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2814 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2815 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2816 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2817 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2818 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2819 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2820 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2821 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2822 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2823 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2824 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2825 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2826 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2827 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2828 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2829 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2830 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2831 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2832 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2833 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2834 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2835 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2836 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2837 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2838 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2839 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2840 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2841 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2842 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2843 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2844 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2845 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2846 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2847 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2848 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2849 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2850 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2851 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2852 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2853 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2854 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2855 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2856
2857 /* Common functions */
2858 /* AGP */
2859 extern int radeon_gpu_reset(struct radeon_device *rdev);
2860 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2861 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2862 extern void radeon_agp_disable(struct radeon_device *rdev);
2863 extern int radeon_modeset_init(struct radeon_device *rdev);
2864 extern void radeon_modeset_fini(struct radeon_device *rdev);
2865 extern bool radeon_card_posted(struct radeon_device *rdev);
2866 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2867 extern void radeon_update_display_priority(struct radeon_device *rdev);
2868 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2869 extern void radeon_scratch_init(struct radeon_device *rdev);
2870 extern void radeon_wb_fini(struct radeon_device *rdev);
2871 extern int radeon_wb_init(struct radeon_device *rdev);
2872 extern void radeon_wb_disable(struct radeon_device *rdev);
2873 extern void radeon_surface_init(struct radeon_device *rdev);
2874 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2875 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2876 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2877 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2878 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2879 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2880 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2881 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2882 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2883 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2884 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2885 const u32 *registers,
2886 const u32 array_size);
2887
2888 /*
2889 * vm
2890 */
2891 int radeon_vm_manager_init(struct radeon_device *rdev);
2892 void radeon_vm_manager_fini(struct radeon_device *rdev);
2893 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2894 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2895 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2896 struct radeon_vm *vm,
2897 struct list_head *head);
2898 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2899 struct radeon_vm *vm, int ring);
2900 void radeon_vm_flush(struct radeon_device *rdev,
2901 struct radeon_vm *vm,
2902 int ring);
2903 void radeon_vm_fence(struct radeon_device *rdev,
2904 struct radeon_vm *vm,
2905 struct radeon_fence *fence);
2906 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2907 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2908 struct radeon_vm *vm);
2909 int radeon_vm_clear_freed(struct radeon_device *rdev,
2910 struct radeon_vm *vm);
2911 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2912 struct radeon_vm *vm);
2913 int radeon_vm_bo_update(struct radeon_device *rdev,
2914 struct radeon_bo_va *bo_va,
2915 struct ttm_mem_reg *mem);
2916 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2917 struct radeon_bo *bo);
2918 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2919 struct radeon_bo *bo);
2920 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2921 struct radeon_vm *vm,
2922 struct radeon_bo *bo);
2923 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2924 struct radeon_bo_va *bo_va,
2925 uint64_t offset,
2926 uint32_t flags);
2927 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2928 struct radeon_bo_va *bo_va);
2929
2930 /* audio */
2931 void r600_audio_update_hdmi(struct work_struct *work);
2932 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2933 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2934 void r600_audio_enable(struct radeon_device *rdev,
2935 struct r600_audio_pin *pin,
2936 bool enable);
2937 void dce6_audio_enable(struct radeon_device *rdev,
2938 struct r600_audio_pin *pin,
2939 bool enable);
2940
2941 /*
2942 * R600 vram scratch functions
2943 */
2944 int r600_vram_scratch_init(struct radeon_device *rdev);
2945 void r600_vram_scratch_fini(struct radeon_device *rdev);
2946
2947 /*
2948 * r600 cs checking helper
2949 */
2950 unsigned r600_mip_minify(unsigned size, unsigned level);
2951 bool r600_fmt_is_valid_color(u32 format);
2952 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2953 int r600_fmt_get_blocksize(u32 format);
2954 int r600_fmt_get_nblocksx(u32 format, u32 w);
2955 int r600_fmt_get_nblocksy(u32 format, u32 h);
2956
2957 /*
2958 * r600 functions used by radeon_encoder.c
2959 */
2960 struct radeon_hdmi_acr {
2961 u32 clock;
2962
2963 int n_32khz;
2964 int cts_32khz;
2965
2966 int n_44_1khz;
2967 int cts_44_1khz;
2968
2969 int n_48khz;
2970 int cts_48khz;
2971
2972 };
2973
2974 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2975
2976 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2977 u32 tiling_pipe_num,
2978 u32 max_rb_num,
2979 u32 total_max_rb_num,
2980 u32 enabled_rb_mask);
2981
2982 /*
2983 * evergreen functions used by radeon_encoder.c
2984 */
2985
2986 extern int ni_init_microcode(struct radeon_device *rdev);
2987 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2988
2989 /* radeon_acpi.c */
2990 #if defined(CONFIG_ACPI)
2991 extern int radeon_acpi_init(struct radeon_device *rdev);
2992 extern void radeon_acpi_fini(struct radeon_device *rdev);
2993 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2994 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2995 u8 perf_req, bool advertise);
2996 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2997 #else
2998 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2999 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3000 #endif
3001
3002 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3003 struct radeon_cs_packet *pkt,
3004 unsigned idx);
3005 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3006 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3007 struct radeon_cs_packet *pkt);
3008 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3009 struct radeon_cs_reloc **cs_reloc,
3010 int nomm);
3011 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3012 uint32_t *vline_start_end,
3013 uint32_t *vline_status);
3014
3015 #include "radeon_object.h"
3016
3017 #endif
Linux kernel - Deliverables
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