2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 #include <asm/atomic.h>
48 #include <linux/wait.h>
49 #include <linux/list.h>
50 #include <linux/kref.h>
52 #include "radeon_mode.h"
53 #include "radeon_reg.h"
59 extern int radeon_no_wb
;
60 extern int radeon_modeset
;
61 extern int radeon_dynclks
;
62 extern int radeon_r4xx_atom
;
63 extern int radeon_agpmode
;
64 extern int radeon_vram_limit
;
65 extern int radeon_gart_size
;
66 extern int radeon_benchmarking
;
67 extern int radeon_connector_table
;
70 * Copy from radeon_drv.h so we don't have to include both and have conflicting
73 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
74 #define RADEON_IB_POOL_SIZE 16
75 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
76 #define RADEONFB_CONN_LIMIT 4
120 enum radeon_chip_flags
{
121 RADEON_FAMILY_MASK
= 0x0000ffffUL
,
122 RADEON_FLAGS_MASK
= 0xffff0000UL
,
123 RADEON_IS_MOBILITY
= 0x00010000UL
,
124 RADEON_IS_IGP
= 0x00020000UL
,
125 RADEON_SINGLE_CRTC
= 0x00040000UL
,
126 RADEON_IS_AGP
= 0x00080000UL
,
127 RADEON_HAS_HIERZ
= 0x00100000UL
,
128 RADEON_IS_PCIE
= 0x00200000UL
,
129 RADEON_NEW_MEMMAP
= 0x00400000UL
,
130 RADEON_IS_PCI
= 0x00800000UL
,
131 RADEON_IS_IGPGART
= 0x01000000UL
,
136 * Errata workarounds.
138 enum radeon_pll_errata
{
139 CHIP_ERRATA_R300_CG
= 0x00000001,
140 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
141 CHIP_ERRATA_PLL_DELAY
= 0x00000004
145 struct radeon_device
;
151 bool radeon_get_bios(struct radeon_device
*rdev
);
157 struct radeon_clock
{
158 struct radeon_pll p1pll
;
159 struct radeon_pll p2pll
;
160 struct radeon_pll spll
;
161 struct radeon_pll mpll
;
163 uint32_t default_mclk
;
164 uint32_t default_sclk
;
170 struct radeon_fence_driver
{
171 uint32_t scratch_reg
;
174 unsigned long count_timeout
;
175 wait_queue_head_t queue
;
177 struct list_head created
;
178 struct list_head emited
;
179 struct list_head signaled
;
182 struct radeon_fence
{
183 struct radeon_device
*rdev
;
185 struct list_head list
;
186 /* protected by radeon_fence.lock */
188 unsigned long timeout
;
193 int radeon_fence_driver_init(struct radeon_device
*rdev
);
194 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
195 int radeon_fence_create(struct radeon_device
*rdev
, struct radeon_fence
**fence
);
196 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
197 void radeon_fence_process(struct radeon_device
*rdev
);
198 bool radeon_fence_signaled(struct radeon_fence
*fence
);
199 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
200 int radeon_fence_wait_next(struct radeon_device
*rdev
);
201 int radeon_fence_wait_last(struct radeon_device
*rdev
);
202 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
203 void radeon_fence_unref(struct radeon_fence
**fence
);
208 struct radeon_surface_reg
{
209 struct radeon_object
*robj
;
212 #define RADEON_GEM_MAX_SURFACES 8
217 struct radeon_object
;
219 struct radeon_object_list
{
220 struct list_head list
;
221 struct radeon_object
*robj
;
225 uint32_t tiling_flags
;
228 int radeon_object_init(struct radeon_device
*rdev
);
229 void radeon_object_fini(struct radeon_device
*rdev
);
230 int radeon_object_create(struct radeon_device
*rdev
,
231 struct drm_gem_object
*gobj
,
236 struct radeon_object
**robj_ptr
);
237 int radeon_object_kmap(struct radeon_object
*robj
, void **ptr
);
238 void radeon_object_kunmap(struct radeon_object
*robj
);
239 void radeon_object_unref(struct radeon_object
**robj
);
240 int radeon_object_pin(struct radeon_object
*robj
, uint32_t domain
,
242 void radeon_object_unpin(struct radeon_object
*robj
);
243 int radeon_object_wait(struct radeon_object
*robj
);
244 int radeon_object_evict_vram(struct radeon_device
*rdev
);
245 int radeon_object_mmap(struct radeon_object
*robj
, uint64_t *offset
);
246 void radeon_object_force_delete(struct radeon_device
*rdev
);
247 void radeon_object_list_add_object(struct radeon_object_list
*lobj
,
248 struct list_head
*head
);
249 int radeon_object_list_validate(struct list_head
*head
, void *fence
);
250 void radeon_object_list_unvalidate(struct list_head
*head
);
251 void radeon_object_list_clean(struct list_head
*head
);
252 int radeon_object_fbdev_mmap(struct radeon_object
*robj
,
253 struct vm_area_struct
*vma
);
254 unsigned long radeon_object_size(struct radeon_object
*robj
);
255 void radeon_object_clear_surface_reg(struct radeon_object
*robj
);
256 int radeon_object_check_tiling(struct radeon_object
*robj
, bool has_moved
,
258 void radeon_object_set_tiling_flags(struct radeon_object
*robj
,
259 uint32_t tiling_flags
, uint32_t pitch
);
260 void radeon_object_get_tiling_flags(struct radeon_object
*robj
, uint32_t *tiling_flags
, uint32_t *pitch
);
261 void radeon_bo_move_notify(struct ttm_buffer_object
*bo
,
262 struct ttm_mem_reg
*mem
);
263 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
);
268 struct list_head objects
;
271 int radeon_gem_init(struct radeon_device
*rdev
);
272 void radeon_gem_fini(struct radeon_device
*rdev
);
273 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
274 int alignment
, int initial_domain
,
275 bool discardable
, bool kernel
,
277 struct drm_gem_object
**obj
);
278 int radeon_gem_object_pin(struct drm_gem_object
*obj
, uint32_t pin_domain
,
280 void radeon_gem_object_unpin(struct drm_gem_object
*obj
);
284 * GART structures, functions & helpers
288 struct radeon_gart_table_ram
{
289 volatile uint32_t *ptr
;
292 struct radeon_gart_table_vram
{
293 struct radeon_object
*robj
;
294 volatile uint32_t *ptr
;
297 union radeon_gart_table
{
298 struct radeon_gart_table_ram ram
;
299 struct radeon_gart_table_vram vram
;
303 dma_addr_t table_addr
;
304 unsigned num_gpu_pages
;
305 unsigned num_cpu_pages
;
307 union radeon_gart_table table
;
309 dma_addr_t
*pages_addr
;
313 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
314 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
315 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
316 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
317 int radeon_gart_init(struct radeon_device
*rdev
);
318 void radeon_gart_fini(struct radeon_device
*rdev
);
319 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
321 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
322 int pages
, struct page
**pagelist
);
326 * GPU MC structures, functions & helpers
329 resource_size_t aper_size
;
330 resource_size_t aper_base
;
331 resource_size_t agp_base
;
332 unsigned gtt_location
;
334 unsigned vram_location
;
341 int radeon_mc_setup(struct radeon_device
*rdev
);
345 * GPU scratch registers structures, functions & helpers
347 struct radeon_scratch
{
353 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
354 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
363 /* FIXME: use a define max crtc rather than hardcode it */
364 bool crtc_vblank_int
[2];
367 int radeon_irq_kms_init(struct radeon_device
*rdev
);
368 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
375 struct list_head list
;
378 struct radeon_fence
*fence
;
379 volatile uint32_t *ptr
;
383 struct radeon_ib_pool
{
385 struct radeon_object
*robj
;
386 struct list_head scheduled_ibs
;
387 struct radeon_ib ibs
[RADEON_IB_POOL_SIZE
];
389 DECLARE_BITMAP(alloc_bm
, RADEON_IB_POOL_SIZE
);
393 struct radeon_object
*ring_obj
;
394 volatile uint32_t *ring
;
399 unsigned ring_free_dw
;
408 int radeon_ib_get(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
409 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
410 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
411 int radeon_ib_pool_init(struct radeon_device
*rdev
);
412 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
413 int radeon_ib_test(struct radeon_device
*rdev
);
414 /* Ring access between begin & end cannot sleep */
415 void radeon_ring_free_size(struct radeon_device
*rdev
);
416 int radeon_ring_lock(struct radeon_device
*rdev
, unsigned ndw
);
417 void radeon_ring_unlock_commit(struct radeon_device
*rdev
);
418 void radeon_ring_unlock_undo(struct radeon_device
*rdev
);
419 int radeon_ring_test(struct radeon_device
*rdev
);
420 int radeon_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
421 void radeon_ring_fini(struct radeon_device
*rdev
);
427 struct radeon_cs_reloc
{
428 struct drm_gem_object
*gobj
;
429 struct radeon_object
*robj
;
430 struct radeon_object_list lobj
;
435 struct radeon_cs_chunk
{
441 struct radeon_cs_parser
{
442 struct radeon_device
*rdev
;
443 struct drm_file
*filp
;
446 struct radeon_cs_chunk
*chunks
;
447 uint64_t *chunks_array
;
452 struct radeon_cs_reloc
*relocs
;
453 struct radeon_cs_reloc
**relocs_ptr
;
454 struct list_head validated
;
455 /* indices of various chunks */
457 int chunk_relocs_idx
;
458 struct radeon_ib
*ib
;
462 struct radeon_cs_packet
{
471 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
472 struct radeon_cs_packet
*pkt
,
473 unsigned idx
, unsigned reg
);
474 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
475 struct radeon_cs_packet
*pkt
);
481 int radeon_agp_init(struct radeon_device
*rdev
);
482 void radeon_agp_fini(struct radeon_device
*rdev
);
489 struct radeon_object
*wb_obj
;
490 volatile uint32_t *wb
;
495 * struct radeon_pm - power management datas
496 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
497 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
498 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
499 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
500 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
501 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
502 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
503 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
504 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
505 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
506 * @needed_bandwidth: current bandwidth needs
508 * It keeps track of various data needed to take powermanagement decision.
509 * Bandwith need is used to determine minimun clock of the GPU and memory.
510 * Equation between gpu/memory clock and available bandwidth is hw dependent
511 * (type of memory, bus size, efficiency, ...)
514 fixed20_12 max_bandwidth
;
515 fixed20_12 igp_sideport_mclk
;
516 fixed20_12 igp_system_mclk
;
517 fixed20_12 igp_ht_link_clk
;
518 fixed20_12 igp_ht_link_width
;
519 fixed20_12 k8_bandwidth
;
520 fixed20_12 sideport_bandwidth
;
521 fixed20_12 ht_bandwidth
;
522 fixed20_12 core_bandwidth
;
524 fixed20_12 needed_bandwidth
;
531 void radeon_benchmark(struct radeon_device
*rdev
);
537 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
538 struct drm_info_list
*files
,
540 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
541 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
);
542 int r100_debugfs_cp_init(struct radeon_device
*rdev
);
546 * ASIC specific functions.
549 int (*init
)(struct radeon_device
*rdev
);
550 void (*errata
)(struct radeon_device
*rdev
);
551 void (*vram_info
)(struct radeon_device
*rdev
);
552 int (*gpu_reset
)(struct radeon_device
*rdev
);
553 int (*mc_init
)(struct radeon_device
*rdev
);
554 void (*mc_fini
)(struct radeon_device
*rdev
);
555 int (*wb_init
)(struct radeon_device
*rdev
);
556 void (*wb_fini
)(struct radeon_device
*rdev
);
557 int (*gart_enable
)(struct radeon_device
*rdev
);
558 void (*gart_disable
)(struct radeon_device
*rdev
);
559 void (*gart_tlb_flush
)(struct radeon_device
*rdev
);
560 int (*gart_set_page
)(struct radeon_device
*rdev
, int i
, uint64_t addr
);
561 int (*cp_init
)(struct radeon_device
*rdev
, unsigned ring_size
);
562 void (*cp_fini
)(struct radeon_device
*rdev
);
563 void (*cp_disable
)(struct radeon_device
*rdev
);
564 void (*ring_start
)(struct radeon_device
*rdev
);
565 int (*irq_set
)(struct radeon_device
*rdev
);
566 int (*irq_process
)(struct radeon_device
*rdev
);
567 void (*fence_ring_emit
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
568 int (*cs_parse
)(struct radeon_cs_parser
*p
);
569 int (*copy_blit
)(struct radeon_device
*rdev
,
573 struct radeon_fence
*fence
);
574 int (*copy_dma
)(struct radeon_device
*rdev
,
578 struct radeon_fence
*fence
);
579 int (*copy
)(struct radeon_device
*rdev
,
583 struct radeon_fence
*fence
);
584 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
585 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
586 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
587 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
588 int (*set_surface_reg
)(struct radeon_device
*rdev
, int reg
,
589 uint32_t tiling_flags
, uint32_t pitch
,
590 uint32_t offset
, uint32_t obj_size
);
591 int (*clear_surface_reg
)(struct radeon_device
*rdev
, int reg
);
592 void (*bandwidth_update
)(struct radeon_device
*rdev
);
595 union radeon_asic_config
{
596 struct r300_asic r300
;
603 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
604 struct drm_file
*filp
);
605 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
606 struct drm_file
*filp
);
607 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
608 struct drm_file
*file_priv
);
609 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
610 struct drm_file
*file_priv
);
611 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
612 struct drm_file
*file_priv
);
613 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
614 struct drm_file
*file_priv
);
615 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
616 struct drm_file
*filp
);
617 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
618 struct drm_file
*filp
);
619 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
620 struct drm_file
*filp
);
621 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
622 struct drm_file
*filp
);
623 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
624 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
625 struct drm_file
*filp
);
626 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
627 struct drm_file
*filp
);
631 * Core structure, functions and helpers.
633 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
634 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
636 struct radeon_device
{
637 struct drm_device
*ddev
;
638 struct pci_dev
*pdev
;
640 union radeon_asic_config config
;
641 enum radeon_family family
;
644 enum radeon_pll_errata pll_errata
;
650 uint16_t bios_header_start
;
651 struct radeon_object
*stollen_vga_memory
;
652 struct fb_info
*fbdev_info
;
653 struct radeon_object
*fbdev_robj
;
654 struct radeon_framebuffer
*fbdev_rfb
;
656 resource_size_t rmmio_base
;
657 resource_size_t rmmio_size
;
659 radeon_rreg_t mm_rreg
;
660 radeon_wreg_t mm_wreg
;
661 radeon_rreg_t mc_rreg
;
662 radeon_wreg_t mc_wreg
;
663 radeon_rreg_t pll_rreg
;
664 radeon_wreg_t pll_wreg
;
665 radeon_rreg_t pcie_rreg
;
666 radeon_wreg_t pcie_wreg
;
667 radeon_rreg_t pciep_rreg
;
668 radeon_wreg_t pciep_wreg
;
669 struct radeon_clock clock
;
671 struct radeon_gart gart
;
672 struct radeon_mode_info mode_info
;
673 struct radeon_scratch scratch
;
674 struct radeon_mman mman
;
675 struct radeon_fence_driver fence_drv
;
677 struct radeon_ib_pool ib_pool
;
678 struct radeon_irq irq
;
679 struct radeon_asic
*asic
;
680 struct radeon_gem gem
;
682 struct mutex cs_mutex
;
688 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
691 int radeon_device_init(struct radeon_device
*rdev
,
692 struct drm_device
*ddev
,
693 struct pci_dev
*pdev
,
695 void radeon_device_fini(struct radeon_device
*rdev
);
696 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
700 * Registers read & write functions.
702 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
703 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
704 #define RREG32(reg) rdev->mm_rreg(rdev, (reg))
705 #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
706 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
707 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
708 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
709 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
710 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
711 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
712 #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
713 #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
714 #define WREG32_P(reg, val, mask) \
716 uint32_t tmp_ = RREG32(reg); \
718 tmp_ |= ((val) & ~(mask)); \
721 #define WREG32_PLL_P(reg, val, mask) \
723 uint32_t tmp_ = RREG32_PLL(reg); \
725 tmp_ |= ((val) & ~(mask)); \
726 WREG32_PLL(reg, tmp_); \
729 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
735 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
736 (rdev->pdev->device == 0x5969))
737 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
738 (rdev->family == CHIP_RV200) || \
739 (rdev->family == CHIP_RS100) || \
740 (rdev->family == CHIP_RS200) || \
741 (rdev->family == CHIP_RV250) || \
742 (rdev->family == CHIP_RV280) || \
743 (rdev->family == CHIP_RS300))
744 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
745 (rdev->family == CHIP_RV350) || \
746 (rdev->family == CHIP_R350) || \
747 (rdev->family == CHIP_RV380) || \
748 (rdev->family == CHIP_R420) || \
749 (rdev->family == CHIP_R423) || \
750 (rdev->family == CHIP_RV410) || \
751 (rdev->family == CHIP_RS400) || \
752 (rdev->family == CHIP_RS480))
753 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
754 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
755 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
761 #define RBIOS8(i) (rdev->bios[i])
762 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
763 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
765 int radeon_combios_init(struct radeon_device
*rdev
);
766 void radeon_combios_fini(struct radeon_device
*rdev
);
767 int radeon_atombios_init(struct radeon_device
*rdev
);
768 void radeon_atombios_fini(struct radeon_device
*rdev
);
774 #define CP_PACKET0 0x00000000
775 #define PACKET0_BASE_INDEX_SHIFT 0
776 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
777 #define PACKET0_COUNT_SHIFT 16
778 #define PACKET0_COUNT_MASK (0x3fff << 16)
779 #define CP_PACKET1 0x40000000
780 #define CP_PACKET2 0x80000000
781 #define PACKET2_PAD_SHIFT 0
782 #define PACKET2_PAD_MASK (0x3fffffff << 0)
783 #define CP_PACKET3 0xC0000000
784 #define PACKET3_IT_OPCODE_SHIFT 8
785 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
786 #define PACKET3_COUNT_SHIFT 16
787 #define PACKET3_COUNT_MASK (0x3fff << 16)
788 /* PACKET3 op code */
789 #define PACKET3_NOP 0x10
790 #define PACKET3_3D_DRAW_VBUF 0x28
791 #define PACKET3_3D_DRAW_IMMD 0x29
792 #define PACKET3_3D_DRAW_INDX 0x2A
793 #define PACKET3_3D_LOAD_VBPNTR 0x2F
794 #define PACKET3_INDX_BUFFER 0x33
795 #define PACKET3_3D_DRAW_VBUF_2 0x34
796 #define PACKET3_3D_DRAW_IMMD_2 0x35
797 #define PACKET3_3D_DRAW_INDX_2 0x36
798 #define PACKET3_BITBLT_MULTI 0x9B
800 #define PACKET0(reg, n) (CP_PACKET0 | \
801 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
802 REG_SET(PACKET0_COUNT, (n)))
803 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
804 #define PACKET3(op, n) (CP_PACKET3 | \
805 REG_SET(PACKET3_IT_OPCODE, (op)) | \
806 REG_SET(PACKET3_COUNT, (n)))
808 #define PACKET_TYPE0 0
809 #define PACKET_TYPE1 1
810 #define PACKET_TYPE2 2
811 #define PACKET_TYPE3 3
813 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
814 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
815 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
816 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
817 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
819 static inline void radeon_ring_write(struct radeon_device
*rdev
, uint32_t v
)
822 if (rdev
->cp
.count_dw
<= 0) {
823 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
826 rdev
->cp
.ring
[rdev
->cp
.wptr
++] = v
;
827 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
829 rdev
->cp
.ring_free_dw
--;
836 #define radeon_init(rdev) (rdev)->asic->init((rdev))
837 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
838 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
839 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
840 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
841 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
842 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
843 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
844 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
845 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
846 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
847 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
848 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
849 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
850 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
851 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
852 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
853 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
854 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
855 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
856 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
857 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
858 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
859 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
860 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
861 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
862 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
863 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
864 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
865 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))