2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb
;
82 extern int radeon_modeset
;
83 extern int radeon_dynclks
;
84 extern int radeon_r4xx_atom
;
85 extern int radeon_agpmode
;
86 extern int radeon_vram_limit
;
87 extern int radeon_gart_size
;
88 extern int radeon_benchmarking
;
89 extern int radeon_testing
;
90 extern int radeon_connector_table
;
92 extern int radeon_audio
;
93 extern int radeon_disp_priority
;
94 extern int radeon_hw_i2c
;
95 extern int radeon_pcie_gen2
;
96 extern int radeon_msi
;
97 extern int radeon_lockup_timeout
;
98 extern int radeon_fastfb
;
99 extern int radeon_dpm
;
100 extern int radeon_aspm
;
101 extern int radeon_runtime_pm
;
102 extern int radeon_hard_reset
;
103 extern int radeon_vm_size
;
106 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
110 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
111 /* RADEON_IB_POOL_SIZE must be a power of 2 */
112 #define RADEON_IB_POOL_SIZE 16
113 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
114 #define RADEONFB_CONN_LIMIT 4
115 #define RADEON_BIOS_NUM_SCRATCH 8
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134 #define R600_RING_TYPE_UVD_INDEX 5
137 #define TN_RING_TYPE_VCE1_INDEX 6
138 #define TN_RING_TYPE_VCE2_INDEX 7
140 /* max number of rings */
141 #define RADEON_NUM_RINGS 8
143 /* number of hw syncs before falling back on blocking */
144 #define RADEON_NUM_SYNCS 4
146 /* number of hw syncs before falling back on blocking */
147 #define RADEON_NUM_SYNCS 4
149 /* hardcode those limit for now */
150 #define RADEON_VA_IB_OFFSET (1 << 20)
151 #define RADEON_VA_RESERVED_SIZE (8 << 20)
152 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
154 /* hard reset data */
155 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
158 #define RADEON_RESET_GFX (1 << 0)
159 #define RADEON_RESET_COMPUTE (1 << 1)
160 #define RADEON_RESET_DMA (1 << 2)
161 #define RADEON_RESET_CP (1 << 3)
162 #define RADEON_RESET_GRBM (1 << 4)
163 #define RADEON_RESET_DMA1 (1 << 5)
164 #define RADEON_RESET_RLC (1 << 6)
165 #define RADEON_RESET_SEM (1 << 7)
166 #define RADEON_RESET_IH (1 << 8)
167 #define RADEON_RESET_VMC (1 << 9)
168 #define RADEON_RESET_MC (1 << 10)
169 #define RADEON_RESET_DISPLAY (1 << 11)
172 #define RADEON_CG_BLOCK_GFX (1 << 0)
173 #define RADEON_CG_BLOCK_MC (1 << 1)
174 #define RADEON_CG_BLOCK_SDMA (1 << 2)
175 #define RADEON_CG_BLOCK_UVD (1 << 3)
176 #define RADEON_CG_BLOCK_VCE (1 << 4)
177 #define RADEON_CG_BLOCK_HDP (1 << 5)
178 #define RADEON_CG_BLOCK_BIF (1 << 6)
181 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
182 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
183 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
184 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
185 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
186 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
187 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
188 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
189 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
190 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
191 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
192 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
193 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
194 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
195 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
196 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
197 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
201 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
202 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
203 #define RADEON_PG_SUPPORT_UVD (1 << 3)
204 #define RADEON_PG_SUPPORT_VCE (1 << 4)
205 #define RADEON_PG_SUPPORT_CP (1 << 5)
206 #define RADEON_PG_SUPPORT_GDS (1 << 6)
207 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
208 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
209 #define RADEON_PG_SUPPORT_ACP (1 << 9)
210 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
212 /* max cursor sizes (in pixels) */
213 #define CURSOR_WIDTH 64
214 #define CURSOR_HEIGHT 64
216 #define CIK_CURSOR_WIDTH 128
217 #define CIK_CURSOR_HEIGHT 128
220 * Errata workarounds.
222 enum radeon_pll_errata
{
223 CHIP_ERRATA_R300_CG
= 0x00000001,
224 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
225 CHIP_ERRATA_PLL_DELAY
= 0x00000004
229 struct radeon_device
;
235 bool radeon_get_bios(struct radeon_device
*rdev
);
240 struct radeon_dummy_page
{
244 int radeon_dummy_page_init(struct radeon_device
*rdev
);
245 void radeon_dummy_page_fini(struct radeon_device
*rdev
);
251 struct radeon_clock
{
252 struct radeon_pll p1pll
;
253 struct radeon_pll p2pll
;
254 struct radeon_pll dcpll
;
255 struct radeon_pll spll
;
256 struct radeon_pll mpll
;
258 uint32_t default_mclk
;
259 uint32_t default_sclk
;
260 uint32_t default_dispclk
;
261 uint32_t current_dispclk
;
263 uint32_t max_pixel_clock
;
269 int radeon_pm_init(struct radeon_device
*rdev
);
270 int radeon_pm_late_init(struct radeon_device
*rdev
);
271 void radeon_pm_fini(struct radeon_device
*rdev
);
272 void radeon_pm_compute_clocks(struct radeon_device
*rdev
);
273 void radeon_pm_suspend(struct radeon_device
*rdev
);
274 void radeon_pm_resume(struct radeon_device
*rdev
);
275 void radeon_combios_get_power_modes(struct radeon_device
*rdev
);
276 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
);
277 int radeon_atom_get_clock_dividers(struct radeon_device
*rdev
,
281 struct atom_clock_dividers
*dividers
);
282 int radeon_atom_get_memory_pll_dividers(struct radeon_device
*rdev
,
285 struct atom_mpll_param
*mpll_param
);
286 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 voltage_level
, u8 voltage_type
);
287 int radeon_atom_get_voltage_gpio_settings(struct radeon_device
*rdev
,
288 u16 voltage_level
, u8 voltage_type
,
289 u32
*gpio_value
, u32
*gpio_mask
);
290 void radeon_atom_set_engine_dram_timings(struct radeon_device
*rdev
,
291 u32 eng_clock
, u32 mem_clock
);
292 int radeon_atom_get_voltage_step(struct radeon_device
*rdev
,
293 u8 voltage_type
, u16
*voltage_step
);
294 int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
295 u16 voltage_id
, u16
*voltage
);
296 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device
*rdev
,
299 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device
*rdev
,
301 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device
*rdev
,
302 u16
*vddc
, u16
*vddci
,
303 u16 virtual_voltage_id
,
304 u16 vbios_voltage_id
);
305 int radeon_atom_round_to_true_voltage(struct radeon_device
*rdev
,
309 int radeon_atom_get_min_voltage(struct radeon_device
*rdev
,
310 u8 voltage_type
, u16
*min_voltage
);
311 int radeon_atom_get_max_voltage(struct radeon_device
*rdev
,
312 u8 voltage_type
, u16
*max_voltage
);
313 int radeon_atom_get_voltage_table(struct radeon_device
*rdev
,
314 u8 voltage_type
, u8 voltage_mode
,
315 struct atom_voltage_table
*voltage_table
);
316 bool radeon_atom_is_voltage_gpio(struct radeon_device
*rdev
,
317 u8 voltage_type
, u8 voltage_mode
);
318 void radeon_atom_update_memory_dll(struct radeon_device
*rdev
,
320 void radeon_atom_set_ac_timing(struct radeon_device
*rdev
,
322 int radeon_atom_init_mc_reg_table(struct radeon_device
*rdev
,
324 struct atom_mc_reg_table
*reg_table
);
325 int radeon_atom_get_memory_info(struct radeon_device
*rdev
,
326 u8 module_index
, struct atom_memory_info
*mem_info
);
327 int radeon_atom_get_mclk_range_table(struct radeon_device
*rdev
,
328 bool gddr5
, u8 module_index
,
329 struct atom_memory_clock_range_table
*mclk_range_table
);
330 int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u8 voltage_type
,
331 u16 voltage_id
, u16
*voltage
);
332 void rs690_pm_info(struct radeon_device
*rdev
);
333 extern void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
334 unsigned *bankh
, unsigned *mtaspect
,
335 unsigned *tile_split
);
340 struct radeon_fence_driver
{
341 uint32_t scratch_reg
;
343 volatile uint32_t *cpu_addr
;
344 /* sync_seq is protected by ring emission lock */
345 uint64_t sync_seq
[RADEON_NUM_RINGS
];
350 struct radeon_fence
{
351 struct radeon_device
*rdev
;
353 /* protected by radeon_fence.lock */
359 int radeon_fence_driver_start_ring(struct radeon_device
*rdev
, int ring
);
360 int radeon_fence_driver_init(struct radeon_device
*rdev
);
361 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
362 void radeon_fence_driver_force_completion(struct radeon_device
*rdev
);
363 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
**fence
, int ring
);
364 void radeon_fence_process(struct radeon_device
*rdev
, int ring
);
365 bool radeon_fence_signaled(struct radeon_fence
*fence
);
366 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
367 int radeon_fence_wait_next(struct radeon_device
*rdev
, int ring
);
368 int radeon_fence_wait_empty(struct radeon_device
*rdev
, int ring
);
369 int radeon_fence_wait_any(struct radeon_device
*rdev
,
370 struct radeon_fence
**fences
,
372 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
373 void radeon_fence_unref(struct radeon_fence
**fence
);
374 unsigned radeon_fence_count_emitted(struct radeon_device
*rdev
, int ring
);
375 bool radeon_fence_need_sync(struct radeon_fence
*fence
, int ring
);
376 void radeon_fence_note_sync(struct radeon_fence
*fence
, int ring
);
377 static inline struct radeon_fence
*radeon_fence_later(struct radeon_fence
*a
,
378 struct radeon_fence
*b
)
388 BUG_ON(a
->ring
!= b
->ring
);
390 if (a
->seq
> b
->seq
) {
397 static inline bool radeon_fence_is_earlier(struct radeon_fence
*a
,
398 struct radeon_fence
*b
)
408 BUG_ON(a
->ring
!= b
->ring
);
410 return a
->seq
< b
->seq
;
416 struct radeon_surface_reg
{
417 struct radeon_bo
*bo
;
420 #define RADEON_GEM_MAX_SURFACES 8
426 struct ttm_bo_global_ref bo_global_ref
;
427 struct drm_global_reference mem_global_ref
;
428 struct ttm_bo_device bdev
;
429 bool mem_global_referenced
;
432 #if defined(CONFIG_DEBUG_FS)
438 /* bo virtual address in a specific vm */
439 struct radeon_bo_va
{
440 /* protected by bo being reserved */
441 struct list_head bo_list
;
448 /* protected by vm mutex */
449 struct list_head vm_list
;
451 /* constant after initialization */
452 struct radeon_vm
*vm
;
453 struct radeon_bo
*bo
;
457 /* Protected by gem.mutex */
458 struct list_head list
;
459 /* Protected by tbo.reserved */
462 struct ttm_placement placement
;
463 struct ttm_buffer_object tbo
;
464 struct ttm_bo_kmap_obj kmap
;
470 /* list of all virtual address to which this bo
474 /* Constant after initialization */
475 struct radeon_device
*rdev
;
476 struct drm_gem_object gem_base
;
478 struct ttm_bo_kmap_obj dma_buf_vmap
;
481 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
483 int radeon_gem_debugfs_init(struct radeon_device
*rdev
);
485 /* sub-allocation manager, it has to be protected by another lock.
486 * By conception this is an helper for other part of the driver
487 * like the indirect buffer or semaphore, which both have their
490 * Principe is simple, we keep a list of sub allocation in offset
491 * order (first entry has offset == 0, last entry has the highest
494 * When allocating new object we first check if there is room at
495 * the end total_size - (last_object_offset + last_object_size) >=
496 * alloc_size. If so we allocate new object there.
498 * When there is not enough room at the end, we start waiting for
499 * each sub object until we reach object_offset+object_size >=
500 * alloc_size, this object then become the sub object we return.
502 * Alignment can't be bigger than page size.
504 * Hole are not considered for allocation to keep things simple.
505 * Assumption is that there won't be hole (all object on same
508 struct radeon_sa_manager
{
509 wait_queue_head_t wq
;
510 struct radeon_bo
*bo
;
511 struct list_head
*hole
;
512 struct list_head flist
[RADEON_NUM_RINGS
];
513 struct list_head olist
;
523 /* sub-allocation buffer */
524 struct radeon_sa_bo
{
525 struct list_head olist
;
526 struct list_head flist
;
527 struct radeon_sa_manager
*manager
;
530 struct radeon_fence
*fence
;
538 struct list_head objects
;
541 int radeon_gem_init(struct radeon_device
*rdev
);
542 void radeon_gem_fini(struct radeon_device
*rdev
);
543 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
544 int alignment
, int initial_domain
,
545 bool discardable
, bool kernel
,
546 struct drm_gem_object
**obj
);
548 int radeon_mode_dumb_create(struct drm_file
*file_priv
,
549 struct drm_device
*dev
,
550 struct drm_mode_create_dumb
*args
);
551 int radeon_mode_dumb_mmap(struct drm_file
*filp
,
552 struct drm_device
*dev
,
553 uint32_t handle
, uint64_t *offset_p
);
558 struct radeon_semaphore
{
559 struct radeon_sa_bo
*sa_bo
;
562 struct radeon_fence
*sync_to
[RADEON_NUM_RINGS
];
565 int radeon_semaphore_create(struct radeon_device
*rdev
,
566 struct radeon_semaphore
**semaphore
);
567 bool radeon_semaphore_emit_signal(struct radeon_device
*rdev
, int ring
,
568 struct radeon_semaphore
*semaphore
);
569 bool radeon_semaphore_emit_wait(struct radeon_device
*rdev
, int ring
,
570 struct radeon_semaphore
*semaphore
);
571 void radeon_semaphore_sync_to(struct radeon_semaphore
*semaphore
,
572 struct radeon_fence
*fence
);
573 int radeon_semaphore_sync_rings(struct radeon_device
*rdev
,
574 struct radeon_semaphore
*semaphore
,
576 void radeon_semaphore_free(struct radeon_device
*rdev
,
577 struct radeon_semaphore
**semaphore
,
578 struct radeon_fence
*fence
);
581 * GART structures, functions & helpers
585 #define RADEON_GPU_PAGE_SIZE 4096
586 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
587 #define RADEON_GPU_PAGE_SHIFT 12
588 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
591 dma_addr_t table_addr
;
592 struct radeon_bo
*robj
;
594 unsigned num_gpu_pages
;
595 unsigned num_cpu_pages
;
598 dma_addr_t
*pages_addr
;
602 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
603 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
604 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
605 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
606 int radeon_gart_table_vram_pin(struct radeon_device
*rdev
);
607 void radeon_gart_table_vram_unpin(struct radeon_device
*rdev
);
608 int radeon_gart_init(struct radeon_device
*rdev
);
609 void radeon_gart_fini(struct radeon_device
*rdev
);
610 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
612 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
613 int pages
, struct page
**pagelist
,
614 dma_addr_t
*dma_addr
);
615 void radeon_gart_restore(struct radeon_device
*rdev
);
619 * GPU MC structures, functions & helpers
622 resource_size_t aper_size
;
623 resource_size_t aper_base
;
624 resource_size_t agp_base
;
625 /* for some chips with <= 32MB we need to lie
626 * about vram size near mc fb location */
628 u64 visible_vram_size
;
638 bool igp_sideport_enabled
;
643 bool radeon_combios_sideport_present(struct radeon_device
*rdev
);
644 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
);
647 * GPU scratch registers structures, functions & helpers
649 struct radeon_scratch
{
656 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
657 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
660 * GPU doorbell structures, functions & helpers
662 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
664 struct radeon_doorbell
{
666 resource_size_t base
;
667 resource_size_t size
;
669 u32 num_doorbells
; /* Number of doorbells actually reserved for radeon. */
670 unsigned long used
[DIV_ROUND_UP(RADEON_MAX_DOORBELLS
, BITS_PER_LONG
)];
673 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*page
);
674 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
);
680 struct radeon_flip_work
{
681 struct work_struct flip_work
;
682 struct work_struct unpin_work
;
683 struct radeon_device
*rdev
;
685 struct drm_framebuffer
*fb
;
686 struct drm_pending_vblank_event
*event
;
687 struct radeon_bo
*old_rbo
;
688 struct radeon_bo
*new_rbo
;
689 struct radeon_fence
*fence
;
692 struct r500_irq_stat_regs
{
697 struct r600_irq_stat_regs
{
707 struct evergreen_irq_stat_regs
{
728 struct cik_irq_stat_regs
{
744 union radeon_irq_stat_regs
{
745 struct r500_irq_stat_regs r500
;
746 struct r600_irq_stat_regs r600
;
747 struct evergreen_irq_stat_regs evergreen
;
748 struct cik_irq_stat_regs cik
;
751 #define RADEON_MAX_HPD_PINS 7
752 #define RADEON_MAX_CRTCS 6
753 #define RADEON_MAX_AFMT_BLOCKS 7
758 atomic_t ring_int
[RADEON_NUM_RINGS
];
759 bool crtc_vblank_int
[RADEON_MAX_CRTCS
];
760 atomic_t pflip
[RADEON_MAX_CRTCS
];
761 wait_queue_head_t vblank_queue
;
762 bool hpd
[RADEON_MAX_HPD_PINS
];
763 bool afmt
[RADEON_MAX_AFMT_BLOCKS
];
764 union radeon_irq_stat_regs stat_regs
;
768 int radeon_irq_kms_init(struct radeon_device
*rdev
);
769 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
770 void radeon_irq_kms_sw_irq_get(struct radeon_device
*rdev
, int ring
);
771 void radeon_irq_kms_sw_irq_put(struct radeon_device
*rdev
, int ring
);
772 void radeon_irq_kms_pflip_irq_get(struct radeon_device
*rdev
, int crtc
);
773 void radeon_irq_kms_pflip_irq_put(struct radeon_device
*rdev
, int crtc
);
774 void radeon_irq_kms_enable_afmt(struct radeon_device
*rdev
, int block
);
775 void radeon_irq_kms_disable_afmt(struct radeon_device
*rdev
, int block
);
776 void radeon_irq_kms_enable_hpd(struct radeon_device
*rdev
, unsigned hpd_mask
);
777 void radeon_irq_kms_disable_hpd(struct radeon_device
*rdev
, unsigned hpd_mask
);
784 struct radeon_sa_bo
*sa_bo
;
789 struct radeon_fence
*fence
;
790 struct radeon_vm
*vm
;
792 struct radeon_semaphore
*semaphore
;
796 struct radeon_bo
*ring_obj
;
797 volatile uint32_t *ring
;
799 unsigned rptr_save_reg
;
800 u64 next_rptr_gpu_addr
;
801 volatile u32
*next_rptr_cpu_addr
;
805 unsigned ring_free_dw
;
808 atomic64_t last_activity
;
815 u64 last_semaphore_signal_addr
;
816 u64 last_semaphore_wait_addr
;
821 struct radeon_bo
*mqd_obj
;
827 struct radeon_bo
*hpd_eop_obj
;
828 u64 hpd_eop_gpu_addr
;
838 /* maximum number of VMIDs */
839 #define RADEON_NUM_VM 16
841 /* defines number of bits in page table versus page directory,
842 * a page is 4KB so we have 12 bits offset, 9 bits in the page
843 * table and the remaining 19 bits are in the page directory */
844 #define RADEON_VM_BLOCK_SIZE 9
846 /* number of entries in page table */
847 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
849 /* PTBs (Page Table Blocks) need to be aligned to 32K */
850 #define RADEON_VM_PTB_ALIGN_SIZE 32768
851 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
852 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
854 #define R600_PTE_VALID (1 << 0)
855 #define R600_PTE_SYSTEM (1 << 1)
856 #define R600_PTE_SNOOPED (1 << 2)
857 #define R600_PTE_READABLE (1 << 5)
858 #define R600_PTE_WRITEABLE (1 << 6)
860 /* PTE (Page Table Entry) fragment field for different page sizes */
861 #define R600_PTE_FRAG_4KB (0 << 7)
862 #define R600_PTE_FRAG_64KB (4 << 7)
863 #define R600_PTE_FRAG_256KB (6 << 7)
865 /* flags used for GART page table entries on R600+ */
866 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
867 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
869 struct radeon_vm_pt
{
870 struct radeon_bo
*bo
;
878 /* contains the page directory */
879 struct radeon_bo
*page_directory
;
880 uint64_t pd_gpu_addr
;
881 unsigned max_pde_used
;
883 /* array of page tables, one for each page directory entry */
884 struct radeon_vm_pt
*page_tables
;
887 /* last fence for cs using this vm */
888 struct radeon_fence
*fence
;
889 /* last flush or NULL if we still need to flush */
890 struct radeon_fence
*last_flush
;
891 /* last use of vmid */
892 struct radeon_fence
*last_id_use
;
895 struct radeon_vm_manager
{
896 struct radeon_fence
*active
[RADEON_NUM_VM
];
898 /* number of VMIDs */
900 /* vram base address for page table entry */
901 u64 vram_base_offset
;
907 * file private structure
909 struct radeon_fpriv
{
917 struct radeon_bo
*ring_obj
;
918 volatile uint32_t *ring
;
930 #include "clearstate_defs.h"
933 /* for power gating */
934 struct radeon_bo
*save_restore_obj
;
935 uint64_t save_restore_gpu_addr
;
936 volatile uint32_t *sr_ptr
;
939 /* for clear state */
940 struct radeon_bo
*clear_state_obj
;
941 uint64_t clear_state_gpu_addr
;
942 volatile uint32_t *cs_ptr
;
943 const struct cs_section_def
*cs_data
;
944 u32 clear_state_size
;
946 struct radeon_bo
*cp_table_obj
;
947 uint64_t cp_table_gpu_addr
;
948 volatile uint32_t *cp_table_ptr
;
952 int radeon_ib_get(struct radeon_device
*rdev
, int ring
,
953 struct radeon_ib
*ib
, struct radeon_vm
*vm
,
955 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
956 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
,
957 struct radeon_ib
*const_ib
);
958 int radeon_ib_pool_init(struct radeon_device
*rdev
);
959 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
960 int radeon_ib_ring_tests(struct radeon_device
*rdev
);
961 /* Ring access between begin & end cannot sleep */
962 bool radeon_ring_supports_scratch_reg(struct radeon_device
*rdev
,
963 struct radeon_ring
*ring
);
964 void radeon_ring_free_size(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
965 int radeon_ring_alloc(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ndw
);
966 int radeon_ring_lock(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ndw
);
967 void radeon_ring_commit(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
968 void radeon_ring_unlock_commit(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
969 void radeon_ring_undo(struct radeon_ring
*ring
);
970 void radeon_ring_unlock_undo(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
971 int radeon_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
972 void radeon_ring_lockup_update(struct radeon_device
*rdev
,
973 struct radeon_ring
*ring
);
974 bool radeon_ring_test_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
975 unsigned radeon_ring_backup(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
977 int radeon_ring_restore(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
978 unsigned size
, uint32_t *data
);
979 int radeon_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ring_size
,
980 unsigned rptr_offs
, u32 nop
);
981 void radeon_ring_fini(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
985 void r600_dma_stop(struct radeon_device
*rdev
);
986 int r600_dma_resume(struct radeon_device
*rdev
);
987 void r600_dma_fini(struct radeon_device
*rdev
);
989 void cayman_dma_stop(struct radeon_device
*rdev
);
990 int cayman_dma_resume(struct radeon_device
*rdev
);
991 void cayman_dma_fini(struct radeon_device
*rdev
);
996 struct radeon_cs_reloc
{
997 struct drm_gem_object
*gobj
;
998 struct radeon_bo
*robj
;
999 struct ttm_validate_buffer tv
;
1000 uint64_t gpu_offset
;
1001 unsigned prefered_domains
;
1002 unsigned allowed_domains
;
1003 uint32_t tiling_flags
;
1007 struct radeon_cs_chunk
{
1011 void __user
*user_ptr
;
1014 struct radeon_cs_parser
{
1016 struct radeon_device
*rdev
;
1017 struct drm_file
*filp
;
1020 struct radeon_cs_chunk
*chunks
;
1021 uint64_t *chunks_array
;
1026 struct radeon_cs_reloc
*relocs
;
1027 struct radeon_cs_reloc
**relocs_ptr
;
1028 struct radeon_cs_reloc
*vm_bos
;
1029 struct list_head validated
;
1030 unsigned dma_reloc_idx
;
1031 /* indices of various chunks */
1033 int chunk_relocs_idx
;
1034 int chunk_flags_idx
;
1035 int chunk_const_ib_idx
;
1036 struct radeon_ib ib
;
1037 struct radeon_ib const_ib
;
1044 struct ww_acquire_ctx ticket
;
1047 static inline u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
)
1049 struct radeon_cs_chunk
*ibc
= &p
->chunks
[p
->chunk_ib_idx
];
1052 return ibc
->kdata
[idx
];
1053 return p
->ib
.ptr
[idx
];
1057 struct radeon_cs_packet
{
1063 unsigned one_reg_wr
;
1066 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
1067 struct radeon_cs_packet
*pkt
,
1068 unsigned idx
, unsigned reg
);
1069 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
1070 struct radeon_cs_packet
*pkt
);
1076 int radeon_agp_init(struct radeon_device
*rdev
);
1077 void radeon_agp_resume(struct radeon_device
*rdev
);
1078 void radeon_agp_suspend(struct radeon_device
*rdev
);
1079 void radeon_agp_fini(struct radeon_device
*rdev
);
1086 struct radeon_bo
*wb_obj
;
1087 volatile uint32_t *wb
;
1093 #define RADEON_WB_SCRATCH_OFFSET 0
1094 #define RADEON_WB_RING0_NEXT_RPTR 256
1095 #define RADEON_WB_CP_RPTR_OFFSET 1024
1096 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1097 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1098 #define R600_WB_DMA_RPTR_OFFSET 1792
1099 #define R600_WB_IH_WPTR_OFFSET 2048
1100 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1101 #define R600_WB_EVENT_OFFSET 3072
1102 #define CIK_WB_CP1_WPTR_OFFSET 3328
1103 #define CIK_WB_CP2_WPTR_OFFSET 3584
1106 * struct radeon_pm - power management datas
1107 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1108 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1109 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1110 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1111 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1112 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1113 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1114 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1115 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1116 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1117 * @needed_bandwidth: current bandwidth needs
1119 * It keeps track of various data needed to take powermanagement decision.
1120 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1121 * Equation between gpu/memory clock and available bandwidth is hw dependent
1122 * (type of memory, bus size, efficiency, ...)
1125 enum radeon_pm_method
{
1131 enum radeon_dynpm_state
{
1132 DYNPM_STATE_DISABLED
,
1133 DYNPM_STATE_MINIMUM
,
1136 DYNPM_STATE_SUSPENDED
,
1138 enum radeon_dynpm_action
{
1140 DYNPM_ACTION_MINIMUM
,
1141 DYNPM_ACTION_DOWNCLOCK
,
1142 DYNPM_ACTION_UPCLOCK
,
1143 DYNPM_ACTION_DEFAULT
1146 enum radeon_voltage_type
{
1153 enum radeon_pm_state_type
{
1154 /* not used for dpm */
1155 POWER_STATE_TYPE_DEFAULT
,
1156 POWER_STATE_TYPE_POWERSAVE
,
1157 /* user selectable states */
1158 POWER_STATE_TYPE_BATTERY
,
1159 POWER_STATE_TYPE_BALANCED
,
1160 POWER_STATE_TYPE_PERFORMANCE
,
1161 /* internal states */
1162 POWER_STATE_TYPE_INTERNAL_UVD
,
1163 POWER_STATE_TYPE_INTERNAL_UVD_SD
,
1164 POWER_STATE_TYPE_INTERNAL_UVD_HD
,
1165 POWER_STATE_TYPE_INTERNAL_UVD_HD2
,
1166 POWER_STATE_TYPE_INTERNAL_UVD_MVC
,
1167 POWER_STATE_TYPE_INTERNAL_BOOT
,
1168 POWER_STATE_TYPE_INTERNAL_THERMAL
,
1169 POWER_STATE_TYPE_INTERNAL_ACPI
,
1170 POWER_STATE_TYPE_INTERNAL_ULV
,
1171 POWER_STATE_TYPE_INTERNAL_3DPERF
,
1174 enum radeon_pm_profile_type
{
1182 #define PM_PROFILE_DEFAULT_IDX 0
1183 #define PM_PROFILE_LOW_SH_IDX 1
1184 #define PM_PROFILE_MID_SH_IDX 2
1185 #define PM_PROFILE_HIGH_SH_IDX 3
1186 #define PM_PROFILE_LOW_MH_IDX 4
1187 #define PM_PROFILE_MID_MH_IDX 5
1188 #define PM_PROFILE_HIGH_MH_IDX 6
1189 #define PM_PROFILE_MAX 7
1191 struct radeon_pm_profile
{
1192 int dpms_off_ps_idx
;
1194 int dpms_off_cm_idx
;
1198 enum radeon_int_thermal_type
{
1200 THERMAL_TYPE_EXTERNAL
,
1201 THERMAL_TYPE_EXTERNAL_GPIO
,
1204 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1205 THERMAL_TYPE_EVERGREEN
,
1209 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1214 struct radeon_voltage
{
1215 enum radeon_voltage_type type
;
1217 struct radeon_gpio_rec gpio
;
1218 u32 delay
; /* delay in usec from voltage drop to sclk change */
1219 bool active_high
; /* voltage drop is active when bit is high */
1221 u8 vddc_id
; /* index into vddc voltage table */
1222 u8 vddci_id
; /* index into vddci voltage table */
1226 /* evergreen+ vddci */
1230 /* clock mode flags */
1231 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1233 struct radeon_pm_clock_info
{
1239 struct radeon_voltage voltage
;
1240 /* standardized clock flags */
1245 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1247 struct radeon_power_state
{
1248 enum radeon_pm_state_type type
;
1249 struct radeon_pm_clock_info
*clock_info
;
1250 /* number of valid clock modes in this power state */
1251 int num_clock_modes
;
1252 struct radeon_pm_clock_info
*default_clock_mode
;
1253 /* standardized state flags */
1255 u32 misc
; /* vbios specific flags */
1256 u32 misc2
; /* vbios specific flags */
1257 int pcie_lanes
; /* pcie lanes */
1261 * Some modes are overclocked by very low value, accept them
1263 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1265 enum radeon_dpm_auto_throttle_src
{
1266 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1267 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1270 enum radeon_dpm_event_src
{
1271 RADEON_DPM_EVENT_SRC_ANALOG
= 0,
1272 RADEON_DPM_EVENT_SRC_EXTERNAL
= 1,
1273 RADEON_DPM_EVENT_SRC_DIGITAL
= 2,
1274 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1275 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1278 #define RADEON_MAX_VCE_LEVELS 6
1280 enum radeon_vce_level
{
1281 RADEON_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1282 RADEON_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1283 RADEON_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1284 RADEON_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1285 RADEON_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1286 RADEON_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1290 u32 caps
; /* vbios flags */
1291 u32
class; /* vbios flags */
1292 u32 class2
; /* vbios flags */
1300 enum radeon_vce_level vce_level
;
1305 struct radeon_dpm_thermal
{
1306 /* thermal interrupt work */
1307 struct work_struct work
;
1308 /* low temperature threshold */
1310 /* high temperature threshold */
1312 /* was interrupt low to high or high to low */
1316 enum radeon_clk_action
1322 struct radeon_blacklist_clocks
1326 enum radeon_clk_action action
;
1329 struct radeon_clock_and_voltage_limits
{
1336 struct radeon_clock_array
{
1341 struct radeon_clock_voltage_dependency_entry
{
1346 struct radeon_clock_voltage_dependency_table
{
1348 struct radeon_clock_voltage_dependency_entry
*entries
;
1351 union radeon_cac_leakage_entry
{
1363 struct radeon_cac_leakage_table
{
1365 union radeon_cac_leakage_entry
*entries
;
1368 struct radeon_phase_shedding_limits_entry
{
1374 struct radeon_phase_shedding_limits_table
{
1376 struct radeon_phase_shedding_limits_entry
*entries
;
1379 struct radeon_uvd_clock_voltage_dependency_entry
{
1385 struct radeon_uvd_clock_voltage_dependency_table
{
1387 struct radeon_uvd_clock_voltage_dependency_entry
*entries
;
1390 struct radeon_vce_clock_voltage_dependency_entry
{
1396 struct radeon_vce_clock_voltage_dependency_table
{
1398 struct radeon_vce_clock_voltage_dependency_entry
*entries
;
1401 struct radeon_ppm_table
{
1403 u16 cpu_core_number
;
1405 u32 small_ac_platform_tdp
;
1407 u32 small_ac_platform_tdc
;
1414 struct radeon_cac_tdp_table
{
1416 u16 configurable_tdp
;
1418 u16 battery_power_limit
;
1419 u16 small_power_limit
;
1420 u16 low_cac_leakage
;
1421 u16 high_cac_leakage
;
1422 u16 maximum_power_delivery_limit
;
1425 struct radeon_dpm_dynamic_state
{
1426 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1427 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1428 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1429 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1430 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1431 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1432 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1433 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1434 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1435 struct radeon_clock_array valid_sclk_values
;
1436 struct radeon_clock_array valid_mclk_values
;
1437 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc
;
1438 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac
;
1439 u32 mclk_sclk_ratio
;
1440 u32 sclk_mclk_delta
;
1441 u16 vddc_vddci_delta
;
1442 u16 min_vddc_for_pcie_gen2
;
1443 struct radeon_cac_leakage_table cac_leakage_table
;
1444 struct radeon_phase_shedding_limits_table phase_shedding_limits_table
;
1445 struct radeon_ppm_table
*ppm_table
;
1446 struct radeon_cac_tdp_table
*cac_tdp_table
;
1449 struct radeon_dpm_fan
{
1459 bool ucode_fan_control
;
1462 enum radeon_pcie_gen
{
1463 RADEON_PCIE_GEN1
= 0,
1464 RADEON_PCIE_GEN2
= 1,
1465 RADEON_PCIE_GEN3
= 2,
1466 RADEON_PCIE_GEN_INVALID
= 0xffff
1469 enum radeon_dpm_forced_level
{
1470 RADEON_DPM_FORCED_LEVEL_AUTO
= 0,
1471 RADEON_DPM_FORCED_LEVEL_LOW
= 1,
1472 RADEON_DPM_FORCED_LEVEL_HIGH
= 2,
1475 struct radeon_vce_state
{
1487 struct radeon_ps
*ps
;
1488 /* number of valid power states */
1490 /* current power state that is active */
1491 struct radeon_ps
*current_ps
;
1492 /* requested power state */
1493 struct radeon_ps
*requested_ps
;
1494 /* boot up power state */
1495 struct radeon_ps
*boot_ps
;
1496 /* default uvd power state */
1497 struct radeon_ps
*uvd_ps
;
1498 /* vce requirements */
1499 struct radeon_vce_state vce_states
[RADEON_MAX_VCE_LEVELS
];
1500 enum radeon_vce_level vce_level
;
1501 enum radeon_pm_state_type state
;
1502 enum radeon_pm_state_type user_state
;
1504 u32 voltage_response_time
;
1505 u32 backbias_response_time
;
1507 u32 new_active_crtcs
;
1508 int new_active_crtc_count
;
1509 u32 current_active_crtcs
;
1510 int current_active_crtc_count
;
1511 struct radeon_dpm_dynamic_state dyn_state
;
1512 struct radeon_dpm_fan fan
;
1515 u32 near_tdp_limit_adjusted
;
1516 u32 sq_ramping_threshold
;
1520 u16 load_line_slope
;
1523 /* special states active */
1524 bool thermal_active
;
1527 /* thermal handling */
1528 struct radeon_dpm_thermal thermal
;
1530 enum radeon_dpm_forced_level forced_level
;
1531 /* track UVD streams */
1536 void radeon_dpm_enable_uvd(struct radeon_device
*rdev
, bool enable
);
1537 void radeon_dpm_enable_vce(struct radeon_device
*rdev
, bool enable
);
1541 /* write locked while reprogramming mclk */
1542 struct rw_semaphore mclk_lock
;
1544 int active_crtc_count
;
1547 fixed20_12 max_bandwidth
;
1548 fixed20_12 igp_sideport_mclk
;
1549 fixed20_12 igp_system_mclk
;
1550 fixed20_12 igp_ht_link_clk
;
1551 fixed20_12 igp_ht_link_width
;
1552 fixed20_12 k8_bandwidth
;
1553 fixed20_12 sideport_bandwidth
;
1554 fixed20_12 ht_bandwidth
;
1555 fixed20_12 core_bandwidth
;
1558 fixed20_12 needed_bandwidth
;
1559 struct radeon_power_state
*power_state
;
1560 /* number of valid power states */
1561 int num_power_states
;
1562 int current_power_state_index
;
1563 int current_clock_mode_index
;
1564 int requested_power_state_index
;
1565 int requested_clock_mode_index
;
1566 int default_power_state_index
;
1575 struct radeon_i2c_chan
*i2c_bus
;
1576 /* selected pm method */
1577 enum radeon_pm_method pm_method
;
1578 /* dynpm power management */
1579 struct delayed_work dynpm_idle_work
;
1580 enum radeon_dynpm_state dynpm_state
;
1581 enum radeon_dynpm_action dynpm_planned_action
;
1582 unsigned long dynpm_action_timeout
;
1583 bool dynpm_can_upclock
;
1584 bool dynpm_can_downclock
;
1585 /* profile-based power management */
1586 enum radeon_pm_profile_type profile
;
1588 struct radeon_pm_profile profiles
[PM_PROFILE_MAX
];
1589 /* internal thermal controller on rv6xx+ */
1590 enum radeon_int_thermal_type int_thermal_type
;
1591 struct device
*int_hwmon_dev
;
1594 struct radeon_dpm dpm
;
1597 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
1598 enum radeon_pm_state_type ps_type
,
1603 #define RADEON_MAX_UVD_HANDLES 10
1604 #define RADEON_UVD_STACK_SIZE (1024*1024)
1605 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1608 struct radeon_bo
*vcpu_bo
;
1612 atomic_t handles
[RADEON_MAX_UVD_HANDLES
];
1613 struct drm_file
*filp
[RADEON_MAX_UVD_HANDLES
];
1614 unsigned img_size
[RADEON_MAX_UVD_HANDLES
];
1615 struct delayed_work idle_work
;
1618 int radeon_uvd_init(struct radeon_device
*rdev
);
1619 void radeon_uvd_fini(struct radeon_device
*rdev
);
1620 int radeon_uvd_suspend(struct radeon_device
*rdev
);
1621 int radeon_uvd_resume(struct radeon_device
*rdev
);
1622 int radeon_uvd_get_create_msg(struct radeon_device
*rdev
, int ring
,
1623 uint32_t handle
, struct radeon_fence
**fence
);
1624 int radeon_uvd_get_destroy_msg(struct radeon_device
*rdev
, int ring
,
1625 uint32_t handle
, struct radeon_fence
**fence
);
1626 void radeon_uvd_force_into_uvd_segment(struct radeon_bo
*rbo
);
1627 void radeon_uvd_free_handles(struct radeon_device
*rdev
,
1628 struct drm_file
*filp
);
1629 int radeon_uvd_cs_parse(struct radeon_cs_parser
*parser
);
1630 void radeon_uvd_note_usage(struct radeon_device
*rdev
);
1631 int radeon_uvd_calc_upll_dividers(struct radeon_device
*rdev
,
1632 unsigned vclk
, unsigned dclk
,
1633 unsigned vco_min
, unsigned vco_max
,
1634 unsigned fb_factor
, unsigned fb_mask
,
1635 unsigned pd_min
, unsigned pd_max
,
1637 unsigned *optimal_fb_div
,
1638 unsigned *optimal_vclk_div
,
1639 unsigned *optimal_dclk_div
);
1640 int radeon_uvd_send_upll_ctlreq(struct radeon_device
*rdev
,
1641 unsigned cg_upll_func_cntl
);
1646 #define RADEON_MAX_VCE_HANDLES 16
1647 #define RADEON_VCE_STACK_SIZE (1024*1024)
1648 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1651 struct radeon_bo
*vcpu_bo
;
1653 unsigned fw_version
;
1654 unsigned fb_version
;
1655 atomic_t handles
[RADEON_MAX_VCE_HANDLES
];
1656 struct drm_file
*filp
[RADEON_MAX_VCE_HANDLES
];
1657 unsigned img_size
[RADEON_MAX_VCE_HANDLES
];
1658 struct delayed_work idle_work
;
1661 int radeon_vce_init(struct radeon_device
*rdev
);
1662 void radeon_vce_fini(struct radeon_device
*rdev
);
1663 int radeon_vce_suspend(struct radeon_device
*rdev
);
1664 int radeon_vce_resume(struct radeon_device
*rdev
);
1665 int radeon_vce_get_create_msg(struct radeon_device
*rdev
, int ring
,
1666 uint32_t handle
, struct radeon_fence
**fence
);
1667 int radeon_vce_get_destroy_msg(struct radeon_device
*rdev
, int ring
,
1668 uint32_t handle
, struct radeon_fence
**fence
);
1669 void radeon_vce_free_handles(struct radeon_device
*rdev
, struct drm_file
*filp
);
1670 void radeon_vce_note_usage(struct radeon_device
*rdev
);
1671 int radeon_vce_cs_reloc(struct radeon_cs_parser
*p
, int lo
, int hi
, unsigned size
);
1672 int radeon_vce_cs_parse(struct radeon_cs_parser
*p
);
1673 bool radeon_vce_semaphore_emit(struct radeon_device
*rdev
,
1674 struct radeon_ring
*ring
,
1675 struct radeon_semaphore
*semaphore
,
1677 void radeon_vce_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
1678 void radeon_vce_fence_emit(struct radeon_device
*rdev
,
1679 struct radeon_fence
*fence
);
1680 int radeon_vce_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
1681 int radeon_vce_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
1683 struct r600_audio_pin
{
1686 int bits_per_sample
;
1696 struct r600_audio_pin pin
[RADEON_MAX_AFMT_BLOCKS
];
1703 void radeon_benchmark(struct radeon_device
*rdev
, int test_number
);
1709 void radeon_test_moves(struct radeon_device
*rdev
);
1710 void radeon_test_ring_sync(struct radeon_device
*rdev
,
1711 struct radeon_ring
*cpA
,
1712 struct radeon_ring
*cpB
);
1713 void radeon_test_syncing(struct radeon_device
*rdev
);
1719 struct radeon_debugfs
{
1720 struct drm_info_list
*files
;
1724 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1725 struct drm_info_list
*files
,
1727 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
1730 * ASIC ring specific functions.
1732 struct radeon_asic_ring
{
1733 /* ring read/write ptr handling */
1734 u32 (*get_rptr
)(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
1735 u32 (*get_wptr
)(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
1736 void (*set_wptr
)(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
1738 /* validating and patching of IBs */
1739 int (*ib_parse
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
1740 int (*cs_parse
)(struct radeon_cs_parser
*p
);
1742 /* command emmit functions */
1743 void (*ib_execute
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
1744 void (*emit_fence
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
1745 bool (*emit_semaphore
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
,
1746 struct radeon_semaphore
*semaphore
, bool emit_wait
);
1747 void (*vm_flush
)(struct radeon_device
*rdev
, int ridx
, struct radeon_vm
*vm
);
1749 /* testing functions */
1750 int (*ring_test
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1751 int (*ib_test
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1752 bool (*is_lockup
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1755 void (*ring_start
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1759 * ASIC specific functions.
1761 struct radeon_asic
{
1762 int (*init
)(struct radeon_device
*rdev
);
1763 void (*fini
)(struct radeon_device
*rdev
);
1764 int (*resume
)(struct radeon_device
*rdev
);
1765 int (*suspend
)(struct radeon_device
*rdev
);
1766 void (*vga_set_state
)(struct radeon_device
*rdev
, bool state
);
1767 int (*asic_reset
)(struct radeon_device
*rdev
);
1768 /* ioctl hw specific callback. Some hw might want to perform special
1769 * operation on specific ioctl. For instance on wait idle some hw
1770 * might want to perform and HDP flush through MMIO as it seems that
1771 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1774 void (*ioctl_wait_idle
)(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
1775 /* check if 3D engine is idle */
1776 bool (*gui_idle
)(struct radeon_device
*rdev
);
1777 /* wait for mc_idle */
1778 int (*mc_wait_for_idle
)(struct radeon_device
*rdev
);
1779 /* get the reference clock */
1780 u32 (*get_xclk
)(struct radeon_device
*rdev
);
1781 /* get the gpu clock counter */
1782 uint64_t (*get_gpu_clock_counter
)(struct radeon_device
*rdev
);
1785 void (*tlb_flush
)(struct radeon_device
*rdev
);
1786 void (*set_page
)(struct radeon_device
*rdev
, unsigned i
,
1790 int (*init
)(struct radeon_device
*rdev
);
1791 void (*fini
)(struct radeon_device
*rdev
);
1792 void (*set_page
)(struct radeon_device
*rdev
,
1793 struct radeon_ib
*ib
,
1795 uint64_t addr
, unsigned count
,
1796 uint32_t incr
, uint32_t flags
);
1798 /* ring specific callbacks */
1799 struct radeon_asic_ring
*ring
[RADEON_NUM_RINGS
];
1802 int (*set
)(struct radeon_device
*rdev
);
1803 int (*process
)(struct radeon_device
*rdev
);
1807 /* display watermarks */
1808 void (*bandwidth_update
)(struct radeon_device
*rdev
);
1809 /* get frame count */
1810 u32 (*get_vblank_counter
)(struct radeon_device
*rdev
, int crtc
);
1811 /* wait for vblank */
1812 void (*wait_for_vblank
)(struct radeon_device
*rdev
, int crtc
);
1813 /* set backlight level */
1814 void (*set_backlight_level
)(struct radeon_encoder
*radeon_encoder
, u8 level
);
1815 /* get backlight level */
1816 u8 (*get_backlight_level
)(struct radeon_encoder
*radeon_encoder
);
1817 /* audio callbacks */
1818 void (*hdmi_enable
)(struct drm_encoder
*encoder
, bool enable
);
1819 void (*hdmi_setmode
)(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
1821 /* copy functions for bo handling */
1823 int (*blit
)(struct radeon_device
*rdev
,
1824 uint64_t src_offset
,
1825 uint64_t dst_offset
,
1826 unsigned num_gpu_pages
,
1827 struct radeon_fence
**fence
);
1828 u32 blit_ring_index
;
1829 int (*dma
)(struct radeon_device
*rdev
,
1830 uint64_t src_offset
,
1831 uint64_t dst_offset
,
1832 unsigned num_gpu_pages
,
1833 struct radeon_fence
**fence
);
1835 /* method used for bo copy */
1836 int (*copy
)(struct radeon_device
*rdev
,
1837 uint64_t src_offset
,
1838 uint64_t dst_offset
,
1839 unsigned num_gpu_pages
,
1840 struct radeon_fence
**fence
);
1841 /* ring used for bo copies */
1842 u32 copy_ring_index
;
1846 int (*set_reg
)(struct radeon_device
*rdev
, int reg
,
1847 uint32_t tiling_flags
, uint32_t pitch
,
1848 uint32_t offset
, uint32_t obj_size
);
1849 void (*clear_reg
)(struct radeon_device
*rdev
, int reg
);
1851 /* hotplug detect */
1853 void (*init
)(struct radeon_device
*rdev
);
1854 void (*fini
)(struct radeon_device
*rdev
);
1855 bool (*sense
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
1856 void (*set_polarity
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
1858 /* static power management */
1860 void (*misc
)(struct radeon_device
*rdev
);
1861 void (*prepare
)(struct radeon_device
*rdev
);
1862 void (*finish
)(struct radeon_device
*rdev
);
1863 void (*init_profile
)(struct radeon_device
*rdev
);
1864 void (*get_dynpm_state
)(struct radeon_device
*rdev
);
1865 uint32_t (*get_engine_clock
)(struct radeon_device
*rdev
);
1866 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
1867 uint32_t (*get_memory_clock
)(struct radeon_device
*rdev
);
1868 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
1869 int (*get_pcie_lanes
)(struct radeon_device
*rdev
);
1870 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
1871 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
1872 int (*set_uvd_clocks
)(struct radeon_device
*rdev
, u32 vclk
, u32 dclk
);
1873 int (*set_vce_clocks
)(struct radeon_device
*rdev
, u32 evclk
, u32 ecclk
);
1874 int (*get_temperature
)(struct radeon_device
*rdev
);
1876 /* dynamic power management */
1878 int (*init
)(struct radeon_device
*rdev
);
1879 void (*setup_asic
)(struct radeon_device
*rdev
);
1880 int (*enable
)(struct radeon_device
*rdev
);
1881 int (*late_enable
)(struct radeon_device
*rdev
);
1882 void (*disable
)(struct radeon_device
*rdev
);
1883 int (*pre_set_power_state
)(struct radeon_device
*rdev
);
1884 int (*set_power_state
)(struct radeon_device
*rdev
);
1885 void (*post_set_power_state
)(struct radeon_device
*rdev
);
1886 void (*display_configuration_changed
)(struct radeon_device
*rdev
);
1887 void (*fini
)(struct radeon_device
*rdev
);
1888 u32 (*get_sclk
)(struct radeon_device
*rdev
, bool low
);
1889 u32 (*get_mclk
)(struct radeon_device
*rdev
, bool low
);
1890 void (*print_power_state
)(struct radeon_device
*rdev
, struct radeon_ps
*ps
);
1891 void (*debugfs_print_current_performance_level
)(struct radeon_device
*rdev
, struct seq_file
*m
);
1892 int (*force_performance_level
)(struct radeon_device
*rdev
, enum radeon_dpm_forced_level level
);
1893 bool (*vblank_too_short
)(struct radeon_device
*rdev
);
1894 void (*powergate_uvd
)(struct radeon_device
*rdev
, bool gate
);
1895 void (*enable_bapm
)(struct radeon_device
*rdev
, bool enable
);
1899 void (*page_flip
)(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
1900 bool (*page_flip_pending
)(struct radeon_device
*rdev
, int crtc
);
1908 const unsigned *reg_safe_bm
;
1909 unsigned reg_safe_bm_size
;
1914 const unsigned *reg_safe_bm
;
1915 unsigned reg_safe_bm_size
;
1922 unsigned max_tile_pipes
;
1924 unsigned max_backends
;
1926 unsigned max_threads
;
1927 unsigned max_stack_entries
;
1928 unsigned max_hw_contexts
;
1929 unsigned max_gs_threads
;
1930 unsigned sx_max_export_size
;
1931 unsigned sx_max_export_pos_size
;
1932 unsigned sx_max_export_smx_size
;
1933 unsigned sq_num_cf_insts
;
1934 unsigned tiling_nbanks
;
1935 unsigned tiling_npipes
;
1936 unsigned tiling_group_size
;
1937 unsigned tile_config
;
1938 unsigned backend_map
;
1943 unsigned max_tile_pipes
;
1945 unsigned max_backends
;
1947 unsigned max_threads
;
1948 unsigned max_stack_entries
;
1949 unsigned max_hw_contexts
;
1950 unsigned max_gs_threads
;
1951 unsigned sx_max_export_size
;
1952 unsigned sx_max_export_pos_size
;
1953 unsigned sx_max_export_smx_size
;
1954 unsigned sq_num_cf_insts
;
1955 unsigned sx_num_of_sets
;
1956 unsigned sc_prim_fifo_size
;
1957 unsigned sc_hiz_tile_fifo_size
;
1958 unsigned sc_earlyz_tile_fifo_fize
;
1959 unsigned tiling_nbanks
;
1960 unsigned tiling_npipes
;
1961 unsigned tiling_group_size
;
1962 unsigned tile_config
;
1963 unsigned backend_map
;
1966 struct evergreen_asic
{
1969 unsigned max_tile_pipes
;
1971 unsigned max_backends
;
1973 unsigned max_threads
;
1974 unsigned max_stack_entries
;
1975 unsigned max_hw_contexts
;
1976 unsigned max_gs_threads
;
1977 unsigned sx_max_export_size
;
1978 unsigned sx_max_export_pos_size
;
1979 unsigned sx_max_export_smx_size
;
1980 unsigned sq_num_cf_insts
;
1981 unsigned sx_num_of_sets
;
1982 unsigned sc_prim_fifo_size
;
1983 unsigned sc_hiz_tile_fifo_size
;
1984 unsigned sc_earlyz_tile_fifo_size
;
1985 unsigned tiling_nbanks
;
1986 unsigned tiling_npipes
;
1987 unsigned tiling_group_size
;
1988 unsigned tile_config
;
1989 unsigned backend_map
;
1992 struct cayman_asic
{
1993 unsigned max_shader_engines
;
1994 unsigned max_pipes_per_simd
;
1995 unsigned max_tile_pipes
;
1996 unsigned max_simds_per_se
;
1997 unsigned max_backends_per_se
;
1998 unsigned max_texture_channel_caches
;
2000 unsigned max_threads
;
2001 unsigned max_gs_threads
;
2002 unsigned max_stack_entries
;
2003 unsigned sx_num_of_sets
;
2004 unsigned sx_max_export_size
;
2005 unsigned sx_max_export_pos_size
;
2006 unsigned sx_max_export_smx_size
;
2007 unsigned max_hw_contexts
;
2008 unsigned sq_num_cf_insts
;
2009 unsigned sc_prim_fifo_size
;
2010 unsigned sc_hiz_tile_fifo_size
;
2011 unsigned sc_earlyz_tile_fifo_size
;
2013 unsigned num_shader_engines
;
2014 unsigned num_shader_pipes_per_simd
;
2015 unsigned num_tile_pipes
;
2016 unsigned num_simds_per_se
;
2017 unsigned num_backends_per_se
;
2018 unsigned backend_disable_mask_per_asic
;
2019 unsigned backend_map
;
2020 unsigned num_texture_channel_caches
;
2021 unsigned mem_max_burst_length_bytes
;
2022 unsigned mem_row_size_in_kb
;
2023 unsigned shader_engine_tile_size
;
2025 unsigned multi_gpu_tile_size
;
2027 unsigned tile_config
;
2031 unsigned max_shader_engines
;
2032 unsigned max_tile_pipes
;
2033 unsigned max_cu_per_sh
;
2034 unsigned max_sh_per_se
;
2035 unsigned max_backends_per_se
;
2036 unsigned max_texture_channel_caches
;
2038 unsigned max_gs_threads
;
2039 unsigned max_hw_contexts
;
2040 unsigned sc_prim_fifo_size_frontend
;
2041 unsigned sc_prim_fifo_size_backend
;
2042 unsigned sc_hiz_tile_fifo_size
;
2043 unsigned sc_earlyz_tile_fifo_size
;
2045 unsigned num_tile_pipes
;
2046 unsigned backend_enable_mask
;
2047 unsigned backend_disable_mask_per_asic
;
2048 unsigned backend_map
;
2049 unsigned num_texture_channel_caches
;
2050 unsigned mem_max_burst_length_bytes
;
2051 unsigned mem_row_size_in_kb
;
2052 unsigned shader_engine_tile_size
;
2054 unsigned multi_gpu_tile_size
;
2056 unsigned tile_config
;
2057 uint32_t tile_mode_array
[32];
2061 unsigned max_shader_engines
;
2062 unsigned max_tile_pipes
;
2063 unsigned max_cu_per_sh
;
2064 unsigned max_sh_per_se
;
2065 unsigned max_backends_per_se
;
2066 unsigned max_texture_channel_caches
;
2068 unsigned max_gs_threads
;
2069 unsigned max_hw_contexts
;
2070 unsigned sc_prim_fifo_size_frontend
;
2071 unsigned sc_prim_fifo_size_backend
;
2072 unsigned sc_hiz_tile_fifo_size
;
2073 unsigned sc_earlyz_tile_fifo_size
;
2075 unsigned num_tile_pipes
;
2076 unsigned backend_enable_mask
;
2077 unsigned backend_disable_mask_per_asic
;
2078 unsigned backend_map
;
2079 unsigned num_texture_channel_caches
;
2080 unsigned mem_max_burst_length_bytes
;
2081 unsigned mem_row_size_in_kb
;
2082 unsigned shader_engine_tile_size
;
2084 unsigned multi_gpu_tile_size
;
2086 unsigned tile_config
;
2087 uint32_t tile_mode_array
[32];
2088 uint32_t macrotile_mode_array
[16];
2091 union radeon_asic_config
{
2092 struct r300_asic r300
;
2093 struct r100_asic r100
;
2094 struct r600_asic r600
;
2095 struct rv770_asic rv770
;
2096 struct evergreen_asic evergreen
;
2097 struct cayman_asic cayman
;
2099 struct cik_asic cik
;
2103 * asic initizalization from radeon_asic.c
2105 void radeon_agp_disable(struct radeon_device
*rdev
);
2106 int radeon_asic_init(struct radeon_device
*rdev
);
2112 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
2113 struct drm_file
*filp
);
2114 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2115 struct drm_file
*filp
);
2116 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2117 struct drm_file
*file_priv
);
2118 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2119 struct drm_file
*file_priv
);
2120 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2121 struct drm_file
*file_priv
);
2122 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2123 struct drm_file
*file_priv
);
2124 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2125 struct drm_file
*filp
);
2126 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2127 struct drm_file
*filp
);
2128 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2129 struct drm_file
*filp
);
2130 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
2131 struct drm_file
*filp
);
2132 int radeon_gem_va_ioctl(struct drm_device
*dev
, void *data
,
2133 struct drm_file
*filp
);
2134 int radeon_gem_op_ioctl(struct drm_device
*dev
, void *data
,
2135 struct drm_file
*filp
);
2136 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
2137 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
2138 struct drm_file
*filp
);
2139 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
2140 struct drm_file
*filp
);
2142 /* VRAM scratch page for HDP bug, default vram page */
2143 struct r600_vram_scratch
{
2144 struct radeon_bo
*robj
;
2145 volatile uint32_t *ptr
;
2152 struct radeon_atif_notification_cfg
{
2157 struct radeon_atif_notifications
{
2158 bool display_switch
;
2159 bool expansion_mode_change
;
2161 bool forced_power_state
;
2162 bool system_power_state
;
2163 bool display_conf_change
;
2165 bool brightness_change
;
2166 bool dgpu_display_event
;
2169 struct radeon_atif_functions
{
2171 bool sbios_requests
;
2172 bool select_active_disp
;
2174 bool get_tv_standard
;
2175 bool set_tv_standard
;
2176 bool get_panel_expansion_mode
;
2177 bool set_panel_expansion_mode
;
2178 bool temperature_change
;
2179 bool graphics_device_types
;
2182 struct radeon_atif
{
2183 struct radeon_atif_notifications notifications
;
2184 struct radeon_atif_functions functions
;
2185 struct radeon_atif_notification_cfg notification_cfg
;
2186 struct radeon_encoder
*encoder_for_bl
;
2189 struct radeon_atcs_functions
{
2193 bool pcie_bus_width
;
2196 struct radeon_atcs
{
2197 struct radeon_atcs_functions functions
;
2201 * Core structure, functions and helpers.
2203 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
2204 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
2206 struct radeon_device
{
2208 struct drm_device
*ddev
;
2209 struct pci_dev
*pdev
;
2210 struct rw_semaphore exclusive_lock
;
2212 union radeon_asic_config config
;
2213 enum radeon_family family
;
2214 unsigned long flags
;
2216 enum radeon_pll_errata pll_errata
;
2223 uint16_t bios_header_start
;
2224 struct radeon_bo
*stollen_vga_memory
;
2226 resource_size_t rmmio_base
;
2227 resource_size_t rmmio_size
;
2228 /* protects concurrent MM_INDEX/DATA based register access */
2229 spinlock_t mmio_idx_lock
;
2230 /* protects concurrent SMC based register access */
2231 spinlock_t smc_idx_lock
;
2232 /* protects concurrent PLL register access */
2233 spinlock_t pll_idx_lock
;
2234 /* protects concurrent MC register access */
2235 spinlock_t mc_idx_lock
;
2236 /* protects concurrent PCIE register access */
2237 spinlock_t pcie_idx_lock
;
2238 /* protects concurrent PCIE_PORT register access */
2239 spinlock_t pciep_idx_lock
;
2240 /* protects concurrent PIF register access */
2241 spinlock_t pif_idx_lock
;
2242 /* protects concurrent CG register access */
2243 spinlock_t cg_idx_lock
;
2244 /* protects concurrent UVD register access */
2245 spinlock_t uvd_idx_lock
;
2246 /* protects concurrent RCU register access */
2247 spinlock_t rcu_idx_lock
;
2248 /* protects concurrent DIDT register access */
2249 spinlock_t didt_idx_lock
;
2250 /* protects concurrent ENDPOINT (audio) register access */
2251 spinlock_t end_idx_lock
;
2252 void __iomem
*rmmio
;
2253 radeon_rreg_t mc_rreg
;
2254 radeon_wreg_t mc_wreg
;
2255 radeon_rreg_t pll_rreg
;
2256 radeon_wreg_t pll_wreg
;
2257 uint32_t pcie_reg_mask
;
2258 radeon_rreg_t pciep_rreg
;
2259 radeon_wreg_t pciep_wreg
;
2261 void __iomem
*rio_mem
;
2262 resource_size_t rio_mem_size
;
2263 struct radeon_clock clock
;
2264 struct radeon_mc mc
;
2265 struct radeon_gart gart
;
2266 struct radeon_mode_info mode_info
;
2267 struct radeon_scratch scratch
;
2268 struct radeon_doorbell doorbell
;
2269 struct radeon_mman mman
;
2270 struct radeon_fence_driver fence_drv
[RADEON_NUM_RINGS
];
2271 wait_queue_head_t fence_queue
;
2272 struct mutex ring_lock
;
2273 struct radeon_ring ring
[RADEON_NUM_RINGS
];
2275 struct radeon_sa_manager ring_tmp_bo
;
2276 struct radeon_irq irq
;
2277 struct radeon_asic
*asic
;
2278 struct radeon_gem gem
;
2279 struct radeon_pm pm
;
2280 struct radeon_uvd uvd
;
2281 struct radeon_vce vce
;
2282 uint32_t bios_scratch
[RADEON_BIOS_NUM_SCRATCH
];
2283 struct radeon_wb wb
;
2284 struct radeon_dummy_page dummy_page
;
2289 bool fastfb_working
; /* IGP feature*/
2291 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
2292 const struct firmware
*me_fw
; /* all family ME firmware */
2293 const struct firmware
*pfp_fw
; /* r6/700 PFP firmware */
2294 const struct firmware
*rlc_fw
; /* r6/700 RLC firmware */
2295 const struct firmware
*mc_fw
; /* NI MC firmware */
2296 const struct firmware
*ce_fw
; /* SI CE firmware */
2297 const struct firmware
*mec_fw
; /* CIK MEC firmware */
2298 const struct firmware
*sdma_fw
; /* CIK SDMA firmware */
2299 const struct firmware
*smc_fw
; /* SMC firmware */
2300 const struct firmware
*uvd_fw
; /* UVD firmware */
2301 const struct firmware
*vce_fw
; /* VCE firmware */
2302 struct r600_vram_scratch vram_scratch
;
2303 int msi_enabled
; /* msi enabled */
2304 struct r600_ih ih
; /* r6/700 interrupt ring */
2305 struct radeon_rlc rlc
;
2306 struct radeon_mec mec
;
2307 struct work_struct hotplug_work
;
2308 struct work_struct audio_work
;
2309 struct work_struct reset_work
;
2310 int num_crtc
; /* number of crtcs */
2311 struct mutex dc_hw_i2c_mutex
; /* display controller hw i2c mutex */
2313 struct r600_audio audio
; /* audio stuff */
2314 struct notifier_block acpi_nb
;
2315 /* only one userspace can use Hyperz features or CMASK at a time */
2316 struct drm_file
*hyperz_filp
;
2317 struct drm_file
*cmask_filp
;
2319 struct radeon_i2c_chan
*i2c_bus
[RADEON_MAX_I2C_BUS
];
2321 struct radeon_debugfs debugfs
[RADEON_DEBUGFS_MAX_COMPONENTS
];
2322 unsigned debugfs_count
;
2323 /* virtual memory */
2324 struct radeon_vm_manager vm_manager
;
2325 struct mutex gpu_clock_mutex
;
2327 atomic64_t vram_usage
;
2328 atomic64_t gtt_usage
;
2329 atomic64_t num_bytes_moved
;
2330 /* ACPI interface */
2331 struct radeon_atif atif
;
2332 struct radeon_atcs atcs
;
2333 /* srbm instance registers */
2334 struct mutex srbm_mutex
;
2335 /* clock, powergating flags */
2339 struct dev_pm_domain vga_pm_domain
;
2340 bool have_disp_power_ref
;
2343 bool radeon_is_px(struct drm_device
*dev
);
2344 int radeon_device_init(struct radeon_device
*rdev
,
2345 struct drm_device
*ddev
,
2346 struct pci_dev
*pdev
,
2348 void radeon_device_fini(struct radeon_device
*rdev
);
2349 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
2351 uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
,
2352 bool always_indirect
);
2353 void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
,
2354 bool always_indirect
);
2355 u32
r100_io_rreg(struct radeon_device
*rdev
, u32 reg
);
2356 void r100_io_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
2358 u32
cik_mm_rdoorbell(struct radeon_device
*rdev
, u32 index
);
2359 void cik_mm_wdoorbell(struct radeon_device
*rdev
, u32 index
, u32 v
);
2364 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2367 * Registers read & write functions.
2369 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2370 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2371 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2372 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2373 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2374 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2375 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2376 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2377 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2378 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2379 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2380 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2381 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2382 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2383 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2384 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2385 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2386 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2387 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2388 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2389 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2390 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2391 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2392 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2393 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2394 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2395 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2396 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2397 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2398 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2399 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2400 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2401 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2402 #define WREG32_P(reg, val, mask) \
2404 uint32_t tmp_ = RREG32(reg); \
2406 tmp_ |= ((val) & ~(mask)); \
2407 WREG32(reg, tmp_); \
2409 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2410 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2411 #define WREG32_PLL_P(reg, val, mask) \
2413 uint32_t tmp_ = RREG32_PLL(reg); \
2415 tmp_ |= ((val) & ~(mask)); \
2416 WREG32_PLL(reg, tmp_); \
2418 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2419 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2420 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2422 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2423 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2426 * Indirect registers accessor
2428 static inline uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
)
2430 unsigned long flags
;
2433 spin_lock_irqsave(&rdev
->pcie_idx_lock
, flags
);
2434 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
2435 r
= RREG32(RADEON_PCIE_DATA
);
2436 spin_unlock_irqrestore(&rdev
->pcie_idx_lock
, flags
);
2440 static inline void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
2442 unsigned long flags
;
2444 spin_lock_irqsave(&rdev
->pcie_idx_lock
, flags
);
2445 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
2446 WREG32(RADEON_PCIE_DATA
, (v
));
2447 spin_unlock_irqrestore(&rdev
->pcie_idx_lock
, flags
);
2450 static inline u32
tn_smc_rreg(struct radeon_device
*rdev
, u32 reg
)
2452 unsigned long flags
;
2455 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
2456 WREG32(TN_SMC_IND_INDEX_0
, (reg
));
2457 r
= RREG32(TN_SMC_IND_DATA_0
);
2458 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
2462 static inline void tn_smc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2464 unsigned long flags
;
2466 spin_lock_irqsave(&rdev
->smc_idx_lock
, flags
);
2467 WREG32(TN_SMC_IND_INDEX_0
, (reg
));
2468 WREG32(TN_SMC_IND_DATA_0
, (v
));
2469 spin_unlock_irqrestore(&rdev
->smc_idx_lock
, flags
);
2472 static inline u32
r600_rcu_rreg(struct radeon_device
*rdev
, u32 reg
)
2474 unsigned long flags
;
2477 spin_lock_irqsave(&rdev
->rcu_idx_lock
, flags
);
2478 WREG32(R600_RCU_INDEX
, ((reg
) & 0x1fff));
2479 r
= RREG32(R600_RCU_DATA
);
2480 spin_unlock_irqrestore(&rdev
->rcu_idx_lock
, flags
);
2484 static inline void r600_rcu_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2486 unsigned long flags
;
2488 spin_lock_irqsave(&rdev
->rcu_idx_lock
, flags
);
2489 WREG32(R600_RCU_INDEX
, ((reg
) & 0x1fff));
2490 WREG32(R600_RCU_DATA
, (v
));
2491 spin_unlock_irqrestore(&rdev
->rcu_idx_lock
, flags
);
2494 static inline u32
eg_cg_rreg(struct radeon_device
*rdev
, u32 reg
)
2496 unsigned long flags
;
2499 spin_lock_irqsave(&rdev
->cg_idx_lock
, flags
);
2500 WREG32(EVERGREEN_CG_IND_ADDR
, ((reg
) & 0xffff));
2501 r
= RREG32(EVERGREEN_CG_IND_DATA
);
2502 spin_unlock_irqrestore(&rdev
->cg_idx_lock
, flags
);
2506 static inline void eg_cg_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2508 unsigned long flags
;
2510 spin_lock_irqsave(&rdev
->cg_idx_lock
, flags
);
2511 WREG32(EVERGREEN_CG_IND_ADDR
, ((reg
) & 0xffff));
2512 WREG32(EVERGREEN_CG_IND_DATA
, (v
));
2513 spin_unlock_irqrestore(&rdev
->cg_idx_lock
, flags
);
2516 static inline u32
eg_pif_phy0_rreg(struct radeon_device
*rdev
, u32 reg
)
2518 unsigned long flags
;
2521 spin_lock_irqsave(&rdev
->pif_idx_lock
, flags
);
2522 WREG32(EVERGREEN_PIF_PHY0_INDEX
, ((reg
) & 0xffff));
2523 r
= RREG32(EVERGREEN_PIF_PHY0_DATA
);
2524 spin_unlock_irqrestore(&rdev
->pif_idx_lock
, flags
);
2528 static inline void eg_pif_phy0_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2530 unsigned long flags
;
2532 spin_lock_irqsave(&rdev
->pif_idx_lock
, flags
);
2533 WREG32(EVERGREEN_PIF_PHY0_INDEX
, ((reg
) & 0xffff));
2534 WREG32(EVERGREEN_PIF_PHY0_DATA
, (v
));
2535 spin_unlock_irqrestore(&rdev
->pif_idx_lock
, flags
);
2538 static inline u32
eg_pif_phy1_rreg(struct radeon_device
*rdev
, u32 reg
)
2540 unsigned long flags
;
2543 spin_lock_irqsave(&rdev
->pif_idx_lock
, flags
);
2544 WREG32(EVERGREEN_PIF_PHY1_INDEX
, ((reg
) & 0xffff));
2545 r
= RREG32(EVERGREEN_PIF_PHY1_DATA
);
2546 spin_unlock_irqrestore(&rdev
->pif_idx_lock
, flags
);
2550 static inline void eg_pif_phy1_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2552 unsigned long flags
;
2554 spin_lock_irqsave(&rdev
->pif_idx_lock
, flags
);
2555 WREG32(EVERGREEN_PIF_PHY1_INDEX
, ((reg
) & 0xffff));
2556 WREG32(EVERGREEN_PIF_PHY1_DATA
, (v
));
2557 spin_unlock_irqrestore(&rdev
->pif_idx_lock
, flags
);
2560 static inline u32
r600_uvd_ctx_rreg(struct radeon_device
*rdev
, u32 reg
)
2562 unsigned long flags
;
2565 spin_lock_irqsave(&rdev
->uvd_idx_lock
, flags
);
2566 WREG32(R600_UVD_CTX_INDEX
, ((reg
) & 0x1ff));
2567 r
= RREG32(R600_UVD_CTX_DATA
);
2568 spin_unlock_irqrestore(&rdev
->uvd_idx_lock
, flags
);
2572 static inline void r600_uvd_ctx_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2574 unsigned long flags
;
2576 spin_lock_irqsave(&rdev
->uvd_idx_lock
, flags
);
2577 WREG32(R600_UVD_CTX_INDEX
, ((reg
) & 0x1ff));
2578 WREG32(R600_UVD_CTX_DATA
, (v
));
2579 spin_unlock_irqrestore(&rdev
->uvd_idx_lock
, flags
);
2583 static inline u32
cik_didt_rreg(struct radeon_device
*rdev
, u32 reg
)
2585 unsigned long flags
;
2588 spin_lock_irqsave(&rdev
->didt_idx_lock
, flags
);
2589 WREG32(CIK_DIDT_IND_INDEX
, (reg
));
2590 r
= RREG32(CIK_DIDT_IND_DATA
);
2591 spin_unlock_irqrestore(&rdev
->didt_idx_lock
, flags
);
2595 static inline void cik_didt_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
2597 unsigned long flags
;
2599 spin_lock_irqsave(&rdev
->didt_idx_lock
, flags
);
2600 WREG32(CIK_DIDT_IND_INDEX
, (reg
));
2601 WREG32(CIK_DIDT_IND_DATA
, (v
));
2602 spin_unlock_irqrestore(&rdev
->didt_idx_lock
, flags
);
2605 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
2611 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2612 (rdev->pdev->device == 0x5969))
2613 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2614 (rdev->family == CHIP_RV200) || \
2615 (rdev->family == CHIP_RS100) || \
2616 (rdev->family == CHIP_RS200) || \
2617 (rdev->family == CHIP_RV250) || \
2618 (rdev->family == CHIP_RV280) || \
2619 (rdev->family == CHIP_RS300))
2620 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2621 (rdev->family == CHIP_RV350) || \
2622 (rdev->family == CHIP_R350) || \
2623 (rdev->family == CHIP_RV380) || \
2624 (rdev->family == CHIP_R420) || \
2625 (rdev->family == CHIP_R423) || \
2626 (rdev->family == CHIP_RV410) || \
2627 (rdev->family == CHIP_RS400) || \
2628 (rdev->family == CHIP_RS480))
2629 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2630 (rdev->ddev->pdev->device == 0x9443) || \
2631 (rdev->ddev->pdev->device == 0x944B) || \
2632 (rdev->ddev->pdev->device == 0x9506) || \
2633 (rdev->ddev->pdev->device == 0x9509) || \
2634 (rdev->ddev->pdev->device == 0x950F) || \
2635 (rdev->ddev->pdev->device == 0x689C) || \
2636 (rdev->ddev->pdev->device == 0x689D))
2637 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2638 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2639 (rdev->family == CHIP_RS690) || \
2640 (rdev->family == CHIP_RS740) || \
2641 (rdev->family >= CHIP_R600))
2642 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2643 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2644 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2645 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2646 (rdev->flags & RADEON_IS_IGP))
2647 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2648 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2649 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2650 (rdev->flags & RADEON_IS_IGP))
2651 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2652 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2653 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2654 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2655 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2656 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2657 (rdev->family == CHIP_MULLINS))
2659 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2660 (rdev->ddev->pdev->device == 0x6850) || \
2661 (rdev->ddev->pdev->device == 0x6858) || \
2662 (rdev->ddev->pdev->device == 0x6859) || \
2663 (rdev->ddev->pdev->device == 0x6840) || \
2664 (rdev->ddev->pdev->device == 0x6841) || \
2665 (rdev->ddev->pdev->device == 0x6842) || \
2666 (rdev->ddev->pdev->device == 0x6843))
2671 #define RBIOS8(i) (rdev->bios[i])
2672 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2673 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2675 int radeon_combios_init(struct radeon_device
*rdev
);
2676 void radeon_combios_fini(struct radeon_device
*rdev
);
2677 int radeon_atombios_init(struct radeon_device
*rdev
);
2678 void radeon_atombios_fini(struct radeon_device
*rdev
);
2684 #if DRM_DEBUG_CODE == 0
2685 static inline void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
)
2687 ring
->ring
[ring
->wptr
++] = v
;
2688 ring
->wptr
&= ring
->ptr_mask
;
2690 ring
->ring_free_dw
--;
2693 /* With debugging this is just too big to inline */
2694 void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
);
2700 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2701 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2702 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2703 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2704 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2705 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2706 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2707 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2708 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2709 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2710 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2711 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2712 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2713 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2714 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2715 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2716 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2717 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2718 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2719 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2720 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2721 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2722 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2723 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2724 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2725 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2726 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2727 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2728 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2729 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2730 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2731 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2732 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2733 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2734 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2735 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2736 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2737 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2738 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2739 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2740 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2741 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2742 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2743 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2744 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2745 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2746 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2747 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2748 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2749 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2750 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2751 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2752 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2753 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2754 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2755 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2756 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2757 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2758 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2759 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2760 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2761 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2762 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2763 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2764 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2765 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2766 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2767 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2768 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2769 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2770 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2771 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2772 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2773 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2774 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2775 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2776 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2777 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2778 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2779 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2780 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2781 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2782 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2783 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2785 /* Common functions */
2787 extern int radeon_gpu_reset(struct radeon_device
*rdev
);
2788 extern void radeon_pci_config_reset(struct radeon_device
*rdev
);
2789 extern void r600_set_bios_scratch_engine_hung(struct radeon_device
*rdev
, bool hung
);
2790 extern void radeon_agp_disable(struct radeon_device
*rdev
);
2791 extern int radeon_modeset_init(struct radeon_device
*rdev
);
2792 extern void radeon_modeset_fini(struct radeon_device
*rdev
);
2793 extern bool radeon_card_posted(struct radeon_device
*rdev
);
2794 extern void radeon_update_bandwidth_info(struct radeon_device
*rdev
);
2795 extern void radeon_update_display_priority(struct radeon_device
*rdev
);
2796 extern bool radeon_boot_test_post_card(struct radeon_device
*rdev
);
2797 extern void radeon_scratch_init(struct radeon_device
*rdev
);
2798 extern void radeon_wb_fini(struct radeon_device
*rdev
);
2799 extern int radeon_wb_init(struct radeon_device
*rdev
);
2800 extern void radeon_wb_disable(struct radeon_device
*rdev
);
2801 extern void radeon_surface_init(struct radeon_device
*rdev
);
2802 extern int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
);
2803 extern void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
2804 extern void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
2805 extern void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
);
2806 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
);
2807 extern void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
);
2808 extern void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
2809 extern int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2810 extern int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2811 extern void radeon_ttm_set_active_vram_size(struct radeon_device
*rdev
, u64 size
);
2812 extern void radeon_program_register_sequence(struct radeon_device
*rdev
,
2813 const u32
*registers
,
2814 const u32 array_size
);
2819 int radeon_vm_manager_init(struct radeon_device
*rdev
);
2820 void radeon_vm_manager_fini(struct radeon_device
*rdev
);
2821 int radeon_vm_init(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
2822 void radeon_vm_fini(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
2823 struct radeon_cs_reloc
*radeon_vm_get_bos(struct radeon_device
*rdev
,
2824 struct radeon_vm
*vm
,
2825 struct list_head
*head
);
2826 struct radeon_fence
*radeon_vm_grab_id(struct radeon_device
*rdev
,
2827 struct radeon_vm
*vm
, int ring
);
2828 void radeon_vm_flush(struct radeon_device
*rdev
,
2829 struct radeon_vm
*vm
,
2831 void radeon_vm_fence(struct radeon_device
*rdev
,
2832 struct radeon_vm
*vm
,
2833 struct radeon_fence
*fence
);
2834 uint64_t radeon_vm_map_gart(struct radeon_device
*rdev
, uint64_t addr
);
2835 int radeon_vm_update_page_directory(struct radeon_device
*rdev
,
2836 struct radeon_vm
*vm
);
2837 int radeon_vm_bo_update(struct radeon_device
*rdev
,
2838 struct radeon_vm
*vm
,
2839 struct radeon_bo
*bo
,
2840 struct ttm_mem_reg
*mem
);
2841 void radeon_vm_bo_invalidate(struct radeon_device
*rdev
,
2842 struct radeon_bo
*bo
);
2843 struct radeon_bo_va
*radeon_vm_bo_find(struct radeon_vm
*vm
,
2844 struct radeon_bo
*bo
);
2845 struct radeon_bo_va
*radeon_vm_bo_add(struct radeon_device
*rdev
,
2846 struct radeon_vm
*vm
,
2847 struct radeon_bo
*bo
);
2848 int radeon_vm_bo_set_addr(struct radeon_device
*rdev
,
2849 struct radeon_bo_va
*bo_va
,
2852 int radeon_vm_bo_rmv(struct radeon_device
*rdev
,
2853 struct radeon_bo_va
*bo_va
);
2856 void r600_audio_update_hdmi(struct work_struct
*work
);
2857 struct r600_audio_pin
*r600_audio_get_pin(struct radeon_device
*rdev
);
2858 struct r600_audio_pin
*dce6_audio_get_pin(struct radeon_device
*rdev
);
2859 void r600_audio_enable(struct radeon_device
*rdev
,
2860 struct r600_audio_pin
*pin
,
2862 void dce6_audio_enable(struct radeon_device
*rdev
,
2863 struct r600_audio_pin
*pin
,
2867 * R600 vram scratch functions
2869 int r600_vram_scratch_init(struct radeon_device
*rdev
);
2870 void r600_vram_scratch_fini(struct radeon_device
*rdev
);
2873 * r600 cs checking helper
2875 unsigned r600_mip_minify(unsigned size
, unsigned level
);
2876 bool r600_fmt_is_valid_color(u32 format
);
2877 bool r600_fmt_is_valid_texture(u32 format
, enum radeon_family family
);
2878 int r600_fmt_get_blocksize(u32 format
);
2879 int r600_fmt_get_nblocksx(u32 format
, u32 w
);
2880 int r600_fmt_get_nblocksy(u32 format
, u32 h
);
2883 * r600 functions used by radeon_encoder.c
2885 struct radeon_hdmi_acr
{
2899 extern struct radeon_hdmi_acr
r600_hdmi_acr(uint32_t clock
);
2901 extern u32
r6xx_remap_render_backend(struct radeon_device
*rdev
,
2902 u32 tiling_pipe_num
,
2904 u32 total_max_rb_num
,
2905 u32 enabled_rb_mask
);
2908 * evergreen functions used by radeon_encoder.c
2911 extern int ni_init_microcode(struct radeon_device
*rdev
);
2912 extern int ni_mc_load_microcode(struct radeon_device
*rdev
);
2915 #if defined(CONFIG_ACPI)
2916 extern int radeon_acpi_init(struct radeon_device
*rdev
);
2917 extern void radeon_acpi_fini(struct radeon_device
*rdev
);
2918 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device
*rdev
);
2919 extern int radeon_acpi_pcie_performance_request(struct radeon_device
*rdev
,
2920 u8 perf_req
, bool advertise
);
2921 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device
*rdev
);
2923 static inline int radeon_acpi_init(struct radeon_device
*rdev
) { return 0; }
2924 static inline void radeon_acpi_fini(struct radeon_device
*rdev
) { }
2927 int radeon_cs_packet_parse(struct radeon_cs_parser
*p
,
2928 struct radeon_cs_packet
*pkt
,
2930 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser
*p
);
2931 void radeon_cs_dump_packet(struct radeon_cs_parser
*p
,
2932 struct radeon_cs_packet
*pkt
);
2933 int radeon_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
2934 struct radeon_cs_reloc
**cs_reloc
,
2936 int r600_cs_common_vline_parse(struct radeon_cs_parser
*p
,
2937 uint32_t *vline_start_end
,
2938 uint32_t *vline_status
);
2940 #include "radeon_object.h"