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drm/radeon/kms: add dpm support for rv7xx (v4)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100
101 /*
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 * symbol;
104 */
105 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
107 /* RADEON_IB_POOL_SIZE must be a power of 2 */
108 #define RADEON_IB_POOL_SIZE 16
109 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
110 #define RADEONFB_CONN_LIMIT 4
111 #define RADEON_BIOS_NUM_SCRATCH 8
112
113 /* max number of rings */
114 #define RADEON_NUM_RINGS 6
115
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
122
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132 /* R600+ */
133 #define R600_RING_TYPE_UVD_INDEX 5
134
135 /* hardcode those limit for now */
136 #define RADEON_VA_IB_OFFSET (1 << 20)
137 #define RADEON_VA_RESERVED_SIZE (8 << 20)
138 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
139
140 /* reset flags */
141 #define RADEON_RESET_GFX (1 << 0)
142 #define RADEON_RESET_COMPUTE (1 << 1)
143 #define RADEON_RESET_DMA (1 << 2)
144 #define RADEON_RESET_CP (1 << 3)
145 #define RADEON_RESET_GRBM (1 << 4)
146 #define RADEON_RESET_DMA1 (1 << 5)
147 #define RADEON_RESET_RLC (1 << 6)
148 #define RADEON_RESET_SEM (1 << 7)
149 #define RADEON_RESET_IH (1 << 8)
150 #define RADEON_RESET_VMC (1 << 9)
151 #define RADEON_RESET_MC (1 << 10)
152 #define RADEON_RESET_DISPLAY (1 << 11)
153
154 /* max cursor sizes (in pixels) */
155 #define CURSOR_WIDTH 64
156 #define CURSOR_HEIGHT 64
157
158 #define CIK_CURSOR_WIDTH 128
159 #define CIK_CURSOR_HEIGHT 128
160
161 /*
162 * Errata workarounds.
163 */
164 enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
168 };
169
170
171 struct radeon_device;
172
173
174 /*
175 * BIOS.
176 */
177 bool radeon_get_bios(struct radeon_device *rdev);
178
179 /*
180 * Dummy page
181 */
182 struct radeon_dummy_page {
183 struct page *page;
184 dma_addr_t addr;
185 };
186 int radeon_dummy_page_init(struct radeon_device *rdev);
187 void radeon_dummy_page_fini(struct radeon_device *rdev);
188
189
190 /*
191 * Clocks
192 */
193 struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
196 struct radeon_pll dcpll;
197 struct radeon_pll spll;
198 struct radeon_pll mpll;
199 /* 10 Khz units */
200 uint32_t default_mclk;
201 uint32_t default_sclk;
202 uint32_t default_dispclk;
203 uint32_t dp_extclk;
204 uint32_t max_pixel_clock;
205 };
206
207 /*
208 * Power management
209 */
210 int radeon_pm_init(struct radeon_device *rdev);
211 void radeon_pm_fini(struct radeon_device *rdev);
212 void radeon_pm_compute_clocks(struct radeon_device *rdev);
213 void radeon_pm_suspend(struct radeon_device *rdev);
214 void radeon_pm_resume(struct radeon_device *rdev);
215 void radeon_combios_get_power_modes(struct radeon_device *rdev);
216 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
217 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
218 u8 clock_type,
219 u32 clock,
220 bool strobe_mode,
221 struct atom_clock_dividers *dividers);
222 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
223 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
224 u16 voltage_level, u8 voltage_type,
225 u32 *gpio_value, u32 *gpio_mask);
226 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
227 u32 eng_clock, u32 mem_clock);
228 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
229 u8 voltage_type, u16 *voltage_step);
230 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
231 u16 voltage_id, u16 *voltage);
232 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
233 u8 voltage_type,
234 u16 nominal_voltage,
235 u16 *true_voltage);
236 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
237 u8 voltage_type, u16 *min_voltage);
238 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
239 u8 voltage_type, u16 *max_voltage);
240 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
241 u8 voltage_type,
242 struct atom_voltage_table *voltage_table);
243 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type);
244 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
245 u32 mem_clock);
246 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
247 u32 mem_clock);
248 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
249 u8 module_index,
250 struct atom_mc_reg_table *reg_table);
251 int radeon_atom_get_memory_info(struct radeon_device *rdev,
252 u8 module_index, struct atom_memory_info *mem_info);
253 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
254 bool gddr5, u8 module_index,
255 struct atom_memory_clock_range_table *mclk_range_table);
256 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
257 u16 voltage_id, u16 *voltage);
258 void rs690_pm_info(struct radeon_device *rdev);
259 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
260 unsigned *bankh, unsigned *mtaspect,
261 unsigned *tile_split);
262
263 /*
264 * Fences.
265 */
266 struct radeon_fence_driver {
267 uint32_t scratch_reg;
268 uint64_t gpu_addr;
269 volatile uint32_t *cpu_addr;
270 /* sync_seq is protected by ring emission lock */
271 uint64_t sync_seq[RADEON_NUM_RINGS];
272 atomic64_t last_seq;
273 unsigned long last_activity;
274 bool initialized;
275 };
276
277 struct radeon_fence {
278 struct radeon_device *rdev;
279 struct kref kref;
280 /* protected by radeon_fence.lock */
281 uint64_t seq;
282 /* RB, DMA, etc. */
283 unsigned ring;
284 };
285
286 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
287 int radeon_fence_driver_init(struct radeon_device *rdev);
288 void radeon_fence_driver_fini(struct radeon_device *rdev);
289 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
290 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
291 void radeon_fence_process(struct radeon_device *rdev, int ring);
292 bool radeon_fence_signaled(struct radeon_fence *fence);
293 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
294 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
295 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
296 int radeon_fence_wait_any(struct radeon_device *rdev,
297 struct radeon_fence **fences,
298 bool intr);
299 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
300 void radeon_fence_unref(struct radeon_fence **fence);
301 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
302 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
303 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
304 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
305 struct radeon_fence *b)
306 {
307 if (!a) {
308 return b;
309 }
310
311 if (!b) {
312 return a;
313 }
314
315 BUG_ON(a->ring != b->ring);
316
317 if (a->seq > b->seq) {
318 return a;
319 } else {
320 return b;
321 }
322 }
323
324 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
325 struct radeon_fence *b)
326 {
327 if (!a) {
328 return false;
329 }
330
331 if (!b) {
332 return true;
333 }
334
335 BUG_ON(a->ring != b->ring);
336
337 return a->seq < b->seq;
338 }
339
340 /*
341 * Tiling registers
342 */
343 struct radeon_surface_reg {
344 struct radeon_bo *bo;
345 };
346
347 #define RADEON_GEM_MAX_SURFACES 8
348
349 /*
350 * TTM.
351 */
352 struct radeon_mman {
353 struct ttm_bo_global_ref bo_global_ref;
354 struct drm_global_reference mem_global_ref;
355 struct ttm_bo_device bdev;
356 bool mem_global_referenced;
357 bool initialized;
358 };
359
360 /* bo virtual address in a specific vm */
361 struct radeon_bo_va {
362 /* protected by bo being reserved */
363 struct list_head bo_list;
364 uint64_t soffset;
365 uint64_t eoffset;
366 uint32_t flags;
367 bool valid;
368 unsigned ref_count;
369
370 /* protected by vm mutex */
371 struct list_head vm_list;
372
373 /* constant after initialization */
374 struct radeon_vm *vm;
375 struct radeon_bo *bo;
376 };
377
378 struct radeon_bo {
379 /* Protected by gem.mutex */
380 struct list_head list;
381 /* Protected by tbo.reserved */
382 u32 placements[3];
383 struct ttm_placement placement;
384 struct ttm_buffer_object tbo;
385 struct ttm_bo_kmap_obj kmap;
386 unsigned pin_count;
387 void *kptr;
388 u32 tiling_flags;
389 u32 pitch;
390 int surface_reg;
391 /* list of all virtual address to which this bo
392 * is associated to
393 */
394 struct list_head va;
395 /* Constant after initialization */
396 struct radeon_device *rdev;
397 struct drm_gem_object gem_base;
398
399 struct ttm_bo_kmap_obj dma_buf_vmap;
400 pid_t pid;
401 };
402 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
403
404 struct radeon_bo_list {
405 struct ttm_validate_buffer tv;
406 struct radeon_bo *bo;
407 uint64_t gpu_offset;
408 bool written;
409 unsigned domain;
410 unsigned alt_domain;
411 u32 tiling_flags;
412 };
413
414 int radeon_gem_debugfs_init(struct radeon_device *rdev);
415
416 /* sub-allocation manager, it has to be protected by another lock.
417 * By conception this is an helper for other part of the driver
418 * like the indirect buffer or semaphore, which both have their
419 * locking.
420 *
421 * Principe is simple, we keep a list of sub allocation in offset
422 * order (first entry has offset == 0, last entry has the highest
423 * offset).
424 *
425 * When allocating new object we first check if there is room at
426 * the end total_size - (last_object_offset + last_object_size) >=
427 * alloc_size. If so we allocate new object there.
428 *
429 * When there is not enough room at the end, we start waiting for
430 * each sub object until we reach object_offset+object_size >=
431 * alloc_size, this object then become the sub object we return.
432 *
433 * Alignment can't be bigger than page size.
434 *
435 * Hole are not considered for allocation to keep things simple.
436 * Assumption is that there won't be hole (all object on same
437 * alignment).
438 */
439 struct radeon_sa_manager {
440 wait_queue_head_t wq;
441 struct radeon_bo *bo;
442 struct list_head *hole;
443 struct list_head flist[RADEON_NUM_RINGS];
444 struct list_head olist;
445 unsigned size;
446 uint64_t gpu_addr;
447 void *cpu_ptr;
448 uint32_t domain;
449 };
450
451 struct radeon_sa_bo;
452
453 /* sub-allocation buffer */
454 struct radeon_sa_bo {
455 struct list_head olist;
456 struct list_head flist;
457 struct radeon_sa_manager *manager;
458 unsigned soffset;
459 unsigned eoffset;
460 struct radeon_fence *fence;
461 };
462
463 /*
464 * GEM objects.
465 */
466 struct radeon_gem {
467 struct mutex mutex;
468 struct list_head objects;
469 };
470
471 int radeon_gem_init(struct radeon_device *rdev);
472 void radeon_gem_fini(struct radeon_device *rdev);
473 int radeon_gem_object_create(struct radeon_device *rdev, int size,
474 int alignment, int initial_domain,
475 bool discardable, bool kernel,
476 struct drm_gem_object **obj);
477
478 int radeon_mode_dumb_create(struct drm_file *file_priv,
479 struct drm_device *dev,
480 struct drm_mode_create_dumb *args);
481 int radeon_mode_dumb_mmap(struct drm_file *filp,
482 struct drm_device *dev,
483 uint32_t handle, uint64_t *offset_p);
484 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
485 struct drm_device *dev,
486 uint32_t handle);
487
488 /*
489 * Semaphores.
490 */
491 /* everything here is constant */
492 struct radeon_semaphore {
493 struct radeon_sa_bo *sa_bo;
494 signed waiters;
495 uint64_t gpu_addr;
496 };
497
498 int radeon_semaphore_create(struct radeon_device *rdev,
499 struct radeon_semaphore **semaphore);
500 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
501 struct radeon_semaphore *semaphore);
502 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
503 struct radeon_semaphore *semaphore);
504 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
505 struct radeon_semaphore *semaphore,
506 int signaler, int waiter);
507 void radeon_semaphore_free(struct radeon_device *rdev,
508 struct radeon_semaphore **semaphore,
509 struct radeon_fence *fence);
510
511 /*
512 * GART structures, functions & helpers
513 */
514 struct radeon_mc;
515
516 #define RADEON_GPU_PAGE_SIZE 4096
517 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
518 #define RADEON_GPU_PAGE_SHIFT 12
519 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
520
521 struct radeon_gart {
522 dma_addr_t table_addr;
523 struct radeon_bo *robj;
524 void *ptr;
525 unsigned num_gpu_pages;
526 unsigned num_cpu_pages;
527 unsigned table_size;
528 struct page **pages;
529 dma_addr_t *pages_addr;
530 bool ready;
531 };
532
533 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
534 void radeon_gart_table_ram_free(struct radeon_device *rdev);
535 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
536 void radeon_gart_table_vram_free(struct radeon_device *rdev);
537 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
538 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
539 int radeon_gart_init(struct radeon_device *rdev);
540 void radeon_gart_fini(struct radeon_device *rdev);
541 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
542 int pages);
543 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
544 int pages, struct page **pagelist,
545 dma_addr_t *dma_addr);
546 void radeon_gart_restore(struct radeon_device *rdev);
547
548
549 /*
550 * GPU MC structures, functions & helpers
551 */
552 struct radeon_mc {
553 resource_size_t aper_size;
554 resource_size_t aper_base;
555 resource_size_t agp_base;
556 /* for some chips with <= 32MB we need to lie
557 * about vram size near mc fb location */
558 u64 mc_vram_size;
559 u64 visible_vram_size;
560 u64 gtt_size;
561 u64 gtt_start;
562 u64 gtt_end;
563 u64 vram_start;
564 u64 vram_end;
565 unsigned vram_width;
566 u64 real_vram_size;
567 int vram_mtrr;
568 bool vram_is_ddr;
569 bool igp_sideport_enabled;
570 u64 gtt_base_align;
571 u64 mc_mask;
572 };
573
574 bool radeon_combios_sideport_present(struct radeon_device *rdev);
575 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
576
577 /*
578 * GPU scratch registers structures, functions & helpers
579 */
580 struct radeon_scratch {
581 unsigned num_reg;
582 uint32_t reg_base;
583 bool free[32];
584 uint32_t reg[32];
585 };
586
587 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
588 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
589
590 /*
591 * GPU doorbell structures, functions & helpers
592 */
593 struct radeon_doorbell {
594 u32 num_pages;
595 bool free[1024];
596 /* doorbell mmio */
597 resource_size_t base;
598 resource_size_t size;
599 void __iomem *ptr;
600 };
601
602 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
603 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
604
605 /*
606 * IRQS.
607 */
608
609 struct radeon_unpin_work {
610 struct work_struct work;
611 struct radeon_device *rdev;
612 int crtc_id;
613 struct radeon_fence *fence;
614 struct drm_pending_vblank_event *event;
615 struct radeon_bo *old_rbo;
616 u64 new_crtc_base;
617 };
618
619 struct r500_irq_stat_regs {
620 u32 disp_int;
621 u32 hdmi0_status;
622 };
623
624 struct r600_irq_stat_regs {
625 u32 disp_int;
626 u32 disp_int_cont;
627 u32 disp_int_cont2;
628 u32 d1grph_int;
629 u32 d2grph_int;
630 u32 hdmi0_status;
631 u32 hdmi1_status;
632 };
633
634 struct evergreen_irq_stat_regs {
635 u32 disp_int;
636 u32 disp_int_cont;
637 u32 disp_int_cont2;
638 u32 disp_int_cont3;
639 u32 disp_int_cont4;
640 u32 disp_int_cont5;
641 u32 d1grph_int;
642 u32 d2grph_int;
643 u32 d3grph_int;
644 u32 d4grph_int;
645 u32 d5grph_int;
646 u32 d6grph_int;
647 u32 afmt_status1;
648 u32 afmt_status2;
649 u32 afmt_status3;
650 u32 afmt_status4;
651 u32 afmt_status5;
652 u32 afmt_status6;
653 };
654
655 struct cik_irq_stat_regs {
656 u32 disp_int;
657 u32 disp_int_cont;
658 u32 disp_int_cont2;
659 u32 disp_int_cont3;
660 u32 disp_int_cont4;
661 u32 disp_int_cont5;
662 u32 disp_int_cont6;
663 };
664
665 union radeon_irq_stat_regs {
666 struct r500_irq_stat_regs r500;
667 struct r600_irq_stat_regs r600;
668 struct evergreen_irq_stat_regs evergreen;
669 struct cik_irq_stat_regs cik;
670 };
671
672 #define RADEON_MAX_HPD_PINS 6
673 #define RADEON_MAX_CRTCS 6
674 #define RADEON_MAX_AFMT_BLOCKS 6
675
676 struct radeon_irq {
677 bool installed;
678 spinlock_t lock;
679 atomic_t ring_int[RADEON_NUM_RINGS];
680 bool crtc_vblank_int[RADEON_MAX_CRTCS];
681 atomic_t pflip[RADEON_MAX_CRTCS];
682 wait_queue_head_t vblank_queue;
683 bool hpd[RADEON_MAX_HPD_PINS];
684 bool afmt[RADEON_MAX_AFMT_BLOCKS];
685 union radeon_irq_stat_regs stat_regs;
686 bool dpm_thermal;
687 };
688
689 int radeon_irq_kms_init(struct radeon_device *rdev);
690 void radeon_irq_kms_fini(struct radeon_device *rdev);
691 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
692 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
693 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
694 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
695 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
696 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
697 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
698 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
699
700 /*
701 * CP & rings.
702 */
703
704 struct radeon_ib {
705 struct radeon_sa_bo *sa_bo;
706 uint32_t length_dw;
707 uint64_t gpu_addr;
708 uint32_t *ptr;
709 int ring;
710 struct radeon_fence *fence;
711 struct radeon_vm *vm;
712 bool is_const_ib;
713 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
714 struct radeon_semaphore *semaphore;
715 };
716
717 struct radeon_ring {
718 struct radeon_bo *ring_obj;
719 volatile uint32_t *ring;
720 unsigned rptr;
721 unsigned rptr_offs;
722 unsigned rptr_reg;
723 unsigned rptr_save_reg;
724 u64 next_rptr_gpu_addr;
725 volatile u32 *next_rptr_cpu_addr;
726 unsigned wptr;
727 unsigned wptr_old;
728 unsigned wptr_reg;
729 unsigned ring_size;
730 unsigned ring_free_dw;
731 int count_dw;
732 unsigned long last_activity;
733 unsigned last_rptr;
734 uint64_t gpu_addr;
735 uint32_t align_mask;
736 uint32_t ptr_mask;
737 bool ready;
738 u32 ptr_reg_shift;
739 u32 ptr_reg_mask;
740 u32 nop;
741 u32 idx;
742 u64 last_semaphore_signal_addr;
743 u64 last_semaphore_wait_addr;
744 /* for CIK queues */
745 u32 me;
746 u32 pipe;
747 u32 queue;
748 struct radeon_bo *mqd_obj;
749 u32 doorbell_page_num;
750 u32 doorbell_offset;
751 unsigned wptr_offs;
752 };
753
754 struct radeon_mec {
755 struct radeon_bo *hpd_eop_obj;
756 u64 hpd_eop_gpu_addr;
757 u32 num_pipe;
758 u32 num_mec;
759 u32 num_queue;
760 };
761
762 /*
763 * VM
764 */
765
766 /* maximum number of VMIDs */
767 #define RADEON_NUM_VM 16
768
769 /* defines number of bits in page table versus page directory,
770 * a page is 4KB so we have 12 bits offset, 9 bits in the page
771 * table and the remaining 19 bits are in the page directory */
772 #define RADEON_VM_BLOCK_SIZE 9
773
774 /* number of entries in page table */
775 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
776
777 struct radeon_vm {
778 struct list_head list;
779 struct list_head va;
780 unsigned id;
781
782 /* contains the page directory */
783 struct radeon_sa_bo *page_directory;
784 uint64_t pd_gpu_addr;
785
786 /* array of page tables, one for each page directory entry */
787 struct radeon_sa_bo **page_tables;
788
789 struct mutex mutex;
790 /* last fence for cs using this vm */
791 struct radeon_fence *fence;
792 /* last flush or NULL if we still need to flush */
793 struct radeon_fence *last_flush;
794 };
795
796 struct radeon_vm_manager {
797 struct mutex lock;
798 struct list_head lru_vm;
799 struct radeon_fence *active[RADEON_NUM_VM];
800 struct radeon_sa_manager sa_manager;
801 uint32_t max_pfn;
802 /* number of VMIDs */
803 unsigned nvm;
804 /* vram base address for page table entry */
805 u64 vram_base_offset;
806 /* is vm enabled? */
807 bool enabled;
808 };
809
810 /*
811 * file private structure
812 */
813 struct radeon_fpriv {
814 struct radeon_vm vm;
815 };
816
817 /*
818 * R6xx+ IH ring
819 */
820 struct r600_ih {
821 struct radeon_bo *ring_obj;
822 volatile uint32_t *ring;
823 unsigned rptr;
824 unsigned ring_size;
825 uint64_t gpu_addr;
826 uint32_t ptr_mask;
827 atomic_t lock;
828 bool enabled;
829 };
830
831 struct r600_blit_cp_primitives {
832 void (*set_render_target)(struct radeon_device *rdev, int format,
833 int w, int h, u64 gpu_addr);
834 void (*cp_set_surface_sync)(struct radeon_device *rdev,
835 u32 sync_type, u32 size,
836 u64 mc_addr);
837 void (*set_shaders)(struct radeon_device *rdev);
838 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
839 void (*set_tex_resource)(struct radeon_device *rdev,
840 int format, int w, int h, int pitch,
841 u64 gpu_addr, u32 size);
842 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
843 int x2, int y2);
844 void (*draw_auto)(struct radeon_device *rdev);
845 void (*set_default_state)(struct radeon_device *rdev);
846 };
847
848 struct r600_blit {
849 struct radeon_bo *shader_obj;
850 struct r600_blit_cp_primitives primitives;
851 int max_dim;
852 int ring_size_common;
853 int ring_size_per_loop;
854 u64 shader_gpu_addr;
855 u32 vs_offset, ps_offset;
856 u32 state_offset;
857 u32 state_len;
858 };
859
860 /*
861 * RLC stuff
862 */
863 #include "clearstate_defs.h"
864
865 struct radeon_rlc {
866 /* for power gating */
867 struct radeon_bo *save_restore_obj;
868 uint64_t save_restore_gpu_addr;
869 volatile uint32_t *sr_ptr;
870 u32 *reg_list;
871 u32 reg_list_size;
872 /* for clear state */
873 struct radeon_bo *clear_state_obj;
874 uint64_t clear_state_gpu_addr;
875 volatile uint32_t *cs_ptr;
876 struct cs_section_def *cs_data;
877 };
878
879 int radeon_ib_get(struct radeon_device *rdev, int ring,
880 struct radeon_ib *ib, struct radeon_vm *vm,
881 unsigned size);
882 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
883 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
884 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
885 struct radeon_ib *const_ib);
886 int radeon_ib_pool_init(struct radeon_device *rdev);
887 void radeon_ib_pool_fini(struct radeon_device *rdev);
888 int radeon_ib_ring_tests(struct radeon_device *rdev);
889 /* Ring access between begin & end cannot sleep */
890 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
891 struct radeon_ring *ring);
892 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
893 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
894 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
895 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
896 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
897 void radeon_ring_undo(struct radeon_ring *ring);
898 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
899 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
900 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
901 void radeon_ring_lockup_update(struct radeon_ring *ring);
902 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
903 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
904 uint32_t **data);
905 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
906 unsigned size, uint32_t *data);
907 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
908 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
909 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
910 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
911
912
913 /* r600 async dma */
914 void r600_dma_stop(struct radeon_device *rdev);
915 int r600_dma_resume(struct radeon_device *rdev);
916 void r600_dma_fini(struct radeon_device *rdev);
917
918 void cayman_dma_stop(struct radeon_device *rdev);
919 int cayman_dma_resume(struct radeon_device *rdev);
920 void cayman_dma_fini(struct radeon_device *rdev);
921
922 /*
923 * CS.
924 */
925 struct radeon_cs_reloc {
926 struct drm_gem_object *gobj;
927 struct radeon_bo *robj;
928 struct radeon_bo_list lobj;
929 uint32_t handle;
930 uint32_t flags;
931 };
932
933 struct radeon_cs_chunk {
934 uint32_t chunk_id;
935 uint32_t length_dw;
936 int kpage_idx[2];
937 uint32_t *kpage[2];
938 uint32_t *kdata;
939 void __user *user_ptr;
940 int last_copied_page;
941 int last_page_index;
942 };
943
944 struct radeon_cs_parser {
945 struct device *dev;
946 struct radeon_device *rdev;
947 struct drm_file *filp;
948 /* chunks */
949 unsigned nchunks;
950 struct radeon_cs_chunk *chunks;
951 uint64_t *chunks_array;
952 /* IB */
953 unsigned idx;
954 /* relocations */
955 unsigned nrelocs;
956 struct radeon_cs_reloc *relocs;
957 struct radeon_cs_reloc **relocs_ptr;
958 struct list_head validated;
959 unsigned dma_reloc_idx;
960 /* indices of various chunks */
961 int chunk_ib_idx;
962 int chunk_relocs_idx;
963 int chunk_flags_idx;
964 int chunk_const_ib_idx;
965 struct radeon_ib ib;
966 struct radeon_ib const_ib;
967 void *track;
968 unsigned family;
969 int parser_error;
970 u32 cs_flags;
971 u32 ring;
972 s32 priority;
973 };
974
975 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
976 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
977
978 struct radeon_cs_packet {
979 unsigned idx;
980 unsigned type;
981 unsigned reg;
982 unsigned opcode;
983 int count;
984 unsigned one_reg_wr;
985 };
986
987 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
988 struct radeon_cs_packet *pkt,
989 unsigned idx, unsigned reg);
990 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
991 struct radeon_cs_packet *pkt);
992
993
994 /*
995 * AGP
996 */
997 int radeon_agp_init(struct radeon_device *rdev);
998 void radeon_agp_resume(struct radeon_device *rdev);
999 void radeon_agp_suspend(struct radeon_device *rdev);
1000 void radeon_agp_fini(struct radeon_device *rdev);
1001
1002
1003 /*
1004 * Writeback
1005 */
1006 struct radeon_wb {
1007 struct radeon_bo *wb_obj;
1008 volatile uint32_t *wb;
1009 uint64_t gpu_addr;
1010 bool enabled;
1011 bool use_event;
1012 };
1013
1014 #define RADEON_WB_SCRATCH_OFFSET 0
1015 #define RADEON_WB_RING0_NEXT_RPTR 256
1016 #define RADEON_WB_CP_RPTR_OFFSET 1024
1017 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1018 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1019 #define R600_WB_DMA_RPTR_OFFSET 1792
1020 #define R600_WB_IH_WPTR_OFFSET 2048
1021 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1022 #define R600_WB_UVD_RPTR_OFFSET 2560
1023 #define R600_WB_EVENT_OFFSET 3072
1024 #define CIK_WB_CP1_WPTR_OFFSET 3328
1025 #define CIK_WB_CP2_WPTR_OFFSET 3584
1026
1027 /**
1028 * struct radeon_pm - power management datas
1029 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1030 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1031 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1032 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1033 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1034 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1035 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1036 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1037 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1038 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1039 * @needed_bandwidth: current bandwidth needs
1040 *
1041 * It keeps track of various data needed to take powermanagement decision.
1042 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1043 * Equation between gpu/memory clock and available bandwidth is hw dependent
1044 * (type of memory, bus size, efficiency, ...)
1045 */
1046
1047 enum radeon_pm_method {
1048 PM_METHOD_PROFILE,
1049 PM_METHOD_DYNPM,
1050 PM_METHOD_DPM,
1051 };
1052
1053 enum radeon_dynpm_state {
1054 DYNPM_STATE_DISABLED,
1055 DYNPM_STATE_MINIMUM,
1056 DYNPM_STATE_PAUSED,
1057 DYNPM_STATE_ACTIVE,
1058 DYNPM_STATE_SUSPENDED,
1059 };
1060 enum radeon_dynpm_action {
1061 DYNPM_ACTION_NONE,
1062 DYNPM_ACTION_MINIMUM,
1063 DYNPM_ACTION_DOWNCLOCK,
1064 DYNPM_ACTION_UPCLOCK,
1065 DYNPM_ACTION_DEFAULT
1066 };
1067
1068 enum radeon_voltage_type {
1069 VOLTAGE_NONE = 0,
1070 VOLTAGE_GPIO,
1071 VOLTAGE_VDDC,
1072 VOLTAGE_SW
1073 };
1074
1075 enum radeon_pm_state_type {
1076 /* not used for dpm */
1077 POWER_STATE_TYPE_DEFAULT,
1078 POWER_STATE_TYPE_POWERSAVE,
1079 /* user selectable states */
1080 POWER_STATE_TYPE_BATTERY,
1081 POWER_STATE_TYPE_BALANCED,
1082 POWER_STATE_TYPE_PERFORMANCE,
1083 /* internal states */
1084 POWER_STATE_TYPE_INTERNAL_UVD,
1085 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1086 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1087 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1088 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1089 POWER_STATE_TYPE_INTERNAL_BOOT,
1090 POWER_STATE_TYPE_INTERNAL_THERMAL,
1091 POWER_STATE_TYPE_INTERNAL_ACPI,
1092 POWER_STATE_TYPE_INTERNAL_ULV,
1093 };
1094
1095 enum radeon_pm_profile_type {
1096 PM_PROFILE_DEFAULT,
1097 PM_PROFILE_AUTO,
1098 PM_PROFILE_LOW,
1099 PM_PROFILE_MID,
1100 PM_PROFILE_HIGH,
1101 };
1102
1103 #define PM_PROFILE_DEFAULT_IDX 0
1104 #define PM_PROFILE_LOW_SH_IDX 1
1105 #define PM_PROFILE_MID_SH_IDX 2
1106 #define PM_PROFILE_HIGH_SH_IDX 3
1107 #define PM_PROFILE_LOW_MH_IDX 4
1108 #define PM_PROFILE_MID_MH_IDX 5
1109 #define PM_PROFILE_HIGH_MH_IDX 6
1110 #define PM_PROFILE_MAX 7
1111
1112 struct radeon_pm_profile {
1113 int dpms_off_ps_idx;
1114 int dpms_on_ps_idx;
1115 int dpms_off_cm_idx;
1116 int dpms_on_cm_idx;
1117 };
1118
1119 enum radeon_int_thermal_type {
1120 THERMAL_TYPE_NONE,
1121 THERMAL_TYPE_EXTERNAL,
1122 THERMAL_TYPE_EXTERNAL_GPIO,
1123 THERMAL_TYPE_RV6XX,
1124 THERMAL_TYPE_RV770,
1125 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1126 THERMAL_TYPE_EVERGREEN,
1127 THERMAL_TYPE_SUMO,
1128 THERMAL_TYPE_NI,
1129 THERMAL_TYPE_SI,
1130 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1131 THERMAL_TYPE_CI,
1132 };
1133
1134 struct radeon_voltage {
1135 enum radeon_voltage_type type;
1136 /* gpio voltage */
1137 struct radeon_gpio_rec gpio;
1138 u32 delay; /* delay in usec from voltage drop to sclk change */
1139 bool active_high; /* voltage drop is active when bit is high */
1140 /* VDDC voltage */
1141 u8 vddc_id; /* index into vddc voltage table */
1142 u8 vddci_id; /* index into vddci voltage table */
1143 bool vddci_enabled;
1144 /* r6xx+ sw */
1145 u16 voltage;
1146 /* evergreen+ vddci */
1147 u16 vddci;
1148 };
1149
1150 /* clock mode flags */
1151 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1152
1153 struct radeon_pm_clock_info {
1154 /* memory clock */
1155 u32 mclk;
1156 /* engine clock */
1157 u32 sclk;
1158 /* voltage info */
1159 struct radeon_voltage voltage;
1160 /* standardized clock flags */
1161 u32 flags;
1162 };
1163
1164 /* state flags */
1165 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1166
1167 struct radeon_power_state {
1168 enum radeon_pm_state_type type;
1169 struct radeon_pm_clock_info *clock_info;
1170 /* number of valid clock modes in this power state */
1171 int num_clock_modes;
1172 struct radeon_pm_clock_info *default_clock_mode;
1173 /* standardized state flags */
1174 u32 flags;
1175 u32 misc; /* vbios specific flags */
1176 u32 misc2; /* vbios specific flags */
1177 int pcie_lanes; /* pcie lanes */
1178 };
1179
1180 /*
1181 * Some modes are overclocked by very low value, accept them
1182 */
1183 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1184
1185 enum radeon_dpm_auto_throttle_src {
1186 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1187 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1188 };
1189
1190 enum radeon_dpm_event_src {
1191 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1192 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1193 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1194 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1195 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1196 };
1197
1198 struct radeon_ps {
1199 u32 caps; /* vbios flags */
1200 u32 class; /* vbios flags */
1201 u32 class2; /* vbios flags */
1202 /* UVD clocks */
1203 u32 vclk;
1204 u32 dclk;
1205 /* asic priv */
1206 void *ps_priv;
1207 };
1208
1209 struct radeon_dpm_thermal {
1210 /* thermal interrupt work */
1211 struct work_struct work;
1212 /* low temperature threshold */
1213 int min_temp;
1214 /* high temperature threshold */
1215 int max_temp;
1216 /* was interrupt low to high or high to low */
1217 bool high_to_low;
1218 };
1219
1220 struct radeon_dpm {
1221 struct radeon_ps *ps;
1222 /* number of valid power states */
1223 int num_ps;
1224 /* current power state that is active */
1225 struct radeon_ps *current_ps;
1226 /* requested power state */
1227 struct radeon_ps *requested_ps;
1228 /* boot up power state */
1229 struct radeon_ps *boot_ps;
1230 /* default uvd power state */
1231 struct radeon_ps *uvd_ps;
1232 enum radeon_pm_state_type state;
1233 enum radeon_pm_state_type user_state;
1234 u32 platform_caps;
1235 u32 voltage_response_time;
1236 u32 backbias_response_time;
1237 void *priv;
1238 u32 new_active_crtcs;
1239 int new_active_crtc_count;
1240 u32 current_active_crtcs;
1241 int current_active_crtc_count;
1242 /* special states active */
1243 bool thermal_active;
1244 /* thermal handling */
1245 struct radeon_dpm_thermal thermal;
1246 };
1247
1248 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1249 enum radeon_pm_state_type dpm_state);
1250
1251
1252 struct radeon_pm {
1253 struct mutex mutex;
1254 /* write locked while reprogramming mclk */
1255 struct rw_semaphore mclk_lock;
1256 u32 active_crtcs;
1257 int active_crtc_count;
1258 int req_vblank;
1259 bool vblank_sync;
1260 fixed20_12 max_bandwidth;
1261 fixed20_12 igp_sideport_mclk;
1262 fixed20_12 igp_system_mclk;
1263 fixed20_12 igp_ht_link_clk;
1264 fixed20_12 igp_ht_link_width;
1265 fixed20_12 k8_bandwidth;
1266 fixed20_12 sideport_bandwidth;
1267 fixed20_12 ht_bandwidth;
1268 fixed20_12 core_bandwidth;
1269 fixed20_12 sclk;
1270 fixed20_12 mclk;
1271 fixed20_12 needed_bandwidth;
1272 struct radeon_power_state *power_state;
1273 /* number of valid power states */
1274 int num_power_states;
1275 int current_power_state_index;
1276 int current_clock_mode_index;
1277 int requested_power_state_index;
1278 int requested_clock_mode_index;
1279 int default_power_state_index;
1280 u32 current_sclk;
1281 u32 current_mclk;
1282 u16 current_vddc;
1283 u16 current_vddci;
1284 u32 default_sclk;
1285 u32 default_mclk;
1286 u16 default_vddc;
1287 u16 default_vddci;
1288 struct radeon_i2c_chan *i2c_bus;
1289 /* selected pm method */
1290 enum radeon_pm_method pm_method;
1291 /* dynpm power management */
1292 struct delayed_work dynpm_idle_work;
1293 enum radeon_dynpm_state dynpm_state;
1294 enum radeon_dynpm_action dynpm_planned_action;
1295 unsigned long dynpm_action_timeout;
1296 bool dynpm_can_upclock;
1297 bool dynpm_can_downclock;
1298 /* profile-based power management */
1299 enum radeon_pm_profile_type profile;
1300 int profile_index;
1301 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1302 /* internal thermal controller on rv6xx+ */
1303 enum radeon_int_thermal_type int_thermal_type;
1304 struct device *int_hwmon_dev;
1305 /* dpm */
1306 bool dpm_enabled;
1307 struct radeon_dpm dpm;
1308 };
1309
1310 int radeon_pm_get_type_index(struct radeon_device *rdev,
1311 enum radeon_pm_state_type ps_type,
1312 int instance);
1313 /*
1314 * UVD
1315 */
1316 #define RADEON_MAX_UVD_HANDLES 10
1317 #define RADEON_UVD_STACK_SIZE (1024*1024)
1318 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1319
1320 struct radeon_uvd {
1321 struct radeon_bo *vcpu_bo;
1322 void *cpu_addr;
1323 uint64_t gpu_addr;
1324 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1325 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1326 struct delayed_work idle_work;
1327 };
1328
1329 int radeon_uvd_init(struct radeon_device *rdev);
1330 void radeon_uvd_fini(struct radeon_device *rdev);
1331 int radeon_uvd_suspend(struct radeon_device *rdev);
1332 int radeon_uvd_resume(struct radeon_device *rdev);
1333 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1334 uint32_t handle, struct radeon_fence **fence);
1335 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1336 uint32_t handle, struct radeon_fence **fence);
1337 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1338 void radeon_uvd_free_handles(struct radeon_device *rdev,
1339 struct drm_file *filp);
1340 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1341 void radeon_uvd_note_usage(struct radeon_device *rdev);
1342 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1343 unsigned vclk, unsigned dclk,
1344 unsigned vco_min, unsigned vco_max,
1345 unsigned fb_factor, unsigned fb_mask,
1346 unsigned pd_min, unsigned pd_max,
1347 unsigned pd_even,
1348 unsigned *optimal_fb_div,
1349 unsigned *optimal_vclk_div,
1350 unsigned *optimal_dclk_div);
1351 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1352 unsigned cg_upll_func_cntl);
1353
1354 struct r600_audio {
1355 int channels;
1356 int rate;
1357 int bits_per_sample;
1358 u8 status_bits;
1359 u8 category_code;
1360 };
1361
1362 /*
1363 * Benchmarking
1364 */
1365 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1366
1367
1368 /*
1369 * Testing
1370 */
1371 void radeon_test_moves(struct radeon_device *rdev);
1372 void radeon_test_ring_sync(struct radeon_device *rdev,
1373 struct radeon_ring *cpA,
1374 struct radeon_ring *cpB);
1375 void radeon_test_syncing(struct radeon_device *rdev);
1376
1377
1378 /*
1379 * Debugfs
1380 */
1381 struct radeon_debugfs {
1382 struct drm_info_list *files;
1383 unsigned num_files;
1384 };
1385
1386 int radeon_debugfs_add_files(struct radeon_device *rdev,
1387 struct drm_info_list *files,
1388 unsigned nfiles);
1389 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1390
1391
1392 /*
1393 * ASIC specific functions.
1394 */
1395 struct radeon_asic {
1396 int (*init)(struct radeon_device *rdev);
1397 void (*fini)(struct radeon_device *rdev);
1398 int (*resume)(struct radeon_device *rdev);
1399 int (*suspend)(struct radeon_device *rdev);
1400 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1401 int (*asic_reset)(struct radeon_device *rdev);
1402 /* ioctl hw specific callback. Some hw might want to perform special
1403 * operation on specific ioctl. For instance on wait idle some hw
1404 * might want to perform and HDP flush through MMIO as it seems that
1405 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1406 * through ring.
1407 */
1408 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1409 /* check if 3D engine is idle */
1410 bool (*gui_idle)(struct radeon_device *rdev);
1411 /* wait for mc_idle */
1412 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1413 /* get the reference clock */
1414 u32 (*get_xclk)(struct radeon_device *rdev);
1415 /* get the gpu clock counter */
1416 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1417 /* gart */
1418 struct {
1419 void (*tlb_flush)(struct radeon_device *rdev);
1420 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1421 } gart;
1422 struct {
1423 int (*init)(struct radeon_device *rdev);
1424 void (*fini)(struct radeon_device *rdev);
1425
1426 u32 pt_ring_index;
1427 void (*set_page)(struct radeon_device *rdev,
1428 struct radeon_ib *ib,
1429 uint64_t pe,
1430 uint64_t addr, unsigned count,
1431 uint32_t incr, uint32_t flags);
1432 } vm;
1433 /* ring specific callbacks */
1434 struct {
1435 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1436 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1437 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1438 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1439 struct radeon_semaphore *semaphore, bool emit_wait);
1440 int (*cs_parse)(struct radeon_cs_parser *p);
1441 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1442 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1443 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1444 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1445 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1446
1447 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1448 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1449 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1450 } ring[RADEON_NUM_RINGS];
1451 /* irqs */
1452 struct {
1453 int (*set)(struct radeon_device *rdev);
1454 int (*process)(struct radeon_device *rdev);
1455 } irq;
1456 /* displays */
1457 struct {
1458 /* display watermarks */
1459 void (*bandwidth_update)(struct radeon_device *rdev);
1460 /* get frame count */
1461 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1462 /* wait for vblank */
1463 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1464 /* set backlight level */
1465 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1466 /* get backlight level */
1467 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1468 /* audio callbacks */
1469 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1470 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1471 } display;
1472 /* copy functions for bo handling */
1473 struct {
1474 int (*blit)(struct radeon_device *rdev,
1475 uint64_t src_offset,
1476 uint64_t dst_offset,
1477 unsigned num_gpu_pages,
1478 struct radeon_fence **fence);
1479 u32 blit_ring_index;
1480 int (*dma)(struct radeon_device *rdev,
1481 uint64_t src_offset,
1482 uint64_t dst_offset,
1483 unsigned num_gpu_pages,
1484 struct radeon_fence **fence);
1485 u32 dma_ring_index;
1486 /* method used for bo copy */
1487 int (*copy)(struct radeon_device *rdev,
1488 uint64_t src_offset,
1489 uint64_t dst_offset,
1490 unsigned num_gpu_pages,
1491 struct radeon_fence **fence);
1492 /* ring used for bo copies */
1493 u32 copy_ring_index;
1494 } copy;
1495 /* surfaces */
1496 struct {
1497 int (*set_reg)(struct radeon_device *rdev, int reg,
1498 uint32_t tiling_flags, uint32_t pitch,
1499 uint32_t offset, uint32_t obj_size);
1500 void (*clear_reg)(struct radeon_device *rdev, int reg);
1501 } surface;
1502 /* hotplug detect */
1503 struct {
1504 void (*init)(struct radeon_device *rdev);
1505 void (*fini)(struct radeon_device *rdev);
1506 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1507 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1508 } hpd;
1509 /* static power management */
1510 struct {
1511 void (*misc)(struct radeon_device *rdev);
1512 void (*prepare)(struct radeon_device *rdev);
1513 void (*finish)(struct radeon_device *rdev);
1514 void (*init_profile)(struct radeon_device *rdev);
1515 void (*get_dynpm_state)(struct radeon_device *rdev);
1516 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1517 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1518 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1519 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1520 int (*get_pcie_lanes)(struct radeon_device *rdev);
1521 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1522 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1523 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1524 int (*get_temperature)(struct radeon_device *rdev);
1525 } pm;
1526 /* dynamic power management */
1527 struct {
1528 int (*init)(struct radeon_device *rdev);
1529 void (*setup_asic)(struct radeon_device *rdev);
1530 int (*enable)(struct radeon_device *rdev);
1531 void (*disable)(struct radeon_device *rdev);
1532 int (*set_power_state)(struct radeon_device *rdev);
1533 void (*display_configuration_changed)(struct radeon_device *rdev);
1534 void (*fini)(struct radeon_device *rdev);
1535 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1536 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1537 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1538 } dpm;
1539 /* pageflipping */
1540 struct {
1541 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1542 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1543 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1544 } pflip;
1545 };
1546
1547 /*
1548 * Asic structures
1549 */
1550 struct r100_asic {
1551 const unsigned *reg_safe_bm;
1552 unsigned reg_safe_bm_size;
1553 u32 hdp_cntl;
1554 };
1555
1556 struct r300_asic {
1557 const unsigned *reg_safe_bm;
1558 unsigned reg_safe_bm_size;
1559 u32 resync_scratch;
1560 u32 hdp_cntl;
1561 };
1562
1563 struct r600_asic {
1564 unsigned max_pipes;
1565 unsigned max_tile_pipes;
1566 unsigned max_simds;
1567 unsigned max_backends;
1568 unsigned max_gprs;
1569 unsigned max_threads;
1570 unsigned max_stack_entries;
1571 unsigned max_hw_contexts;
1572 unsigned max_gs_threads;
1573 unsigned sx_max_export_size;
1574 unsigned sx_max_export_pos_size;
1575 unsigned sx_max_export_smx_size;
1576 unsigned sq_num_cf_insts;
1577 unsigned tiling_nbanks;
1578 unsigned tiling_npipes;
1579 unsigned tiling_group_size;
1580 unsigned tile_config;
1581 unsigned backend_map;
1582 };
1583
1584 struct rv770_asic {
1585 unsigned max_pipes;
1586 unsigned max_tile_pipes;
1587 unsigned max_simds;
1588 unsigned max_backends;
1589 unsigned max_gprs;
1590 unsigned max_threads;
1591 unsigned max_stack_entries;
1592 unsigned max_hw_contexts;
1593 unsigned max_gs_threads;
1594 unsigned sx_max_export_size;
1595 unsigned sx_max_export_pos_size;
1596 unsigned sx_max_export_smx_size;
1597 unsigned sq_num_cf_insts;
1598 unsigned sx_num_of_sets;
1599 unsigned sc_prim_fifo_size;
1600 unsigned sc_hiz_tile_fifo_size;
1601 unsigned sc_earlyz_tile_fifo_fize;
1602 unsigned tiling_nbanks;
1603 unsigned tiling_npipes;
1604 unsigned tiling_group_size;
1605 unsigned tile_config;
1606 unsigned backend_map;
1607 };
1608
1609 struct evergreen_asic {
1610 unsigned num_ses;
1611 unsigned max_pipes;
1612 unsigned max_tile_pipes;
1613 unsigned max_simds;
1614 unsigned max_backends;
1615 unsigned max_gprs;
1616 unsigned max_threads;
1617 unsigned max_stack_entries;
1618 unsigned max_hw_contexts;
1619 unsigned max_gs_threads;
1620 unsigned sx_max_export_size;
1621 unsigned sx_max_export_pos_size;
1622 unsigned sx_max_export_smx_size;
1623 unsigned sq_num_cf_insts;
1624 unsigned sx_num_of_sets;
1625 unsigned sc_prim_fifo_size;
1626 unsigned sc_hiz_tile_fifo_size;
1627 unsigned sc_earlyz_tile_fifo_size;
1628 unsigned tiling_nbanks;
1629 unsigned tiling_npipes;
1630 unsigned tiling_group_size;
1631 unsigned tile_config;
1632 unsigned backend_map;
1633 };
1634
1635 struct cayman_asic {
1636 unsigned max_shader_engines;
1637 unsigned max_pipes_per_simd;
1638 unsigned max_tile_pipes;
1639 unsigned max_simds_per_se;
1640 unsigned max_backends_per_se;
1641 unsigned max_texture_channel_caches;
1642 unsigned max_gprs;
1643 unsigned max_threads;
1644 unsigned max_gs_threads;
1645 unsigned max_stack_entries;
1646 unsigned sx_num_of_sets;
1647 unsigned sx_max_export_size;
1648 unsigned sx_max_export_pos_size;
1649 unsigned sx_max_export_smx_size;
1650 unsigned max_hw_contexts;
1651 unsigned sq_num_cf_insts;
1652 unsigned sc_prim_fifo_size;
1653 unsigned sc_hiz_tile_fifo_size;
1654 unsigned sc_earlyz_tile_fifo_size;
1655
1656 unsigned num_shader_engines;
1657 unsigned num_shader_pipes_per_simd;
1658 unsigned num_tile_pipes;
1659 unsigned num_simds_per_se;
1660 unsigned num_backends_per_se;
1661 unsigned backend_disable_mask_per_asic;
1662 unsigned backend_map;
1663 unsigned num_texture_channel_caches;
1664 unsigned mem_max_burst_length_bytes;
1665 unsigned mem_row_size_in_kb;
1666 unsigned shader_engine_tile_size;
1667 unsigned num_gpus;
1668 unsigned multi_gpu_tile_size;
1669
1670 unsigned tile_config;
1671 };
1672
1673 struct si_asic {
1674 unsigned max_shader_engines;
1675 unsigned max_tile_pipes;
1676 unsigned max_cu_per_sh;
1677 unsigned max_sh_per_se;
1678 unsigned max_backends_per_se;
1679 unsigned max_texture_channel_caches;
1680 unsigned max_gprs;
1681 unsigned max_gs_threads;
1682 unsigned max_hw_contexts;
1683 unsigned sc_prim_fifo_size_frontend;
1684 unsigned sc_prim_fifo_size_backend;
1685 unsigned sc_hiz_tile_fifo_size;
1686 unsigned sc_earlyz_tile_fifo_size;
1687
1688 unsigned num_tile_pipes;
1689 unsigned num_backends_per_se;
1690 unsigned backend_disable_mask_per_asic;
1691 unsigned backend_map;
1692 unsigned num_texture_channel_caches;
1693 unsigned mem_max_burst_length_bytes;
1694 unsigned mem_row_size_in_kb;
1695 unsigned shader_engine_tile_size;
1696 unsigned num_gpus;
1697 unsigned multi_gpu_tile_size;
1698
1699 unsigned tile_config;
1700 uint32_t tile_mode_array[32];
1701 };
1702
1703 struct cik_asic {
1704 unsigned max_shader_engines;
1705 unsigned max_tile_pipes;
1706 unsigned max_cu_per_sh;
1707 unsigned max_sh_per_se;
1708 unsigned max_backends_per_se;
1709 unsigned max_texture_channel_caches;
1710 unsigned max_gprs;
1711 unsigned max_gs_threads;
1712 unsigned max_hw_contexts;
1713 unsigned sc_prim_fifo_size_frontend;
1714 unsigned sc_prim_fifo_size_backend;
1715 unsigned sc_hiz_tile_fifo_size;
1716 unsigned sc_earlyz_tile_fifo_size;
1717
1718 unsigned num_tile_pipes;
1719 unsigned num_backends_per_se;
1720 unsigned backend_disable_mask_per_asic;
1721 unsigned backend_map;
1722 unsigned num_texture_channel_caches;
1723 unsigned mem_max_burst_length_bytes;
1724 unsigned mem_row_size_in_kb;
1725 unsigned shader_engine_tile_size;
1726 unsigned num_gpus;
1727 unsigned multi_gpu_tile_size;
1728
1729 unsigned tile_config;
1730 uint32_t tile_mode_array[32];
1731 };
1732
1733 union radeon_asic_config {
1734 struct r300_asic r300;
1735 struct r100_asic r100;
1736 struct r600_asic r600;
1737 struct rv770_asic rv770;
1738 struct evergreen_asic evergreen;
1739 struct cayman_asic cayman;
1740 struct si_asic si;
1741 struct cik_asic cik;
1742 };
1743
1744 /*
1745 * asic initizalization from radeon_asic.c
1746 */
1747 void radeon_agp_disable(struct radeon_device *rdev);
1748 int radeon_asic_init(struct radeon_device *rdev);
1749
1750
1751 /*
1752 * IOCTL.
1753 */
1754 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1755 struct drm_file *filp);
1756 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1757 struct drm_file *filp);
1758 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1759 struct drm_file *file_priv);
1760 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1761 struct drm_file *file_priv);
1762 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1763 struct drm_file *file_priv);
1764 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1765 struct drm_file *file_priv);
1766 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1767 struct drm_file *filp);
1768 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1769 struct drm_file *filp);
1770 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1771 struct drm_file *filp);
1772 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1773 struct drm_file *filp);
1774 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1775 struct drm_file *filp);
1776 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1777 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1778 struct drm_file *filp);
1779 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1780 struct drm_file *filp);
1781
1782 /* VRAM scratch page for HDP bug, default vram page */
1783 struct r600_vram_scratch {
1784 struct radeon_bo *robj;
1785 volatile uint32_t *ptr;
1786 u64 gpu_addr;
1787 };
1788
1789 /*
1790 * ACPI
1791 */
1792 struct radeon_atif_notification_cfg {
1793 bool enabled;
1794 int command_code;
1795 };
1796
1797 struct radeon_atif_notifications {
1798 bool display_switch;
1799 bool expansion_mode_change;
1800 bool thermal_state;
1801 bool forced_power_state;
1802 bool system_power_state;
1803 bool display_conf_change;
1804 bool px_gfx_switch;
1805 bool brightness_change;
1806 bool dgpu_display_event;
1807 };
1808
1809 struct radeon_atif_functions {
1810 bool system_params;
1811 bool sbios_requests;
1812 bool select_active_disp;
1813 bool lid_state;
1814 bool get_tv_standard;
1815 bool set_tv_standard;
1816 bool get_panel_expansion_mode;
1817 bool set_panel_expansion_mode;
1818 bool temperature_change;
1819 bool graphics_device_types;
1820 };
1821
1822 struct radeon_atif {
1823 struct radeon_atif_notifications notifications;
1824 struct radeon_atif_functions functions;
1825 struct radeon_atif_notification_cfg notification_cfg;
1826 struct radeon_encoder *encoder_for_bl;
1827 };
1828
1829 struct radeon_atcs_functions {
1830 bool get_ext_state;
1831 bool pcie_perf_req;
1832 bool pcie_dev_rdy;
1833 bool pcie_bus_width;
1834 };
1835
1836 struct radeon_atcs {
1837 struct radeon_atcs_functions functions;
1838 };
1839
1840 /*
1841 * Core structure, functions and helpers.
1842 */
1843 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1844 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1845
1846 struct radeon_device {
1847 struct device *dev;
1848 struct drm_device *ddev;
1849 struct pci_dev *pdev;
1850 struct rw_semaphore exclusive_lock;
1851 /* ASIC */
1852 union radeon_asic_config config;
1853 enum radeon_family family;
1854 unsigned long flags;
1855 int usec_timeout;
1856 enum radeon_pll_errata pll_errata;
1857 int num_gb_pipes;
1858 int num_z_pipes;
1859 int disp_priority;
1860 /* BIOS */
1861 uint8_t *bios;
1862 bool is_atom_bios;
1863 uint16_t bios_header_start;
1864 struct radeon_bo *stollen_vga_memory;
1865 /* Register mmio */
1866 resource_size_t rmmio_base;
1867 resource_size_t rmmio_size;
1868 /* protects concurrent MM_INDEX/DATA based register access */
1869 spinlock_t mmio_idx_lock;
1870 void __iomem *rmmio;
1871 radeon_rreg_t mc_rreg;
1872 radeon_wreg_t mc_wreg;
1873 radeon_rreg_t pll_rreg;
1874 radeon_wreg_t pll_wreg;
1875 uint32_t pcie_reg_mask;
1876 radeon_rreg_t pciep_rreg;
1877 radeon_wreg_t pciep_wreg;
1878 /* io port */
1879 void __iomem *rio_mem;
1880 resource_size_t rio_mem_size;
1881 struct radeon_clock clock;
1882 struct radeon_mc mc;
1883 struct radeon_gart gart;
1884 struct radeon_mode_info mode_info;
1885 struct radeon_scratch scratch;
1886 struct radeon_doorbell doorbell;
1887 struct radeon_mman mman;
1888 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1889 wait_queue_head_t fence_queue;
1890 struct mutex ring_lock;
1891 struct radeon_ring ring[RADEON_NUM_RINGS];
1892 bool ib_pool_ready;
1893 struct radeon_sa_manager ring_tmp_bo;
1894 struct radeon_irq irq;
1895 struct radeon_asic *asic;
1896 struct radeon_gem gem;
1897 struct radeon_pm pm;
1898 struct radeon_uvd uvd;
1899 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1900 struct radeon_wb wb;
1901 struct radeon_dummy_page dummy_page;
1902 bool shutdown;
1903 bool suspend;
1904 bool need_dma32;
1905 bool accel_working;
1906 bool fastfb_working; /* IGP feature*/
1907 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1908 const struct firmware *me_fw; /* all family ME firmware */
1909 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1910 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1911 const struct firmware *mc_fw; /* NI MC firmware */
1912 const struct firmware *ce_fw; /* SI CE firmware */
1913 const struct firmware *uvd_fw; /* UVD firmware */
1914 const struct firmware *mec_fw; /* CIK MEC firmware */
1915 const struct firmware *sdma_fw; /* CIK SDMA firmware */
1916 const struct firmware *smc_fw; /* SMC firmware */
1917 struct r600_blit r600_blit;
1918 struct r600_vram_scratch vram_scratch;
1919 int msi_enabled; /* msi enabled */
1920 struct r600_ih ih; /* r6/700 interrupt ring */
1921 struct radeon_rlc rlc;
1922 struct radeon_mec mec;
1923 struct work_struct hotplug_work;
1924 struct work_struct audio_work;
1925 struct work_struct reset_work;
1926 int num_crtc; /* number of crtcs */
1927 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1928 bool audio_enabled;
1929 bool has_uvd;
1930 struct r600_audio audio_status; /* audio stuff */
1931 struct notifier_block acpi_nb;
1932 /* only one userspace can use Hyperz features or CMASK at a time */
1933 struct drm_file *hyperz_filp;
1934 struct drm_file *cmask_filp;
1935 /* i2c buses */
1936 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1937 /* debugfs */
1938 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1939 unsigned debugfs_count;
1940 /* virtual memory */
1941 struct radeon_vm_manager vm_manager;
1942 struct mutex gpu_clock_mutex;
1943 /* ACPI interface */
1944 struct radeon_atif atif;
1945 struct radeon_atcs atcs;
1946 };
1947
1948 int radeon_device_init(struct radeon_device *rdev,
1949 struct drm_device *ddev,
1950 struct pci_dev *pdev,
1951 uint32_t flags);
1952 void radeon_device_fini(struct radeon_device *rdev);
1953 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1954
1955 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1956 bool always_indirect);
1957 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1958 bool always_indirect);
1959 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1960 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1961
1962 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
1963 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
1964
1965 /*
1966 * Cast helper
1967 */
1968 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1969
1970 /*
1971 * Registers read & write functions.
1972 */
1973 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1974 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1975 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1976 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1977 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1978 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1979 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1980 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1981 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1982 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1983 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1984 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1985 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1986 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1987 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1988 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1989 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1990 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1991 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1992 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
1993 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
1994 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
1995 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
1996 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
1997 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
1998 #define WREG32_P(reg, val, mask) \
1999 do { \
2000 uint32_t tmp_ = RREG32(reg); \
2001 tmp_ &= (mask); \
2002 tmp_ |= ((val) & ~(mask)); \
2003 WREG32(reg, tmp_); \
2004 } while (0)
2005 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2006 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
2007 #define WREG32_PLL_P(reg, val, mask) \
2008 do { \
2009 uint32_t tmp_ = RREG32_PLL(reg); \
2010 tmp_ &= (mask); \
2011 tmp_ |= ((val) & ~(mask)); \
2012 WREG32_PLL(reg, tmp_); \
2013 } while (0)
2014 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2015 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2016 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2017
2018 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2019 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2020
2021 /*
2022 * Indirect registers accessor
2023 */
2024 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2025 {
2026 uint32_t r;
2027
2028 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2029 r = RREG32(RADEON_PCIE_DATA);
2030 return r;
2031 }
2032
2033 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2034 {
2035 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2036 WREG32(RADEON_PCIE_DATA, (v));
2037 }
2038
2039 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2040 {
2041 u32 r;
2042
2043 WREG32(TN_SMC_IND_INDEX_0, (reg));
2044 r = RREG32(TN_SMC_IND_DATA_0);
2045 return r;
2046 }
2047
2048 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2049 {
2050 WREG32(TN_SMC_IND_INDEX_0, (reg));
2051 WREG32(TN_SMC_IND_DATA_0, (v));
2052 }
2053
2054 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2055 {
2056 u32 r;
2057
2058 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2059 r = RREG32(R600_RCU_DATA);
2060 return r;
2061 }
2062
2063 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2064 {
2065 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2066 WREG32(R600_RCU_DATA, (v));
2067 }
2068
2069 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2070 {
2071 u32 r;
2072
2073 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2074 r = RREG32(EVERGREEN_CG_IND_DATA);
2075 return r;
2076 }
2077
2078 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2079 {
2080 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2081 WREG32(EVERGREEN_CG_IND_DATA, (v));
2082 }
2083
2084 void r100_pll_errata_after_index(struct radeon_device *rdev);
2085
2086
2087 /*
2088 * ASICs helpers.
2089 */
2090 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2091 (rdev->pdev->device == 0x5969))
2092 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2093 (rdev->family == CHIP_RV200) || \
2094 (rdev->family == CHIP_RS100) || \
2095 (rdev->family == CHIP_RS200) || \
2096 (rdev->family == CHIP_RV250) || \
2097 (rdev->family == CHIP_RV280) || \
2098 (rdev->family == CHIP_RS300))
2099 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2100 (rdev->family == CHIP_RV350) || \
2101 (rdev->family == CHIP_R350) || \
2102 (rdev->family == CHIP_RV380) || \
2103 (rdev->family == CHIP_R420) || \
2104 (rdev->family == CHIP_R423) || \
2105 (rdev->family == CHIP_RV410) || \
2106 (rdev->family == CHIP_RS400) || \
2107 (rdev->family == CHIP_RS480))
2108 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2109 (rdev->ddev->pdev->device == 0x9443) || \
2110 (rdev->ddev->pdev->device == 0x944B) || \
2111 (rdev->ddev->pdev->device == 0x9506) || \
2112 (rdev->ddev->pdev->device == 0x9509) || \
2113 (rdev->ddev->pdev->device == 0x950F) || \
2114 (rdev->ddev->pdev->device == 0x689C) || \
2115 (rdev->ddev->pdev->device == 0x689D))
2116 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2117 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2118 (rdev->family == CHIP_RS690) || \
2119 (rdev->family == CHIP_RS740) || \
2120 (rdev->family >= CHIP_R600))
2121 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2122 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2123 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2124 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2125 (rdev->flags & RADEON_IS_IGP))
2126 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2127 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2128 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2129 (rdev->flags & RADEON_IS_IGP))
2130 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2131 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2132 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2133
2134 /*
2135 * BIOS helpers.
2136 */
2137 #define RBIOS8(i) (rdev->bios[i])
2138 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2139 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2140
2141 int radeon_combios_init(struct radeon_device *rdev);
2142 void radeon_combios_fini(struct radeon_device *rdev);
2143 int radeon_atombios_init(struct radeon_device *rdev);
2144 void radeon_atombios_fini(struct radeon_device *rdev);
2145
2146
2147 /*
2148 * RING helpers.
2149 */
2150 #if DRM_DEBUG_CODE == 0
2151 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2152 {
2153 ring->ring[ring->wptr++] = v;
2154 ring->wptr &= ring->ptr_mask;
2155 ring->count_dw--;
2156 ring->ring_free_dw--;
2157 }
2158 #else
2159 /* With debugging this is just too big to inline */
2160 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2161 #endif
2162
2163 /*
2164 * ASICs macro.
2165 */
2166 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2167 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2168 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2169 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2170 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2171 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2172 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2173 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2174 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2175 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2176 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2177 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2178 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2179 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2180 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2181 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2182 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2183 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2184 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2185 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2186 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2187 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2188 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2189 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2190 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2191 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2192 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2193 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2194 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2195 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2196 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2197 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2198 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2199 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2200 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2201 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2202 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2203 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2204 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2205 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2206 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2207 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2208 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2209 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2210 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2211 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2212 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2213 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2214 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2215 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2216 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2217 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2218 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2219 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2220 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2221 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2222 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2223 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2224 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2225 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2226 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2227 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2228 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2229 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2230 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2231 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2232 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2233 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2234 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2235 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2236 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2237 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2238 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2239 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2240 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2241 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2242
2243 /* Common functions */
2244 /* AGP */
2245 extern int radeon_gpu_reset(struct radeon_device *rdev);
2246 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2247 extern void radeon_agp_disable(struct radeon_device *rdev);
2248 extern int radeon_modeset_init(struct radeon_device *rdev);
2249 extern void radeon_modeset_fini(struct radeon_device *rdev);
2250 extern bool radeon_card_posted(struct radeon_device *rdev);
2251 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2252 extern void radeon_update_display_priority(struct radeon_device *rdev);
2253 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2254 extern void radeon_scratch_init(struct radeon_device *rdev);
2255 extern void radeon_wb_fini(struct radeon_device *rdev);
2256 extern int radeon_wb_init(struct radeon_device *rdev);
2257 extern void radeon_wb_disable(struct radeon_device *rdev);
2258 extern void radeon_surface_init(struct radeon_device *rdev);
2259 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2260 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2261 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2262 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2263 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2264 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2265 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2266 extern int radeon_resume_kms(struct drm_device *dev);
2267 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2268 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2269 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2270 const u32 *registers,
2271 const u32 array_size);
2272
2273 /*
2274 * vm
2275 */
2276 int radeon_vm_manager_init(struct radeon_device *rdev);
2277 void radeon_vm_manager_fini(struct radeon_device *rdev);
2278 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2279 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2280 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2281 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2282 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2283 struct radeon_vm *vm, int ring);
2284 void radeon_vm_fence(struct radeon_device *rdev,
2285 struct radeon_vm *vm,
2286 struct radeon_fence *fence);
2287 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2288 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2289 struct radeon_vm *vm,
2290 struct radeon_bo *bo,
2291 struct ttm_mem_reg *mem);
2292 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2293 struct radeon_bo *bo);
2294 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2295 struct radeon_bo *bo);
2296 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2297 struct radeon_vm *vm,
2298 struct radeon_bo *bo);
2299 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2300 struct radeon_bo_va *bo_va,
2301 uint64_t offset,
2302 uint32_t flags);
2303 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2304 struct radeon_bo_va *bo_va);
2305
2306 /* audio */
2307 void r600_audio_update_hdmi(struct work_struct *work);
2308
2309 /*
2310 * R600 vram scratch functions
2311 */
2312 int r600_vram_scratch_init(struct radeon_device *rdev);
2313 void r600_vram_scratch_fini(struct radeon_device *rdev);
2314
2315 /*
2316 * r600 cs checking helper
2317 */
2318 unsigned r600_mip_minify(unsigned size, unsigned level);
2319 bool r600_fmt_is_valid_color(u32 format);
2320 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2321 int r600_fmt_get_blocksize(u32 format);
2322 int r600_fmt_get_nblocksx(u32 format, u32 w);
2323 int r600_fmt_get_nblocksy(u32 format, u32 h);
2324
2325 /*
2326 * r600 functions used by radeon_encoder.c
2327 */
2328 struct radeon_hdmi_acr {
2329 u32 clock;
2330
2331 int n_32khz;
2332 int cts_32khz;
2333
2334 int n_44_1khz;
2335 int cts_44_1khz;
2336
2337 int n_48khz;
2338 int cts_48khz;
2339
2340 };
2341
2342 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2343
2344 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2345 u32 tiling_pipe_num,
2346 u32 max_rb_num,
2347 u32 total_max_rb_num,
2348 u32 enabled_rb_mask);
2349
2350 /*
2351 * evergreen functions used by radeon_encoder.c
2352 */
2353
2354 extern int ni_init_microcode(struct radeon_device *rdev);
2355 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2356
2357 /* radeon_acpi.c */
2358 #if defined(CONFIG_ACPI)
2359 extern int radeon_acpi_init(struct radeon_device *rdev);
2360 extern void radeon_acpi_fini(struct radeon_device *rdev);
2361 #else
2362 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2363 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2364 #endif
2365
2366 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2367 struct radeon_cs_packet *pkt,
2368 unsigned idx);
2369 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2370 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2371 struct radeon_cs_packet *pkt);
2372 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2373 struct radeon_cs_reloc **cs_reloc,
2374 int nomm);
2375 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2376 uint32_t *vline_start_end,
2377 uint32_t *vline_status);
2378
2379 #include "radeon_object.h"
2380
2381 #endif
Linux kernel - Deliverables
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