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drm/radeon: Use direct mapping for fast fb access on RS690
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99
100 /*
101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 * symbol;
103 */
104 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
105 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
106 /* RADEON_IB_POOL_SIZE must be a power of 2 */
107 #define RADEON_IB_POOL_SIZE 16
108 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
109 #define RADEONFB_CONN_LIMIT 4
110 #define RADEON_BIOS_NUM_SCRATCH 8
111
112 /* max number of rings */
113 #define RADEON_NUM_RINGS 5
114
115 /* fence seq are set to this number when signaled */
116 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117
118 /* internal ring indices */
119 /* r1xx+ has gfx CP ring */
120 #define RADEON_RING_TYPE_GFX_INDEX 0
121
122 /* cayman has 2 compute CP rings */
123 #define CAYMAN_RING_TYPE_CP1_INDEX 1
124 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125
126 /* R600+ has an async dma ring */
127 #define R600_RING_TYPE_DMA_INDEX 3
128 /* cayman add a second async dma ring */
129 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
130
131 /* hardcode those limit for now */
132 #define RADEON_VA_IB_OFFSET (1 << 20)
133 #define RADEON_VA_RESERVED_SIZE (8 << 20)
134 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
135
136 /* reset flags */
137 #define RADEON_RESET_GFX (1 << 0)
138 #define RADEON_RESET_COMPUTE (1 << 1)
139 #define RADEON_RESET_DMA (1 << 2)
140 #define RADEON_RESET_CP (1 << 3)
141 #define RADEON_RESET_GRBM (1 << 4)
142 #define RADEON_RESET_DMA1 (1 << 5)
143 #define RADEON_RESET_RLC (1 << 6)
144 #define RADEON_RESET_SEM (1 << 7)
145 #define RADEON_RESET_IH (1 << 8)
146 #define RADEON_RESET_VMC (1 << 9)
147 #define RADEON_RESET_MC (1 << 10)
148 #define RADEON_RESET_DISPLAY (1 << 11)
149
150 /*
151 * Errata workarounds.
152 */
153 enum radeon_pll_errata {
154 CHIP_ERRATA_R300_CG = 0x00000001,
155 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
156 CHIP_ERRATA_PLL_DELAY = 0x00000004
157 };
158
159
160 struct radeon_device;
161
162
163 /*
164 * BIOS.
165 */
166 bool radeon_get_bios(struct radeon_device *rdev);
167
168 /*
169 * Dummy page
170 */
171 struct radeon_dummy_page {
172 struct page *page;
173 dma_addr_t addr;
174 };
175 int radeon_dummy_page_init(struct radeon_device *rdev);
176 void radeon_dummy_page_fini(struct radeon_device *rdev);
177
178
179 /*
180 * Clocks
181 */
182 struct radeon_clock {
183 struct radeon_pll p1pll;
184 struct radeon_pll p2pll;
185 struct radeon_pll dcpll;
186 struct radeon_pll spll;
187 struct radeon_pll mpll;
188 /* 10 Khz units */
189 uint32_t default_mclk;
190 uint32_t default_sclk;
191 uint32_t default_dispclk;
192 uint32_t dp_extclk;
193 uint32_t max_pixel_clock;
194 };
195
196 /*
197 * Power management
198 */
199 int radeon_pm_init(struct radeon_device *rdev);
200 void radeon_pm_fini(struct radeon_device *rdev);
201 void radeon_pm_compute_clocks(struct radeon_device *rdev);
202 void radeon_pm_suspend(struct radeon_device *rdev);
203 void radeon_pm_resume(struct radeon_device *rdev);
204 void radeon_combios_get_power_modes(struct radeon_device *rdev);
205 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
206 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
207 void rs690_pm_info(struct radeon_device *rdev);
208 extern int rv6xx_get_temp(struct radeon_device *rdev);
209 extern int rv770_get_temp(struct radeon_device *rdev);
210 extern int evergreen_get_temp(struct radeon_device *rdev);
211 extern int sumo_get_temp(struct radeon_device *rdev);
212 extern int si_get_temp(struct radeon_device *rdev);
213 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
214 unsigned *bankh, unsigned *mtaspect,
215 unsigned *tile_split);
216
217 /*
218 * Fences.
219 */
220 struct radeon_fence_driver {
221 uint32_t scratch_reg;
222 uint64_t gpu_addr;
223 volatile uint32_t *cpu_addr;
224 /* sync_seq is protected by ring emission lock */
225 uint64_t sync_seq[RADEON_NUM_RINGS];
226 atomic64_t last_seq;
227 unsigned long last_activity;
228 bool initialized;
229 };
230
231 struct radeon_fence {
232 struct radeon_device *rdev;
233 struct kref kref;
234 /* protected by radeon_fence.lock */
235 uint64_t seq;
236 /* RB, DMA, etc. */
237 unsigned ring;
238 };
239
240 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
241 int radeon_fence_driver_init(struct radeon_device *rdev);
242 void radeon_fence_driver_fini(struct radeon_device *rdev);
243 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
244 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
245 void radeon_fence_process(struct radeon_device *rdev, int ring);
246 bool radeon_fence_signaled(struct radeon_fence *fence);
247 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
248 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
249 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
250 int radeon_fence_wait_any(struct radeon_device *rdev,
251 struct radeon_fence **fences,
252 bool intr);
253 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
254 void radeon_fence_unref(struct radeon_fence **fence);
255 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
256 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
257 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
258 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
259 struct radeon_fence *b)
260 {
261 if (!a) {
262 return b;
263 }
264
265 if (!b) {
266 return a;
267 }
268
269 BUG_ON(a->ring != b->ring);
270
271 if (a->seq > b->seq) {
272 return a;
273 } else {
274 return b;
275 }
276 }
277
278 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
279 struct radeon_fence *b)
280 {
281 if (!a) {
282 return false;
283 }
284
285 if (!b) {
286 return true;
287 }
288
289 BUG_ON(a->ring != b->ring);
290
291 return a->seq < b->seq;
292 }
293
294 /*
295 * Tiling registers
296 */
297 struct radeon_surface_reg {
298 struct radeon_bo *bo;
299 };
300
301 #define RADEON_GEM_MAX_SURFACES 8
302
303 /*
304 * TTM.
305 */
306 struct radeon_mman {
307 struct ttm_bo_global_ref bo_global_ref;
308 struct drm_global_reference mem_global_ref;
309 struct ttm_bo_device bdev;
310 bool mem_global_referenced;
311 bool initialized;
312 };
313
314 /* bo virtual address in a specific vm */
315 struct radeon_bo_va {
316 /* protected by bo being reserved */
317 struct list_head bo_list;
318 uint64_t soffset;
319 uint64_t eoffset;
320 uint32_t flags;
321 bool valid;
322 unsigned ref_count;
323
324 /* protected by vm mutex */
325 struct list_head vm_list;
326
327 /* constant after initialization */
328 struct radeon_vm *vm;
329 struct radeon_bo *bo;
330 };
331
332 struct radeon_bo {
333 /* Protected by gem.mutex */
334 struct list_head list;
335 /* Protected by tbo.reserved */
336 u32 placements[3];
337 struct ttm_placement placement;
338 struct ttm_buffer_object tbo;
339 struct ttm_bo_kmap_obj kmap;
340 unsigned pin_count;
341 void *kptr;
342 u32 tiling_flags;
343 u32 pitch;
344 int surface_reg;
345 /* list of all virtual address to which this bo
346 * is associated to
347 */
348 struct list_head va;
349 /* Constant after initialization */
350 struct radeon_device *rdev;
351 struct drm_gem_object gem_base;
352
353 struct ttm_bo_kmap_obj dma_buf_vmap;
354 };
355 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
356
357 struct radeon_bo_list {
358 struct ttm_validate_buffer tv;
359 struct radeon_bo *bo;
360 uint64_t gpu_offset;
361 unsigned rdomain;
362 unsigned wdomain;
363 u32 tiling_flags;
364 };
365
366 /* sub-allocation manager, it has to be protected by another lock.
367 * By conception this is an helper for other part of the driver
368 * like the indirect buffer or semaphore, which both have their
369 * locking.
370 *
371 * Principe is simple, we keep a list of sub allocation in offset
372 * order (first entry has offset == 0, last entry has the highest
373 * offset).
374 *
375 * When allocating new object we first check if there is room at
376 * the end total_size - (last_object_offset + last_object_size) >=
377 * alloc_size. If so we allocate new object there.
378 *
379 * When there is not enough room at the end, we start waiting for
380 * each sub object until we reach object_offset+object_size >=
381 * alloc_size, this object then become the sub object we return.
382 *
383 * Alignment can't be bigger than page size.
384 *
385 * Hole are not considered for allocation to keep things simple.
386 * Assumption is that there won't be hole (all object on same
387 * alignment).
388 */
389 struct radeon_sa_manager {
390 wait_queue_head_t wq;
391 struct radeon_bo *bo;
392 struct list_head *hole;
393 struct list_head flist[RADEON_NUM_RINGS];
394 struct list_head olist;
395 unsigned size;
396 uint64_t gpu_addr;
397 void *cpu_ptr;
398 uint32_t domain;
399 };
400
401 struct radeon_sa_bo;
402
403 /* sub-allocation buffer */
404 struct radeon_sa_bo {
405 struct list_head olist;
406 struct list_head flist;
407 struct radeon_sa_manager *manager;
408 unsigned soffset;
409 unsigned eoffset;
410 struct radeon_fence *fence;
411 };
412
413 /*
414 * GEM objects.
415 */
416 struct radeon_gem {
417 struct mutex mutex;
418 struct list_head objects;
419 };
420
421 int radeon_gem_init(struct radeon_device *rdev);
422 void radeon_gem_fini(struct radeon_device *rdev);
423 int radeon_gem_object_create(struct radeon_device *rdev, int size,
424 int alignment, int initial_domain,
425 bool discardable, bool kernel,
426 struct drm_gem_object **obj);
427
428 int radeon_mode_dumb_create(struct drm_file *file_priv,
429 struct drm_device *dev,
430 struct drm_mode_create_dumb *args);
431 int radeon_mode_dumb_mmap(struct drm_file *filp,
432 struct drm_device *dev,
433 uint32_t handle, uint64_t *offset_p);
434 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
435 struct drm_device *dev,
436 uint32_t handle);
437
438 /*
439 * Semaphores.
440 */
441 /* everything here is constant */
442 struct radeon_semaphore {
443 struct radeon_sa_bo *sa_bo;
444 signed waiters;
445 uint64_t gpu_addr;
446 };
447
448 int radeon_semaphore_create(struct radeon_device *rdev,
449 struct radeon_semaphore **semaphore);
450 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
451 struct radeon_semaphore *semaphore);
452 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
453 struct radeon_semaphore *semaphore);
454 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
455 struct radeon_semaphore *semaphore,
456 int signaler, int waiter);
457 void radeon_semaphore_free(struct radeon_device *rdev,
458 struct radeon_semaphore **semaphore,
459 struct radeon_fence *fence);
460
461 /*
462 * GART structures, functions & helpers
463 */
464 struct radeon_mc;
465
466 #define RADEON_GPU_PAGE_SIZE 4096
467 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
468 #define RADEON_GPU_PAGE_SHIFT 12
469 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
470
471 struct radeon_gart {
472 dma_addr_t table_addr;
473 struct radeon_bo *robj;
474 void *ptr;
475 unsigned num_gpu_pages;
476 unsigned num_cpu_pages;
477 unsigned table_size;
478 struct page **pages;
479 dma_addr_t *pages_addr;
480 bool ready;
481 };
482
483 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
484 void radeon_gart_table_ram_free(struct radeon_device *rdev);
485 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
486 void radeon_gart_table_vram_free(struct radeon_device *rdev);
487 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
488 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
489 int radeon_gart_init(struct radeon_device *rdev);
490 void radeon_gart_fini(struct radeon_device *rdev);
491 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
492 int pages);
493 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
494 int pages, struct page **pagelist,
495 dma_addr_t *dma_addr);
496 void radeon_gart_restore(struct radeon_device *rdev);
497
498
499 /*
500 * GPU MC structures, functions & helpers
501 */
502 struct radeon_mc {
503 resource_size_t aper_size;
504 resource_size_t aper_base;
505 resource_size_t agp_base;
506 /* for some chips with <= 32MB we need to lie
507 * about vram size near mc fb location */
508 u64 mc_vram_size;
509 u64 visible_vram_size;
510 u64 gtt_size;
511 u64 gtt_start;
512 u64 gtt_end;
513 u64 vram_start;
514 u64 vram_end;
515 unsigned vram_width;
516 u64 real_vram_size;
517 int vram_mtrr;
518 bool vram_is_ddr;
519 bool igp_sideport_enabled;
520 u64 gtt_base_align;
521 u64 mc_mask;
522 };
523
524 bool radeon_combios_sideport_present(struct radeon_device *rdev);
525 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
526
527 /*
528 * GPU scratch registers structures, functions & helpers
529 */
530 struct radeon_scratch {
531 unsigned num_reg;
532 uint32_t reg_base;
533 bool free[32];
534 uint32_t reg[32];
535 };
536
537 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
538 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
539
540
541 /*
542 * IRQS.
543 */
544
545 struct radeon_unpin_work {
546 struct work_struct work;
547 struct radeon_device *rdev;
548 int crtc_id;
549 struct radeon_fence *fence;
550 struct drm_pending_vblank_event *event;
551 struct radeon_bo *old_rbo;
552 u64 new_crtc_base;
553 };
554
555 struct r500_irq_stat_regs {
556 u32 disp_int;
557 u32 hdmi0_status;
558 };
559
560 struct r600_irq_stat_regs {
561 u32 disp_int;
562 u32 disp_int_cont;
563 u32 disp_int_cont2;
564 u32 d1grph_int;
565 u32 d2grph_int;
566 u32 hdmi0_status;
567 u32 hdmi1_status;
568 };
569
570 struct evergreen_irq_stat_regs {
571 u32 disp_int;
572 u32 disp_int_cont;
573 u32 disp_int_cont2;
574 u32 disp_int_cont3;
575 u32 disp_int_cont4;
576 u32 disp_int_cont5;
577 u32 d1grph_int;
578 u32 d2grph_int;
579 u32 d3grph_int;
580 u32 d4grph_int;
581 u32 d5grph_int;
582 u32 d6grph_int;
583 u32 afmt_status1;
584 u32 afmt_status2;
585 u32 afmt_status3;
586 u32 afmt_status4;
587 u32 afmt_status5;
588 u32 afmt_status6;
589 };
590
591 union radeon_irq_stat_regs {
592 struct r500_irq_stat_regs r500;
593 struct r600_irq_stat_regs r600;
594 struct evergreen_irq_stat_regs evergreen;
595 };
596
597 #define RADEON_MAX_HPD_PINS 6
598 #define RADEON_MAX_CRTCS 6
599 #define RADEON_MAX_AFMT_BLOCKS 6
600
601 struct radeon_irq {
602 bool installed;
603 spinlock_t lock;
604 atomic_t ring_int[RADEON_NUM_RINGS];
605 bool crtc_vblank_int[RADEON_MAX_CRTCS];
606 atomic_t pflip[RADEON_MAX_CRTCS];
607 wait_queue_head_t vblank_queue;
608 bool hpd[RADEON_MAX_HPD_PINS];
609 bool afmt[RADEON_MAX_AFMT_BLOCKS];
610 union radeon_irq_stat_regs stat_regs;
611 };
612
613 int radeon_irq_kms_init(struct radeon_device *rdev);
614 void radeon_irq_kms_fini(struct radeon_device *rdev);
615 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
616 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
617 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
618 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
619 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
620 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
621 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
622 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
623
624 /*
625 * CP & rings.
626 */
627
628 struct radeon_ib {
629 struct radeon_sa_bo *sa_bo;
630 uint32_t length_dw;
631 uint64_t gpu_addr;
632 uint32_t *ptr;
633 int ring;
634 struct radeon_fence *fence;
635 struct radeon_vm *vm;
636 bool is_const_ib;
637 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
638 struct radeon_semaphore *semaphore;
639 };
640
641 struct radeon_ring {
642 struct radeon_bo *ring_obj;
643 volatile uint32_t *ring;
644 unsigned rptr;
645 unsigned rptr_offs;
646 unsigned rptr_reg;
647 unsigned rptr_save_reg;
648 u64 next_rptr_gpu_addr;
649 volatile u32 *next_rptr_cpu_addr;
650 unsigned wptr;
651 unsigned wptr_old;
652 unsigned wptr_reg;
653 unsigned ring_size;
654 unsigned ring_free_dw;
655 int count_dw;
656 unsigned long last_activity;
657 unsigned last_rptr;
658 uint64_t gpu_addr;
659 uint32_t align_mask;
660 uint32_t ptr_mask;
661 bool ready;
662 u32 ptr_reg_shift;
663 u32 ptr_reg_mask;
664 u32 nop;
665 u32 idx;
666 u64 last_semaphore_signal_addr;
667 u64 last_semaphore_wait_addr;
668 };
669
670 /*
671 * VM
672 */
673
674 /* maximum number of VMIDs */
675 #define RADEON_NUM_VM 16
676
677 /* defines number of bits in page table versus page directory,
678 * a page is 4KB so we have 12 bits offset, 9 bits in the page
679 * table and the remaining 19 bits are in the page directory */
680 #define RADEON_VM_BLOCK_SIZE 9
681
682 /* number of entries in page table */
683 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
684
685 struct radeon_vm {
686 struct list_head list;
687 struct list_head va;
688 unsigned id;
689
690 /* contains the page directory */
691 struct radeon_sa_bo *page_directory;
692 uint64_t pd_gpu_addr;
693
694 /* array of page tables, one for each page directory entry */
695 struct radeon_sa_bo **page_tables;
696
697 struct mutex mutex;
698 /* last fence for cs using this vm */
699 struct radeon_fence *fence;
700 /* last flush or NULL if we still need to flush */
701 struct radeon_fence *last_flush;
702 };
703
704 struct radeon_vm_manager {
705 struct mutex lock;
706 struct list_head lru_vm;
707 struct radeon_fence *active[RADEON_NUM_VM];
708 struct radeon_sa_manager sa_manager;
709 uint32_t max_pfn;
710 /* number of VMIDs */
711 unsigned nvm;
712 /* vram base address for page table entry */
713 u64 vram_base_offset;
714 /* is vm enabled? */
715 bool enabled;
716 };
717
718 /*
719 * file private structure
720 */
721 struct radeon_fpriv {
722 struct radeon_vm vm;
723 };
724
725 /*
726 * R6xx+ IH ring
727 */
728 struct r600_ih {
729 struct radeon_bo *ring_obj;
730 volatile uint32_t *ring;
731 unsigned rptr;
732 unsigned ring_size;
733 uint64_t gpu_addr;
734 uint32_t ptr_mask;
735 atomic_t lock;
736 bool enabled;
737 };
738
739 struct r600_blit_cp_primitives {
740 void (*set_render_target)(struct radeon_device *rdev, int format,
741 int w, int h, u64 gpu_addr);
742 void (*cp_set_surface_sync)(struct radeon_device *rdev,
743 u32 sync_type, u32 size,
744 u64 mc_addr);
745 void (*set_shaders)(struct radeon_device *rdev);
746 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
747 void (*set_tex_resource)(struct radeon_device *rdev,
748 int format, int w, int h, int pitch,
749 u64 gpu_addr, u32 size);
750 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
751 int x2, int y2);
752 void (*draw_auto)(struct radeon_device *rdev);
753 void (*set_default_state)(struct radeon_device *rdev);
754 };
755
756 struct r600_blit {
757 struct radeon_bo *shader_obj;
758 struct r600_blit_cp_primitives primitives;
759 int max_dim;
760 int ring_size_common;
761 int ring_size_per_loop;
762 u64 shader_gpu_addr;
763 u32 vs_offset, ps_offset;
764 u32 state_offset;
765 u32 state_len;
766 };
767
768 /*
769 * SI RLC stuff
770 */
771 struct si_rlc {
772 /* for power gating */
773 struct radeon_bo *save_restore_obj;
774 uint64_t save_restore_gpu_addr;
775 /* for clear state */
776 struct radeon_bo *clear_state_obj;
777 uint64_t clear_state_gpu_addr;
778 };
779
780 int radeon_ib_get(struct radeon_device *rdev, int ring,
781 struct radeon_ib *ib, struct radeon_vm *vm,
782 unsigned size);
783 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
784 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
785 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
786 struct radeon_ib *const_ib);
787 int radeon_ib_pool_init(struct radeon_device *rdev);
788 void radeon_ib_pool_fini(struct radeon_device *rdev);
789 int radeon_ib_ring_tests(struct radeon_device *rdev);
790 /* Ring access between begin & end cannot sleep */
791 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
792 struct radeon_ring *ring);
793 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
794 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
795 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
796 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
797 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
798 void radeon_ring_undo(struct radeon_ring *ring);
799 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
800 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
801 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
802 void radeon_ring_lockup_update(struct radeon_ring *ring);
803 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
804 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
805 uint32_t **data);
806 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
807 unsigned size, uint32_t *data);
808 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
809 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
810 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
811 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
812
813
814 /* r600 async dma */
815 void r600_dma_stop(struct radeon_device *rdev);
816 int r600_dma_resume(struct radeon_device *rdev);
817 void r600_dma_fini(struct radeon_device *rdev);
818
819 void cayman_dma_stop(struct radeon_device *rdev);
820 int cayman_dma_resume(struct radeon_device *rdev);
821 void cayman_dma_fini(struct radeon_device *rdev);
822
823 /*
824 * CS.
825 */
826 struct radeon_cs_reloc {
827 struct drm_gem_object *gobj;
828 struct radeon_bo *robj;
829 struct radeon_bo_list lobj;
830 uint32_t handle;
831 uint32_t flags;
832 };
833
834 struct radeon_cs_chunk {
835 uint32_t chunk_id;
836 uint32_t length_dw;
837 int kpage_idx[2];
838 uint32_t *kpage[2];
839 uint32_t *kdata;
840 void __user *user_ptr;
841 int last_copied_page;
842 int last_page_index;
843 };
844
845 struct radeon_cs_parser {
846 struct device *dev;
847 struct radeon_device *rdev;
848 struct drm_file *filp;
849 /* chunks */
850 unsigned nchunks;
851 struct radeon_cs_chunk *chunks;
852 uint64_t *chunks_array;
853 /* IB */
854 unsigned idx;
855 /* relocations */
856 unsigned nrelocs;
857 struct radeon_cs_reloc *relocs;
858 struct radeon_cs_reloc **relocs_ptr;
859 struct list_head validated;
860 unsigned dma_reloc_idx;
861 /* indices of various chunks */
862 int chunk_ib_idx;
863 int chunk_relocs_idx;
864 int chunk_flags_idx;
865 int chunk_const_ib_idx;
866 struct radeon_ib ib;
867 struct radeon_ib const_ib;
868 void *track;
869 unsigned family;
870 int parser_error;
871 u32 cs_flags;
872 u32 ring;
873 s32 priority;
874 };
875
876 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
877 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
878
879 struct radeon_cs_packet {
880 unsigned idx;
881 unsigned type;
882 unsigned reg;
883 unsigned opcode;
884 int count;
885 unsigned one_reg_wr;
886 };
887
888 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
889 struct radeon_cs_packet *pkt,
890 unsigned idx, unsigned reg);
891 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
892 struct radeon_cs_packet *pkt);
893
894
895 /*
896 * AGP
897 */
898 int radeon_agp_init(struct radeon_device *rdev);
899 void radeon_agp_resume(struct radeon_device *rdev);
900 void radeon_agp_suspend(struct radeon_device *rdev);
901 void radeon_agp_fini(struct radeon_device *rdev);
902
903
904 /*
905 * Writeback
906 */
907 struct radeon_wb {
908 struct radeon_bo *wb_obj;
909 volatile uint32_t *wb;
910 uint64_t gpu_addr;
911 bool enabled;
912 bool use_event;
913 };
914
915 #define RADEON_WB_SCRATCH_OFFSET 0
916 #define RADEON_WB_RING0_NEXT_RPTR 256
917 #define RADEON_WB_CP_RPTR_OFFSET 1024
918 #define RADEON_WB_CP1_RPTR_OFFSET 1280
919 #define RADEON_WB_CP2_RPTR_OFFSET 1536
920 #define R600_WB_DMA_RPTR_OFFSET 1792
921 #define R600_WB_IH_WPTR_OFFSET 2048
922 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
923 #define R600_WB_EVENT_OFFSET 3072
924
925 /**
926 * struct radeon_pm - power management datas
927 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
928 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
929 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
930 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
931 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
932 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
933 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
934 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
935 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
936 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
937 * @needed_bandwidth: current bandwidth needs
938 *
939 * It keeps track of various data needed to take powermanagement decision.
940 * Bandwidth need is used to determine minimun clock of the GPU and memory.
941 * Equation between gpu/memory clock and available bandwidth is hw dependent
942 * (type of memory, bus size, efficiency, ...)
943 */
944
945 enum radeon_pm_method {
946 PM_METHOD_PROFILE,
947 PM_METHOD_DYNPM,
948 };
949
950 enum radeon_dynpm_state {
951 DYNPM_STATE_DISABLED,
952 DYNPM_STATE_MINIMUM,
953 DYNPM_STATE_PAUSED,
954 DYNPM_STATE_ACTIVE,
955 DYNPM_STATE_SUSPENDED,
956 };
957 enum radeon_dynpm_action {
958 DYNPM_ACTION_NONE,
959 DYNPM_ACTION_MINIMUM,
960 DYNPM_ACTION_DOWNCLOCK,
961 DYNPM_ACTION_UPCLOCK,
962 DYNPM_ACTION_DEFAULT
963 };
964
965 enum radeon_voltage_type {
966 VOLTAGE_NONE = 0,
967 VOLTAGE_GPIO,
968 VOLTAGE_VDDC,
969 VOLTAGE_SW
970 };
971
972 enum radeon_pm_state_type {
973 POWER_STATE_TYPE_DEFAULT,
974 POWER_STATE_TYPE_POWERSAVE,
975 POWER_STATE_TYPE_BATTERY,
976 POWER_STATE_TYPE_BALANCED,
977 POWER_STATE_TYPE_PERFORMANCE,
978 };
979
980 enum radeon_pm_profile_type {
981 PM_PROFILE_DEFAULT,
982 PM_PROFILE_AUTO,
983 PM_PROFILE_LOW,
984 PM_PROFILE_MID,
985 PM_PROFILE_HIGH,
986 };
987
988 #define PM_PROFILE_DEFAULT_IDX 0
989 #define PM_PROFILE_LOW_SH_IDX 1
990 #define PM_PROFILE_MID_SH_IDX 2
991 #define PM_PROFILE_HIGH_SH_IDX 3
992 #define PM_PROFILE_LOW_MH_IDX 4
993 #define PM_PROFILE_MID_MH_IDX 5
994 #define PM_PROFILE_HIGH_MH_IDX 6
995 #define PM_PROFILE_MAX 7
996
997 struct radeon_pm_profile {
998 int dpms_off_ps_idx;
999 int dpms_on_ps_idx;
1000 int dpms_off_cm_idx;
1001 int dpms_on_cm_idx;
1002 };
1003
1004 enum radeon_int_thermal_type {
1005 THERMAL_TYPE_NONE,
1006 THERMAL_TYPE_RV6XX,
1007 THERMAL_TYPE_RV770,
1008 THERMAL_TYPE_EVERGREEN,
1009 THERMAL_TYPE_SUMO,
1010 THERMAL_TYPE_NI,
1011 THERMAL_TYPE_SI,
1012 };
1013
1014 struct radeon_voltage {
1015 enum radeon_voltage_type type;
1016 /* gpio voltage */
1017 struct radeon_gpio_rec gpio;
1018 u32 delay; /* delay in usec from voltage drop to sclk change */
1019 bool active_high; /* voltage drop is active when bit is high */
1020 /* VDDC voltage */
1021 u8 vddc_id; /* index into vddc voltage table */
1022 u8 vddci_id; /* index into vddci voltage table */
1023 bool vddci_enabled;
1024 /* r6xx+ sw */
1025 u16 voltage;
1026 /* evergreen+ vddci */
1027 u16 vddci;
1028 };
1029
1030 /* clock mode flags */
1031 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1032
1033 struct radeon_pm_clock_info {
1034 /* memory clock */
1035 u32 mclk;
1036 /* engine clock */
1037 u32 sclk;
1038 /* voltage info */
1039 struct radeon_voltage voltage;
1040 /* standardized clock flags */
1041 u32 flags;
1042 };
1043
1044 /* state flags */
1045 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1046
1047 struct radeon_power_state {
1048 enum radeon_pm_state_type type;
1049 struct radeon_pm_clock_info *clock_info;
1050 /* number of valid clock modes in this power state */
1051 int num_clock_modes;
1052 struct radeon_pm_clock_info *default_clock_mode;
1053 /* standardized state flags */
1054 u32 flags;
1055 u32 misc; /* vbios specific flags */
1056 u32 misc2; /* vbios specific flags */
1057 int pcie_lanes; /* pcie lanes */
1058 };
1059
1060 /*
1061 * Some modes are overclocked by very low value, accept them
1062 */
1063 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1064
1065 struct radeon_pm {
1066 struct mutex mutex;
1067 /* write locked while reprogramming mclk */
1068 struct rw_semaphore mclk_lock;
1069 u32 active_crtcs;
1070 int active_crtc_count;
1071 int req_vblank;
1072 bool vblank_sync;
1073 fixed20_12 max_bandwidth;
1074 fixed20_12 igp_sideport_mclk;
1075 fixed20_12 igp_system_mclk;
1076 fixed20_12 igp_ht_link_clk;
1077 fixed20_12 igp_ht_link_width;
1078 fixed20_12 k8_bandwidth;
1079 fixed20_12 sideport_bandwidth;
1080 fixed20_12 ht_bandwidth;
1081 fixed20_12 core_bandwidth;
1082 fixed20_12 sclk;
1083 fixed20_12 mclk;
1084 fixed20_12 needed_bandwidth;
1085 struct radeon_power_state *power_state;
1086 /* number of valid power states */
1087 int num_power_states;
1088 int current_power_state_index;
1089 int current_clock_mode_index;
1090 int requested_power_state_index;
1091 int requested_clock_mode_index;
1092 int default_power_state_index;
1093 u32 current_sclk;
1094 u32 current_mclk;
1095 u16 current_vddc;
1096 u16 current_vddci;
1097 u32 default_sclk;
1098 u32 default_mclk;
1099 u16 default_vddc;
1100 u16 default_vddci;
1101 struct radeon_i2c_chan *i2c_bus;
1102 /* selected pm method */
1103 enum radeon_pm_method pm_method;
1104 /* dynpm power management */
1105 struct delayed_work dynpm_idle_work;
1106 enum radeon_dynpm_state dynpm_state;
1107 enum radeon_dynpm_action dynpm_planned_action;
1108 unsigned long dynpm_action_timeout;
1109 bool dynpm_can_upclock;
1110 bool dynpm_can_downclock;
1111 /* profile-based power management */
1112 enum radeon_pm_profile_type profile;
1113 int profile_index;
1114 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1115 /* internal thermal controller on rv6xx+ */
1116 enum radeon_int_thermal_type int_thermal_type;
1117 struct device *int_hwmon_dev;
1118 };
1119
1120 int radeon_pm_get_type_index(struct radeon_device *rdev,
1121 enum radeon_pm_state_type ps_type,
1122 int instance);
1123
1124 struct r600_audio {
1125 int channels;
1126 int rate;
1127 int bits_per_sample;
1128 u8 status_bits;
1129 u8 category_code;
1130 };
1131
1132 /*
1133 * Benchmarking
1134 */
1135 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1136
1137
1138 /*
1139 * Testing
1140 */
1141 void radeon_test_moves(struct radeon_device *rdev);
1142 void radeon_test_ring_sync(struct radeon_device *rdev,
1143 struct radeon_ring *cpA,
1144 struct radeon_ring *cpB);
1145 void radeon_test_syncing(struct radeon_device *rdev);
1146
1147
1148 /*
1149 * Debugfs
1150 */
1151 struct radeon_debugfs {
1152 struct drm_info_list *files;
1153 unsigned num_files;
1154 };
1155
1156 int radeon_debugfs_add_files(struct radeon_device *rdev,
1157 struct drm_info_list *files,
1158 unsigned nfiles);
1159 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1160
1161
1162 /*
1163 * ASIC specific functions.
1164 */
1165 struct radeon_asic {
1166 int (*init)(struct radeon_device *rdev);
1167 void (*fini)(struct radeon_device *rdev);
1168 int (*resume)(struct radeon_device *rdev);
1169 int (*suspend)(struct radeon_device *rdev);
1170 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1171 int (*asic_reset)(struct radeon_device *rdev);
1172 /* ioctl hw specific callback. Some hw might want to perform special
1173 * operation on specific ioctl. For instance on wait idle some hw
1174 * might want to perform and HDP flush through MMIO as it seems that
1175 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1176 * through ring.
1177 */
1178 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1179 /* check if 3D engine is idle */
1180 bool (*gui_idle)(struct radeon_device *rdev);
1181 /* wait for mc_idle */
1182 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1183 /* get the reference clock */
1184 u32 (*get_xclk)(struct radeon_device *rdev);
1185 /* get the gpu clock counter */
1186 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1187 /* gart */
1188 struct {
1189 void (*tlb_flush)(struct radeon_device *rdev);
1190 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1191 } gart;
1192 struct {
1193 int (*init)(struct radeon_device *rdev);
1194 void (*fini)(struct radeon_device *rdev);
1195
1196 u32 pt_ring_index;
1197 void (*set_page)(struct radeon_device *rdev,
1198 struct radeon_ib *ib,
1199 uint64_t pe,
1200 uint64_t addr, unsigned count,
1201 uint32_t incr, uint32_t flags);
1202 } vm;
1203 /* ring specific callbacks */
1204 struct {
1205 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1206 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1207 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1208 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1209 struct radeon_semaphore *semaphore, bool emit_wait);
1210 int (*cs_parse)(struct radeon_cs_parser *p);
1211 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1212 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1213 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1214 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1215 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1216 } ring[RADEON_NUM_RINGS];
1217 /* irqs */
1218 struct {
1219 int (*set)(struct radeon_device *rdev);
1220 int (*process)(struct radeon_device *rdev);
1221 } irq;
1222 /* displays */
1223 struct {
1224 /* display watermarks */
1225 void (*bandwidth_update)(struct radeon_device *rdev);
1226 /* get frame count */
1227 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1228 /* wait for vblank */
1229 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1230 /* set backlight level */
1231 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1232 /* get backlight level */
1233 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1234 } display;
1235 /* copy functions for bo handling */
1236 struct {
1237 int (*blit)(struct radeon_device *rdev,
1238 uint64_t src_offset,
1239 uint64_t dst_offset,
1240 unsigned num_gpu_pages,
1241 struct radeon_fence **fence);
1242 u32 blit_ring_index;
1243 int (*dma)(struct radeon_device *rdev,
1244 uint64_t src_offset,
1245 uint64_t dst_offset,
1246 unsigned num_gpu_pages,
1247 struct radeon_fence **fence);
1248 u32 dma_ring_index;
1249 /* method used for bo copy */
1250 int (*copy)(struct radeon_device *rdev,
1251 uint64_t src_offset,
1252 uint64_t dst_offset,
1253 unsigned num_gpu_pages,
1254 struct radeon_fence **fence);
1255 /* ring used for bo copies */
1256 u32 copy_ring_index;
1257 } copy;
1258 /* surfaces */
1259 struct {
1260 int (*set_reg)(struct radeon_device *rdev, int reg,
1261 uint32_t tiling_flags, uint32_t pitch,
1262 uint32_t offset, uint32_t obj_size);
1263 void (*clear_reg)(struct radeon_device *rdev, int reg);
1264 } surface;
1265 /* hotplug detect */
1266 struct {
1267 void (*init)(struct radeon_device *rdev);
1268 void (*fini)(struct radeon_device *rdev);
1269 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1270 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1271 } hpd;
1272 /* power management */
1273 struct {
1274 void (*misc)(struct radeon_device *rdev);
1275 void (*prepare)(struct radeon_device *rdev);
1276 void (*finish)(struct radeon_device *rdev);
1277 void (*init_profile)(struct radeon_device *rdev);
1278 void (*get_dynpm_state)(struct radeon_device *rdev);
1279 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1280 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1281 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1282 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1283 int (*get_pcie_lanes)(struct radeon_device *rdev);
1284 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1285 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1286 } pm;
1287 /* pageflipping */
1288 struct {
1289 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1290 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1291 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1292 } pflip;
1293 };
1294
1295 /*
1296 * Asic structures
1297 */
1298 struct r100_asic {
1299 const unsigned *reg_safe_bm;
1300 unsigned reg_safe_bm_size;
1301 u32 hdp_cntl;
1302 };
1303
1304 struct r300_asic {
1305 const unsigned *reg_safe_bm;
1306 unsigned reg_safe_bm_size;
1307 u32 resync_scratch;
1308 u32 hdp_cntl;
1309 };
1310
1311 struct r600_asic {
1312 unsigned max_pipes;
1313 unsigned max_tile_pipes;
1314 unsigned max_simds;
1315 unsigned max_backends;
1316 unsigned max_gprs;
1317 unsigned max_threads;
1318 unsigned max_stack_entries;
1319 unsigned max_hw_contexts;
1320 unsigned max_gs_threads;
1321 unsigned sx_max_export_size;
1322 unsigned sx_max_export_pos_size;
1323 unsigned sx_max_export_smx_size;
1324 unsigned sq_num_cf_insts;
1325 unsigned tiling_nbanks;
1326 unsigned tiling_npipes;
1327 unsigned tiling_group_size;
1328 unsigned tile_config;
1329 unsigned backend_map;
1330 };
1331
1332 struct rv770_asic {
1333 unsigned max_pipes;
1334 unsigned max_tile_pipes;
1335 unsigned max_simds;
1336 unsigned max_backends;
1337 unsigned max_gprs;
1338 unsigned max_threads;
1339 unsigned max_stack_entries;
1340 unsigned max_hw_contexts;
1341 unsigned max_gs_threads;
1342 unsigned sx_max_export_size;
1343 unsigned sx_max_export_pos_size;
1344 unsigned sx_max_export_smx_size;
1345 unsigned sq_num_cf_insts;
1346 unsigned sx_num_of_sets;
1347 unsigned sc_prim_fifo_size;
1348 unsigned sc_hiz_tile_fifo_size;
1349 unsigned sc_earlyz_tile_fifo_fize;
1350 unsigned tiling_nbanks;
1351 unsigned tiling_npipes;
1352 unsigned tiling_group_size;
1353 unsigned tile_config;
1354 unsigned backend_map;
1355 };
1356
1357 struct evergreen_asic {
1358 unsigned num_ses;
1359 unsigned max_pipes;
1360 unsigned max_tile_pipes;
1361 unsigned max_simds;
1362 unsigned max_backends;
1363 unsigned max_gprs;
1364 unsigned max_threads;
1365 unsigned max_stack_entries;
1366 unsigned max_hw_contexts;
1367 unsigned max_gs_threads;
1368 unsigned sx_max_export_size;
1369 unsigned sx_max_export_pos_size;
1370 unsigned sx_max_export_smx_size;
1371 unsigned sq_num_cf_insts;
1372 unsigned sx_num_of_sets;
1373 unsigned sc_prim_fifo_size;
1374 unsigned sc_hiz_tile_fifo_size;
1375 unsigned sc_earlyz_tile_fifo_size;
1376 unsigned tiling_nbanks;
1377 unsigned tiling_npipes;
1378 unsigned tiling_group_size;
1379 unsigned tile_config;
1380 unsigned backend_map;
1381 };
1382
1383 struct cayman_asic {
1384 unsigned max_shader_engines;
1385 unsigned max_pipes_per_simd;
1386 unsigned max_tile_pipes;
1387 unsigned max_simds_per_se;
1388 unsigned max_backends_per_se;
1389 unsigned max_texture_channel_caches;
1390 unsigned max_gprs;
1391 unsigned max_threads;
1392 unsigned max_gs_threads;
1393 unsigned max_stack_entries;
1394 unsigned sx_num_of_sets;
1395 unsigned sx_max_export_size;
1396 unsigned sx_max_export_pos_size;
1397 unsigned sx_max_export_smx_size;
1398 unsigned max_hw_contexts;
1399 unsigned sq_num_cf_insts;
1400 unsigned sc_prim_fifo_size;
1401 unsigned sc_hiz_tile_fifo_size;
1402 unsigned sc_earlyz_tile_fifo_size;
1403
1404 unsigned num_shader_engines;
1405 unsigned num_shader_pipes_per_simd;
1406 unsigned num_tile_pipes;
1407 unsigned num_simds_per_se;
1408 unsigned num_backends_per_se;
1409 unsigned backend_disable_mask_per_asic;
1410 unsigned backend_map;
1411 unsigned num_texture_channel_caches;
1412 unsigned mem_max_burst_length_bytes;
1413 unsigned mem_row_size_in_kb;
1414 unsigned shader_engine_tile_size;
1415 unsigned num_gpus;
1416 unsigned multi_gpu_tile_size;
1417
1418 unsigned tile_config;
1419 };
1420
1421 struct si_asic {
1422 unsigned max_shader_engines;
1423 unsigned max_tile_pipes;
1424 unsigned max_cu_per_sh;
1425 unsigned max_sh_per_se;
1426 unsigned max_backends_per_se;
1427 unsigned max_texture_channel_caches;
1428 unsigned max_gprs;
1429 unsigned max_gs_threads;
1430 unsigned max_hw_contexts;
1431 unsigned sc_prim_fifo_size_frontend;
1432 unsigned sc_prim_fifo_size_backend;
1433 unsigned sc_hiz_tile_fifo_size;
1434 unsigned sc_earlyz_tile_fifo_size;
1435
1436 unsigned num_tile_pipes;
1437 unsigned num_backends_per_se;
1438 unsigned backend_disable_mask_per_asic;
1439 unsigned backend_map;
1440 unsigned num_texture_channel_caches;
1441 unsigned mem_max_burst_length_bytes;
1442 unsigned mem_row_size_in_kb;
1443 unsigned shader_engine_tile_size;
1444 unsigned num_gpus;
1445 unsigned multi_gpu_tile_size;
1446
1447 unsigned tile_config;
1448 };
1449
1450 union radeon_asic_config {
1451 struct r300_asic r300;
1452 struct r100_asic r100;
1453 struct r600_asic r600;
1454 struct rv770_asic rv770;
1455 struct evergreen_asic evergreen;
1456 struct cayman_asic cayman;
1457 struct si_asic si;
1458 };
1459
1460 /*
1461 * asic initizalization from radeon_asic.c
1462 */
1463 void radeon_agp_disable(struct radeon_device *rdev);
1464 int radeon_asic_init(struct radeon_device *rdev);
1465
1466
1467 /*
1468 * IOCTL.
1469 */
1470 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1471 struct drm_file *filp);
1472 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1473 struct drm_file *filp);
1474 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1475 struct drm_file *file_priv);
1476 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1477 struct drm_file *file_priv);
1478 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1479 struct drm_file *file_priv);
1480 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *file_priv);
1482 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1483 struct drm_file *filp);
1484 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1485 struct drm_file *filp);
1486 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1487 struct drm_file *filp);
1488 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1489 struct drm_file *filp);
1490 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *filp);
1492 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1493 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1494 struct drm_file *filp);
1495 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1496 struct drm_file *filp);
1497
1498 /* VRAM scratch page for HDP bug, default vram page */
1499 struct r600_vram_scratch {
1500 struct radeon_bo *robj;
1501 volatile uint32_t *ptr;
1502 u64 gpu_addr;
1503 };
1504
1505 /*
1506 * ACPI
1507 */
1508 struct radeon_atif_notification_cfg {
1509 bool enabled;
1510 int command_code;
1511 };
1512
1513 struct radeon_atif_notifications {
1514 bool display_switch;
1515 bool expansion_mode_change;
1516 bool thermal_state;
1517 bool forced_power_state;
1518 bool system_power_state;
1519 bool display_conf_change;
1520 bool px_gfx_switch;
1521 bool brightness_change;
1522 bool dgpu_display_event;
1523 };
1524
1525 struct radeon_atif_functions {
1526 bool system_params;
1527 bool sbios_requests;
1528 bool select_active_disp;
1529 bool lid_state;
1530 bool get_tv_standard;
1531 bool set_tv_standard;
1532 bool get_panel_expansion_mode;
1533 bool set_panel_expansion_mode;
1534 bool temperature_change;
1535 bool graphics_device_types;
1536 };
1537
1538 struct radeon_atif {
1539 struct radeon_atif_notifications notifications;
1540 struct radeon_atif_functions functions;
1541 struct radeon_atif_notification_cfg notification_cfg;
1542 struct radeon_encoder *encoder_for_bl;
1543 };
1544
1545 struct radeon_atcs_functions {
1546 bool get_ext_state;
1547 bool pcie_perf_req;
1548 bool pcie_dev_rdy;
1549 bool pcie_bus_width;
1550 };
1551
1552 struct radeon_atcs {
1553 struct radeon_atcs_functions functions;
1554 };
1555
1556 /*
1557 * Core structure, functions and helpers.
1558 */
1559 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1560 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1561
1562 struct radeon_device {
1563 struct device *dev;
1564 struct drm_device *ddev;
1565 struct pci_dev *pdev;
1566 struct rw_semaphore exclusive_lock;
1567 /* ASIC */
1568 union radeon_asic_config config;
1569 enum radeon_family family;
1570 unsigned long flags;
1571 int usec_timeout;
1572 enum radeon_pll_errata pll_errata;
1573 int num_gb_pipes;
1574 int num_z_pipes;
1575 int disp_priority;
1576 /* BIOS */
1577 uint8_t *bios;
1578 bool is_atom_bios;
1579 uint16_t bios_header_start;
1580 struct radeon_bo *stollen_vga_memory;
1581 /* Register mmio */
1582 resource_size_t rmmio_base;
1583 resource_size_t rmmio_size;
1584 /* protects concurrent MM_INDEX/DATA based register access */
1585 spinlock_t mmio_idx_lock;
1586 void __iomem *rmmio;
1587 radeon_rreg_t mc_rreg;
1588 radeon_wreg_t mc_wreg;
1589 radeon_rreg_t pll_rreg;
1590 radeon_wreg_t pll_wreg;
1591 uint32_t pcie_reg_mask;
1592 radeon_rreg_t pciep_rreg;
1593 radeon_wreg_t pciep_wreg;
1594 /* io port */
1595 void __iomem *rio_mem;
1596 resource_size_t rio_mem_size;
1597 struct radeon_clock clock;
1598 struct radeon_mc mc;
1599 struct radeon_gart gart;
1600 struct radeon_mode_info mode_info;
1601 struct radeon_scratch scratch;
1602 struct radeon_mman mman;
1603 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1604 wait_queue_head_t fence_queue;
1605 struct mutex ring_lock;
1606 struct radeon_ring ring[RADEON_NUM_RINGS];
1607 bool ib_pool_ready;
1608 struct radeon_sa_manager ring_tmp_bo;
1609 struct radeon_irq irq;
1610 struct radeon_asic *asic;
1611 struct radeon_gem gem;
1612 struct radeon_pm pm;
1613 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1614 struct radeon_wb wb;
1615 struct radeon_dummy_page dummy_page;
1616 bool shutdown;
1617 bool suspend;
1618 bool need_dma32;
1619 bool accel_working;
1620 bool fastfb_working; /* IGP feature*/
1621 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1622 const struct firmware *me_fw; /* all family ME firmware */
1623 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1624 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1625 const struct firmware *mc_fw; /* NI MC firmware */
1626 const struct firmware *ce_fw; /* SI CE firmware */
1627 struct r600_blit r600_blit;
1628 struct r600_vram_scratch vram_scratch;
1629 int msi_enabled; /* msi enabled */
1630 struct r600_ih ih; /* r6/700 interrupt ring */
1631 struct si_rlc rlc;
1632 struct work_struct hotplug_work;
1633 struct work_struct audio_work;
1634 int num_crtc; /* number of crtcs */
1635 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1636 bool audio_enabled;
1637 struct r600_audio audio_status; /* audio stuff */
1638 struct notifier_block acpi_nb;
1639 /* only one userspace can use Hyperz features or CMASK at a time */
1640 struct drm_file *hyperz_filp;
1641 struct drm_file *cmask_filp;
1642 /* i2c buses */
1643 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1644 /* debugfs */
1645 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1646 unsigned debugfs_count;
1647 /* virtual memory */
1648 struct radeon_vm_manager vm_manager;
1649 struct mutex gpu_clock_mutex;
1650 /* ACPI interface */
1651 struct radeon_atif atif;
1652 struct radeon_atcs atcs;
1653 };
1654
1655 int radeon_device_init(struct radeon_device *rdev,
1656 struct drm_device *ddev,
1657 struct pci_dev *pdev,
1658 uint32_t flags);
1659 void radeon_device_fini(struct radeon_device *rdev);
1660 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1661
1662 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1663 bool always_indirect);
1664 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1665 bool always_indirect);
1666 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1667 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1668
1669 /*
1670 * Cast helper
1671 */
1672 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1673
1674 /*
1675 * Registers read & write functions.
1676 */
1677 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1678 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1679 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1680 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1681 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1682 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1683 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1684 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1685 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1686 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1687 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1688 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1689 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1690 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1691 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1692 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1693 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1694 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1695 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1696 #define WREG32_P(reg, val, mask) \
1697 do { \
1698 uint32_t tmp_ = RREG32(reg); \
1699 tmp_ &= (mask); \
1700 tmp_ |= ((val) & ~(mask)); \
1701 WREG32(reg, tmp_); \
1702 } while (0)
1703 #define WREG32_PLL_P(reg, val, mask) \
1704 do { \
1705 uint32_t tmp_ = RREG32_PLL(reg); \
1706 tmp_ &= (mask); \
1707 tmp_ |= ((val) & ~(mask)); \
1708 WREG32_PLL(reg, tmp_); \
1709 } while (0)
1710 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1711 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1712 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1713
1714 /*
1715 * Indirect registers accessor
1716 */
1717 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1718 {
1719 uint32_t r;
1720
1721 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1722 r = RREG32(RADEON_PCIE_DATA);
1723 return r;
1724 }
1725
1726 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1727 {
1728 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1729 WREG32(RADEON_PCIE_DATA, (v));
1730 }
1731
1732 void r100_pll_errata_after_index(struct radeon_device *rdev);
1733
1734
1735 /*
1736 * ASICs helpers.
1737 */
1738 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1739 (rdev->pdev->device == 0x5969))
1740 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1741 (rdev->family == CHIP_RV200) || \
1742 (rdev->family == CHIP_RS100) || \
1743 (rdev->family == CHIP_RS200) || \
1744 (rdev->family == CHIP_RV250) || \
1745 (rdev->family == CHIP_RV280) || \
1746 (rdev->family == CHIP_RS300))
1747 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1748 (rdev->family == CHIP_RV350) || \
1749 (rdev->family == CHIP_R350) || \
1750 (rdev->family == CHIP_RV380) || \
1751 (rdev->family == CHIP_R420) || \
1752 (rdev->family == CHIP_R423) || \
1753 (rdev->family == CHIP_RV410) || \
1754 (rdev->family == CHIP_RS400) || \
1755 (rdev->family == CHIP_RS480))
1756 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1757 (rdev->ddev->pdev->device == 0x9443) || \
1758 (rdev->ddev->pdev->device == 0x944B) || \
1759 (rdev->ddev->pdev->device == 0x9506) || \
1760 (rdev->ddev->pdev->device == 0x9509) || \
1761 (rdev->ddev->pdev->device == 0x950F) || \
1762 (rdev->ddev->pdev->device == 0x689C) || \
1763 (rdev->ddev->pdev->device == 0x689D))
1764 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1765 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1766 (rdev->family == CHIP_RS690) || \
1767 (rdev->family == CHIP_RS740) || \
1768 (rdev->family >= CHIP_R600))
1769 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1770 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1771 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1772 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1773 (rdev->flags & RADEON_IS_IGP))
1774 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1775 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1776 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1777 (rdev->flags & RADEON_IS_IGP))
1778 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1779
1780 /*
1781 * BIOS helpers.
1782 */
1783 #define RBIOS8(i) (rdev->bios[i])
1784 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1785 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1786
1787 int radeon_combios_init(struct radeon_device *rdev);
1788 void radeon_combios_fini(struct radeon_device *rdev);
1789 int radeon_atombios_init(struct radeon_device *rdev);
1790 void radeon_atombios_fini(struct radeon_device *rdev);
1791
1792
1793 /*
1794 * RING helpers.
1795 */
1796 #if DRM_DEBUG_CODE == 0
1797 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1798 {
1799 ring->ring[ring->wptr++] = v;
1800 ring->wptr &= ring->ptr_mask;
1801 ring->count_dw--;
1802 ring->ring_free_dw--;
1803 }
1804 #else
1805 /* With debugging this is just too big to inline */
1806 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1807 #endif
1808
1809 /*
1810 * ASICs macro.
1811 */
1812 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1813 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1814 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1815 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1816 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1817 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1818 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1819 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1820 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1821 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1822 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1823 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1824 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1825 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1826 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1827 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1828 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1829 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1830 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1831 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1832 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1833 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1834 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1835 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1836 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1837 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1838 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1839 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1840 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1841 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1842 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1843 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1844 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1845 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1846 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1847 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1848 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1849 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1850 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1851 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1852 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1853 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1854 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1855 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1856 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1857 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1858 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1859 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1860 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1861 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1862 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1863 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1864 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1865 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1866 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1867 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1868 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1869 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1870 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
1871
1872 /* Common functions */
1873 /* AGP */
1874 extern int radeon_gpu_reset(struct radeon_device *rdev);
1875 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1876 extern void radeon_agp_disable(struct radeon_device *rdev);
1877 extern int radeon_modeset_init(struct radeon_device *rdev);
1878 extern void radeon_modeset_fini(struct radeon_device *rdev);
1879 extern bool radeon_card_posted(struct radeon_device *rdev);
1880 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1881 extern void radeon_update_display_priority(struct radeon_device *rdev);
1882 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1883 extern void radeon_scratch_init(struct radeon_device *rdev);
1884 extern void radeon_wb_fini(struct radeon_device *rdev);
1885 extern int radeon_wb_init(struct radeon_device *rdev);
1886 extern void radeon_wb_disable(struct radeon_device *rdev);
1887 extern void radeon_surface_init(struct radeon_device *rdev);
1888 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1889 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1890 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1891 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1892 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1893 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1894 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1895 extern int radeon_resume_kms(struct drm_device *dev);
1896 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1897 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1898
1899 /*
1900 * vm
1901 */
1902 int radeon_vm_manager_init(struct radeon_device *rdev);
1903 void radeon_vm_manager_fini(struct radeon_device *rdev);
1904 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1905 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1906 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1907 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1908 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1909 struct radeon_vm *vm, int ring);
1910 void radeon_vm_fence(struct radeon_device *rdev,
1911 struct radeon_vm *vm,
1912 struct radeon_fence *fence);
1913 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1914 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1915 struct radeon_vm *vm,
1916 struct radeon_bo *bo,
1917 struct ttm_mem_reg *mem);
1918 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1919 struct radeon_bo *bo);
1920 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1921 struct radeon_bo *bo);
1922 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1923 struct radeon_vm *vm,
1924 struct radeon_bo *bo);
1925 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1926 struct radeon_bo_va *bo_va,
1927 uint64_t offset,
1928 uint32_t flags);
1929 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1930 struct radeon_bo_va *bo_va);
1931
1932 /* audio */
1933 void r600_audio_update_hdmi(struct work_struct *work);
1934
1935 /*
1936 * R600 vram scratch functions
1937 */
1938 int r600_vram_scratch_init(struct radeon_device *rdev);
1939 void r600_vram_scratch_fini(struct radeon_device *rdev);
1940
1941 /*
1942 * r600 cs checking helper
1943 */
1944 unsigned r600_mip_minify(unsigned size, unsigned level);
1945 bool r600_fmt_is_valid_color(u32 format);
1946 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1947 int r600_fmt_get_blocksize(u32 format);
1948 int r600_fmt_get_nblocksx(u32 format, u32 w);
1949 int r600_fmt_get_nblocksy(u32 format, u32 h);
1950
1951 /*
1952 * r600 functions used by radeon_encoder.c
1953 */
1954 struct radeon_hdmi_acr {
1955 u32 clock;
1956
1957 int n_32khz;
1958 int cts_32khz;
1959
1960 int n_44_1khz;
1961 int cts_44_1khz;
1962
1963 int n_48khz;
1964 int cts_48khz;
1965
1966 };
1967
1968 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1969
1970 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1971 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1972 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1973 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1974 u32 tiling_pipe_num,
1975 u32 max_rb_num,
1976 u32 total_max_rb_num,
1977 u32 enabled_rb_mask);
1978
1979 /*
1980 * evergreen functions used by radeon_encoder.c
1981 */
1982
1983 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1984
1985 extern int ni_init_microcode(struct radeon_device *rdev);
1986 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1987
1988 /* radeon_acpi.c */
1989 #if defined(CONFIG_ACPI)
1990 extern int radeon_acpi_init(struct radeon_device *rdev);
1991 extern void radeon_acpi_fini(struct radeon_device *rdev);
1992 #else
1993 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1994 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1995 #endif
1996
1997 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
1998 struct radeon_cs_packet *pkt,
1999 unsigned idx);
2000 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2001 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2002 struct radeon_cs_packet *pkt);
2003 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2004 struct radeon_cs_reloc **cs_reloc,
2005 int nomm);
2006 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2007 uint32_t *vline_start_end,
2008 uint32_t *vline_status);
2009
2010 #include "radeon_object.h"
2011
2012 #endif
Linux kernel - Deliverables
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