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drm/radeon: add a module parameter to control deep color support
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103 extern int radeon_vm_size;
104 extern int radeon_vm_block_size;
105 extern int radeon_deep_color;
106
107 /*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
111 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
113 /* RADEON_IB_POOL_SIZE must be a power of 2 */
114 #define RADEON_IB_POOL_SIZE 16
115 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
116 #define RADEONFB_CONN_LIMIT 4
117 #define RADEON_BIOS_NUM_SCRATCH 8
118
119 /* fence seq are set to this number when signaled */
120 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122 /* internal ring indices */
123 /* r1xx+ has gfx CP ring */
124 #define RADEON_RING_TYPE_GFX_INDEX 0
125
126 /* cayman has 2 compute CP rings */
127 #define CAYMAN_RING_TYPE_CP1_INDEX 1
128 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129
130 /* R600+ has an async dma ring */
131 #define R600_RING_TYPE_DMA_INDEX 3
132 /* cayman add a second async dma ring */
133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134
135 /* R600+ */
136 #define R600_RING_TYPE_UVD_INDEX 5
137
138 /* TN+ */
139 #define TN_RING_TYPE_VCE1_INDEX 6
140 #define TN_RING_TYPE_VCE2_INDEX 7
141
142 /* max number of rings */
143 #define RADEON_NUM_RINGS 8
144
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* hardcode those limit for now */
152 #define RADEON_VA_IB_OFFSET (1 << 20)
153 #define RADEON_VA_RESERVED_SIZE (8 << 20)
154 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
155
156 /* hard reset data */
157 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
159 /* reset flags */
160 #define RADEON_RESET_GFX (1 << 0)
161 #define RADEON_RESET_COMPUTE (1 << 1)
162 #define RADEON_RESET_DMA (1 << 2)
163 #define RADEON_RESET_CP (1 << 3)
164 #define RADEON_RESET_GRBM (1 << 4)
165 #define RADEON_RESET_DMA1 (1 << 5)
166 #define RADEON_RESET_RLC (1 << 6)
167 #define RADEON_RESET_SEM (1 << 7)
168 #define RADEON_RESET_IH (1 << 8)
169 #define RADEON_RESET_VMC (1 << 9)
170 #define RADEON_RESET_MC (1 << 10)
171 #define RADEON_RESET_DISPLAY (1 << 11)
172
173 /* CG block flags */
174 #define RADEON_CG_BLOCK_GFX (1 << 0)
175 #define RADEON_CG_BLOCK_MC (1 << 1)
176 #define RADEON_CG_BLOCK_SDMA (1 << 2)
177 #define RADEON_CG_BLOCK_UVD (1 << 3)
178 #define RADEON_CG_BLOCK_VCE (1 << 4)
179 #define RADEON_CG_BLOCK_HDP (1 << 5)
180 #define RADEON_CG_BLOCK_BIF (1 << 6)
181
182 /* CG flags */
183 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201 /* PG flags */
202 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
203 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205 #define RADEON_PG_SUPPORT_UVD (1 << 3)
206 #define RADEON_PG_SUPPORT_VCE (1 << 4)
207 #define RADEON_PG_SUPPORT_CP (1 << 5)
208 #define RADEON_PG_SUPPORT_GDS (1 << 6)
209 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
211 #define RADEON_PG_SUPPORT_ACP (1 << 9)
212 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
214 /* max cursor sizes (in pixels) */
215 #define CURSOR_WIDTH 64
216 #define CURSOR_HEIGHT 64
217
218 #define CIK_CURSOR_WIDTH 128
219 #define CIK_CURSOR_HEIGHT 128
220
221 /*
222 * Errata workarounds.
223 */
224 enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228 };
229
230
231 struct radeon_device;
232
233
234 /*
235 * BIOS.
236 */
237 bool radeon_get_bios(struct radeon_device *rdev);
238
239 /*
240 * Dummy page
241 */
242 struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245 };
246 int radeon_dummy_page_init(struct radeon_device *rdev);
247 void radeon_dummy_page_fini(struct radeon_device *rdev);
248
249
250 /*
251 * Clocks
252 */
253 struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
256 struct radeon_pll dcpll;
257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
262 uint32_t default_dispclk;
263 uint32_t current_dispclk;
264 uint32_t dp_extclk;
265 uint32_t max_pixel_clock;
266 };
267
268 /*
269 * Power management
270 */
271 int radeon_pm_init(struct radeon_device *rdev);
272 int radeon_pm_late_init(struct radeon_device *rdev);
273 void radeon_pm_fini(struct radeon_device *rdev);
274 void radeon_pm_compute_clocks(struct radeon_device *rdev);
275 void radeon_pm_suspend(struct radeon_device *rdev);
276 void radeon_pm_resume(struct radeon_device *rdev);
277 void radeon_combios_get_power_modes(struct radeon_device *rdev);
278 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
279 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
284 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
288 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
289 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
296 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
298 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
301 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
307 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode,
317 struct atom_voltage_table *voltage_table);
318 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
320 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
321 u32 mem_clock);
322 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
323 u32 mem_clock);
324 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
325 u8 module_index,
326 struct atom_mc_reg_table *reg_table);
327 int radeon_atom_get_memory_info(struct radeon_device *rdev,
328 u8 module_index, struct atom_memory_info *mem_info);
329 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
330 bool gddr5, u8 module_index,
331 struct atom_memory_clock_range_table *mclk_range_table);
332 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
333 u16 voltage_id, u16 *voltage);
334 void rs690_pm_info(struct radeon_device *rdev);
335 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
336 unsigned *bankh, unsigned *mtaspect,
337 unsigned *tile_split);
338
339 /*
340 * Fences.
341 */
342 struct radeon_fence_driver {
343 uint32_t scratch_reg;
344 uint64_t gpu_addr;
345 volatile uint32_t *cpu_addr;
346 /* sync_seq is protected by ring emission lock */
347 uint64_t sync_seq[RADEON_NUM_RINGS];
348 atomic64_t last_seq;
349 bool initialized;
350 };
351
352 struct radeon_fence {
353 struct radeon_device *rdev;
354 struct kref kref;
355 /* protected by radeon_fence.lock */
356 uint64_t seq;
357 /* RB, DMA, etc. */
358 unsigned ring;
359 };
360
361 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
362 int radeon_fence_driver_init(struct radeon_device *rdev);
363 void radeon_fence_driver_fini(struct radeon_device *rdev);
364 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
365 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
366 void radeon_fence_process(struct radeon_device *rdev, int ring);
367 bool radeon_fence_signaled(struct radeon_fence *fence);
368 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
369 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
370 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
371 int radeon_fence_wait_any(struct radeon_device *rdev,
372 struct radeon_fence **fences,
373 bool intr);
374 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
375 void radeon_fence_unref(struct radeon_fence **fence);
376 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
377 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
378 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
379 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
380 struct radeon_fence *b)
381 {
382 if (!a) {
383 return b;
384 }
385
386 if (!b) {
387 return a;
388 }
389
390 BUG_ON(a->ring != b->ring);
391
392 if (a->seq > b->seq) {
393 return a;
394 } else {
395 return b;
396 }
397 }
398
399 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
400 struct radeon_fence *b)
401 {
402 if (!a) {
403 return false;
404 }
405
406 if (!b) {
407 return true;
408 }
409
410 BUG_ON(a->ring != b->ring);
411
412 return a->seq < b->seq;
413 }
414
415 /*
416 * Tiling registers
417 */
418 struct radeon_surface_reg {
419 struct radeon_bo *bo;
420 };
421
422 #define RADEON_GEM_MAX_SURFACES 8
423
424 /*
425 * TTM.
426 */
427 struct radeon_mman {
428 struct ttm_bo_global_ref bo_global_ref;
429 struct drm_global_reference mem_global_ref;
430 struct ttm_bo_device bdev;
431 bool mem_global_referenced;
432 bool initialized;
433
434 #if defined(CONFIG_DEBUG_FS)
435 struct dentry *vram;
436 struct dentry *gtt;
437 #endif
438 };
439
440 /* bo virtual address in a specific vm */
441 struct radeon_bo_va {
442 /* protected by bo being reserved */
443 struct list_head bo_list;
444 uint64_t soffset;
445 uint64_t eoffset;
446 uint32_t flags;
447 bool valid;
448 unsigned ref_count;
449
450 /* protected by vm mutex */
451 struct list_head vm_list;
452
453 /* constant after initialization */
454 struct radeon_vm *vm;
455 struct radeon_bo *bo;
456 };
457
458 struct radeon_bo {
459 /* Protected by gem.mutex */
460 struct list_head list;
461 /* Protected by tbo.reserved */
462 u32 initial_domain;
463 u32 placements[3];
464 struct ttm_placement placement;
465 struct ttm_buffer_object tbo;
466 struct ttm_bo_kmap_obj kmap;
467 unsigned pin_count;
468 void *kptr;
469 u32 tiling_flags;
470 u32 pitch;
471 int surface_reg;
472 /* list of all virtual address to which this bo
473 * is associated to
474 */
475 struct list_head va;
476 /* Constant after initialization */
477 struct radeon_device *rdev;
478 struct drm_gem_object gem_base;
479
480 struct ttm_bo_kmap_obj dma_buf_vmap;
481 pid_t pid;
482 };
483 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
484
485 int radeon_gem_debugfs_init(struct radeon_device *rdev);
486
487 /* sub-allocation manager, it has to be protected by another lock.
488 * By conception this is an helper for other part of the driver
489 * like the indirect buffer or semaphore, which both have their
490 * locking.
491 *
492 * Principe is simple, we keep a list of sub allocation in offset
493 * order (first entry has offset == 0, last entry has the highest
494 * offset).
495 *
496 * When allocating new object we first check if there is room at
497 * the end total_size - (last_object_offset + last_object_size) >=
498 * alloc_size. If so we allocate new object there.
499 *
500 * When there is not enough room at the end, we start waiting for
501 * each sub object until we reach object_offset+object_size >=
502 * alloc_size, this object then become the sub object we return.
503 *
504 * Alignment can't be bigger than page size.
505 *
506 * Hole are not considered for allocation to keep things simple.
507 * Assumption is that there won't be hole (all object on same
508 * alignment).
509 */
510 struct radeon_sa_manager {
511 wait_queue_head_t wq;
512 struct radeon_bo *bo;
513 struct list_head *hole;
514 struct list_head flist[RADEON_NUM_RINGS];
515 struct list_head olist;
516 unsigned size;
517 uint64_t gpu_addr;
518 void *cpu_ptr;
519 uint32_t domain;
520 uint32_t align;
521 };
522
523 struct radeon_sa_bo;
524
525 /* sub-allocation buffer */
526 struct radeon_sa_bo {
527 struct list_head olist;
528 struct list_head flist;
529 struct radeon_sa_manager *manager;
530 unsigned soffset;
531 unsigned eoffset;
532 struct radeon_fence *fence;
533 };
534
535 /*
536 * GEM objects.
537 */
538 struct radeon_gem {
539 struct mutex mutex;
540 struct list_head objects;
541 };
542
543 int radeon_gem_init(struct radeon_device *rdev);
544 void radeon_gem_fini(struct radeon_device *rdev);
545 int radeon_gem_object_create(struct radeon_device *rdev, int size,
546 int alignment, int initial_domain,
547 bool discardable, bool kernel,
548 struct drm_gem_object **obj);
549
550 int radeon_mode_dumb_create(struct drm_file *file_priv,
551 struct drm_device *dev,
552 struct drm_mode_create_dumb *args);
553 int radeon_mode_dumb_mmap(struct drm_file *filp,
554 struct drm_device *dev,
555 uint32_t handle, uint64_t *offset_p);
556
557 /*
558 * Semaphores.
559 */
560 struct radeon_semaphore {
561 struct radeon_sa_bo *sa_bo;
562 signed waiters;
563 uint64_t gpu_addr;
564 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
565 };
566
567 int radeon_semaphore_create(struct radeon_device *rdev,
568 struct radeon_semaphore **semaphore);
569 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
570 struct radeon_semaphore *semaphore);
571 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
572 struct radeon_semaphore *semaphore);
573 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
574 struct radeon_fence *fence);
575 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
576 struct radeon_semaphore *semaphore,
577 int waiting_ring);
578 void radeon_semaphore_free(struct radeon_device *rdev,
579 struct radeon_semaphore **semaphore,
580 struct radeon_fence *fence);
581
582 /*
583 * GART structures, functions & helpers
584 */
585 struct radeon_mc;
586
587 #define RADEON_GPU_PAGE_SIZE 4096
588 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
589 #define RADEON_GPU_PAGE_SHIFT 12
590 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
591
592 struct radeon_gart {
593 dma_addr_t table_addr;
594 struct radeon_bo *robj;
595 void *ptr;
596 unsigned num_gpu_pages;
597 unsigned num_cpu_pages;
598 unsigned table_size;
599 struct page **pages;
600 dma_addr_t *pages_addr;
601 bool ready;
602 };
603
604 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
605 void radeon_gart_table_ram_free(struct radeon_device *rdev);
606 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
607 void radeon_gart_table_vram_free(struct radeon_device *rdev);
608 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
609 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
610 int radeon_gart_init(struct radeon_device *rdev);
611 void radeon_gart_fini(struct radeon_device *rdev);
612 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
613 int pages);
614 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
615 int pages, struct page **pagelist,
616 dma_addr_t *dma_addr);
617 void radeon_gart_restore(struct radeon_device *rdev);
618
619
620 /*
621 * GPU MC structures, functions & helpers
622 */
623 struct radeon_mc {
624 resource_size_t aper_size;
625 resource_size_t aper_base;
626 resource_size_t agp_base;
627 /* for some chips with <= 32MB we need to lie
628 * about vram size near mc fb location */
629 u64 mc_vram_size;
630 u64 visible_vram_size;
631 u64 gtt_size;
632 u64 gtt_start;
633 u64 gtt_end;
634 u64 vram_start;
635 u64 vram_end;
636 unsigned vram_width;
637 u64 real_vram_size;
638 int vram_mtrr;
639 bool vram_is_ddr;
640 bool igp_sideport_enabled;
641 u64 gtt_base_align;
642 u64 mc_mask;
643 };
644
645 bool radeon_combios_sideport_present(struct radeon_device *rdev);
646 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
647
648 /*
649 * GPU scratch registers structures, functions & helpers
650 */
651 struct radeon_scratch {
652 unsigned num_reg;
653 uint32_t reg_base;
654 bool free[32];
655 uint32_t reg[32];
656 };
657
658 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
659 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
660
661 /*
662 * GPU doorbell structures, functions & helpers
663 */
664 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
665
666 struct radeon_doorbell {
667 /* doorbell mmio */
668 resource_size_t base;
669 resource_size_t size;
670 u32 __iomem *ptr;
671 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
672 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
673 };
674
675 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
676 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
677
678 /*
679 * IRQS.
680 */
681
682 struct radeon_flip_work {
683 struct work_struct flip_work;
684 struct work_struct unpin_work;
685 struct radeon_device *rdev;
686 int crtc_id;
687 struct drm_framebuffer *fb;
688 struct drm_pending_vblank_event *event;
689 struct radeon_bo *old_rbo;
690 struct radeon_bo *new_rbo;
691 struct radeon_fence *fence;
692 };
693
694 struct r500_irq_stat_regs {
695 u32 disp_int;
696 u32 hdmi0_status;
697 };
698
699 struct r600_irq_stat_regs {
700 u32 disp_int;
701 u32 disp_int_cont;
702 u32 disp_int_cont2;
703 u32 d1grph_int;
704 u32 d2grph_int;
705 u32 hdmi0_status;
706 u32 hdmi1_status;
707 };
708
709 struct evergreen_irq_stat_regs {
710 u32 disp_int;
711 u32 disp_int_cont;
712 u32 disp_int_cont2;
713 u32 disp_int_cont3;
714 u32 disp_int_cont4;
715 u32 disp_int_cont5;
716 u32 d1grph_int;
717 u32 d2grph_int;
718 u32 d3grph_int;
719 u32 d4grph_int;
720 u32 d5grph_int;
721 u32 d6grph_int;
722 u32 afmt_status1;
723 u32 afmt_status2;
724 u32 afmt_status3;
725 u32 afmt_status4;
726 u32 afmt_status5;
727 u32 afmt_status6;
728 };
729
730 struct cik_irq_stat_regs {
731 u32 disp_int;
732 u32 disp_int_cont;
733 u32 disp_int_cont2;
734 u32 disp_int_cont3;
735 u32 disp_int_cont4;
736 u32 disp_int_cont5;
737 u32 disp_int_cont6;
738 u32 d1grph_int;
739 u32 d2grph_int;
740 u32 d3grph_int;
741 u32 d4grph_int;
742 u32 d5grph_int;
743 u32 d6grph_int;
744 };
745
746 union radeon_irq_stat_regs {
747 struct r500_irq_stat_regs r500;
748 struct r600_irq_stat_regs r600;
749 struct evergreen_irq_stat_regs evergreen;
750 struct cik_irq_stat_regs cik;
751 };
752
753 #define RADEON_MAX_HPD_PINS 7
754 #define RADEON_MAX_CRTCS 6
755 #define RADEON_MAX_AFMT_BLOCKS 7
756
757 struct radeon_irq {
758 bool installed;
759 spinlock_t lock;
760 atomic_t ring_int[RADEON_NUM_RINGS];
761 bool crtc_vblank_int[RADEON_MAX_CRTCS];
762 atomic_t pflip[RADEON_MAX_CRTCS];
763 wait_queue_head_t vblank_queue;
764 bool hpd[RADEON_MAX_HPD_PINS];
765 bool afmt[RADEON_MAX_AFMT_BLOCKS];
766 union radeon_irq_stat_regs stat_regs;
767 bool dpm_thermal;
768 };
769
770 int radeon_irq_kms_init(struct radeon_device *rdev);
771 void radeon_irq_kms_fini(struct radeon_device *rdev);
772 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
773 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
774 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
775 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
776 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
777 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
778 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
779 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
780
781 /*
782 * CP & rings.
783 */
784
785 struct radeon_ib {
786 struct radeon_sa_bo *sa_bo;
787 uint32_t length_dw;
788 uint64_t gpu_addr;
789 uint32_t *ptr;
790 int ring;
791 struct radeon_fence *fence;
792 struct radeon_vm *vm;
793 bool is_const_ib;
794 struct radeon_semaphore *semaphore;
795 };
796
797 struct radeon_ring {
798 struct radeon_bo *ring_obj;
799 volatile uint32_t *ring;
800 unsigned rptr_offs;
801 unsigned rptr_save_reg;
802 u64 next_rptr_gpu_addr;
803 volatile u32 *next_rptr_cpu_addr;
804 unsigned wptr;
805 unsigned wptr_old;
806 unsigned ring_size;
807 unsigned ring_free_dw;
808 int count_dw;
809 atomic_t last_rptr;
810 atomic64_t last_activity;
811 uint64_t gpu_addr;
812 uint32_t align_mask;
813 uint32_t ptr_mask;
814 bool ready;
815 u32 nop;
816 u32 idx;
817 u64 last_semaphore_signal_addr;
818 u64 last_semaphore_wait_addr;
819 /* for CIK queues */
820 u32 me;
821 u32 pipe;
822 u32 queue;
823 struct radeon_bo *mqd_obj;
824 u32 doorbell_index;
825 unsigned wptr_offs;
826 };
827
828 struct radeon_mec {
829 struct radeon_bo *hpd_eop_obj;
830 u64 hpd_eop_gpu_addr;
831 u32 num_pipe;
832 u32 num_mec;
833 u32 num_queue;
834 };
835
836 /*
837 * VM
838 */
839
840 /* maximum number of VMIDs */
841 #define RADEON_NUM_VM 16
842
843 /* number of entries in page table */
844 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
845
846 /* PTBs (Page Table Blocks) need to be aligned to 32K */
847 #define RADEON_VM_PTB_ALIGN_SIZE 32768
848 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
849 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
850
851 #define R600_PTE_VALID (1 << 0)
852 #define R600_PTE_SYSTEM (1 << 1)
853 #define R600_PTE_SNOOPED (1 << 2)
854 #define R600_PTE_READABLE (1 << 5)
855 #define R600_PTE_WRITEABLE (1 << 6)
856
857 /* PTE (Page Table Entry) fragment field for different page sizes */
858 #define R600_PTE_FRAG_4KB (0 << 7)
859 #define R600_PTE_FRAG_64KB (4 << 7)
860 #define R600_PTE_FRAG_256KB (6 << 7)
861
862 /* flags used for GART page table entries on R600+ */
863 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
864 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
865
866 struct radeon_vm_pt {
867 struct radeon_bo *bo;
868 uint64_t addr;
869 };
870
871 struct radeon_vm {
872 struct list_head va;
873 unsigned id;
874
875 /* contains the page directory */
876 struct radeon_bo *page_directory;
877 uint64_t pd_gpu_addr;
878 unsigned max_pde_used;
879
880 /* array of page tables, one for each page directory entry */
881 struct radeon_vm_pt *page_tables;
882
883 struct mutex mutex;
884 /* last fence for cs using this vm */
885 struct radeon_fence *fence;
886 /* last flush or NULL if we still need to flush */
887 struct radeon_fence *last_flush;
888 /* last use of vmid */
889 struct radeon_fence *last_id_use;
890 };
891
892 struct radeon_vm_manager {
893 struct radeon_fence *active[RADEON_NUM_VM];
894 uint32_t max_pfn;
895 /* number of VMIDs */
896 unsigned nvm;
897 /* vram base address for page table entry */
898 u64 vram_base_offset;
899 /* is vm enabled? */
900 bool enabled;
901 };
902
903 /*
904 * file private structure
905 */
906 struct radeon_fpriv {
907 struct radeon_vm vm;
908 };
909
910 /*
911 * R6xx+ IH ring
912 */
913 struct r600_ih {
914 struct radeon_bo *ring_obj;
915 volatile uint32_t *ring;
916 unsigned rptr;
917 unsigned ring_size;
918 uint64_t gpu_addr;
919 uint32_t ptr_mask;
920 atomic_t lock;
921 bool enabled;
922 };
923
924 /*
925 * RLC stuff
926 */
927 #include "clearstate_defs.h"
928
929 struct radeon_rlc {
930 /* for power gating */
931 struct radeon_bo *save_restore_obj;
932 uint64_t save_restore_gpu_addr;
933 volatile uint32_t *sr_ptr;
934 const u32 *reg_list;
935 u32 reg_list_size;
936 /* for clear state */
937 struct radeon_bo *clear_state_obj;
938 uint64_t clear_state_gpu_addr;
939 volatile uint32_t *cs_ptr;
940 const struct cs_section_def *cs_data;
941 u32 clear_state_size;
942 /* for cp tables */
943 struct radeon_bo *cp_table_obj;
944 uint64_t cp_table_gpu_addr;
945 volatile uint32_t *cp_table_ptr;
946 u32 cp_table_size;
947 };
948
949 int radeon_ib_get(struct radeon_device *rdev, int ring,
950 struct radeon_ib *ib, struct radeon_vm *vm,
951 unsigned size);
952 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
953 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
954 struct radeon_ib *const_ib);
955 int radeon_ib_pool_init(struct radeon_device *rdev);
956 void radeon_ib_pool_fini(struct radeon_device *rdev);
957 int radeon_ib_ring_tests(struct radeon_device *rdev);
958 /* Ring access between begin & end cannot sleep */
959 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
960 struct radeon_ring *ring);
961 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
962 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
963 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
964 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
965 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
966 void radeon_ring_undo(struct radeon_ring *ring);
967 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
968 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
969 void radeon_ring_lockup_update(struct radeon_device *rdev,
970 struct radeon_ring *ring);
971 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
972 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
973 uint32_t **data);
974 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
975 unsigned size, uint32_t *data);
976 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
977 unsigned rptr_offs, u32 nop);
978 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
979
980
981 /* r600 async dma */
982 void r600_dma_stop(struct radeon_device *rdev);
983 int r600_dma_resume(struct radeon_device *rdev);
984 void r600_dma_fini(struct radeon_device *rdev);
985
986 void cayman_dma_stop(struct radeon_device *rdev);
987 int cayman_dma_resume(struct radeon_device *rdev);
988 void cayman_dma_fini(struct radeon_device *rdev);
989
990 /*
991 * CS.
992 */
993 struct radeon_cs_reloc {
994 struct drm_gem_object *gobj;
995 struct radeon_bo *robj;
996 struct ttm_validate_buffer tv;
997 uint64_t gpu_offset;
998 unsigned prefered_domains;
999 unsigned allowed_domains;
1000 uint32_t tiling_flags;
1001 uint32_t handle;
1002 };
1003
1004 struct radeon_cs_chunk {
1005 uint32_t chunk_id;
1006 uint32_t length_dw;
1007 uint32_t *kdata;
1008 void __user *user_ptr;
1009 };
1010
1011 struct radeon_cs_parser {
1012 struct device *dev;
1013 struct radeon_device *rdev;
1014 struct drm_file *filp;
1015 /* chunks */
1016 unsigned nchunks;
1017 struct radeon_cs_chunk *chunks;
1018 uint64_t *chunks_array;
1019 /* IB */
1020 unsigned idx;
1021 /* relocations */
1022 unsigned nrelocs;
1023 struct radeon_cs_reloc *relocs;
1024 struct radeon_cs_reloc **relocs_ptr;
1025 struct radeon_cs_reloc *vm_bos;
1026 struct list_head validated;
1027 unsigned dma_reloc_idx;
1028 /* indices of various chunks */
1029 int chunk_ib_idx;
1030 int chunk_relocs_idx;
1031 int chunk_flags_idx;
1032 int chunk_const_ib_idx;
1033 struct radeon_ib ib;
1034 struct radeon_ib const_ib;
1035 void *track;
1036 unsigned family;
1037 int parser_error;
1038 u32 cs_flags;
1039 u32 ring;
1040 s32 priority;
1041 struct ww_acquire_ctx ticket;
1042 };
1043
1044 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1045 {
1046 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1047
1048 if (ibc->kdata)
1049 return ibc->kdata[idx];
1050 return p->ib.ptr[idx];
1051 }
1052
1053
1054 struct radeon_cs_packet {
1055 unsigned idx;
1056 unsigned type;
1057 unsigned reg;
1058 unsigned opcode;
1059 int count;
1060 unsigned one_reg_wr;
1061 };
1062
1063 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1064 struct radeon_cs_packet *pkt,
1065 unsigned idx, unsigned reg);
1066 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1067 struct radeon_cs_packet *pkt);
1068
1069
1070 /*
1071 * AGP
1072 */
1073 int radeon_agp_init(struct radeon_device *rdev);
1074 void radeon_agp_resume(struct radeon_device *rdev);
1075 void radeon_agp_suspend(struct radeon_device *rdev);
1076 void radeon_agp_fini(struct radeon_device *rdev);
1077
1078
1079 /*
1080 * Writeback
1081 */
1082 struct radeon_wb {
1083 struct radeon_bo *wb_obj;
1084 volatile uint32_t *wb;
1085 uint64_t gpu_addr;
1086 bool enabled;
1087 bool use_event;
1088 };
1089
1090 #define RADEON_WB_SCRATCH_OFFSET 0
1091 #define RADEON_WB_RING0_NEXT_RPTR 256
1092 #define RADEON_WB_CP_RPTR_OFFSET 1024
1093 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1094 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1095 #define R600_WB_DMA_RPTR_OFFSET 1792
1096 #define R600_WB_IH_WPTR_OFFSET 2048
1097 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1098 #define R600_WB_EVENT_OFFSET 3072
1099 #define CIK_WB_CP1_WPTR_OFFSET 3328
1100 #define CIK_WB_CP2_WPTR_OFFSET 3584
1101
1102 /**
1103 * struct radeon_pm - power management datas
1104 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1105 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1106 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1107 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1108 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1109 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1110 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1111 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1112 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1113 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1114 * @needed_bandwidth: current bandwidth needs
1115 *
1116 * It keeps track of various data needed to take powermanagement decision.
1117 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1118 * Equation between gpu/memory clock and available bandwidth is hw dependent
1119 * (type of memory, bus size, efficiency, ...)
1120 */
1121
1122 enum radeon_pm_method {
1123 PM_METHOD_PROFILE,
1124 PM_METHOD_DYNPM,
1125 PM_METHOD_DPM,
1126 };
1127
1128 enum radeon_dynpm_state {
1129 DYNPM_STATE_DISABLED,
1130 DYNPM_STATE_MINIMUM,
1131 DYNPM_STATE_PAUSED,
1132 DYNPM_STATE_ACTIVE,
1133 DYNPM_STATE_SUSPENDED,
1134 };
1135 enum radeon_dynpm_action {
1136 DYNPM_ACTION_NONE,
1137 DYNPM_ACTION_MINIMUM,
1138 DYNPM_ACTION_DOWNCLOCK,
1139 DYNPM_ACTION_UPCLOCK,
1140 DYNPM_ACTION_DEFAULT
1141 };
1142
1143 enum radeon_voltage_type {
1144 VOLTAGE_NONE = 0,
1145 VOLTAGE_GPIO,
1146 VOLTAGE_VDDC,
1147 VOLTAGE_SW
1148 };
1149
1150 enum radeon_pm_state_type {
1151 /* not used for dpm */
1152 POWER_STATE_TYPE_DEFAULT,
1153 POWER_STATE_TYPE_POWERSAVE,
1154 /* user selectable states */
1155 POWER_STATE_TYPE_BATTERY,
1156 POWER_STATE_TYPE_BALANCED,
1157 POWER_STATE_TYPE_PERFORMANCE,
1158 /* internal states */
1159 POWER_STATE_TYPE_INTERNAL_UVD,
1160 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1161 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1162 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1163 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1164 POWER_STATE_TYPE_INTERNAL_BOOT,
1165 POWER_STATE_TYPE_INTERNAL_THERMAL,
1166 POWER_STATE_TYPE_INTERNAL_ACPI,
1167 POWER_STATE_TYPE_INTERNAL_ULV,
1168 POWER_STATE_TYPE_INTERNAL_3DPERF,
1169 };
1170
1171 enum radeon_pm_profile_type {
1172 PM_PROFILE_DEFAULT,
1173 PM_PROFILE_AUTO,
1174 PM_PROFILE_LOW,
1175 PM_PROFILE_MID,
1176 PM_PROFILE_HIGH,
1177 };
1178
1179 #define PM_PROFILE_DEFAULT_IDX 0
1180 #define PM_PROFILE_LOW_SH_IDX 1
1181 #define PM_PROFILE_MID_SH_IDX 2
1182 #define PM_PROFILE_HIGH_SH_IDX 3
1183 #define PM_PROFILE_LOW_MH_IDX 4
1184 #define PM_PROFILE_MID_MH_IDX 5
1185 #define PM_PROFILE_HIGH_MH_IDX 6
1186 #define PM_PROFILE_MAX 7
1187
1188 struct radeon_pm_profile {
1189 int dpms_off_ps_idx;
1190 int dpms_on_ps_idx;
1191 int dpms_off_cm_idx;
1192 int dpms_on_cm_idx;
1193 };
1194
1195 enum radeon_int_thermal_type {
1196 THERMAL_TYPE_NONE,
1197 THERMAL_TYPE_EXTERNAL,
1198 THERMAL_TYPE_EXTERNAL_GPIO,
1199 THERMAL_TYPE_RV6XX,
1200 THERMAL_TYPE_RV770,
1201 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1202 THERMAL_TYPE_EVERGREEN,
1203 THERMAL_TYPE_SUMO,
1204 THERMAL_TYPE_NI,
1205 THERMAL_TYPE_SI,
1206 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1207 THERMAL_TYPE_CI,
1208 THERMAL_TYPE_KV,
1209 };
1210
1211 struct radeon_voltage {
1212 enum radeon_voltage_type type;
1213 /* gpio voltage */
1214 struct radeon_gpio_rec gpio;
1215 u32 delay; /* delay in usec from voltage drop to sclk change */
1216 bool active_high; /* voltage drop is active when bit is high */
1217 /* VDDC voltage */
1218 u8 vddc_id; /* index into vddc voltage table */
1219 u8 vddci_id; /* index into vddci voltage table */
1220 bool vddci_enabled;
1221 /* r6xx+ sw */
1222 u16 voltage;
1223 /* evergreen+ vddci */
1224 u16 vddci;
1225 };
1226
1227 /* clock mode flags */
1228 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1229
1230 struct radeon_pm_clock_info {
1231 /* memory clock */
1232 u32 mclk;
1233 /* engine clock */
1234 u32 sclk;
1235 /* voltage info */
1236 struct radeon_voltage voltage;
1237 /* standardized clock flags */
1238 u32 flags;
1239 };
1240
1241 /* state flags */
1242 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1243
1244 struct radeon_power_state {
1245 enum radeon_pm_state_type type;
1246 struct radeon_pm_clock_info *clock_info;
1247 /* number of valid clock modes in this power state */
1248 int num_clock_modes;
1249 struct radeon_pm_clock_info *default_clock_mode;
1250 /* standardized state flags */
1251 u32 flags;
1252 u32 misc; /* vbios specific flags */
1253 u32 misc2; /* vbios specific flags */
1254 int pcie_lanes; /* pcie lanes */
1255 };
1256
1257 /*
1258 * Some modes are overclocked by very low value, accept them
1259 */
1260 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1261
1262 enum radeon_dpm_auto_throttle_src {
1263 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1264 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1265 };
1266
1267 enum radeon_dpm_event_src {
1268 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1269 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1270 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1271 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1272 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1273 };
1274
1275 #define RADEON_MAX_VCE_LEVELS 6
1276
1277 enum radeon_vce_level {
1278 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1279 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1280 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1281 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1282 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1283 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1284 };
1285
1286 struct radeon_ps {
1287 u32 caps; /* vbios flags */
1288 u32 class; /* vbios flags */
1289 u32 class2; /* vbios flags */
1290 /* UVD clocks */
1291 u32 vclk;
1292 u32 dclk;
1293 /* VCE clocks */
1294 u32 evclk;
1295 u32 ecclk;
1296 bool vce_active;
1297 enum radeon_vce_level vce_level;
1298 /* asic priv */
1299 void *ps_priv;
1300 };
1301
1302 struct radeon_dpm_thermal {
1303 /* thermal interrupt work */
1304 struct work_struct work;
1305 /* low temperature threshold */
1306 int min_temp;
1307 /* high temperature threshold */
1308 int max_temp;
1309 /* was interrupt low to high or high to low */
1310 bool high_to_low;
1311 };
1312
1313 enum radeon_clk_action
1314 {
1315 RADEON_SCLK_UP = 1,
1316 RADEON_SCLK_DOWN
1317 };
1318
1319 struct radeon_blacklist_clocks
1320 {
1321 u32 sclk;
1322 u32 mclk;
1323 enum radeon_clk_action action;
1324 };
1325
1326 struct radeon_clock_and_voltage_limits {
1327 u32 sclk;
1328 u32 mclk;
1329 u16 vddc;
1330 u16 vddci;
1331 };
1332
1333 struct radeon_clock_array {
1334 u32 count;
1335 u32 *values;
1336 };
1337
1338 struct radeon_clock_voltage_dependency_entry {
1339 u32 clk;
1340 u16 v;
1341 };
1342
1343 struct radeon_clock_voltage_dependency_table {
1344 u32 count;
1345 struct radeon_clock_voltage_dependency_entry *entries;
1346 };
1347
1348 union radeon_cac_leakage_entry {
1349 struct {
1350 u16 vddc;
1351 u32 leakage;
1352 };
1353 struct {
1354 u16 vddc1;
1355 u16 vddc2;
1356 u16 vddc3;
1357 };
1358 };
1359
1360 struct radeon_cac_leakage_table {
1361 u32 count;
1362 union radeon_cac_leakage_entry *entries;
1363 };
1364
1365 struct radeon_phase_shedding_limits_entry {
1366 u16 voltage;
1367 u32 sclk;
1368 u32 mclk;
1369 };
1370
1371 struct radeon_phase_shedding_limits_table {
1372 u32 count;
1373 struct radeon_phase_shedding_limits_entry *entries;
1374 };
1375
1376 struct radeon_uvd_clock_voltage_dependency_entry {
1377 u32 vclk;
1378 u32 dclk;
1379 u16 v;
1380 };
1381
1382 struct radeon_uvd_clock_voltage_dependency_table {
1383 u8 count;
1384 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1385 };
1386
1387 struct radeon_vce_clock_voltage_dependency_entry {
1388 u32 ecclk;
1389 u32 evclk;
1390 u16 v;
1391 };
1392
1393 struct radeon_vce_clock_voltage_dependency_table {
1394 u8 count;
1395 struct radeon_vce_clock_voltage_dependency_entry *entries;
1396 };
1397
1398 struct radeon_ppm_table {
1399 u8 ppm_design;
1400 u16 cpu_core_number;
1401 u32 platform_tdp;
1402 u32 small_ac_platform_tdp;
1403 u32 platform_tdc;
1404 u32 small_ac_platform_tdc;
1405 u32 apu_tdp;
1406 u32 dgpu_tdp;
1407 u32 dgpu_ulv_power;
1408 u32 tj_max;
1409 };
1410
1411 struct radeon_cac_tdp_table {
1412 u16 tdp;
1413 u16 configurable_tdp;
1414 u16 tdc;
1415 u16 battery_power_limit;
1416 u16 small_power_limit;
1417 u16 low_cac_leakage;
1418 u16 high_cac_leakage;
1419 u16 maximum_power_delivery_limit;
1420 };
1421
1422 struct radeon_dpm_dynamic_state {
1423 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1424 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1425 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1426 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1427 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1428 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1429 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1430 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1431 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1432 struct radeon_clock_array valid_sclk_values;
1433 struct radeon_clock_array valid_mclk_values;
1434 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1435 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1436 u32 mclk_sclk_ratio;
1437 u32 sclk_mclk_delta;
1438 u16 vddc_vddci_delta;
1439 u16 min_vddc_for_pcie_gen2;
1440 struct radeon_cac_leakage_table cac_leakage_table;
1441 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1442 struct radeon_ppm_table *ppm_table;
1443 struct radeon_cac_tdp_table *cac_tdp_table;
1444 };
1445
1446 struct radeon_dpm_fan {
1447 u16 t_min;
1448 u16 t_med;
1449 u16 t_high;
1450 u16 pwm_min;
1451 u16 pwm_med;
1452 u16 pwm_high;
1453 u8 t_hyst;
1454 u32 cycle_delay;
1455 u16 t_max;
1456 bool ucode_fan_control;
1457 };
1458
1459 enum radeon_pcie_gen {
1460 RADEON_PCIE_GEN1 = 0,
1461 RADEON_PCIE_GEN2 = 1,
1462 RADEON_PCIE_GEN3 = 2,
1463 RADEON_PCIE_GEN_INVALID = 0xffff
1464 };
1465
1466 enum radeon_dpm_forced_level {
1467 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1468 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1469 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1470 };
1471
1472 struct radeon_vce_state {
1473 /* vce clocks */
1474 u32 evclk;
1475 u32 ecclk;
1476 /* gpu clocks */
1477 u32 sclk;
1478 u32 mclk;
1479 u8 clk_idx;
1480 u8 pstate;
1481 };
1482
1483 struct radeon_dpm {
1484 struct radeon_ps *ps;
1485 /* number of valid power states */
1486 int num_ps;
1487 /* current power state that is active */
1488 struct radeon_ps *current_ps;
1489 /* requested power state */
1490 struct radeon_ps *requested_ps;
1491 /* boot up power state */
1492 struct radeon_ps *boot_ps;
1493 /* default uvd power state */
1494 struct radeon_ps *uvd_ps;
1495 /* vce requirements */
1496 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1497 enum radeon_vce_level vce_level;
1498 enum radeon_pm_state_type state;
1499 enum radeon_pm_state_type user_state;
1500 u32 platform_caps;
1501 u32 voltage_response_time;
1502 u32 backbias_response_time;
1503 void *priv;
1504 u32 new_active_crtcs;
1505 int new_active_crtc_count;
1506 u32 current_active_crtcs;
1507 int current_active_crtc_count;
1508 struct radeon_dpm_dynamic_state dyn_state;
1509 struct radeon_dpm_fan fan;
1510 u32 tdp_limit;
1511 u32 near_tdp_limit;
1512 u32 near_tdp_limit_adjusted;
1513 u32 sq_ramping_threshold;
1514 u32 cac_leakage;
1515 u16 tdp_od_limit;
1516 u32 tdp_adjustment;
1517 u16 load_line_slope;
1518 bool power_control;
1519 bool ac_power;
1520 /* special states active */
1521 bool thermal_active;
1522 bool uvd_active;
1523 bool vce_active;
1524 /* thermal handling */
1525 struct radeon_dpm_thermal thermal;
1526 /* forced levels */
1527 enum radeon_dpm_forced_level forced_level;
1528 /* track UVD streams */
1529 unsigned sd;
1530 unsigned hd;
1531 };
1532
1533 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1534 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1535
1536 struct radeon_pm {
1537 struct mutex mutex;
1538 /* write locked while reprogramming mclk */
1539 struct rw_semaphore mclk_lock;
1540 u32 active_crtcs;
1541 int active_crtc_count;
1542 int req_vblank;
1543 bool vblank_sync;
1544 fixed20_12 max_bandwidth;
1545 fixed20_12 igp_sideport_mclk;
1546 fixed20_12 igp_system_mclk;
1547 fixed20_12 igp_ht_link_clk;
1548 fixed20_12 igp_ht_link_width;
1549 fixed20_12 k8_bandwidth;
1550 fixed20_12 sideport_bandwidth;
1551 fixed20_12 ht_bandwidth;
1552 fixed20_12 core_bandwidth;
1553 fixed20_12 sclk;
1554 fixed20_12 mclk;
1555 fixed20_12 needed_bandwidth;
1556 struct radeon_power_state *power_state;
1557 /* number of valid power states */
1558 int num_power_states;
1559 int current_power_state_index;
1560 int current_clock_mode_index;
1561 int requested_power_state_index;
1562 int requested_clock_mode_index;
1563 int default_power_state_index;
1564 u32 current_sclk;
1565 u32 current_mclk;
1566 u16 current_vddc;
1567 u16 current_vddci;
1568 u32 default_sclk;
1569 u32 default_mclk;
1570 u16 default_vddc;
1571 u16 default_vddci;
1572 struct radeon_i2c_chan *i2c_bus;
1573 /* selected pm method */
1574 enum radeon_pm_method pm_method;
1575 /* dynpm power management */
1576 struct delayed_work dynpm_idle_work;
1577 enum radeon_dynpm_state dynpm_state;
1578 enum radeon_dynpm_action dynpm_planned_action;
1579 unsigned long dynpm_action_timeout;
1580 bool dynpm_can_upclock;
1581 bool dynpm_can_downclock;
1582 /* profile-based power management */
1583 enum radeon_pm_profile_type profile;
1584 int profile_index;
1585 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1586 /* internal thermal controller on rv6xx+ */
1587 enum radeon_int_thermal_type int_thermal_type;
1588 struct device *int_hwmon_dev;
1589 /* dpm */
1590 bool dpm_enabled;
1591 struct radeon_dpm dpm;
1592 };
1593
1594 int radeon_pm_get_type_index(struct radeon_device *rdev,
1595 enum radeon_pm_state_type ps_type,
1596 int instance);
1597 /*
1598 * UVD
1599 */
1600 #define RADEON_MAX_UVD_HANDLES 10
1601 #define RADEON_UVD_STACK_SIZE (1024*1024)
1602 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1603
1604 struct radeon_uvd {
1605 struct radeon_bo *vcpu_bo;
1606 void *cpu_addr;
1607 uint64_t gpu_addr;
1608 void *saved_bo;
1609 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1610 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1611 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1612 struct delayed_work idle_work;
1613 };
1614
1615 int radeon_uvd_init(struct radeon_device *rdev);
1616 void radeon_uvd_fini(struct radeon_device *rdev);
1617 int radeon_uvd_suspend(struct radeon_device *rdev);
1618 int radeon_uvd_resume(struct radeon_device *rdev);
1619 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1620 uint32_t handle, struct radeon_fence **fence);
1621 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1622 uint32_t handle, struct radeon_fence **fence);
1623 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1624 void radeon_uvd_free_handles(struct radeon_device *rdev,
1625 struct drm_file *filp);
1626 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1627 void radeon_uvd_note_usage(struct radeon_device *rdev);
1628 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1629 unsigned vclk, unsigned dclk,
1630 unsigned vco_min, unsigned vco_max,
1631 unsigned fb_factor, unsigned fb_mask,
1632 unsigned pd_min, unsigned pd_max,
1633 unsigned pd_even,
1634 unsigned *optimal_fb_div,
1635 unsigned *optimal_vclk_div,
1636 unsigned *optimal_dclk_div);
1637 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1638 unsigned cg_upll_func_cntl);
1639
1640 /*
1641 * VCE
1642 */
1643 #define RADEON_MAX_VCE_HANDLES 16
1644 #define RADEON_VCE_STACK_SIZE (1024*1024)
1645 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1646
1647 struct radeon_vce {
1648 struct radeon_bo *vcpu_bo;
1649 uint64_t gpu_addr;
1650 unsigned fw_version;
1651 unsigned fb_version;
1652 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1653 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1654 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1655 struct delayed_work idle_work;
1656 };
1657
1658 int radeon_vce_init(struct radeon_device *rdev);
1659 void radeon_vce_fini(struct radeon_device *rdev);
1660 int radeon_vce_suspend(struct radeon_device *rdev);
1661 int radeon_vce_resume(struct radeon_device *rdev);
1662 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1663 uint32_t handle, struct radeon_fence **fence);
1664 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1665 uint32_t handle, struct radeon_fence **fence);
1666 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1667 void radeon_vce_note_usage(struct radeon_device *rdev);
1668 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1669 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1670 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1671 struct radeon_ring *ring,
1672 struct radeon_semaphore *semaphore,
1673 bool emit_wait);
1674 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1675 void radeon_vce_fence_emit(struct radeon_device *rdev,
1676 struct radeon_fence *fence);
1677 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1678 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1679
1680 struct r600_audio_pin {
1681 int channels;
1682 int rate;
1683 int bits_per_sample;
1684 u8 status_bits;
1685 u8 category_code;
1686 u32 offset;
1687 bool connected;
1688 u32 id;
1689 };
1690
1691 struct r600_audio {
1692 bool enabled;
1693 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1694 int num_pins;
1695 };
1696
1697 /*
1698 * Benchmarking
1699 */
1700 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1701
1702
1703 /*
1704 * Testing
1705 */
1706 void radeon_test_moves(struct radeon_device *rdev);
1707 void radeon_test_ring_sync(struct radeon_device *rdev,
1708 struct radeon_ring *cpA,
1709 struct radeon_ring *cpB);
1710 void radeon_test_syncing(struct radeon_device *rdev);
1711
1712
1713 /*
1714 * Debugfs
1715 */
1716 struct radeon_debugfs {
1717 struct drm_info_list *files;
1718 unsigned num_files;
1719 };
1720
1721 int radeon_debugfs_add_files(struct radeon_device *rdev,
1722 struct drm_info_list *files,
1723 unsigned nfiles);
1724 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1725
1726 /*
1727 * ASIC ring specific functions.
1728 */
1729 struct radeon_asic_ring {
1730 /* ring read/write ptr handling */
1731 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1732 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1733 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1734
1735 /* validating and patching of IBs */
1736 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1737 int (*cs_parse)(struct radeon_cs_parser *p);
1738
1739 /* command emmit functions */
1740 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1741 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1742 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1743 struct radeon_semaphore *semaphore, bool emit_wait);
1744 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1745
1746 /* testing functions */
1747 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1748 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1749 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1750
1751 /* deprecated */
1752 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1753 };
1754
1755 /*
1756 * ASIC specific functions.
1757 */
1758 struct radeon_asic {
1759 int (*init)(struct radeon_device *rdev);
1760 void (*fini)(struct radeon_device *rdev);
1761 int (*resume)(struct radeon_device *rdev);
1762 int (*suspend)(struct radeon_device *rdev);
1763 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1764 int (*asic_reset)(struct radeon_device *rdev);
1765 /* ioctl hw specific callback. Some hw might want to perform special
1766 * operation on specific ioctl. For instance on wait idle some hw
1767 * might want to perform and HDP flush through MMIO as it seems that
1768 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1769 * through ring.
1770 */
1771 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1772 /* check if 3D engine is idle */
1773 bool (*gui_idle)(struct radeon_device *rdev);
1774 /* wait for mc_idle */
1775 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1776 /* get the reference clock */
1777 u32 (*get_xclk)(struct radeon_device *rdev);
1778 /* get the gpu clock counter */
1779 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1780 /* gart */
1781 struct {
1782 void (*tlb_flush)(struct radeon_device *rdev);
1783 void (*set_page)(struct radeon_device *rdev, unsigned i,
1784 uint64_t addr);
1785 } gart;
1786 struct {
1787 int (*init)(struct radeon_device *rdev);
1788 void (*fini)(struct radeon_device *rdev);
1789 void (*set_page)(struct radeon_device *rdev,
1790 struct radeon_ib *ib,
1791 uint64_t pe,
1792 uint64_t addr, unsigned count,
1793 uint32_t incr, uint32_t flags);
1794 } vm;
1795 /* ring specific callbacks */
1796 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1797 /* irqs */
1798 struct {
1799 int (*set)(struct radeon_device *rdev);
1800 int (*process)(struct radeon_device *rdev);
1801 } irq;
1802 /* displays */
1803 struct {
1804 /* display watermarks */
1805 void (*bandwidth_update)(struct radeon_device *rdev);
1806 /* get frame count */
1807 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1808 /* wait for vblank */
1809 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1810 /* set backlight level */
1811 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1812 /* get backlight level */
1813 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1814 /* audio callbacks */
1815 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1816 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1817 } display;
1818 /* copy functions for bo handling */
1819 struct {
1820 int (*blit)(struct radeon_device *rdev,
1821 uint64_t src_offset,
1822 uint64_t dst_offset,
1823 unsigned num_gpu_pages,
1824 struct radeon_fence **fence);
1825 u32 blit_ring_index;
1826 int (*dma)(struct radeon_device *rdev,
1827 uint64_t src_offset,
1828 uint64_t dst_offset,
1829 unsigned num_gpu_pages,
1830 struct radeon_fence **fence);
1831 u32 dma_ring_index;
1832 /* method used for bo copy */
1833 int (*copy)(struct radeon_device *rdev,
1834 uint64_t src_offset,
1835 uint64_t dst_offset,
1836 unsigned num_gpu_pages,
1837 struct radeon_fence **fence);
1838 /* ring used for bo copies */
1839 u32 copy_ring_index;
1840 } copy;
1841 /* surfaces */
1842 struct {
1843 int (*set_reg)(struct radeon_device *rdev, int reg,
1844 uint32_t tiling_flags, uint32_t pitch,
1845 uint32_t offset, uint32_t obj_size);
1846 void (*clear_reg)(struct radeon_device *rdev, int reg);
1847 } surface;
1848 /* hotplug detect */
1849 struct {
1850 void (*init)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1853 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1854 } hpd;
1855 /* static power management */
1856 struct {
1857 void (*misc)(struct radeon_device *rdev);
1858 void (*prepare)(struct radeon_device *rdev);
1859 void (*finish)(struct radeon_device *rdev);
1860 void (*init_profile)(struct radeon_device *rdev);
1861 void (*get_dynpm_state)(struct radeon_device *rdev);
1862 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1863 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1864 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1865 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1866 int (*get_pcie_lanes)(struct radeon_device *rdev);
1867 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1868 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1869 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1870 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1871 int (*get_temperature)(struct radeon_device *rdev);
1872 } pm;
1873 /* dynamic power management */
1874 struct {
1875 int (*init)(struct radeon_device *rdev);
1876 void (*setup_asic)(struct radeon_device *rdev);
1877 int (*enable)(struct radeon_device *rdev);
1878 int (*late_enable)(struct radeon_device *rdev);
1879 void (*disable)(struct radeon_device *rdev);
1880 int (*pre_set_power_state)(struct radeon_device *rdev);
1881 int (*set_power_state)(struct radeon_device *rdev);
1882 void (*post_set_power_state)(struct radeon_device *rdev);
1883 void (*display_configuration_changed)(struct radeon_device *rdev);
1884 void (*fini)(struct radeon_device *rdev);
1885 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1886 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1887 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1888 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1889 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1890 bool (*vblank_too_short)(struct radeon_device *rdev);
1891 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1892 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1893 } dpm;
1894 /* pageflipping */
1895 struct {
1896 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1897 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1898 } pflip;
1899 };
1900
1901 /*
1902 * Asic structures
1903 */
1904 struct r100_asic {
1905 const unsigned *reg_safe_bm;
1906 unsigned reg_safe_bm_size;
1907 u32 hdp_cntl;
1908 };
1909
1910 struct r300_asic {
1911 const unsigned *reg_safe_bm;
1912 unsigned reg_safe_bm_size;
1913 u32 resync_scratch;
1914 u32 hdp_cntl;
1915 };
1916
1917 struct r600_asic {
1918 unsigned max_pipes;
1919 unsigned max_tile_pipes;
1920 unsigned max_simds;
1921 unsigned max_backends;
1922 unsigned max_gprs;
1923 unsigned max_threads;
1924 unsigned max_stack_entries;
1925 unsigned max_hw_contexts;
1926 unsigned max_gs_threads;
1927 unsigned sx_max_export_size;
1928 unsigned sx_max_export_pos_size;
1929 unsigned sx_max_export_smx_size;
1930 unsigned sq_num_cf_insts;
1931 unsigned tiling_nbanks;
1932 unsigned tiling_npipes;
1933 unsigned tiling_group_size;
1934 unsigned tile_config;
1935 unsigned backend_map;
1936 unsigned active_simds;
1937 };
1938
1939 struct rv770_asic {
1940 unsigned max_pipes;
1941 unsigned max_tile_pipes;
1942 unsigned max_simds;
1943 unsigned max_backends;
1944 unsigned max_gprs;
1945 unsigned max_threads;
1946 unsigned max_stack_entries;
1947 unsigned max_hw_contexts;
1948 unsigned max_gs_threads;
1949 unsigned sx_max_export_size;
1950 unsigned sx_max_export_pos_size;
1951 unsigned sx_max_export_smx_size;
1952 unsigned sq_num_cf_insts;
1953 unsigned sx_num_of_sets;
1954 unsigned sc_prim_fifo_size;
1955 unsigned sc_hiz_tile_fifo_size;
1956 unsigned sc_earlyz_tile_fifo_fize;
1957 unsigned tiling_nbanks;
1958 unsigned tiling_npipes;
1959 unsigned tiling_group_size;
1960 unsigned tile_config;
1961 unsigned backend_map;
1962 unsigned active_simds;
1963 };
1964
1965 struct evergreen_asic {
1966 unsigned num_ses;
1967 unsigned max_pipes;
1968 unsigned max_tile_pipes;
1969 unsigned max_simds;
1970 unsigned max_backends;
1971 unsigned max_gprs;
1972 unsigned max_threads;
1973 unsigned max_stack_entries;
1974 unsigned max_hw_contexts;
1975 unsigned max_gs_threads;
1976 unsigned sx_max_export_size;
1977 unsigned sx_max_export_pos_size;
1978 unsigned sx_max_export_smx_size;
1979 unsigned sq_num_cf_insts;
1980 unsigned sx_num_of_sets;
1981 unsigned sc_prim_fifo_size;
1982 unsigned sc_hiz_tile_fifo_size;
1983 unsigned sc_earlyz_tile_fifo_size;
1984 unsigned tiling_nbanks;
1985 unsigned tiling_npipes;
1986 unsigned tiling_group_size;
1987 unsigned tile_config;
1988 unsigned backend_map;
1989 unsigned active_simds;
1990 };
1991
1992 struct cayman_asic {
1993 unsigned max_shader_engines;
1994 unsigned max_pipes_per_simd;
1995 unsigned max_tile_pipes;
1996 unsigned max_simds_per_se;
1997 unsigned max_backends_per_se;
1998 unsigned max_texture_channel_caches;
1999 unsigned max_gprs;
2000 unsigned max_threads;
2001 unsigned max_gs_threads;
2002 unsigned max_stack_entries;
2003 unsigned sx_num_of_sets;
2004 unsigned sx_max_export_size;
2005 unsigned sx_max_export_pos_size;
2006 unsigned sx_max_export_smx_size;
2007 unsigned max_hw_contexts;
2008 unsigned sq_num_cf_insts;
2009 unsigned sc_prim_fifo_size;
2010 unsigned sc_hiz_tile_fifo_size;
2011 unsigned sc_earlyz_tile_fifo_size;
2012
2013 unsigned num_shader_engines;
2014 unsigned num_shader_pipes_per_simd;
2015 unsigned num_tile_pipes;
2016 unsigned num_simds_per_se;
2017 unsigned num_backends_per_se;
2018 unsigned backend_disable_mask_per_asic;
2019 unsigned backend_map;
2020 unsigned num_texture_channel_caches;
2021 unsigned mem_max_burst_length_bytes;
2022 unsigned mem_row_size_in_kb;
2023 unsigned shader_engine_tile_size;
2024 unsigned num_gpus;
2025 unsigned multi_gpu_tile_size;
2026
2027 unsigned tile_config;
2028 unsigned active_simds;
2029 };
2030
2031 struct si_asic {
2032 unsigned max_shader_engines;
2033 unsigned max_tile_pipes;
2034 unsigned max_cu_per_sh;
2035 unsigned max_sh_per_se;
2036 unsigned max_backends_per_se;
2037 unsigned max_texture_channel_caches;
2038 unsigned max_gprs;
2039 unsigned max_gs_threads;
2040 unsigned max_hw_contexts;
2041 unsigned sc_prim_fifo_size_frontend;
2042 unsigned sc_prim_fifo_size_backend;
2043 unsigned sc_hiz_tile_fifo_size;
2044 unsigned sc_earlyz_tile_fifo_size;
2045
2046 unsigned num_tile_pipes;
2047 unsigned backend_enable_mask;
2048 unsigned backend_disable_mask_per_asic;
2049 unsigned backend_map;
2050 unsigned num_texture_channel_caches;
2051 unsigned mem_max_burst_length_bytes;
2052 unsigned mem_row_size_in_kb;
2053 unsigned shader_engine_tile_size;
2054 unsigned num_gpus;
2055 unsigned multi_gpu_tile_size;
2056
2057 unsigned tile_config;
2058 uint32_t tile_mode_array[32];
2059 uint32_t active_cus;
2060 };
2061
2062 struct cik_asic {
2063 unsigned max_shader_engines;
2064 unsigned max_tile_pipes;
2065 unsigned max_cu_per_sh;
2066 unsigned max_sh_per_se;
2067 unsigned max_backends_per_se;
2068 unsigned max_texture_channel_caches;
2069 unsigned max_gprs;
2070 unsigned max_gs_threads;
2071 unsigned max_hw_contexts;
2072 unsigned sc_prim_fifo_size_frontend;
2073 unsigned sc_prim_fifo_size_backend;
2074 unsigned sc_hiz_tile_fifo_size;
2075 unsigned sc_earlyz_tile_fifo_size;
2076
2077 unsigned num_tile_pipes;
2078 unsigned backend_enable_mask;
2079 unsigned backend_disable_mask_per_asic;
2080 unsigned backend_map;
2081 unsigned num_texture_channel_caches;
2082 unsigned mem_max_burst_length_bytes;
2083 unsigned mem_row_size_in_kb;
2084 unsigned shader_engine_tile_size;
2085 unsigned num_gpus;
2086 unsigned multi_gpu_tile_size;
2087
2088 unsigned tile_config;
2089 uint32_t tile_mode_array[32];
2090 uint32_t macrotile_mode_array[16];
2091 uint32_t active_cus;
2092 };
2093
2094 union radeon_asic_config {
2095 struct r300_asic r300;
2096 struct r100_asic r100;
2097 struct r600_asic r600;
2098 struct rv770_asic rv770;
2099 struct evergreen_asic evergreen;
2100 struct cayman_asic cayman;
2101 struct si_asic si;
2102 struct cik_asic cik;
2103 };
2104
2105 /*
2106 * asic initizalization from radeon_asic.c
2107 */
2108 void radeon_agp_disable(struct radeon_device *rdev);
2109 int radeon_asic_init(struct radeon_device *rdev);
2110
2111
2112 /*
2113 * IOCTL.
2114 */
2115 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2116 struct drm_file *filp);
2117 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2118 struct drm_file *filp);
2119 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *file_priv);
2121 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *file_priv);
2123 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2124 struct drm_file *file_priv);
2125 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *file_priv);
2127 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2129 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2130 struct drm_file *filp);
2131 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *filp);
2133 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *filp);
2135 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *filp);
2137 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *filp);
2139 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2140 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2141 struct drm_file *filp);
2142 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2143 struct drm_file *filp);
2144
2145 /* VRAM scratch page for HDP bug, default vram page */
2146 struct r600_vram_scratch {
2147 struct radeon_bo *robj;
2148 volatile uint32_t *ptr;
2149 u64 gpu_addr;
2150 };
2151
2152 /*
2153 * ACPI
2154 */
2155 struct radeon_atif_notification_cfg {
2156 bool enabled;
2157 int command_code;
2158 };
2159
2160 struct radeon_atif_notifications {
2161 bool display_switch;
2162 bool expansion_mode_change;
2163 bool thermal_state;
2164 bool forced_power_state;
2165 bool system_power_state;
2166 bool display_conf_change;
2167 bool px_gfx_switch;
2168 bool brightness_change;
2169 bool dgpu_display_event;
2170 };
2171
2172 struct radeon_atif_functions {
2173 bool system_params;
2174 bool sbios_requests;
2175 bool select_active_disp;
2176 bool lid_state;
2177 bool get_tv_standard;
2178 bool set_tv_standard;
2179 bool get_panel_expansion_mode;
2180 bool set_panel_expansion_mode;
2181 bool temperature_change;
2182 bool graphics_device_types;
2183 };
2184
2185 struct radeon_atif {
2186 struct radeon_atif_notifications notifications;
2187 struct radeon_atif_functions functions;
2188 struct radeon_atif_notification_cfg notification_cfg;
2189 struct radeon_encoder *encoder_for_bl;
2190 };
2191
2192 struct radeon_atcs_functions {
2193 bool get_ext_state;
2194 bool pcie_perf_req;
2195 bool pcie_dev_rdy;
2196 bool pcie_bus_width;
2197 };
2198
2199 struct radeon_atcs {
2200 struct radeon_atcs_functions functions;
2201 };
2202
2203 /*
2204 * Core structure, functions and helpers.
2205 */
2206 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2207 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2208
2209 struct radeon_device {
2210 struct device *dev;
2211 struct drm_device *ddev;
2212 struct pci_dev *pdev;
2213 struct rw_semaphore exclusive_lock;
2214 /* ASIC */
2215 union radeon_asic_config config;
2216 enum radeon_family family;
2217 unsigned long flags;
2218 int usec_timeout;
2219 enum radeon_pll_errata pll_errata;
2220 int num_gb_pipes;
2221 int num_z_pipes;
2222 int disp_priority;
2223 /* BIOS */
2224 uint8_t *bios;
2225 bool is_atom_bios;
2226 uint16_t bios_header_start;
2227 struct radeon_bo *stollen_vga_memory;
2228 /* Register mmio */
2229 resource_size_t rmmio_base;
2230 resource_size_t rmmio_size;
2231 /* protects concurrent MM_INDEX/DATA based register access */
2232 spinlock_t mmio_idx_lock;
2233 /* protects concurrent SMC based register access */
2234 spinlock_t smc_idx_lock;
2235 /* protects concurrent PLL register access */
2236 spinlock_t pll_idx_lock;
2237 /* protects concurrent MC register access */
2238 spinlock_t mc_idx_lock;
2239 /* protects concurrent PCIE register access */
2240 spinlock_t pcie_idx_lock;
2241 /* protects concurrent PCIE_PORT register access */
2242 spinlock_t pciep_idx_lock;
2243 /* protects concurrent PIF register access */
2244 spinlock_t pif_idx_lock;
2245 /* protects concurrent CG register access */
2246 spinlock_t cg_idx_lock;
2247 /* protects concurrent UVD register access */
2248 spinlock_t uvd_idx_lock;
2249 /* protects concurrent RCU register access */
2250 spinlock_t rcu_idx_lock;
2251 /* protects concurrent DIDT register access */
2252 spinlock_t didt_idx_lock;
2253 /* protects concurrent ENDPOINT (audio) register access */
2254 spinlock_t end_idx_lock;
2255 void __iomem *rmmio;
2256 radeon_rreg_t mc_rreg;
2257 radeon_wreg_t mc_wreg;
2258 radeon_rreg_t pll_rreg;
2259 radeon_wreg_t pll_wreg;
2260 uint32_t pcie_reg_mask;
2261 radeon_rreg_t pciep_rreg;
2262 radeon_wreg_t pciep_wreg;
2263 /* io port */
2264 void __iomem *rio_mem;
2265 resource_size_t rio_mem_size;
2266 struct radeon_clock clock;
2267 struct radeon_mc mc;
2268 struct radeon_gart gart;
2269 struct radeon_mode_info mode_info;
2270 struct radeon_scratch scratch;
2271 struct radeon_doorbell doorbell;
2272 struct radeon_mman mman;
2273 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2274 wait_queue_head_t fence_queue;
2275 struct mutex ring_lock;
2276 struct radeon_ring ring[RADEON_NUM_RINGS];
2277 bool ib_pool_ready;
2278 struct radeon_sa_manager ring_tmp_bo;
2279 struct radeon_irq irq;
2280 struct radeon_asic *asic;
2281 struct radeon_gem gem;
2282 struct radeon_pm pm;
2283 struct radeon_uvd uvd;
2284 struct radeon_vce vce;
2285 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2286 struct radeon_wb wb;
2287 struct radeon_dummy_page dummy_page;
2288 bool shutdown;
2289 bool suspend;
2290 bool need_dma32;
2291 bool accel_working;
2292 bool fastfb_working; /* IGP feature*/
2293 bool needs_reset;
2294 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2295 const struct firmware *me_fw; /* all family ME firmware */
2296 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2297 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2298 const struct firmware *mc_fw; /* NI MC firmware */
2299 const struct firmware *ce_fw; /* SI CE firmware */
2300 const struct firmware *mec_fw; /* CIK MEC firmware */
2301 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2302 const struct firmware *smc_fw; /* SMC firmware */
2303 const struct firmware *uvd_fw; /* UVD firmware */
2304 const struct firmware *vce_fw; /* VCE firmware */
2305 struct r600_vram_scratch vram_scratch;
2306 int msi_enabled; /* msi enabled */
2307 struct r600_ih ih; /* r6/700 interrupt ring */
2308 struct radeon_rlc rlc;
2309 struct radeon_mec mec;
2310 struct work_struct hotplug_work;
2311 struct work_struct audio_work;
2312 struct work_struct reset_work;
2313 int num_crtc; /* number of crtcs */
2314 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2315 bool has_uvd;
2316 struct r600_audio audio; /* audio stuff */
2317 struct notifier_block acpi_nb;
2318 /* only one userspace can use Hyperz features or CMASK at a time */
2319 struct drm_file *hyperz_filp;
2320 struct drm_file *cmask_filp;
2321 /* i2c buses */
2322 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2323 /* debugfs */
2324 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2325 unsigned debugfs_count;
2326 /* virtual memory */
2327 struct radeon_vm_manager vm_manager;
2328 struct mutex gpu_clock_mutex;
2329 /* memory stats */
2330 atomic64_t vram_usage;
2331 atomic64_t gtt_usage;
2332 atomic64_t num_bytes_moved;
2333 /* ACPI interface */
2334 struct radeon_atif atif;
2335 struct radeon_atcs atcs;
2336 /* srbm instance registers */
2337 struct mutex srbm_mutex;
2338 /* clock, powergating flags */
2339 u32 cg_flags;
2340 u32 pg_flags;
2341
2342 struct dev_pm_domain vga_pm_domain;
2343 bool have_disp_power_ref;
2344 };
2345
2346 bool radeon_is_px(struct drm_device *dev);
2347 int radeon_device_init(struct radeon_device *rdev,
2348 struct drm_device *ddev,
2349 struct pci_dev *pdev,
2350 uint32_t flags);
2351 void radeon_device_fini(struct radeon_device *rdev);
2352 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2353
2354 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2355 bool always_indirect);
2356 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2357 bool always_indirect);
2358 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2359 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2360
2361 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2362 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2363
2364 /*
2365 * Cast helper
2366 */
2367 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2368
2369 /*
2370 * Registers read & write functions.
2371 */
2372 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2373 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2374 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2375 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2376 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2377 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2378 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2379 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2380 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2381 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2382 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2383 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2384 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2385 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2386 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2387 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2388 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2389 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2390 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2391 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2392 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2393 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2394 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2395 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2396 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2397 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2398 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2399 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2400 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2401 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2402 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2403 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2404 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2405 #define WREG32_P(reg, val, mask) \
2406 do { \
2407 uint32_t tmp_ = RREG32(reg); \
2408 tmp_ &= (mask); \
2409 tmp_ |= ((val) & ~(mask)); \
2410 WREG32(reg, tmp_); \
2411 } while (0)
2412 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2413 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2414 #define WREG32_PLL_P(reg, val, mask) \
2415 do { \
2416 uint32_t tmp_ = RREG32_PLL(reg); \
2417 tmp_ &= (mask); \
2418 tmp_ |= ((val) & ~(mask)); \
2419 WREG32_PLL(reg, tmp_); \
2420 } while (0)
2421 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2422 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2423 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2424
2425 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2426 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2427
2428 /*
2429 * Indirect registers accessor
2430 */
2431 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2432 {
2433 unsigned long flags;
2434 uint32_t r;
2435
2436 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2437 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2438 r = RREG32(RADEON_PCIE_DATA);
2439 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2440 return r;
2441 }
2442
2443 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2444 {
2445 unsigned long flags;
2446
2447 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2448 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2449 WREG32(RADEON_PCIE_DATA, (v));
2450 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2451 }
2452
2453 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2454 {
2455 unsigned long flags;
2456 u32 r;
2457
2458 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2459 WREG32(TN_SMC_IND_INDEX_0, (reg));
2460 r = RREG32(TN_SMC_IND_DATA_0);
2461 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2462 return r;
2463 }
2464
2465 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2466 {
2467 unsigned long flags;
2468
2469 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2470 WREG32(TN_SMC_IND_INDEX_0, (reg));
2471 WREG32(TN_SMC_IND_DATA_0, (v));
2472 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2473 }
2474
2475 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2476 {
2477 unsigned long flags;
2478 u32 r;
2479
2480 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2481 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2482 r = RREG32(R600_RCU_DATA);
2483 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2484 return r;
2485 }
2486
2487 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2488 {
2489 unsigned long flags;
2490
2491 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2492 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2493 WREG32(R600_RCU_DATA, (v));
2494 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2495 }
2496
2497 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2498 {
2499 unsigned long flags;
2500 u32 r;
2501
2502 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2503 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2504 r = RREG32(EVERGREEN_CG_IND_DATA);
2505 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2506 return r;
2507 }
2508
2509 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2510 {
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2514 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2515 WREG32(EVERGREEN_CG_IND_DATA, (v));
2516 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2517 }
2518
2519 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2520 {
2521 unsigned long flags;
2522 u32 r;
2523
2524 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2525 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2526 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2527 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2528 return r;
2529 }
2530
2531 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2532 {
2533 unsigned long flags;
2534
2535 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2536 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2537 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2538 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2539 }
2540
2541 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2542 {
2543 unsigned long flags;
2544 u32 r;
2545
2546 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2547 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2548 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2549 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2550 return r;
2551 }
2552
2553 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2554 {
2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2558 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2559 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2560 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2561 }
2562
2563 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2564 {
2565 unsigned long flags;
2566 u32 r;
2567
2568 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2569 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2570 r = RREG32(R600_UVD_CTX_DATA);
2571 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2572 return r;
2573 }
2574
2575 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2576 {
2577 unsigned long flags;
2578
2579 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2580 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2581 WREG32(R600_UVD_CTX_DATA, (v));
2582 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2583 }
2584
2585
2586 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2587 {
2588 unsigned long flags;
2589 u32 r;
2590
2591 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2592 WREG32(CIK_DIDT_IND_INDEX, (reg));
2593 r = RREG32(CIK_DIDT_IND_DATA);
2594 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2595 return r;
2596 }
2597
2598 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2599 {
2600 unsigned long flags;
2601
2602 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2603 WREG32(CIK_DIDT_IND_INDEX, (reg));
2604 WREG32(CIK_DIDT_IND_DATA, (v));
2605 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2606 }
2607
2608 void r100_pll_errata_after_index(struct radeon_device *rdev);
2609
2610
2611 /*
2612 * ASICs helpers.
2613 */
2614 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2615 (rdev->pdev->device == 0x5969))
2616 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2617 (rdev->family == CHIP_RV200) || \
2618 (rdev->family == CHIP_RS100) || \
2619 (rdev->family == CHIP_RS200) || \
2620 (rdev->family == CHIP_RV250) || \
2621 (rdev->family == CHIP_RV280) || \
2622 (rdev->family == CHIP_RS300))
2623 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2624 (rdev->family == CHIP_RV350) || \
2625 (rdev->family == CHIP_R350) || \
2626 (rdev->family == CHIP_RV380) || \
2627 (rdev->family == CHIP_R420) || \
2628 (rdev->family == CHIP_R423) || \
2629 (rdev->family == CHIP_RV410) || \
2630 (rdev->family == CHIP_RS400) || \
2631 (rdev->family == CHIP_RS480))
2632 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2633 (rdev->ddev->pdev->device == 0x9443) || \
2634 (rdev->ddev->pdev->device == 0x944B) || \
2635 (rdev->ddev->pdev->device == 0x9506) || \
2636 (rdev->ddev->pdev->device == 0x9509) || \
2637 (rdev->ddev->pdev->device == 0x950F) || \
2638 (rdev->ddev->pdev->device == 0x689C) || \
2639 (rdev->ddev->pdev->device == 0x689D))
2640 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2641 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2642 (rdev->family == CHIP_RS690) || \
2643 (rdev->family == CHIP_RS740) || \
2644 (rdev->family >= CHIP_R600))
2645 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2646 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2647 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2648 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2649 (rdev->flags & RADEON_IS_IGP))
2650 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2651 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2652 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2653 (rdev->flags & RADEON_IS_IGP))
2654 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2655 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2656 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2657 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2658 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2659 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2660 (rdev->family == CHIP_MULLINS))
2661
2662 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2663 (rdev->ddev->pdev->device == 0x6850) || \
2664 (rdev->ddev->pdev->device == 0x6858) || \
2665 (rdev->ddev->pdev->device == 0x6859) || \
2666 (rdev->ddev->pdev->device == 0x6840) || \
2667 (rdev->ddev->pdev->device == 0x6841) || \
2668 (rdev->ddev->pdev->device == 0x6842) || \
2669 (rdev->ddev->pdev->device == 0x6843))
2670
2671 /*
2672 * BIOS helpers.
2673 */
2674 #define RBIOS8(i) (rdev->bios[i])
2675 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2676 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2677
2678 int radeon_combios_init(struct radeon_device *rdev);
2679 void radeon_combios_fini(struct radeon_device *rdev);
2680 int radeon_atombios_init(struct radeon_device *rdev);
2681 void radeon_atombios_fini(struct radeon_device *rdev);
2682
2683
2684 /*
2685 * RING helpers.
2686 */
2687 #if DRM_DEBUG_CODE == 0
2688 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2689 {
2690 ring->ring[ring->wptr++] = v;
2691 ring->wptr &= ring->ptr_mask;
2692 ring->count_dw--;
2693 ring->ring_free_dw--;
2694 }
2695 #else
2696 /* With debugging this is just too big to inline */
2697 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2698 #endif
2699
2700 /*
2701 * ASICs macro.
2702 */
2703 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2704 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2705 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2706 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2707 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2708 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2709 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2710 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2711 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2712 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2713 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2714 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2715 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2716 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2717 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2718 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2719 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2720 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2721 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2722 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2723 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2724 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2725 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2726 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2727 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2728 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2729 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2730 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2731 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2732 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2733 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2734 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2735 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2736 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2737 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2738 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2739 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2740 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2741 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2742 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2743 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2744 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2745 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2746 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2747 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2748 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2749 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2750 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2751 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2752 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2753 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2754 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2755 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2756 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2757 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2758 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2759 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2760 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2761 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2762 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2763 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2764 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2765 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2766 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2767 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2768 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2769 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2770 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2771 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2772 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2773 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2774 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2775 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2776 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2777 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2778 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2779 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2780 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2781 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2782 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2783 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2784 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2785 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2786 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2787
2788 /* Common functions */
2789 /* AGP */
2790 extern int radeon_gpu_reset(struct radeon_device *rdev);
2791 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2792 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2793 extern void radeon_agp_disable(struct radeon_device *rdev);
2794 extern int radeon_modeset_init(struct radeon_device *rdev);
2795 extern void radeon_modeset_fini(struct radeon_device *rdev);
2796 extern bool radeon_card_posted(struct radeon_device *rdev);
2797 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2798 extern void radeon_update_display_priority(struct radeon_device *rdev);
2799 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2800 extern void radeon_scratch_init(struct radeon_device *rdev);
2801 extern void radeon_wb_fini(struct radeon_device *rdev);
2802 extern int radeon_wb_init(struct radeon_device *rdev);
2803 extern void radeon_wb_disable(struct radeon_device *rdev);
2804 extern void radeon_surface_init(struct radeon_device *rdev);
2805 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2806 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2807 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2808 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2809 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2810 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2811 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2812 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2813 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2814 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2815 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2816 const u32 *registers,
2817 const u32 array_size);
2818
2819 /*
2820 * vm
2821 */
2822 int radeon_vm_manager_init(struct radeon_device *rdev);
2823 void radeon_vm_manager_fini(struct radeon_device *rdev);
2824 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2825 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2826 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 struct list_head *head);
2829 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2830 struct radeon_vm *vm, int ring);
2831 void radeon_vm_flush(struct radeon_device *rdev,
2832 struct radeon_vm *vm,
2833 int ring);
2834 void radeon_vm_fence(struct radeon_device *rdev,
2835 struct radeon_vm *vm,
2836 struct radeon_fence *fence);
2837 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2838 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2839 struct radeon_vm *vm);
2840 int radeon_vm_bo_update(struct radeon_device *rdev,
2841 struct radeon_vm *vm,
2842 struct radeon_bo *bo,
2843 struct ttm_mem_reg *mem);
2844 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2845 struct radeon_bo *bo);
2846 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2847 struct radeon_bo *bo);
2848 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2849 struct radeon_vm *vm,
2850 struct radeon_bo *bo);
2851 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2852 struct radeon_bo_va *bo_va,
2853 uint64_t offset,
2854 uint32_t flags);
2855 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2856 struct radeon_bo_va *bo_va);
2857
2858 /* audio */
2859 void r600_audio_update_hdmi(struct work_struct *work);
2860 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2861 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2862 void r600_audio_enable(struct radeon_device *rdev,
2863 struct r600_audio_pin *pin,
2864 bool enable);
2865 void dce6_audio_enable(struct radeon_device *rdev,
2866 struct r600_audio_pin *pin,
2867 bool enable);
2868
2869 /*
2870 * R600 vram scratch functions
2871 */
2872 int r600_vram_scratch_init(struct radeon_device *rdev);
2873 void r600_vram_scratch_fini(struct radeon_device *rdev);
2874
2875 /*
2876 * r600 cs checking helper
2877 */
2878 unsigned r600_mip_minify(unsigned size, unsigned level);
2879 bool r600_fmt_is_valid_color(u32 format);
2880 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2881 int r600_fmt_get_blocksize(u32 format);
2882 int r600_fmt_get_nblocksx(u32 format, u32 w);
2883 int r600_fmt_get_nblocksy(u32 format, u32 h);
2884
2885 /*
2886 * r600 functions used by radeon_encoder.c
2887 */
2888 struct radeon_hdmi_acr {
2889 u32 clock;
2890
2891 int n_32khz;
2892 int cts_32khz;
2893
2894 int n_44_1khz;
2895 int cts_44_1khz;
2896
2897 int n_48khz;
2898 int cts_48khz;
2899
2900 };
2901
2902 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2903
2904 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2905 u32 tiling_pipe_num,
2906 u32 max_rb_num,
2907 u32 total_max_rb_num,
2908 u32 enabled_rb_mask);
2909
2910 /*
2911 * evergreen functions used by radeon_encoder.c
2912 */
2913
2914 extern int ni_init_microcode(struct radeon_device *rdev);
2915 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2916
2917 /* radeon_acpi.c */
2918 #if defined(CONFIG_ACPI)
2919 extern int radeon_acpi_init(struct radeon_device *rdev);
2920 extern void radeon_acpi_fini(struct radeon_device *rdev);
2921 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2922 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2923 u8 perf_req, bool advertise);
2924 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2925 #else
2926 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2927 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2928 #endif
2929
2930 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2931 struct radeon_cs_packet *pkt,
2932 unsigned idx);
2933 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2934 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2935 struct radeon_cs_packet *pkt);
2936 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2937 struct radeon_cs_reloc **cs_reloc,
2938 int nomm);
2939 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2940 uint32_t *vline_start_end,
2941 uint32_t *vline_status);
2942
2943 #include "radeon_object.h"
2944
2945 #endif
Linux kernel - Deliverables
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