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drm/radeon/kms: add dpm support for SI (v7)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100
101 /*
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 * symbol;
104 */
105 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
107 /* RADEON_IB_POOL_SIZE must be a power of 2 */
108 #define RADEON_IB_POOL_SIZE 16
109 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
110 #define RADEONFB_CONN_LIMIT 4
111 #define RADEON_BIOS_NUM_SCRATCH 8
112
113 /* max number of rings */
114 #define RADEON_NUM_RINGS 6
115
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
122
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132 /* R600+ */
133 #define R600_RING_TYPE_UVD_INDEX 5
134
135 /* hardcode those limit for now */
136 #define RADEON_VA_IB_OFFSET (1 << 20)
137 #define RADEON_VA_RESERVED_SIZE (8 << 20)
138 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
139
140 /* reset flags */
141 #define RADEON_RESET_GFX (1 << 0)
142 #define RADEON_RESET_COMPUTE (1 << 1)
143 #define RADEON_RESET_DMA (1 << 2)
144 #define RADEON_RESET_CP (1 << 3)
145 #define RADEON_RESET_GRBM (1 << 4)
146 #define RADEON_RESET_DMA1 (1 << 5)
147 #define RADEON_RESET_RLC (1 << 6)
148 #define RADEON_RESET_SEM (1 << 7)
149 #define RADEON_RESET_IH (1 << 8)
150 #define RADEON_RESET_VMC (1 << 9)
151 #define RADEON_RESET_MC (1 << 10)
152 #define RADEON_RESET_DISPLAY (1 << 11)
153
154 /* max cursor sizes (in pixels) */
155 #define CURSOR_WIDTH 64
156 #define CURSOR_HEIGHT 64
157
158 #define CIK_CURSOR_WIDTH 128
159 #define CIK_CURSOR_HEIGHT 128
160
161 /*
162 * Errata workarounds.
163 */
164 enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
168 };
169
170
171 struct radeon_device;
172
173
174 /*
175 * BIOS.
176 */
177 bool radeon_get_bios(struct radeon_device *rdev);
178
179 /*
180 * Dummy page
181 */
182 struct radeon_dummy_page {
183 struct page *page;
184 dma_addr_t addr;
185 };
186 int radeon_dummy_page_init(struct radeon_device *rdev);
187 void radeon_dummy_page_fini(struct radeon_device *rdev);
188
189
190 /*
191 * Clocks
192 */
193 struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
196 struct radeon_pll dcpll;
197 struct radeon_pll spll;
198 struct radeon_pll mpll;
199 /* 10 Khz units */
200 uint32_t default_mclk;
201 uint32_t default_sclk;
202 uint32_t default_dispclk;
203 uint32_t current_dispclk;
204 uint32_t dp_extclk;
205 uint32_t max_pixel_clock;
206 };
207
208 /*
209 * Power management
210 */
211 int radeon_pm_init(struct radeon_device *rdev);
212 void radeon_pm_fini(struct radeon_device *rdev);
213 void radeon_pm_compute_clocks(struct radeon_device *rdev);
214 void radeon_pm_suspend(struct radeon_device *rdev);
215 void radeon_pm_resume(struct radeon_device *rdev);
216 void radeon_combios_get_power_modes(struct radeon_device *rdev);
217 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
218 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
219 u8 clock_type,
220 u32 clock,
221 bool strobe_mode,
222 struct atom_clock_dividers *dividers);
223 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
224 u32 clock,
225 bool strobe_mode,
226 struct atom_mpll_param *mpll_param);
227 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
228 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
229 u16 voltage_level, u8 voltage_type,
230 u32 *gpio_value, u32 *gpio_mask);
231 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
232 u32 eng_clock, u32 mem_clock);
233 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
234 u8 voltage_type, u16 *voltage_step);
235 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
236 u16 voltage_id, u16 *voltage);
237 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
238 u16 *voltage,
239 u16 leakage_idx);
240 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
241 u8 voltage_type,
242 u16 nominal_voltage,
243 u16 *true_voltage);
244 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
245 u8 voltage_type, u16 *min_voltage);
246 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
247 u8 voltage_type, u16 *max_voltage);
248 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
249 u8 voltage_type, u8 voltage_mode,
250 struct atom_voltage_table *voltage_table);
251 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
252 u8 voltage_type, u8 voltage_mode);
253 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
254 u32 mem_clock);
255 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
256 u32 mem_clock);
257 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
258 u8 module_index,
259 struct atom_mc_reg_table *reg_table);
260 int radeon_atom_get_memory_info(struct radeon_device *rdev,
261 u8 module_index, struct atom_memory_info *mem_info);
262 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
263 bool gddr5, u8 module_index,
264 struct atom_memory_clock_range_table *mclk_range_table);
265 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
266 u16 voltage_id, u16 *voltage);
267 void rs690_pm_info(struct radeon_device *rdev);
268 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
269 unsigned *bankh, unsigned *mtaspect,
270 unsigned *tile_split);
271
272 /*
273 * Fences.
274 */
275 struct radeon_fence_driver {
276 uint32_t scratch_reg;
277 uint64_t gpu_addr;
278 volatile uint32_t *cpu_addr;
279 /* sync_seq is protected by ring emission lock */
280 uint64_t sync_seq[RADEON_NUM_RINGS];
281 atomic64_t last_seq;
282 unsigned long last_activity;
283 bool initialized;
284 };
285
286 struct radeon_fence {
287 struct radeon_device *rdev;
288 struct kref kref;
289 /* protected by radeon_fence.lock */
290 uint64_t seq;
291 /* RB, DMA, etc. */
292 unsigned ring;
293 };
294
295 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
296 int radeon_fence_driver_init(struct radeon_device *rdev);
297 void radeon_fence_driver_fini(struct radeon_device *rdev);
298 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
299 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
300 void radeon_fence_process(struct radeon_device *rdev, int ring);
301 bool radeon_fence_signaled(struct radeon_fence *fence);
302 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
303 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
304 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
305 int radeon_fence_wait_any(struct radeon_device *rdev,
306 struct radeon_fence **fences,
307 bool intr);
308 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
309 void radeon_fence_unref(struct radeon_fence **fence);
310 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
311 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
312 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
313 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
314 struct radeon_fence *b)
315 {
316 if (!a) {
317 return b;
318 }
319
320 if (!b) {
321 return a;
322 }
323
324 BUG_ON(a->ring != b->ring);
325
326 if (a->seq > b->seq) {
327 return a;
328 } else {
329 return b;
330 }
331 }
332
333 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
334 struct radeon_fence *b)
335 {
336 if (!a) {
337 return false;
338 }
339
340 if (!b) {
341 return true;
342 }
343
344 BUG_ON(a->ring != b->ring);
345
346 return a->seq < b->seq;
347 }
348
349 /*
350 * Tiling registers
351 */
352 struct radeon_surface_reg {
353 struct radeon_bo *bo;
354 };
355
356 #define RADEON_GEM_MAX_SURFACES 8
357
358 /*
359 * TTM.
360 */
361 struct radeon_mman {
362 struct ttm_bo_global_ref bo_global_ref;
363 struct drm_global_reference mem_global_ref;
364 struct ttm_bo_device bdev;
365 bool mem_global_referenced;
366 bool initialized;
367 };
368
369 /* bo virtual address in a specific vm */
370 struct radeon_bo_va {
371 /* protected by bo being reserved */
372 struct list_head bo_list;
373 uint64_t soffset;
374 uint64_t eoffset;
375 uint32_t flags;
376 bool valid;
377 unsigned ref_count;
378
379 /* protected by vm mutex */
380 struct list_head vm_list;
381
382 /* constant after initialization */
383 struct radeon_vm *vm;
384 struct radeon_bo *bo;
385 };
386
387 struct radeon_bo {
388 /* Protected by gem.mutex */
389 struct list_head list;
390 /* Protected by tbo.reserved */
391 u32 placements[3];
392 struct ttm_placement placement;
393 struct ttm_buffer_object tbo;
394 struct ttm_bo_kmap_obj kmap;
395 unsigned pin_count;
396 void *kptr;
397 u32 tiling_flags;
398 u32 pitch;
399 int surface_reg;
400 /* list of all virtual address to which this bo
401 * is associated to
402 */
403 struct list_head va;
404 /* Constant after initialization */
405 struct radeon_device *rdev;
406 struct drm_gem_object gem_base;
407
408 struct ttm_bo_kmap_obj dma_buf_vmap;
409 pid_t pid;
410 };
411 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
412
413 struct radeon_bo_list {
414 struct ttm_validate_buffer tv;
415 struct radeon_bo *bo;
416 uint64_t gpu_offset;
417 bool written;
418 unsigned domain;
419 unsigned alt_domain;
420 u32 tiling_flags;
421 };
422
423 int radeon_gem_debugfs_init(struct radeon_device *rdev);
424
425 /* sub-allocation manager, it has to be protected by another lock.
426 * By conception this is an helper for other part of the driver
427 * like the indirect buffer or semaphore, which both have their
428 * locking.
429 *
430 * Principe is simple, we keep a list of sub allocation in offset
431 * order (first entry has offset == 0, last entry has the highest
432 * offset).
433 *
434 * When allocating new object we first check if there is room at
435 * the end total_size - (last_object_offset + last_object_size) >=
436 * alloc_size. If so we allocate new object there.
437 *
438 * When there is not enough room at the end, we start waiting for
439 * each sub object until we reach object_offset+object_size >=
440 * alloc_size, this object then become the sub object we return.
441 *
442 * Alignment can't be bigger than page size.
443 *
444 * Hole are not considered for allocation to keep things simple.
445 * Assumption is that there won't be hole (all object on same
446 * alignment).
447 */
448 struct radeon_sa_manager {
449 wait_queue_head_t wq;
450 struct radeon_bo *bo;
451 struct list_head *hole;
452 struct list_head flist[RADEON_NUM_RINGS];
453 struct list_head olist;
454 unsigned size;
455 uint64_t gpu_addr;
456 void *cpu_ptr;
457 uint32_t domain;
458 };
459
460 struct radeon_sa_bo;
461
462 /* sub-allocation buffer */
463 struct radeon_sa_bo {
464 struct list_head olist;
465 struct list_head flist;
466 struct radeon_sa_manager *manager;
467 unsigned soffset;
468 unsigned eoffset;
469 struct radeon_fence *fence;
470 };
471
472 /*
473 * GEM objects.
474 */
475 struct radeon_gem {
476 struct mutex mutex;
477 struct list_head objects;
478 };
479
480 int radeon_gem_init(struct radeon_device *rdev);
481 void radeon_gem_fini(struct radeon_device *rdev);
482 int radeon_gem_object_create(struct radeon_device *rdev, int size,
483 int alignment, int initial_domain,
484 bool discardable, bool kernel,
485 struct drm_gem_object **obj);
486
487 int radeon_mode_dumb_create(struct drm_file *file_priv,
488 struct drm_device *dev,
489 struct drm_mode_create_dumb *args);
490 int radeon_mode_dumb_mmap(struct drm_file *filp,
491 struct drm_device *dev,
492 uint32_t handle, uint64_t *offset_p);
493 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
494 struct drm_device *dev,
495 uint32_t handle);
496
497 /*
498 * Semaphores.
499 */
500 /* everything here is constant */
501 struct radeon_semaphore {
502 struct radeon_sa_bo *sa_bo;
503 signed waiters;
504 uint64_t gpu_addr;
505 };
506
507 int radeon_semaphore_create(struct radeon_device *rdev,
508 struct radeon_semaphore **semaphore);
509 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
510 struct radeon_semaphore *semaphore);
511 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
512 struct radeon_semaphore *semaphore);
513 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
514 struct radeon_semaphore *semaphore,
515 int signaler, int waiter);
516 void radeon_semaphore_free(struct radeon_device *rdev,
517 struct radeon_semaphore **semaphore,
518 struct radeon_fence *fence);
519
520 /*
521 * GART structures, functions & helpers
522 */
523 struct radeon_mc;
524
525 #define RADEON_GPU_PAGE_SIZE 4096
526 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
527 #define RADEON_GPU_PAGE_SHIFT 12
528 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
529
530 struct radeon_gart {
531 dma_addr_t table_addr;
532 struct radeon_bo *robj;
533 void *ptr;
534 unsigned num_gpu_pages;
535 unsigned num_cpu_pages;
536 unsigned table_size;
537 struct page **pages;
538 dma_addr_t *pages_addr;
539 bool ready;
540 };
541
542 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
543 void radeon_gart_table_ram_free(struct radeon_device *rdev);
544 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
545 void radeon_gart_table_vram_free(struct radeon_device *rdev);
546 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
547 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
548 int radeon_gart_init(struct radeon_device *rdev);
549 void radeon_gart_fini(struct radeon_device *rdev);
550 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
551 int pages);
552 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
553 int pages, struct page **pagelist,
554 dma_addr_t *dma_addr);
555 void radeon_gart_restore(struct radeon_device *rdev);
556
557
558 /*
559 * GPU MC structures, functions & helpers
560 */
561 struct radeon_mc {
562 resource_size_t aper_size;
563 resource_size_t aper_base;
564 resource_size_t agp_base;
565 /* for some chips with <= 32MB we need to lie
566 * about vram size near mc fb location */
567 u64 mc_vram_size;
568 u64 visible_vram_size;
569 u64 gtt_size;
570 u64 gtt_start;
571 u64 gtt_end;
572 u64 vram_start;
573 u64 vram_end;
574 unsigned vram_width;
575 u64 real_vram_size;
576 int vram_mtrr;
577 bool vram_is_ddr;
578 bool igp_sideport_enabled;
579 u64 gtt_base_align;
580 u64 mc_mask;
581 };
582
583 bool radeon_combios_sideport_present(struct radeon_device *rdev);
584 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
585
586 /*
587 * GPU scratch registers structures, functions & helpers
588 */
589 struct radeon_scratch {
590 unsigned num_reg;
591 uint32_t reg_base;
592 bool free[32];
593 uint32_t reg[32];
594 };
595
596 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
597 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
598
599 /*
600 * GPU doorbell structures, functions & helpers
601 */
602 struct radeon_doorbell {
603 u32 num_pages;
604 bool free[1024];
605 /* doorbell mmio */
606 resource_size_t base;
607 resource_size_t size;
608 void __iomem *ptr;
609 };
610
611 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
612 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
613
614 /*
615 * IRQS.
616 */
617
618 struct radeon_unpin_work {
619 struct work_struct work;
620 struct radeon_device *rdev;
621 int crtc_id;
622 struct radeon_fence *fence;
623 struct drm_pending_vblank_event *event;
624 struct radeon_bo *old_rbo;
625 u64 new_crtc_base;
626 };
627
628 struct r500_irq_stat_regs {
629 u32 disp_int;
630 u32 hdmi0_status;
631 };
632
633 struct r600_irq_stat_regs {
634 u32 disp_int;
635 u32 disp_int_cont;
636 u32 disp_int_cont2;
637 u32 d1grph_int;
638 u32 d2grph_int;
639 u32 hdmi0_status;
640 u32 hdmi1_status;
641 };
642
643 struct evergreen_irq_stat_regs {
644 u32 disp_int;
645 u32 disp_int_cont;
646 u32 disp_int_cont2;
647 u32 disp_int_cont3;
648 u32 disp_int_cont4;
649 u32 disp_int_cont5;
650 u32 d1grph_int;
651 u32 d2grph_int;
652 u32 d3grph_int;
653 u32 d4grph_int;
654 u32 d5grph_int;
655 u32 d6grph_int;
656 u32 afmt_status1;
657 u32 afmt_status2;
658 u32 afmt_status3;
659 u32 afmt_status4;
660 u32 afmt_status5;
661 u32 afmt_status6;
662 };
663
664 struct cik_irq_stat_regs {
665 u32 disp_int;
666 u32 disp_int_cont;
667 u32 disp_int_cont2;
668 u32 disp_int_cont3;
669 u32 disp_int_cont4;
670 u32 disp_int_cont5;
671 u32 disp_int_cont6;
672 };
673
674 union radeon_irq_stat_regs {
675 struct r500_irq_stat_regs r500;
676 struct r600_irq_stat_regs r600;
677 struct evergreen_irq_stat_regs evergreen;
678 struct cik_irq_stat_regs cik;
679 };
680
681 #define RADEON_MAX_HPD_PINS 6
682 #define RADEON_MAX_CRTCS 6
683 #define RADEON_MAX_AFMT_BLOCKS 6
684
685 struct radeon_irq {
686 bool installed;
687 spinlock_t lock;
688 atomic_t ring_int[RADEON_NUM_RINGS];
689 bool crtc_vblank_int[RADEON_MAX_CRTCS];
690 atomic_t pflip[RADEON_MAX_CRTCS];
691 wait_queue_head_t vblank_queue;
692 bool hpd[RADEON_MAX_HPD_PINS];
693 bool afmt[RADEON_MAX_AFMT_BLOCKS];
694 union radeon_irq_stat_regs stat_regs;
695 bool dpm_thermal;
696 };
697
698 int radeon_irq_kms_init(struct radeon_device *rdev);
699 void radeon_irq_kms_fini(struct radeon_device *rdev);
700 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
701 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
702 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
703 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
704 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
705 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
706 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
707 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
708
709 /*
710 * CP & rings.
711 */
712
713 struct radeon_ib {
714 struct radeon_sa_bo *sa_bo;
715 uint32_t length_dw;
716 uint64_t gpu_addr;
717 uint32_t *ptr;
718 int ring;
719 struct radeon_fence *fence;
720 struct radeon_vm *vm;
721 bool is_const_ib;
722 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
723 struct radeon_semaphore *semaphore;
724 };
725
726 struct radeon_ring {
727 struct radeon_bo *ring_obj;
728 volatile uint32_t *ring;
729 unsigned rptr;
730 unsigned rptr_offs;
731 unsigned rptr_reg;
732 unsigned rptr_save_reg;
733 u64 next_rptr_gpu_addr;
734 volatile u32 *next_rptr_cpu_addr;
735 unsigned wptr;
736 unsigned wptr_old;
737 unsigned wptr_reg;
738 unsigned ring_size;
739 unsigned ring_free_dw;
740 int count_dw;
741 unsigned long last_activity;
742 unsigned last_rptr;
743 uint64_t gpu_addr;
744 uint32_t align_mask;
745 uint32_t ptr_mask;
746 bool ready;
747 u32 ptr_reg_shift;
748 u32 ptr_reg_mask;
749 u32 nop;
750 u32 idx;
751 u64 last_semaphore_signal_addr;
752 u64 last_semaphore_wait_addr;
753 /* for CIK queues */
754 u32 me;
755 u32 pipe;
756 u32 queue;
757 struct radeon_bo *mqd_obj;
758 u32 doorbell_page_num;
759 u32 doorbell_offset;
760 unsigned wptr_offs;
761 };
762
763 struct radeon_mec {
764 struct radeon_bo *hpd_eop_obj;
765 u64 hpd_eop_gpu_addr;
766 u32 num_pipe;
767 u32 num_mec;
768 u32 num_queue;
769 };
770
771 /*
772 * VM
773 */
774
775 /* maximum number of VMIDs */
776 #define RADEON_NUM_VM 16
777
778 /* defines number of bits in page table versus page directory,
779 * a page is 4KB so we have 12 bits offset, 9 bits in the page
780 * table and the remaining 19 bits are in the page directory */
781 #define RADEON_VM_BLOCK_SIZE 9
782
783 /* number of entries in page table */
784 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
785
786 struct radeon_vm {
787 struct list_head list;
788 struct list_head va;
789 unsigned id;
790
791 /* contains the page directory */
792 struct radeon_sa_bo *page_directory;
793 uint64_t pd_gpu_addr;
794
795 /* array of page tables, one for each page directory entry */
796 struct radeon_sa_bo **page_tables;
797
798 struct mutex mutex;
799 /* last fence for cs using this vm */
800 struct radeon_fence *fence;
801 /* last flush or NULL if we still need to flush */
802 struct radeon_fence *last_flush;
803 };
804
805 struct radeon_vm_manager {
806 struct mutex lock;
807 struct list_head lru_vm;
808 struct radeon_fence *active[RADEON_NUM_VM];
809 struct radeon_sa_manager sa_manager;
810 uint32_t max_pfn;
811 /* number of VMIDs */
812 unsigned nvm;
813 /* vram base address for page table entry */
814 u64 vram_base_offset;
815 /* is vm enabled? */
816 bool enabled;
817 };
818
819 /*
820 * file private structure
821 */
822 struct radeon_fpriv {
823 struct radeon_vm vm;
824 };
825
826 /*
827 * R6xx+ IH ring
828 */
829 struct r600_ih {
830 struct radeon_bo *ring_obj;
831 volatile uint32_t *ring;
832 unsigned rptr;
833 unsigned ring_size;
834 uint64_t gpu_addr;
835 uint32_t ptr_mask;
836 atomic_t lock;
837 bool enabled;
838 };
839
840 struct r600_blit_cp_primitives {
841 void (*set_render_target)(struct radeon_device *rdev, int format,
842 int w, int h, u64 gpu_addr);
843 void (*cp_set_surface_sync)(struct radeon_device *rdev,
844 u32 sync_type, u32 size,
845 u64 mc_addr);
846 void (*set_shaders)(struct radeon_device *rdev);
847 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
848 void (*set_tex_resource)(struct radeon_device *rdev,
849 int format, int w, int h, int pitch,
850 u64 gpu_addr, u32 size);
851 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
852 int x2, int y2);
853 void (*draw_auto)(struct radeon_device *rdev);
854 void (*set_default_state)(struct radeon_device *rdev);
855 };
856
857 struct r600_blit {
858 struct radeon_bo *shader_obj;
859 struct r600_blit_cp_primitives primitives;
860 int max_dim;
861 int ring_size_common;
862 int ring_size_per_loop;
863 u64 shader_gpu_addr;
864 u32 vs_offset, ps_offset;
865 u32 state_offset;
866 u32 state_len;
867 };
868
869 /*
870 * RLC stuff
871 */
872 #include "clearstate_defs.h"
873
874 struct radeon_rlc {
875 /* for power gating */
876 struct radeon_bo *save_restore_obj;
877 uint64_t save_restore_gpu_addr;
878 volatile uint32_t *sr_ptr;
879 u32 *reg_list;
880 u32 reg_list_size;
881 /* for clear state */
882 struct radeon_bo *clear_state_obj;
883 uint64_t clear_state_gpu_addr;
884 volatile uint32_t *cs_ptr;
885 struct cs_section_def *cs_data;
886 };
887
888 int radeon_ib_get(struct radeon_device *rdev, int ring,
889 struct radeon_ib *ib, struct radeon_vm *vm,
890 unsigned size);
891 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
892 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
893 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
894 struct radeon_ib *const_ib);
895 int radeon_ib_pool_init(struct radeon_device *rdev);
896 void radeon_ib_pool_fini(struct radeon_device *rdev);
897 int radeon_ib_ring_tests(struct radeon_device *rdev);
898 /* Ring access between begin & end cannot sleep */
899 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
900 struct radeon_ring *ring);
901 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
902 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
903 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
904 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
905 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
906 void radeon_ring_undo(struct radeon_ring *ring);
907 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
908 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
909 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
910 void radeon_ring_lockup_update(struct radeon_ring *ring);
911 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
912 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
913 uint32_t **data);
914 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
915 unsigned size, uint32_t *data);
916 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
917 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
918 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
919 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
920
921
922 /* r600 async dma */
923 void r600_dma_stop(struct radeon_device *rdev);
924 int r600_dma_resume(struct radeon_device *rdev);
925 void r600_dma_fini(struct radeon_device *rdev);
926
927 void cayman_dma_stop(struct radeon_device *rdev);
928 int cayman_dma_resume(struct radeon_device *rdev);
929 void cayman_dma_fini(struct radeon_device *rdev);
930
931 /*
932 * CS.
933 */
934 struct radeon_cs_reloc {
935 struct drm_gem_object *gobj;
936 struct radeon_bo *robj;
937 struct radeon_bo_list lobj;
938 uint32_t handle;
939 uint32_t flags;
940 };
941
942 struct radeon_cs_chunk {
943 uint32_t chunk_id;
944 uint32_t length_dw;
945 int kpage_idx[2];
946 uint32_t *kpage[2];
947 uint32_t *kdata;
948 void __user *user_ptr;
949 int last_copied_page;
950 int last_page_index;
951 };
952
953 struct radeon_cs_parser {
954 struct device *dev;
955 struct radeon_device *rdev;
956 struct drm_file *filp;
957 /* chunks */
958 unsigned nchunks;
959 struct radeon_cs_chunk *chunks;
960 uint64_t *chunks_array;
961 /* IB */
962 unsigned idx;
963 /* relocations */
964 unsigned nrelocs;
965 struct radeon_cs_reloc *relocs;
966 struct radeon_cs_reloc **relocs_ptr;
967 struct list_head validated;
968 unsigned dma_reloc_idx;
969 /* indices of various chunks */
970 int chunk_ib_idx;
971 int chunk_relocs_idx;
972 int chunk_flags_idx;
973 int chunk_const_ib_idx;
974 struct radeon_ib ib;
975 struct radeon_ib const_ib;
976 void *track;
977 unsigned family;
978 int parser_error;
979 u32 cs_flags;
980 u32 ring;
981 s32 priority;
982 };
983
984 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
985 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
986
987 struct radeon_cs_packet {
988 unsigned idx;
989 unsigned type;
990 unsigned reg;
991 unsigned opcode;
992 int count;
993 unsigned one_reg_wr;
994 };
995
996 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
997 struct radeon_cs_packet *pkt,
998 unsigned idx, unsigned reg);
999 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1000 struct radeon_cs_packet *pkt);
1001
1002
1003 /*
1004 * AGP
1005 */
1006 int radeon_agp_init(struct radeon_device *rdev);
1007 void radeon_agp_resume(struct radeon_device *rdev);
1008 void radeon_agp_suspend(struct radeon_device *rdev);
1009 void radeon_agp_fini(struct radeon_device *rdev);
1010
1011
1012 /*
1013 * Writeback
1014 */
1015 struct radeon_wb {
1016 struct radeon_bo *wb_obj;
1017 volatile uint32_t *wb;
1018 uint64_t gpu_addr;
1019 bool enabled;
1020 bool use_event;
1021 };
1022
1023 #define RADEON_WB_SCRATCH_OFFSET 0
1024 #define RADEON_WB_RING0_NEXT_RPTR 256
1025 #define RADEON_WB_CP_RPTR_OFFSET 1024
1026 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1027 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1028 #define R600_WB_DMA_RPTR_OFFSET 1792
1029 #define R600_WB_IH_WPTR_OFFSET 2048
1030 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1031 #define R600_WB_UVD_RPTR_OFFSET 2560
1032 #define R600_WB_EVENT_OFFSET 3072
1033 #define CIK_WB_CP1_WPTR_OFFSET 3328
1034 #define CIK_WB_CP2_WPTR_OFFSET 3584
1035
1036 /**
1037 * struct radeon_pm - power management datas
1038 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1039 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1040 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1041 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1042 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1043 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1044 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1045 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1046 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1047 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1048 * @needed_bandwidth: current bandwidth needs
1049 *
1050 * It keeps track of various data needed to take powermanagement decision.
1051 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1052 * Equation between gpu/memory clock and available bandwidth is hw dependent
1053 * (type of memory, bus size, efficiency, ...)
1054 */
1055
1056 enum radeon_pm_method {
1057 PM_METHOD_PROFILE,
1058 PM_METHOD_DYNPM,
1059 PM_METHOD_DPM,
1060 };
1061
1062 enum radeon_dynpm_state {
1063 DYNPM_STATE_DISABLED,
1064 DYNPM_STATE_MINIMUM,
1065 DYNPM_STATE_PAUSED,
1066 DYNPM_STATE_ACTIVE,
1067 DYNPM_STATE_SUSPENDED,
1068 };
1069 enum radeon_dynpm_action {
1070 DYNPM_ACTION_NONE,
1071 DYNPM_ACTION_MINIMUM,
1072 DYNPM_ACTION_DOWNCLOCK,
1073 DYNPM_ACTION_UPCLOCK,
1074 DYNPM_ACTION_DEFAULT
1075 };
1076
1077 enum radeon_voltage_type {
1078 VOLTAGE_NONE = 0,
1079 VOLTAGE_GPIO,
1080 VOLTAGE_VDDC,
1081 VOLTAGE_SW
1082 };
1083
1084 enum radeon_pm_state_type {
1085 /* not used for dpm */
1086 POWER_STATE_TYPE_DEFAULT,
1087 POWER_STATE_TYPE_POWERSAVE,
1088 /* user selectable states */
1089 POWER_STATE_TYPE_BATTERY,
1090 POWER_STATE_TYPE_BALANCED,
1091 POWER_STATE_TYPE_PERFORMANCE,
1092 /* internal states */
1093 POWER_STATE_TYPE_INTERNAL_UVD,
1094 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1095 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1096 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1097 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1098 POWER_STATE_TYPE_INTERNAL_BOOT,
1099 POWER_STATE_TYPE_INTERNAL_THERMAL,
1100 POWER_STATE_TYPE_INTERNAL_ACPI,
1101 POWER_STATE_TYPE_INTERNAL_ULV,
1102 };
1103
1104 enum radeon_pm_profile_type {
1105 PM_PROFILE_DEFAULT,
1106 PM_PROFILE_AUTO,
1107 PM_PROFILE_LOW,
1108 PM_PROFILE_MID,
1109 PM_PROFILE_HIGH,
1110 };
1111
1112 #define PM_PROFILE_DEFAULT_IDX 0
1113 #define PM_PROFILE_LOW_SH_IDX 1
1114 #define PM_PROFILE_MID_SH_IDX 2
1115 #define PM_PROFILE_HIGH_SH_IDX 3
1116 #define PM_PROFILE_LOW_MH_IDX 4
1117 #define PM_PROFILE_MID_MH_IDX 5
1118 #define PM_PROFILE_HIGH_MH_IDX 6
1119 #define PM_PROFILE_MAX 7
1120
1121 struct radeon_pm_profile {
1122 int dpms_off_ps_idx;
1123 int dpms_on_ps_idx;
1124 int dpms_off_cm_idx;
1125 int dpms_on_cm_idx;
1126 };
1127
1128 enum radeon_int_thermal_type {
1129 THERMAL_TYPE_NONE,
1130 THERMAL_TYPE_EXTERNAL,
1131 THERMAL_TYPE_EXTERNAL_GPIO,
1132 THERMAL_TYPE_RV6XX,
1133 THERMAL_TYPE_RV770,
1134 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1135 THERMAL_TYPE_EVERGREEN,
1136 THERMAL_TYPE_SUMO,
1137 THERMAL_TYPE_NI,
1138 THERMAL_TYPE_SI,
1139 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1140 THERMAL_TYPE_CI,
1141 };
1142
1143 struct radeon_voltage {
1144 enum radeon_voltage_type type;
1145 /* gpio voltage */
1146 struct radeon_gpio_rec gpio;
1147 u32 delay; /* delay in usec from voltage drop to sclk change */
1148 bool active_high; /* voltage drop is active when bit is high */
1149 /* VDDC voltage */
1150 u8 vddc_id; /* index into vddc voltage table */
1151 u8 vddci_id; /* index into vddci voltage table */
1152 bool vddci_enabled;
1153 /* r6xx+ sw */
1154 u16 voltage;
1155 /* evergreen+ vddci */
1156 u16 vddci;
1157 };
1158
1159 /* clock mode flags */
1160 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1161
1162 struct radeon_pm_clock_info {
1163 /* memory clock */
1164 u32 mclk;
1165 /* engine clock */
1166 u32 sclk;
1167 /* voltage info */
1168 struct radeon_voltage voltage;
1169 /* standardized clock flags */
1170 u32 flags;
1171 };
1172
1173 /* state flags */
1174 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1175
1176 struct radeon_power_state {
1177 enum radeon_pm_state_type type;
1178 struct radeon_pm_clock_info *clock_info;
1179 /* number of valid clock modes in this power state */
1180 int num_clock_modes;
1181 struct radeon_pm_clock_info *default_clock_mode;
1182 /* standardized state flags */
1183 u32 flags;
1184 u32 misc; /* vbios specific flags */
1185 u32 misc2; /* vbios specific flags */
1186 int pcie_lanes; /* pcie lanes */
1187 };
1188
1189 /*
1190 * Some modes are overclocked by very low value, accept them
1191 */
1192 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1193
1194 enum radeon_dpm_auto_throttle_src {
1195 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1196 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1197 };
1198
1199 enum radeon_dpm_event_src {
1200 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1201 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1202 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1203 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1204 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1205 };
1206
1207 struct radeon_ps {
1208 u32 caps; /* vbios flags */
1209 u32 class; /* vbios flags */
1210 u32 class2; /* vbios flags */
1211 /* UVD clocks */
1212 u32 vclk;
1213 u32 dclk;
1214 /* asic priv */
1215 void *ps_priv;
1216 };
1217
1218 struct radeon_dpm_thermal {
1219 /* thermal interrupt work */
1220 struct work_struct work;
1221 /* low temperature threshold */
1222 int min_temp;
1223 /* high temperature threshold */
1224 int max_temp;
1225 /* was interrupt low to high or high to low */
1226 bool high_to_low;
1227 };
1228
1229 enum radeon_clk_action
1230 {
1231 RADEON_SCLK_UP = 1,
1232 RADEON_SCLK_DOWN
1233 };
1234
1235 struct radeon_blacklist_clocks
1236 {
1237 u32 sclk;
1238 u32 mclk;
1239 enum radeon_clk_action action;
1240 };
1241
1242 struct radeon_clock_and_voltage_limits {
1243 u32 sclk;
1244 u32 mclk;
1245 u32 vddc;
1246 u32 vddci;
1247 };
1248
1249 struct radeon_clock_array {
1250 u32 count;
1251 u32 *values;
1252 };
1253
1254 struct radeon_clock_voltage_dependency_entry {
1255 u32 clk;
1256 u16 v;
1257 };
1258
1259 struct radeon_clock_voltage_dependency_table {
1260 u32 count;
1261 struct radeon_clock_voltage_dependency_entry *entries;
1262 };
1263
1264 struct radeon_cac_leakage_entry {
1265 u16 vddc;
1266 u32 leakage;
1267 };
1268
1269 struct radeon_cac_leakage_table {
1270 u32 count;
1271 struct radeon_cac_leakage_entry *entries;
1272 };
1273
1274 struct radeon_phase_shedding_limits_entry {
1275 u16 voltage;
1276 u32 sclk;
1277 u32 mclk;
1278 };
1279
1280 struct radeon_phase_shedding_limits_table {
1281 u32 count;
1282 struct radeon_phase_shedding_limits_entry *entries;
1283 };
1284
1285 struct radeon_ppm_table {
1286 u8 ppm_design;
1287 u16 cpu_core_number;
1288 u32 platform_tdp;
1289 u32 small_ac_platform_tdp;
1290 u32 platform_tdc;
1291 u32 small_ac_platform_tdc;
1292 u32 apu_tdp;
1293 u32 dgpu_tdp;
1294 u32 dgpu_ulv_power;
1295 u32 tj_max;
1296 };
1297
1298 struct radeon_dpm_dynamic_state {
1299 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1300 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1301 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1302 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1303 struct radeon_clock_array valid_sclk_values;
1304 struct radeon_clock_array valid_mclk_values;
1305 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1306 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1307 u32 mclk_sclk_ratio;
1308 u32 sclk_mclk_delta;
1309 u16 vddc_vddci_delta;
1310 u16 min_vddc_for_pcie_gen2;
1311 struct radeon_cac_leakage_table cac_leakage_table;
1312 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1313 struct radeon_ppm_table *ppm_table;
1314 };
1315
1316 struct radeon_dpm_fan {
1317 u16 t_min;
1318 u16 t_med;
1319 u16 t_high;
1320 u16 pwm_min;
1321 u16 pwm_med;
1322 u16 pwm_high;
1323 u8 t_hyst;
1324 u32 cycle_delay;
1325 u16 t_max;
1326 bool ucode_fan_control;
1327 };
1328
1329 enum radeon_pcie_gen {
1330 RADEON_PCIE_GEN1 = 0,
1331 RADEON_PCIE_GEN2 = 1,
1332 RADEON_PCIE_GEN3 = 2,
1333 RADEON_PCIE_GEN_INVALID = 0xffff
1334 };
1335
1336 struct radeon_dpm {
1337 struct radeon_ps *ps;
1338 /* number of valid power states */
1339 int num_ps;
1340 /* current power state that is active */
1341 struct radeon_ps *current_ps;
1342 /* requested power state */
1343 struct radeon_ps *requested_ps;
1344 /* boot up power state */
1345 struct radeon_ps *boot_ps;
1346 /* default uvd power state */
1347 struct radeon_ps *uvd_ps;
1348 enum radeon_pm_state_type state;
1349 enum radeon_pm_state_type user_state;
1350 u32 platform_caps;
1351 u32 voltage_response_time;
1352 u32 backbias_response_time;
1353 void *priv;
1354 u32 new_active_crtcs;
1355 int new_active_crtc_count;
1356 u32 current_active_crtcs;
1357 int current_active_crtc_count;
1358 struct radeon_dpm_dynamic_state dyn_state;
1359 struct radeon_dpm_fan fan;
1360 u32 tdp_limit;
1361 u32 near_tdp_limit;
1362 u32 near_tdp_limit_adjusted;
1363 u32 sq_ramping_threshold;
1364 u32 cac_leakage;
1365 u16 tdp_od_limit;
1366 u32 tdp_adjustment;
1367 u16 load_line_slope;
1368 bool power_control;
1369 bool ac_power;
1370 /* special states active */
1371 bool thermal_active;
1372 bool uvd_active;
1373 /* thermal handling */
1374 struct radeon_dpm_thermal thermal;
1375 };
1376
1377 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1378 enum radeon_pm_state_type dpm_state);
1379
1380
1381 struct radeon_pm {
1382 struct mutex mutex;
1383 /* write locked while reprogramming mclk */
1384 struct rw_semaphore mclk_lock;
1385 u32 active_crtcs;
1386 int active_crtc_count;
1387 int req_vblank;
1388 bool vblank_sync;
1389 fixed20_12 max_bandwidth;
1390 fixed20_12 igp_sideport_mclk;
1391 fixed20_12 igp_system_mclk;
1392 fixed20_12 igp_ht_link_clk;
1393 fixed20_12 igp_ht_link_width;
1394 fixed20_12 k8_bandwidth;
1395 fixed20_12 sideport_bandwidth;
1396 fixed20_12 ht_bandwidth;
1397 fixed20_12 core_bandwidth;
1398 fixed20_12 sclk;
1399 fixed20_12 mclk;
1400 fixed20_12 needed_bandwidth;
1401 struct radeon_power_state *power_state;
1402 /* number of valid power states */
1403 int num_power_states;
1404 int current_power_state_index;
1405 int current_clock_mode_index;
1406 int requested_power_state_index;
1407 int requested_clock_mode_index;
1408 int default_power_state_index;
1409 u32 current_sclk;
1410 u32 current_mclk;
1411 u16 current_vddc;
1412 u16 current_vddci;
1413 u32 default_sclk;
1414 u32 default_mclk;
1415 u16 default_vddc;
1416 u16 default_vddci;
1417 struct radeon_i2c_chan *i2c_bus;
1418 /* selected pm method */
1419 enum radeon_pm_method pm_method;
1420 /* dynpm power management */
1421 struct delayed_work dynpm_idle_work;
1422 enum radeon_dynpm_state dynpm_state;
1423 enum radeon_dynpm_action dynpm_planned_action;
1424 unsigned long dynpm_action_timeout;
1425 bool dynpm_can_upclock;
1426 bool dynpm_can_downclock;
1427 /* profile-based power management */
1428 enum radeon_pm_profile_type profile;
1429 int profile_index;
1430 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1431 /* internal thermal controller on rv6xx+ */
1432 enum radeon_int_thermal_type int_thermal_type;
1433 struct device *int_hwmon_dev;
1434 /* dpm */
1435 bool dpm_enabled;
1436 struct radeon_dpm dpm;
1437 };
1438
1439 int radeon_pm_get_type_index(struct radeon_device *rdev,
1440 enum radeon_pm_state_type ps_type,
1441 int instance);
1442 /*
1443 * UVD
1444 */
1445 #define RADEON_MAX_UVD_HANDLES 10
1446 #define RADEON_UVD_STACK_SIZE (1024*1024)
1447 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1448
1449 struct radeon_uvd {
1450 struct radeon_bo *vcpu_bo;
1451 void *cpu_addr;
1452 uint64_t gpu_addr;
1453 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1454 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1455 struct delayed_work idle_work;
1456 };
1457
1458 int radeon_uvd_init(struct radeon_device *rdev);
1459 void radeon_uvd_fini(struct radeon_device *rdev);
1460 int radeon_uvd_suspend(struct radeon_device *rdev);
1461 int radeon_uvd_resume(struct radeon_device *rdev);
1462 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1463 uint32_t handle, struct radeon_fence **fence);
1464 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1465 uint32_t handle, struct radeon_fence **fence);
1466 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1467 void radeon_uvd_free_handles(struct radeon_device *rdev,
1468 struct drm_file *filp);
1469 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1470 void radeon_uvd_note_usage(struct radeon_device *rdev);
1471 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1472 unsigned vclk, unsigned dclk,
1473 unsigned vco_min, unsigned vco_max,
1474 unsigned fb_factor, unsigned fb_mask,
1475 unsigned pd_min, unsigned pd_max,
1476 unsigned pd_even,
1477 unsigned *optimal_fb_div,
1478 unsigned *optimal_vclk_div,
1479 unsigned *optimal_dclk_div);
1480 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1481 unsigned cg_upll_func_cntl);
1482
1483 struct r600_audio {
1484 int channels;
1485 int rate;
1486 int bits_per_sample;
1487 u8 status_bits;
1488 u8 category_code;
1489 };
1490
1491 /*
1492 * Benchmarking
1493 */
1494 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1495
1496
1497 /*
1498 * Testing
1499 */
1500 void radeon_test_moves(struct radeon_device *rdev);
1501 void radeon_test_ring_sync(struct radeon_device *rdev,
1502 struct radeon_ring *cpA,
1503 struct radeon_ring *cpB);
1504 void radeon_test_syncing(struct radeon_device *rdev);
1505
1506
1507 /*
1508 * Debugfs
1509 */
1510 struct radeon_debugfs {
1511 struct drm_info_list *files;
1512 unsigned num_files;
1513 };
1514
1515 int radeon_debugfs_add_files(struct radeon_device *rdev,
1516 struct drm_info_list *files,
1517 unsigned nfiles);
1518 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1519
1520
1521 /*
1522 * ASIC specific functions.
1523 */
1524 struct radeon_asic {
1525 int (*init)(struct radeon_device *rdev);
1526 void (*fini)(struct radeon_device *rdev);
1527 int (*resume)(struct radeon_device *rdev);
1528 int (*suspend)(struct radeon_device *rdev);
1529 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1530 int (*asic_reset)(struct radeon_device *rdev);
1531 /* ioctl hw specific callback. Some hw might want to perform special
1532 * operation on specific ioctl. For instance on wait idle some hw
1533 * might want to perform and HDP flush through MMIO as it seems that
1534 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1535 * through ring.
1536 */
1537 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1538 /* check if 3D engine is idle */
1539 bool (*gui_idle)(struct radeon_device *rdev);
1540 /* wait for mc_idle */
1541 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1542 /* get the reference clock */
1543 u32 (*get_xclk)(struct radeon_device *rdev);
1544 /* get the gpu clock counter */
1545 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1546 /* gart */
1547 struct {
1548 void (*tlb_flush)(struct radeon_device *rdev);
1549 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1550 } gart;
1551 struct {
1552 int (*init)(struct radeon_device *rdev);
1553 void (*fini)(struct radeon_device *rdev);
1554
1555 u32 pt_ring_index;
1556 void (*set_page)(struct radeon_device *rdev,
1557 struct radeon_ib *ib,
1558 uint64_t pe,
1559 uint64_t addr, unsigned count,
1560 uint32_t incr, uint32_t flags);
1561 } vm;
1562 /* ring specific callbacks */
1563 struct {
1564 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1565 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1566 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1567 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1568 struct radeon_semaphore *semaphore, bool emit_wait);
1569 int (*cs_parse)(struct radeon_cs_parser *p);
1570 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1571 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1572 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1573 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1574 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1575
1576 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1577 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1578 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1579 } ring[RADEON_NUM_RINGS];
1580 /* irqs */
1581 struct {
1582 int (*set)(struct radeon_device *rdev);
1583 int (*process)(struct radeon_device *rdev);
1584 } irq;
1585 /* displays */
1586 struct {
1587 /* display watermarks */
1588 void (*bandwidth_update)(struct radeon_device *rdev);
1589 /* get frame count */
1590 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1591 /* wait for vblank */
1592 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1593 /* set backlight level */
1594 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1595 /* get backlight level */
1596 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1597 /* audio callbacks */
1598 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1599 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1600 } display;
1601 /* copy functions for bo handling */
1602 struct {
1603 int (*blit)(struct radeon_device *rdev,
1604 uint64_t src_offset,
1605 uint64_t dst_offset,
1606 unsigned num_gpu_pages,
1607 struct radeon_fence **fence);
1608 u32 blit_ring_index;
1609 int (*dma)(struct radeon_device *rdev,
1610 uint64_t src_offset,
1611 uint64_t dst_offset,
1612 unsigned num_gpu_pages,
1613 struct radeon_fence **fence);
1614 u32 dma_ring_index;
1615 /* method used for bo copy */
1616 int (*copy)(struct radeon_device *rdev,
1617 uint64_t src_offset,
1618 uint64_t dst_offset,
1619 unsigned num_gpu_pages,
1620 struct radeon_fence **fence);
1621 /* ring used for bo copies */
1622 u32 copy_ring_index;
1623 } copy;
1624 /* surfaces */
1625 struct {
1626 int (*set_reg)(struct radeon_device *rdev, int reg,
1627 uint32_t tiling_flags, uint32_t pitch,
1628 uint32_t offset, uint32_t obj_size);
1629 void (*clear_reg)(struct radeon_device *rdev, int reg);
1630 } surface;
1631 /* hotplug detect */
1632 struct {
1633 void (*init)(struct radeon_device *rdev);
1634 void (*fini)(struct radeon_device *rdev);
1635 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1636 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1637 } hpd;
1638 /* static power management */
1639 struct {
1640 void (*misc)(struct radeon_device *rdev);
1641 void (*prepare)(struct radeon_device *rdev);
1642 void (*finish)(struct radeon_device *rdev);
1643 void (*init_profile)(struct radeon_device *rdev);
1644 void (*get_dynpm_state)(struct radeon_device *rdev);
1645 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1646 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1647 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1648 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1649 int (*get_pcie_lanes)(struct radeon_device *rdev);
1650 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1651 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1652 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1653 int (*get_temperature)(struct radeon_device *rdev);
1654 } pm;
1655 /* dynamic power management */
1656 struct {
1657 int (*init)(struct radeon_device *rdev);
1658 void (*setup_asic)(struct radeon_device *rdev);
1659 int (*enable)(struct radeon_device *rdev);
1660 void (*disable)(struct radeon_device *rdev);
1661 int (*pre_set_power_state)(struct radeon_device *rdev);
1662 int (*set_power_state)(struct radeon_device *rdev);
1663 void (*post_set_power_state)(struct radeon_device *rdev);
1664 void (*display_configuration_changed)(struct radeon_device *rdev);
1665 void (*fini)(struct radeon_device *rdev);
1666 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1667 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1668 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1669 } dpm;
1670 /* pageflipping */
1671 struct {
1672 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1673 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1674 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1675 } pflip;
1676 };
1677
1678 /*
1679 * Asic structures
1680 */
1681 struct r100_asic {
1682 const unsigned *reg_safe_bm;
1683 unsigned reg_safe_bm_size;
1684 u32 hdp_cntl;
1685 };
1686
1687 struct r300_asic {
1688 const unsigned *reg_safe_bm;
1689 unsigned reg_safe_bm_size;
1690 u32 resync_scratch;
1691 u32 hdp_cntl;
1692 };
1693
1694 struct r600_asic {
1695 unsigned max_pipes;
1696 unsigned max_tile_pipes;
1697 unsigned max_simds;
1698 unsigned max_backends;
1699 unsigned max_gprs;
1700 unsigned max_threads;
1701 unsigned max_stack_entries;
1702 unsigned max_hw_contexts;
1703 unsigned max_gs_threads;
1704 unsigned sx_max_export_size;
1705 unsigned sx_max_export_pos_size;
1706 unsigned sx_max_export_smx_size;
1707 unsigned sq_num_cf_insts;
1708 unsigned tiling_nbanks;
1709 unsigned tiling_npipes;
1710 unsigned tiling_group_size;
1711 unsigned tile_config;
1712 unsigned backend_map;
1713 };
1714
1715 struct rv770_asic {
1716 unsigned max_pipes;
1717 unsigned max_tile_pipes;
1718 unsigned max_simds;
1719 unsigned max_backends;
1720 unsigned max_gprs;
1721 unsigned max_threads;
1722 unsigned max_stack_entries;
1723 unsigned max_hw_contexts;
1724 unsigned max_gs_threads;
1725 unsigned sx_max_export_size;
1726 unsigned sx_max_export_pos_size;
1727 unsigned sx_max_export_smx_size;
1728 unsigned sq_num_cf_insts;
1729 unsigned sx_num_of_sets;
1730 unsigned sc_prim_fifo_size;
1731 unsigned sc_hiz_tile_fifo_size;
1732 unsigned sc_earlyz_tile_fifo_fize;
1733 unsigned tiling_nbanks;
1734 unsigned tiling_npipes;
1735 unsigned tiling_group_size;
1736 unsigned tile_config;
1737 unsigned backend_map;
1738 };
1739
1740 struct evergreen_asic {
1741 unsigned num_ses;
1742 unsigned max_pipes;
1743 unsigned max_tile_pipes;
1744 unsigned max_simds;
1745 unsigned max_backends;
1746 unsigned max_gprs;
1747 unsigned max_threads;
1748 unsigned max_stack_entries;
1749 unsigned max_hw_contexts;
1750 unsigned max_gs_threads;
1751 unsigned sx_max_export_size;
1752 unsigned sx_max_export_pos_size;
1753 unsigned sx_max_export_smx_size;
1754 unsigned sq_num_cf_insts;
1755 unsigned sx_num_of_sets;
1756 unsigned sc_prim_fifo_size;
1757 unsigned sc_hiz_tile_fifo_size;
1758 unsigned sc_earlyz_tile_fifo_size;
1759 unsigned tiling_nbanks;
1760 unsigned tiling_npipes;
1761 unsigned tiling_group_size;
1762 unsigned tile_config;
1763 unsigned backend_map;
1764 };
1765
1766 struct cayman_asic {
1767 unsigned max_shader_engines;
1768 unsigned max_pipes_per_simd;
1769 unsigned max_tile_pipes;
1770 unsigned max_simds_per_se;
1771 unsigned max_backends_per_se;
1772 unsigned max_texture_channel_caches;
1773 unsigned max_gprs;
1774 unsigned max_threads;
1775 unsigned max_gs_threads;
1776 unsigned max_stack_entries;
1777 unsigned sx_num_of_sets;
1778 unsigned sx_max_export_size;
1779 unsigned sx_max_export_pos_size;
1780 unsigned sx_max_export_smx_size;
1781 unsigned max_hw_contexts;
1782 unsigned sq_num_cf_insts;
1783 unsigned sc_prim_fifo_size;
1784 unsigned sc_hiz_tile_fifo_size;
1785 unsigned sc_earlyz_tile_fifo_size;
1786
1787 unsigned num_shader_engines;
1788 unsigned num_shader_pipes_per_simd;
1789 unsigned num_tile_pipes;
1790 unsigned num_simds_per_se;
1791 unsigned num_backends_per_se;
1792 unsigned backend_disable_mask_per_asic;
1793 unsigned backend_map;
1794 unsigned num_texture_channel_caches;
1795 unsigned mem_max_burst_length_bytes;
1796 unsigned mem_row_size_in_kb;
1797 unsigned shader_engine_tile_size;
1798 unsigned num_gpus;
1799 unsigned multi_gpu_tile_size;
1800
1801 unsigned tile_config;
1802 };
1803
1804 struct si_asic {
1805 unsigned max_shader_engines;
1806 unsigned max_tile_pipes;
1807 unsigned max_cu_per_sh;
1808 unsigned max_sh_per_se;
1809 unsigned max_backends_per_se;
1810 unsigned max_texture_channel_caches;
1811 unsigned max_gprs;
1812 unsigned max_gs_threads;
1813 unsigned max_hw_contexts;
1814 unsigned sc_prim_fifo_size_frontend;
1815 unsigned sc_prim_fifo_size_backend;
1816 unsigned sc_hiz_tile_fifo_size;
1817 unsigned sc_earlyz_tile_fifo_size;
1818
1819 unsigned num_tile_pipes;
1820 unsigned num_backends_per_se;
1821 unsigned backend_disable_mask_per_asic;
1822 unsigned backend_map;
1823 unsigned num_texture_channel_caches;
1824 unsigned mem_max_burst_length_bytes;
1825 unsigned mem_row_size_in_kb;
1826 unsigned shader_engine_tile_size;
1827 unsigned num_gpus;
1828 unsigned multi_gpu_tile_size;
1829
1830 unsigned tile_config;
1831 uint32_t tile_mode_array[32];
1832 };
1833
1834 struct cik_asic {
1835 unsigned max_shader_engines;
1836 unsigned max_tile_pipes;
1837 unsigned max_cu_per_sh;
1838 unsigned max_sh_per_se;
1839 unsigned max_backends_per_se;
1840 unsigned max_texture_channel_caches;
1841 unsigned max_gprs;
1842 unsigned max_gs_threads;
1843 unsigned max_hw_contexts;
1844 unsigned sc_prim_fifo_size_frontend;
1845 unsigned sc_prim_fifo_size_backend;
1846 unsigned sc_hiz_tile_fifo_size;
1847 unsigned sc_earlyz_tile_fifo_size;
1848
1849 unsigned num_tile_pipes;
1850 unsigned num_backends_per_se;
1851 unsigned backend_disable_mask_per_asic;
1852 unsigned backend_map;
1853 unsigned num_texture_channel_caches;
1854 unsigned mem_max_burst_length_bytes;
1855 unsigned mem_row_size_in_kb;
1856 unsigned shader_engine_tile_size;
1857 unsigned num_gpus;
1858 unsigned multi_gpu_tile_size;
1859
1860 unsigned tile_config;
1861 uint32_t tile_mode_array[32];
1862 };
1863
1864 union radeon_asic_config {
1865 struct r300_asic r300;
1866 struct r100_asic r100;
1867 struct r600_asic r600;
1868 struct rv770_asic rv770;
1869 struct evergreen_asic evergreen;
1870 struct cayman_asic cayman;
1871 struct si_asic si;
1872 struct cik_asic cik;
1873 };
1874
1875 /*
1876 * asic initizalization from radeon_asic.c
1877 */
1878 void radeon_agp_disable(struct radeon_device *rdev);
1879 int radeon_asic_init(struct radeon_device *rdev);
1880
1881
1882 /*
1883 * IOCTL.
1884 */
1885 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1886 struct drm_file *filp);
1887 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1888 struct drm_file *filp);
1889 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1890 struct drm_file *file_priv);
1891 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1892 struct drm_file *file_priv);
1893 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1894 struct drm_file *file_priv);
1895 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1896 struct drm_file *file_priv);
1897 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1898 struct drm_file *filp);
1899 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1900 struct drm_file *filp);
1901 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1902 struct drm_file *filp);
1903 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1904 struct drm_file *filp);
1905 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1906 struct drm_file *filp);
1907 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1908 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1909 struct drm_file *filp);
1910 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1911 struct drm_file *filp);
1912
1913 /* VRAM scratch page for HDP bug, default vram page */
1914 struct r600_vram_scratch {
1915 struct radeon_bo *robj;
1916 volatile uint32_t *ptr;
1917 u64 gpu_addr;
1918 };
1919
1920 /*
1921 * ACPI
1922 */
1923 struct radeon_atif_notification_cfg {
1924 bool enabled;
1925 int command_code;
1926 };
1927
1928 struct radeon_atif_notifications {
1929 bool display_switch;
1930 bool expansion_mode_change;
1931 bool thermal_state;
1932 bool forced_power_state;
1933 bool system_power_state;
1934 bool display_conf_change;
1935 bool px_gfx_switch;
1936 bool brightness_change;
1937 bool dgpu_display_event;
1938 };
1939
1940 struct radeon_atif_functions {
1941 bool system_params;
1942 bool sbios_requests;
1943 bool select_active_disp;
1944 bool lid_state;
1945 bool get_tv_standard;
1946 bool set_tv_standard;
1947 bool get_panel_expansion_mode;
1948 bool set_panel_expansion_mode;
1949 bool temperature_change;
1950 bool graphics_device_types;
1951 };
1952
1953 struct radeon_atif {
1954 struct radeon_atif_notifications notifications;
1955 struct radeon_atif_functions functions;
1956 struct radeon_atif_notification_cfg notification_cfg;
1957 struct radeon_encoder *encoder_for_bl;
1958 };
1959
1960 struct radeon_atcs_functions {
1961 bool get_ext_state;
1962 bool pcie_perf_req;
1963 bool pcie_dev_rdy;
1964 bool pcie_bus_width;
1965 };
1966
1967 struct radeon_atcs {
1968 struct radeon_atcs_functions functions;
1969 };
1970
1971 /*
1972 * Core structure, functions and helpers.
1973 */
1974 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1975 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1976
1977 struct radeon_device {
1978 struct device *dev;
1979 struct drm_device *ddev;
1980 struct pci_dev *pdev;
1981 struct rw_semaphore exclusive_lock;
1982 /* ASIC */
1983 union radeon_asic_config config;
1984 enum radeon_family family;
1985 unsigned long flags;
1986 int usec_timeout;
1987 enum radeon_pll_errata pll_errata;
1988 int num_gb_pipes;
1989 int num_z_pipes;
1990 int disp_priority;
1991 /* BIOS */
1992 uint8_t *bios;
1993 bool is_atom_bios;
1994 uint16_t bios_header_start;
1995 struct radeon_bo *stollen_vga_memory;
1996 /* Register mmio */
1997 resource_size_t rmmio_base;
1998 resource_size_t rmmio_size;
1999 /* protects concurrent MM_INDEX/DATA based register access */
2000 spinlock_t mmio_idx_lock;
2001 void __iomem *rmmio;
2002 radeon_rreg_t mc_rreg;
2003 radeon_wreg_t mc_wreg;
2004 radeon_rreg_t pll_rreg;
2005 radeon_wreg_t pll_wreg;
2006 uint32_t pcie_reg_mask;
2007 radeon_rreg_t pciep_rreg;
2008 radeon_wreg_t pciep_wreg;
2009 /* io port */
2010 void __iomem *rio_mem;
2011 resource_size_t rio_mem_size;
2012 struct radeon_clock clock;
2013 struct radeon_mc mc;
2014 struct radeon_gart gart;
2015 struct radeon_mode_info mode_info;
2016 struct radeon_scratch scratch;
2017 struct radeon_doorbell doorbell;
2018 struct radeon_mman mman;
2019 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2020 wait_queue_head_t fence_queue;
2021 struct mutex ring_lock;
2022 struct radeon_ring ring[RADEON_NUM_RINGS];
2023 bool ib_pool_ready;
2024 struct radeon_sa_manager ring_tmp_bo;
2025 struct radeon_irq irq;
2026 struct radeon_asic *asic;
2027 struct radeon_gem gem;
2028 struct radeon_pm pm;
2029 struct radeon_uvd uvd;
2030 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2031 struct radeon_wb wb;
2032 struct radeon_dummy_page dummy_page;
2033 bool shutdown;
2034 bool suspend;
2035 bool need_dma32;
2036 bool accel_working;
2037 bool fastfb_working; /* IGP feature*/
2038 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2039 const struct firmware *me_fw; /* all family ME firmware */
2040 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2041 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2042 const struct firmware *mc_fw; /* NI MC firmware */
2043 const struct firmware *ce_fw; /* SI CE firmware */
2044 const struct firmware *uvd_fw; /* UVD firmware */
2045 const struct firmware *mec_fw; /* CIK MEC firmware */
2046 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2047 const struct firmware *smc_fw; /* SMC firmware */
2048 struct r600_blit r600_blit;
2049 struct r600_vram_scratch vram_scratch;
2050 int msi_enabled; /* msi enabled */
2051 struct r600_ih ih; /* r6/700 interrupt ring */
2052 struct radeon_rlc rlc;
2053 struct radeon_mec mec;
2054 struct work_struct hotplug_work;
2055 struct work_struct audio_work;
2056 struct work_struct reset_work;
2057 int num_crtc; /* number of crtcs */
2058 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2059 bool audio_enabled;
2060 bool has_uvd;
2061 struct r600_audio audio_status; /* audio stuff */
2062 struct notifier_block acpi_nb;
2063 /* only one userspace can use Hyperz features or CMASK at a time */
2064 struct drm_file *hyperz_filp;
2065 struct drm_file *cmask_filp;
2066 /* i2c buses */
2067 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2068 /* debugfs */
2069 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2070 unsigned debugfs_count;
2071 /* virtual memory */
2072 struct radeon_vm_manager vm_manager;
2073 struct mutex gpu_clock_mutex;
2074 /* ACPI interface */
2075 struct radeon_atif atif;
2076 struct radeon_atcs atcs;
2077 };
2078
2079 int radeon_device_init(struct radeon_device *rdev,
2080 struct drm_device *ddev,
2081 struct pci_dev *pdev,
2082 uint32_t flags);
2083 void radeon_device_fini(struct radeon_device *rdev);
2084 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2085
2086 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2087 bool always_indirect);
2088 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2089 bool always_indirect);
2090 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2091 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2092
2093 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2094 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2095
2096 /*
2097 * Cast helper
2098 */
2099 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2100
2101 /*
2102 * Registers read & write functions.
2103 */
2104 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2105 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2106 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2107 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2108 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2109 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2110 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2111 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2112 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2113 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2114 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2115 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2116 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2117 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2118 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2119 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2120 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2121 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2122 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2123 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2124 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2125 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2126 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2127 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2128 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2129 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2130 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2131 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2132 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2133 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2134 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2135 #define WREG32_P(reg, val, mask) \
2136 do { \
2137 uint32_t tmp_ = RREG32(reg); \
2138 tmp_ &= (mask); \
2139 tmp_ |= ((val) & ~(mask)); \
2140 WREG32(reg, tmp_); \
2141 } while (0)
2142 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2143 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
2144 #define WREG32_PLL_P(reg, val, mask) \
2145 do { \
2146 uint32_t tmp_ = RREG32_PLL(reg); \
2147 tmp_ &= (mask); \
2148 tmp_ |= ((val) & ~(mask)); \
2149 WREG32_PLL(reg, tmp_); \
2150 } while (0)
2151 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2152 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2153 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2154
2155 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2156 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2157
2158 /*
2159 * Indirect registers accessor
2160 */
2161 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2162 {
2163 uint32_t r;
2164
2165 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2166 r = RREG32(RADEON_PCIE_DATA);
2167 return r;
2168 }
2169
2170 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2171 {
2172 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2173 WREG32(RADEON_PCIE_DATA, (v));
2174 }
2175
2176 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2177 {
2178 u32 r;
2179
2180 WREG32(TN_SMC_IND_INDEX_0, (reg));
2181 r = RREG32(TN_SMC_IND_DATA_0);
2182 return r;
2183 }
2184
2185 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2186 {
2187 WREG32(TN_SMC_IND_INDEX_0, (reg));
2188 WREG32(TN_SMC_IND_DATA_0, (v));
2189 }
2190
2191 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2192 {
2193 u32 r;
2194
2195 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2196 r = RREG32(R600_RCU_DATA);
2197 return r;
2198 }
2199
2200 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2201 {
2202 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2203 WREG32(R600_RCU_DATA, (v));
2204 }
2205
2206 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2207 {
2208 u32 r;
2209
2210 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2211 r = RREG32(EVERGREEN_CG_IND_DATA);
2212 return r;
2213 }
2214
2215 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2216 {
2217 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2218 WREG32(EVERGREEN_CG_IND_DATA, (v));
2219 }
2220
2221 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2222 {
2223 u32 r;
2224
2225 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2226 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2227 return r;
2228 }
2229
2230 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2231 {
2232 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2233 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2234 }
2235
2236 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2237 {
2238 u32 r;
2239
2240 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2241 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2242 return r;
2243 }
2244
2245 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2246 {
2247 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2248 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2249 }
2250
2251 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2252 {
2253 u32 r;
2254
2255 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2256 r = RREG32(R600_UVD_CTX_DATA);
2257 return r;
2258 }
2259
2260 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2261 {
2262 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2263 WREG32(R600_UVD_CTX_DATA, (v));
2264 }
2265
2266 void r100_pll_errata_after_index(struct radeon_device *rdev);
2267
2268
2269 /*
2270 * ASICs helpers.
2271 */
2272 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2273 (rdev->pdev->device == 0x5969))
2274 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2275 (rdev->family == CHIP_RV200) || \
2276 (rdev->family == CHIP_RS100) || \
2277 (rdev->family == CHIP_RS200) || \
2278 (rdev->family == CHIP_RV250) || \
2279 (rdev->family == CHIP_RV280) || \
2280 (rdev->family == CHIP_RS300))
2281 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2282 (rdev->family == CHIP_RV350) || \
2283 (rdev->family == CHIP_R350) || \
2284 (rdev->family == CHIP_RV380) || \
2285 (rdev->family == CHIP_R420) || \
2286 (rdev->family == CHIP_R423) || \
2287 (rdev->family == CHIP_RV410) || \
2288 (rdev->family == CHIP_RS400) || \
2289 (rdev->family == CHIP_RS480))
2290 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2291 (rdev->ddev->pdev->device == 0x9443) || \
2292 (rdev->ddev->pdev->device == 0x944B) || \
2293 (rdev->ddev->pdev->device == 0x9506) || \
2294 (rdev->ddev->pdev->device == 0x9509) || \
2295 (rdev->ddev->pdev->device == 0x950F) || \
2296 (rdev->ddev->pdev->device == 0x689C) || \
2297 (rdev->ddev->pdev->device == 0x689D))
2298 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2299 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2300 (rdev->family == CHIP_RS690) || \
2301 (rdev->family == CHIP_RS740) || \
2302 (rdev->family >= CHIP_R600))
2303 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2304 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2305 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2306 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2307 (rdev->flags & RADEON_IS_IGP))
2308 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2309 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2310 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2311 (rdev->flags & RADEON_IS_IGP))
2312 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2313 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2314 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2315
2316 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2317 (rdev->ddev->pdev->device == 0x6850) || \
2318 (rdev->ddev->pdev->device == 0x6858) || \
2319 (rdev->ddev->pdev->device == 0x6859) || \
2320 (rdev->ddev->pdev->device == 0x6840) || \
2321 (rdev->ddev->pdev->device == 0x6841) || \
2322 (rdev->ddev->pdev->device == 0x6842) || \
2323 (rdev->ddev->pdev->device == 0x6843))
2324
2325 /*
2326 * BIOS helpers.
2327 */
2328 #define RBIOS8(i) (rdev->bios[i])
2329 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2330 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2331
2332 int radeon_combios_init(struct radeon_device *rdev);
2333 void radeon_combios_fini(struct radeon_device *rdev);
2334 int radeon_atombios_init(struct radeon_device *rdev);
2335 void radeon_atombios_fini(struct radeon_device *rdev);
2336
2337
2338 /*
2339 * RING helpers.
2340 */
2341 #if DRM_DEBUG_CODE == 0
2342 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2343 {
2344 ring->ring[ring->wptr++] = v;
2345 ring->wptr &= ring->ptr_mask;
2346 ring->count_dw--;
2347 ring->ring_free_dw--;
2348 }
2349 #else
2350 /* With debugging this is just too big to inline */
2351 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2352 #endif
2353
2354 /*
2355 * ASICs macro.
2356 */
2357 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2358 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2359 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2360 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2361 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2362 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2363 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2364 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2365 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2366 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2367 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2368 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2369 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2370 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2371 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2372 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2373 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2374 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2375 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2376 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2377 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2378 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2379 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2380 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2381 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2382 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2383 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2384 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2385 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2386 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2387 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2388 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2389 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2390 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2391 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2392 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2393 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2394 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2395 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2396 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2397 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2398 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2399 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2400 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2401 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2402 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2403 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2404 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2405 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2406 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2407 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2408 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2409 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2410 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2411 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2412 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2413 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2414 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2415 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2416 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2417 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2418 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2419 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2420 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2421 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2422 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2423 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2424 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2425 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2426 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2427 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2428 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2429 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2430 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2431 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2432 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2433 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2434 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2435
2436 /* Common functions */
2437 /* AGP */
2438 extern int radeon_gpu_reset(struct radeon_device *rdev);
2439 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2440 extern void radeon_agp_disable(struct radeon_device *rdev);
2441 extern int radeon_modeset_init(struct radeon_device *rdev);
2442 extern void radeon_modeset_fini(struct radeon_device *rdev);
2443 extern bool radeon_card_posted(struct radeon_device *rdev);
2444 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2445 extern void radeon_update_display_priority(struct radeon_device *rdev);
2446 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2447 extern void radeon_scratch_init(struct radeon_device *rdev);
2448 extern void radeon_wb_fini(struct radeon_device *rdev);
2449 extern int radeon_wb_init(struct radeon_device *rdev);
2450 extern void radeon_wb_disable(struct radeon_device *rdev);
2451 extern void radeon_surface_init(struct radeon_device *rdev);
2452 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2453 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2454 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2455 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2456 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2457 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2458 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2459 extern int radeon_resume_kms(struct drm_device *dev);
2460 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2461 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2462 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2463 const u32 *registers,
2464 const u32 array_size);
2465
2466 /*
2467 * vm
2468 */
2469 int radeon_vm_manager_init(struct radeon_device *rdev);
2470 void radeon_vm_manager_fini(struct radeon_device *rdev);
2471 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2472 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2473 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2474 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2475 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2476 struct radeon_vm *vm, int ring);
2477 void radeon_vm_fence(struct radeon_device *rdev,
2478 struct radeon_vm *vm,
2479 struct radeon_fence *fence);
2480 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2481 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2482 struct radeon_vm *vm,
2483 struct radeon_bo *bo,
2484 struct ttm_mem_reg *mem);
2485 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2486 struct radeon_bo *bo);
2487 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2488 struct radeon_bo *bo);
2489 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2490 struct radeon_vm *vm,
2491 struct radeon_bo *bo);
2492 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2493 struct radeon_bo_va *bo_va,
2494 uint64_t offset,
2495 uint32_t flags);
2496 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2497 struct radeon_bo_va *bo_va);
2498
2499 /* audio */
2500 void r600_audio_update_hdmi(struct work_struct *work);
2501
2502 /*
2503 * R600 vram scratch functions
2504 */
2505 int r600_vram_scratch_init(struct radeon_device *rdev);
2506 void r600_vram_scratch_fini(struct radeon_device *rdev);
2507
2508 /*
2509 * r600 cs checking helper
2510 */
2511 unsigned r600_mip_minify(unsigned size, unsigned level);
2512 bool r600_fmt_is_valid_color(u32 format);
2513 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2514 int r600_fmt_get_blocksize(u32 format);
2515 int r600_fmt_get_nblocksx(u32 format, u32 w);
2516 int r600_fmt_get_nblocksy(u32 format, u32 h);
2517
2518 /*
2519 * r600 functions used by radeon_encoder.c
2520 */
2521 struct radeon_hdmi_acr {
2522 u32 clock;
2523
2524 int n_32khz;
2525 int cts_32khz;
2526
2527 int n_44_1khz;
2528 int cts_44_1khz;
2529
2530 int n_48khz;
2531 int cts_48khz;
2532
2533 };
2534
2535 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2536
2537 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2538 u32 tiling_pipe_num,
2539 u32 max_rb_num,
2540 u32 total_max_rb_num,
2541 u32 enabled_rb_mask);
2542
2543 /*
2544 * evergreen functions used by radeon_encoder.c
2545 */
2546
2547 extern int ni_init_microcode(struct radeon_device *rdev);
2548 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2549
2550 /* radeon_acpi.c */
2551 #if defined(CONFIG_ACPI)
2552 extern int radeon_acpi_init(struct radeon_device *rdev);
2553 extern void radeon_acpi_fini(struct radeon_device *rdev);
2554 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2555 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2556 u8 perf_req, bool advertise);
2557 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2558 #else
2559 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2560 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2561 #endif
2562
2563 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2564 struct radeon_cs_packet *pkt,
2565 unsigned idx);
2566 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2567 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2568 struct radeon_cs_packet *pkt);
2569 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2570 struct radeon_cs_reloc **cs_reloc,
2571 int nomm);
2572 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2573 uint32_t *vline_start_end,
2574 uint32_t *vline_status);
2575
2576 #include "radeon_object.h"
2577
2578 #endif
Linux kernel - Deliverables
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