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SUNRPC: Prevent kernel stack corruption on long values of flush
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98
99 /*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
110
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 3
113
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
116
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
120
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
124
125 /* hardcode those limit for now */
126 #define RADEON_VA_IB_OFFSET (1 << 20)
127 #define RADEON_VA_RESERVED_SIZE (8 << 20)
128 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
129
130 /*
131 * Errata workarounds.
132 */
133 enum radeon_pll_errata {
134 CHIP_ERRATA_R300_CG = 0x00000001,
135 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
136 CHIP_ERRATA_PLL_DELAY = 0x00000004
137 };
138
139
140 struct radeon_device;
141
142
143 /*
144 * BIOS.
145 */
146 bool radeon_get_bios(struct radeon_device *rdev);
147
148 /*
149 * Dummy page
150 */
151 struct radeon_dummy_page {
152 struct page *page;
153 dma_addr_t addr;
154 };
155 int radeon_dummy_page_init(struct radeon_device *rdev);
156 void radeon_dummy_page_fini(struct radeon_device *rdev);
157
158
159 /*
160 * Clocks
161 */
162 struct radeon_clock {
163 struct radeon_pll p1pll;
164 struct radeon_pll p2pll;
165 struct radeon_pll dcpll;
166 struct radeon_pll spll;
167 struct radeon_pll mpll;
168 /* 10 Khz units */
169 uint32_t default_mclk;
170 uint32_t default_sclk;
171 uint32_t default_dispclk;
172 uint32_t dp_extclk;
173 uint32_t max_pixel_clock;
174 };
175
176 /*
177 * Power management
178 */
179 int radeon_pm_init(struct radeon_device *rdev);
180 void radeon_pm_fini(struct radeon_device *rdev);
181 void radeon_pm_compute_clocks(struct radeon_device *rdev);
182 void radeon_pm_suspend(struct radeon_device *rdev);
183 void radeon_pm_resume(struct radeon_device *rdev);
184 void radeon_combios_get_power_modes(struct radeon_device *rdev);
185 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
186 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
187 void rs690_pm_info(struct radeon_device *rdev);
188 extern int rv6xx_get_temp(struct radeon_device *rdev);
189 extern int rv770_get_temp(struct radeon_device *rdev);
190 extern int evergreen_get_temp(struct radeon_device *rdev);
191 extern int sumo_get_temp(struct radeon_device *rdev);
192 extern int si_get_temp(struct radeon_device *rdev);
193 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
194 unsigned *bankh, unsigned *mtaspect,
195 unsigned *tile_split);
196
197 /*
198 * Fences.
199 */
200 struct radeon_fence_driver {
201 uint32_t scratch_reg;
202 uint64_t gpu_addr;
203 volatile uint32_t *cpu_addr;
204 /* sync_seq is protected by ring emission lock */
205 uint64_t sync_seq[RADEON_NUM_RINGS];
206 atomic64_t last_seq;
207 unsigned long last_activity;
208 bool initialized;
209 };
210
211 struct radeon_fence {
212 struct radeon_device *rdev;
213 struct kref kref;
214 /* protected by radeon_fence.lock */
215 uint64_t seq;
216 /* RB, DMA, etc. */
217 unsigned ring;
218 };
219
220 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
221 int radeon_fence_driver_init(struct radeon_device *rdev);
222 void radeon_fence_driver_fini(struct radeon_device *rdev);
223 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
224 void radeon_fence_process(struct radeon_device *rdev, int ring);
225 bool radeon_fence_signaled(struct radeon_fence *fence);
226 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
227 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
228 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
229 int radeon_fence_wait_any(struct radeon_device *rdev,
230 struct radeon_fence **fences,
231 bool intr);
232 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
233 void radeon_fence_unref(struct radeon_fence **fence);
234 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
235 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
236 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
237 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
238 struct radeon_fence *b)
239 {
240 if (!a) {
241 return b;
242 }
243
244 if (!b) {
245 return a;
246 }
247
248 BUG_ON(a->ring != b->ring);
249
250 if (a->seq > b->seq) {
251 return a;
252 } else {
253 return b;
254 }
255 }
256
257 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
258 struct radeon_fence *b)
259 {
260 if (!a) {
261 return false;
262 }
263
264 if (!b) {
265 return true;
266 }
267
268 BUG_ON(a->ring != b->ring);
269
270 return a->seq < b->seq;
271 }
272
273 /*
274 * Tiling registers
275 */
276 struct radeon_surface_reg {
277 struct radeon_bo *bo;
278 };
279
280 #define RADEON_GEM_MAX_SURFACES 8
281
282 /*
283 * TTM.
284 */
285 struct radeon_mman {
286 struct ttm_bo_global_ref bo_global_ref;
287 struct drm_global_reference mem_global_ref;
288 struct ttm_bo_device bdev;
289 bool mem_global_referenced;
290 bool initialized;
291 };
292
293 /* bo virtual address in a specific vm */
294 struct radeon_bo_va {
295 /* protected by bo being reserved */
296 struct list_head bo_list;
297 uint64_t soffset;
298 uint64_t eoffset;
299 uint32_t flags;
300 bool valid;
301 unsigned ref_count;
302
303 /* protected by vm mutex */
304 struct list_head vm_list;
305
306 /* constant after initialization */
307 struct radeon_vm *vm;
308 struct radeon_bo *bo;
309 };
310
311 struct radeon_bo {
312 /* Protected by gem.mutex */
313 struct list_head list;
314 /* Protected by tbo.reserved */
315 u32 placements[3];
316 struct ttm_placement placement;
317 struct ttm_buffer_object tbo;
318 struct ttm_bo_kmap_obj kmap;
319 unsigned pin_count;
320 void *kptr;
321 u32 tiling_flags;
322 u32 pitch;
323 int surface_reg;
324 /* list of all virtual address to which this bo
325 * is associated to
326 */
327 struct list_head va;
328 /* Constant after initialization */
329 struct radeon_device *rdev;
330 struct drm_gem_object gem_base;
331
332 struct ttm_bo_kmap_obj dma_buf_vmap;
333 int vmapping_count;
334 };
335 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
336
337 struct radeon_bo_list {
338 struct ttm_validate_buffer tv;
339 struct radeon_bo *bo;
340 uint64_t gpu_offset;
341 unsigned rdomain;
342 unsigned wdomain;
343 u32 tiling_flags;
344 };
345
346 /* sub-allocation manager, it has to be protected by another lock.
347 * By conception this is an helper for other part of the driver
348 * like the indirect buffer or semaphore, which both have their
349 * locking.
350 *
351 * Principe is simple, we keep a list of sub allocation in offset
352 * order (first entry has offset == 0, last entry has the highest
353 * offset).
354 *
355 * When allocating new object we first check if there is room at
356 * the end total_size - (last_object_offset + last_object_size) >=
357 * alloc_size. If so we allocate new object there.
358 *
359 * When there is not enough room at the end, we start waiting for
360 * each sub object until we reach object_offset+object_size >=
361 * alloc_size, this object then become the sub object we return.
362 *
363 * Alignment can't be bigger than page size.
364 *
365 * Hole are not considered for allocation to keep things simple.
366 * Assumption is that there won't be hole (all object on same
367 * alignment).
368 */
369 struct radeon_sa_manager {
370 wait_queue_head_t wq;
371 struct radeon_bo *bo;
372 struct list_head *hole;
373 struct list_head flist[RADEON_NUM_RINGS];
374 struct list_head olist;
375 unsigned size;
376 uint64_t gpu_addr;
377 void *cpu_ptr;
378 uint32_t domain;
379 };
380
381 struct radeon_sa_bo;
382
383 /* sub-allocation buffer */
384 struct radeon_sa_bo {
385 struct list_head olist;
386 struct list_head flist;
387 struct radeon_sa_manager *manager;
388 unsigned soffset;
389 unsigned eoffset;
390 struct radeon_fence *fence;
391 };
392
393 /*
394 * GEM objects.
395 */
396 struct radeon_gem {
397 struct mutex mutex;
398 struct list_head objects;
399 };
400
401 int radeon_gem_init(struct radeon_device *rdev);
402 void radeon_gem_fini(struct radeon_device *rdev);
403 int radeon_gem_object_create(struct radeon_device *rdev, int size,
404 int alignment, int initial_domain,
405 bool discardable, bool kernel,
406 struct drm_gem_object **obj);
407
408 int radeon_mode_dumb_create(struct drm_file *file_priv,
409 struct drm_device *dev,
410 struct drm_mode_create_dumb *args);
411 int radeon_mode_dumb_mmap(struct drm_file *filp,
412 struct drm_device *dev,
413 uint32_t handle, uint64_t *offset_p);
414 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
415 struct drm_device *dev,
416 uint32_t handle);
417
418 /*
419 * Semaphores.
420 */
421 /* everything here is constant */
422 struct radeon_semaphore {
423 struct radeon_sa_bo *sa_bo;
424 signed waiters;
425 uint64_t gpu_addr;
426 };
427
428 int radeon_semaphore_create(struct radeon_device *rdev,
429 struct radeon_semaphore **semaphore);
430 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
431 struct radeon_semaphore *semaphore);
432 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
433 struct radeon_semaphore *semaphore);
434 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
435 struct radeon_semaphore *semaphore,
436 int signaler, int waiter);
437 void radeon_semaphore_free(struct radeon_device *rdev,
438 struct radeon_semaphore **semaphore,
439 struct radeon_fence *fence);
440
441 /*
442 * GART structures, functions & helpers
443 */
444 struct radeon_mc;
445
446 #define RADEON_GPU_PAGE_SIZE 4096
447 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
448 #define RADEON_GPU_PAGE_SHIFT 12
449 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
450
451 struct radeon_gart {
452 dma_addr_t table_addr;
453 struct radeon_bo *robj;
454 void *ptr;
455 unsigned num_gpu_pages;
456 unsigned num_cpu_pages;
457 unsigned table_size;
458 struct page **pages;
459 dma_addr_t *pages_addr;
460 bool ready;
461 };
462
463 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
464 void radeon_gart_table_ram_free(struct radeon_device *rdev);
465 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
466 void radeon_gart_table_vram_free(struct radeon_device *rdev);
467 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
468 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
469 int radeon_gart_init(struct radeon_device *rdev);
470 void radeon_gart_fini(struct radeon_device *rdev);
471 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
472 int pages);
473 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
474 int pages, struct page **pagelist,
475 dma_addr_t *dma_addr);
476 void radeon_gart_restore(struct radeon_device *rdev);
477
478
479 /*
480 * GPU MC structures, functions & helpers
481 */
482 struct radeon_mc {
483 resource_size_t aper_size;
484 resource_size_t aper_base;
485 resource_size_t agp_base;
486 /* for some chips with <= 32MB we need to lie
487 * about vram size near mc fb location */
488 u64 mc_vram_size;
489 u64 visible_vram_size;
490 u64 gtt_size;
491 u64 gtt_start;
492 u64 gtt_end;
493 u64 vram_start;
494 u64 vram_end;
495 unsigned vram_width;
496 u64 real_vram_size;
497 int vram_mtrr;
498 bool vram_is_ddr;
499 bool igp_sideport_enabled;
500 u64 gtt_base_align;
501 };
502
503 bool radeon_combios_sideport_present(struct radeon_device *rdev);
504 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
505
506 /*
507 * GPU scratch registers structures, functions & helpers
508 */
509 struct radeon_scratch {
510 unsigned num_reg;
511 uint32_t reg_base;
512 bool free[32];
513 uint32_t reg[32];
514 };
515
516 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
517 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
518
519
520 /*
521 * IRQS.
522 */
523
524 struct radeon_unpin_work {
525 struct work_struct work;
526 struct radeon_device *rdev;
527 int crtc_id;
528 struct radeon_fence *fence;
529 struct drm_pending_vblank_event *event;
530 struct radeon_bo *old_rbo;
531 u64 new_crtc_base;
532 };
533
534 struct r500_irq_stat_regs {
535 u32 disp_int;
536 u32 hdmi0_status;
537 };
538
539 struct r600_irq_stat_regs {
540 u32 disp_int;
541 u32 disp_int_cont;
542 u32 disp_int_cont2;
543 u32 d1grph_int;
544 u32 d2grph_int;
545 u32 hdmi0_status;
546 u32 hdmi1_status;
547 };
548
549 struct evergreen_irq_stat_regs {
550 u32 disp_int;
551 u32 disp_int_cont;
552 u32 disp_int_cont2;
553 u32 disp_int_cont3;
554 u32 disp_int_cont4;
555 u32 disp_int_cont5;
556 u32 d1grph_int;
557 u32 d2grph_int;
558 u32 d3grph_int;
559 u32 d4grph_int;
560 u32 d5grph_int;
561 u32 d6grph_int;
562 u32 afmt_status1;
563 u32 afmt_status2;
564 u32 afmt_status3;
565 u32 afmt_status4;
566 u32 afmt_status5;
567 u32 afmt_status6;
568 };
569
570 union radeon_irq_stat_regs {
571 struct r500_irq_stat_regs r500;
572 struct r600_irq_stat_regs r600;
573 struct evergreen_irq_stat_regs evergreen;
574 };
575
576 #define RADEON_MAX_HPD_PINS 6
577 #define RADEON_MAX_CRTCS 6
578 #define RADEON_MAX_AFMT_BLOCKS 6
579
580 struct radeon_irq {
581 bool installed;
582 spinlock_t lock;
583 atomic_t ring_int[RADEON_NUM_RINGS];
584 bool crtc_vblank_int[RADEON_MAX_CRTCS];
585 atomic_t pflip[RADEON_MAX_CRTCS];
586 wait_queue_head_t vblank_queue;
587 bool hpd[RADEON_MAX_HPD_PINS];
588 bool afmt[RADEON_MAX_AFMT_BLOCKS];
589 union radeon_irq_stat_regs stat_regs;
590 };
591
592 int radeon_irq_kms_init(struct radeon_device *rdev);
593 void radeon_irq_kms_fini(struct radeon_device *rdev);
594 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
595 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
596 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
597 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
598 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
599 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
600 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
601 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
602
603 /*
604 * CP & rings.
605 */
606
607 struct radeon_ib {
608 struct radeon_sa_bo *sa_bo;
609 uint32_t length_dw;
610 uint64_t gpu_addr;
611 uint32_t *ptr;
612 int ring;
613 struct radeon_fence *fence;
614 struct radeon_vm *vm;
615 bool is_const_ib;
616 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
617 struct radeon_semaphore *semaphore;
618 };
619
620 struct radeon_ring {
621 struct radeon_bo *ring_obj;
622 volatile uint32_t *ring;
623 unsigned rptr;
624 unsigned rptr_offs;
625 unsigned rptr_reg;
626 unsigned rptr_save_reg;
627 u64 next_rptr_gpu_addr;
628 volatile u32 *next_rptr_cpu_addr;
629 unsigned wptr;
630 unsigned wptr_old;
631 unsigned wptr_reg;
632 unsigned ring_size;
633 unsigned ring_free_dw;
634 int count_dw;
635 unsigned long last_activity;
636 unsigned last_rptr;
637 uint64_t gpu_addr;
638 uint32_t align_mask;
639 uint32_t ptr_mask;
640 bool ready;
641 u32 ptr_reg_shift;
642 u32 ptr_reg_mask;
643 u32 nop;
644 u32 idx;
645 };
646
647 /*
648 * VM
649 */
650
651 /* maximum number of VMIDs */
652 #define RADEON_NUM_VM 16
653
654 /* defines number of bits in page table versus page directory,
655 * a page is 4KB so we have 12 bits offset, 9 bits in the page
656 * table and the remaining 19 bits are in the page directory */
657 #define RADEON_VM_BLOCK_SIZE 9
658
659 /* number of entries in page table */
660 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
661
662 struct radeon_vm {
663 struct list_head list;
664 struct list_head va;
665 unsigned id;
666 unsigned last_pfn;
667 u64 pd_gpu_addr;
668 struct radeon_sa_bo *sa_bo;
669 struct mutex mutex;
670 /* last fence for cs using this vm */
671 struct radeon_fence *fence;
672 /* last flush or NULL if we still need to flush */
673 struct radeon_fence *last_flush;
674 };
675
676 struct radeon_vm_manager {
677 struct mutex lock;
678 struct list_head lru_vm;
679 struct radeon_fence *active[RADEON_NUM_VM];
680 struct radeon_sa_manager sa_manager;
681 uint32_t max_pfn;
682 /* number of VMIDs */
683 unsigned nvm;
684 /* vram base address for page table entry */
685 u64 vram_base_offset;
686 /* is vm enabled? */
687 bool enabled;
688 };
689
690 /*
691 * file private structure
692 */
693 struct radeon_fpriv {
694 struct radeon_vm vm;
695 };
696
697 /*
698 * R6xx+ IH ring
699 */
700 struct r600_ih {
701 struct radeon_bo *ring_obj;
702 volatile uint32_t *ring;
703 unsigned rptr;
704 unsigned ring_size;
705 uint64_t gpu_addr;
706 uint32_t ptr_mask;
707 atomic_t lock;
708 bool enabled;
709 };
710
711 struct r600_blit_cp_primitives {
712 void (*set_render_target)(struct radeon_device *rdev, int format,
713 int w, int h, u64 gpu_addr);
714 void (*cp_set_surface_sync)(struct radeon_device *rdev,
715 u32 sync_type, u32 size,
716 u64 mc_addr);
717 void (*set_shaders)(struct radeon_device *rdev);
718 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
719 void (*set_tex_resource)(struct radeon_device *rdev,
720 int format, int w, int h, int pitch,
721 u64 gpu_addr, u32 size);
722 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
723 int x2, int y2);
724 void (*draw_auto)(struct radeon_device *rdev);
725 void (*set_default_state)(struct radeon_device *rdev);
726 };
727
728 struct r600_blit {
729 struct radeon_bo *shader_obj;
730 struct r600_blit_cp_primitives primitives;
731 int max_dim;
732 int ring_size_common;
733 int ring_size_per_loop;
734 u64 shader_gpu_addr;
735 u32 vs_offset, ps_offset;
736 u32 state_offset;
737 u32 state_len;
738 };
739
740 /*
741 * SI RLC stuff
742 */
743 struct si_rlc {
744 /* for power gating */
745 struct radeon_bo *save_restore_obj;
746 uint64_t save_restore_gpu_addr;
747 /* for clear state */
748 struct radeon_bo *clear_state_obj;
749 uint64_t clear_state_gpu_addr;
750 };
751
752 int radeon_ib_get(struct radeon_device *rdev, int ring,
753 struct radeon_ib *ib, struct radeon_vm *vm,
754 unsigned size);
755 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
756 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
757 struct radeon_ib *const_ib);
758 int radeon_ib_pool_init(struct radeon_device *rdev);
759 void radeon_ib_pool_fini(struct radeon_device *rdev);
760 int radeon_ib_ring_tests(struct radeon_device *rdev);
761 /* Ring access between begin & end cannot sleep */
762 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
763 struct radeon_ring *ring);
764 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
765 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
766 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
767 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
768 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
769 void radeon_ring_undo(struct radeon_ring *ring);
770 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
771 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
772 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
773 void radeon_ring_lockup_update(struct radeon_ring *ring);
774 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
775 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
776 uint32_t **data);
777 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
778 unsigned size, uint32_t *data);
779 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
780 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
781 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
782 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
783
784
785 /*
786 * CS.
787 */
788 struct radeon_cs_reloc {
789 struct drm_gem_object *gobj;
790 struct radeon_bo *robj;
791 struct radeon_bo_list lobj;
792 uint32_t handle;
793 uint32_t flags;
794 };
795
796 struct radeon_cs_chunk {
797 uint32_t chunk_id;
798 uint32_t length_dw;
799 int kpage_idx[2];
800 uint32_t *kpage[2];
801 uint32_t *kdata;
802 void __user *user_ptr;
803 int last_copied_page;
804 int last_page_index;
805 };
806
807 struct radeon_cs_parser {
808 struct device *dev;
809 struct radeon_device *rdev;
810 struct drm_file *filp;
811 /* chunks */
812 unsigned nchunks;
813 struct radeon_cs_chunk *chunks;
814 uint64_t *chunks_array;
815 /* IB */
816 unsigned idx;
817 /* relocations */
818 unsigned nrelocs;
819 struct radeon_cs_reloc *relocs;
820 struct radeon_cs_reloc **relocs_ptr;
821 struct list_head validated;
822 /* indices of various chunks */
823 int chunk_ib_idx;
824 int chunk_relocs_idx;
825 int chunk_flags_idx;
826 int chunk_const_ib_idx;
827 struct radeon_ib ib;
828 struct radeon_ib const_ib;
829 void *track;
830 unsigned family;
831 int parser_error;
832 u32 cs_flags;
833 u32 ring;
834 s32 priority;
835 };
836
837 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
838 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
839
840 struct radeon_cs_packet {
841 unsigned idx;
842 unsigned type;
843 unsigned reg;
844 unsigned opcode;
845 int count;
846 unsigned one_reg_wr;
847 };
848
849 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
850 struct radeon_cs_packet *pkt,
851 unsigned idx, unsigned reg);
852 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
853 struct radeon_cs_packet *pkt);
854
855
856 /*
857 * AGP
858 */
859 int radeon_agp_init(struct radeon_device *rdev);
860 void radeon_agp_resume(struct radeon_device *rdev);
861 void radeon_agp_suspend(struct radeon_device *rdev);
862 void radeon_agp_fini(struct radeon_device *rdev);
863
864
865 /*
866 * Writeback
867 */
868 struct radeon_wb {
869 struct radeon_bo *wb_obj;
870 volatile uint32_t *wb;
871 uint64_t gpu_addr;
872 bool enabled;
873 bool use_event;
874 };
875
876 #define RADEON_WB_SCRATCH_OFFSET 0
877 #define RADEON_WB_RING0_NEXT_RPTR 256
878 #define RADEON_WB_CP_RPTR_OFFSET 1024
879 #define RADEON_WB_CP1_RPTR_OFFSET 1280
880 #define RADEON_WB_CP2_RPTR_OFFSET 1536
881 #define R600_WB_IH_WPTR_OFFSET 2048
882 #define R600_WB_EVENT_OFFSET 3072
883
884 /**
885 * struct radeon_pm - power management datas
886 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
887 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
888 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
889 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
890 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
891 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
892 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
893 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
894 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
895 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
896 * @needed_bandwidth: current bandwidth needs
897 *
898 * It keeps track of various data needed to take powermanagement decision.
899 * Bandwidth need is used to determine minimun clock of the GPU and memory.
900 * Equation between gpu/memory clock and available bandwidth is hw dependent
901 * (type of memory, bus size, efficiency, ...)
902 */
903
904 enum radeon_pm_method {
905 PM_METHOD_PROFILE,
906 PM_METHOD_DYNPM,
907 };
908
909 enum radeon_dynpm_state {
910 DYNPM_STATE_DISABLED,
911 DYNPM_STATE_MINIMUM,
912 DYNPM_STATE_PAUSED,
913 DYNPM_STATE_ACTIVE,
914 DYNPM_STATE_SUSPENDED,
915 };
916 enum radeon_dynpm_action {
917 DYNPM_ACTION_NONE,
918 DYNPM_ACTION_MINIMUM,
919 DYNPM_ACTION_DOWNCLOCK,
920 DYNPM_ACTION_UPCLOCK,
921 DYNPM_ACTION_DEFAULT
922 };
923
924 enum radeon_voltage_type {
925 VOLTAGE_NONE = 0,
926 VOLTAGE_GPIO,
927 VOLTAGE_VDDC,
928 VOLTAGE_SW
929 };
930
931 enum radeon_pm_state_type {
932 POWER_STATE_TYPE_DEFAULT,
933 POWER_STATE_TYPE_POWERSAVE,
934 POWER_STATE_TYPE_BATTERY,
935 POWER_STATE_TYPE_BALANCED,
936 POWER_STATE_TYPE_PERFORMANCE,
937 };
938
939 enum radeon_pm_profile_type {
940 PM_PROFILE_DEFAULT,
941 PM_PROFILE_AUTO,
942 PM_PROFILE_LOW,
943 PM_PROFILE_MID,
944 PM_PROFILE_HIGH,
945 };
946
947 #define PM_PROFILE_DEFAULT_IDX 0
948 #define PM_PROFILE_LOW_SH_IDX 1
949 #define PM_PROFILE_MID_SH_IDX 2
950 #define PM_PROFILE_HIGH_SH_IDX 3
951 #define PM_PROFILE_LOW_MH_IDX 4
952 #define PM_PROFILE_MID_MH_IDX 5
953 #define PM_PROFILE_HIGH_MH_IDX 6
954 #define PM_PROFILE_MAX 7
955
956 struct radeon_pm_profile {
957 int dpms_off_ps_idx;
958 int dpms_on_ps_idx;
959 int dpms_off_cm_idx;
960 int dpms_on_cm_idx;
961 };
962
963 enum radeon_int_thermal_type {
964 THERMAL_TYPE_NONE,
965 THERMAL_TYPE_RV6XX,
966 THERMAL_TYPE_RV770,
967 THERMAL_TYPE_EVERGREEN,
968 THERMAL_TYPE_SUMO,
969 THERMAL_TYPE_NI,
970 THERMAL_TYPE_SI,
971 };
972
973 struct radeon_voltage {
974 enum radeon_voltage_type type;
975 /* gpio voltage */
976 struct radeon_gpio_rec gpio;
977 u32 delay; /* delay in usec from voltage drop to sclk change */
978 bool active_high; /* voltage drop is active when bit is high */
979 /* VDDC voltage */
980 u8 vddc_id; /* index into vddc voltage table */
981 u8 vddci_id; /* index into vddci voltage table */
982 bool vddci_enabled;
983 /* r6xx+ sw */
984 u16 voltage;
985 /* evergreen+ vddci */
986 u16 vddci;
987 };
988
989 /* clock mode flags */
990 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
991
992 struct radeon_pm_clock_info {
993 /* memory clock */
994 u32 mclk;
995 /* engine clock */
996 u32 sclk;
997 /* voltage info */
998 struct radeon_voltage voltage;
999 /* standardized clock flags */
1000 u32 flags;
1001 };
1002
1003 /* state flags */
1004 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1005
1006 struct radeon_power_state {
1007 enum radeon_pm_state_type type;
1008 struct radeon_pm_clock_info *clock_info;
1009 /* number of valid clock modes in this power state */
1010 int num_clock_modes;
1011 struct radeon_pm_clock_info *default_clock_mode;
1012 /* standardized state flags */
1013 u32 flags;
1014 u32 misc; /* vbios specific flags */
1015 u32 misc2; /* vbios specific flags */
1016 int pcie_lanes; /* pcie lanes */
1017 };
1018
1019 /*
1020 * Some modes are overclocked by very low value, accept them
1021 */
1022 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1023
1024 struct radeon_pm {
1025 struct mutex mutex;
1026 /* write locked while reprogramming mclk */
1027 struct rw_semaphore mclk_lock;
1028 u32 active_crtcs;
1029 int active_crtc_count;
1030 int req_vblank;
1031 bool vblank_sync;
1032 fixed20_12 max_bandwidth;
1033 fixed20_12 igp_sideport_mclk;
1034 fixed20_12 igp_system_mclk;
1035 fixed20_12 igp_ht_link_clk;
1036 fixed20_12 igp_ht_link_width;
1037 fixed20_12 k8_bandwidth;
1038 fixed20_12 sideport_bandwidth;
1039 fixed20_12 ht_bandwidth;
1040 fixed20_12 core_bandwidth;
1041 fixed20_12 sclk;
1042 fixed20_12 mclk;
1043 fixed20_12 needed_bandwidth;
1044 struct radeon_power_state *power_state;
1045 /* number of valid power states */
1046 int num_power_states;
1047 int current_power_state_index;
1048 int current_clock_mode_index;
1049 int requested_power_state_index;
1050 int requested_clock_mode_index;
1051 int default_power_state_index;
1052 u32 current_sclk;
1053 u32 current_mclk;
1054 u16 current_vddc;
1055 u16 current_vddci;
1056 u32 default_sclk;
1057 u32 default_mclk;
1058 u16 default_vddc;
1059 u16 default_vddci;
1060 struct radeon_i2c_chan *i2c_bus;
1061 /* selected pm method */
1062 enum radeon_pm_method pm_method;
1063 /* dynpm power management */
1064 struct delayed_work dynpm_idle_work;
1065 enum radeon_dynpm_state dynpm_state;
1066 enum radeon_dynpm_action dynpm_planned_action;
1067 unsigned long dynpm_action_timeout;
1068 bool dynpm_can_upclock;
1069 bool dynpm_can_downclock;
1070 /* profile-based power management */
1071 enum radeon_pm_profile_type profile;
1072 int profile_index;
1073 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1074 /* internal thermal controller on rv6xx+ */
1075 enum radeon_int_thermal_type int_thermal_type;
1076 struct device *int_hwmon_dev;
1077 };
1078
1079 int radeon_pm_get_type_index(struct radeon_device *rdev,
1080 enum radeon_pm_state_type ps_type,
1081 int instance);
1082
1083 struct r600_audio {
1084 int channels;
1085 int rate;
1086 int bits_per_sample;
1087 u8 status_bits;
1088 u8 category_code;
1089 };
1090
1091 /*
1092 * Benchmarking
1093 */
1094 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1095
1096
1097 /*
1098 * Testing
1099 */
1100 void radeon_test_moves(struct radeon_device *rdev);
1101 void radeon_test_ring_sync(struct radeon_device *rdev,
1102 struct radeon_ring *cpA,
1103 struct radeon_ring *cpB);
1104 void radeon_test_syncing(struct radeon_device *rdev);
1105
1106
1107 /*
1108 * Debugfs
1109 */
1110 struct radeon_debugfs {
1111 struct drm_info_list *files;
1112 unsigned num_files;
1113 };
1114
1115 int radeon_debugfs_add_files(struct radeon_device *rdev,
1116 struct drm_info_list *files,
1117 unsigned nfiles);
1118 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1119
1120
1121 /*
1122 * ASIC specific functions.
1123 */
1124 struct radeon_asic {
1125 int (*init)(struct radeon_device *rdev);
1126 void (*fini)(struct radeon_device *rdev);
1127 int (*resume)(struct radeon_device *rdev);
1128 int (*suspend)(struct radeon_device *rdev);
1129 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1130 int (*asic_reset)(struct radeon_device *rdev);
1131 /* ioctl hw specific callback. Some hw might want to perform special
1132 * operation on specific ioctl. For instance on wait idle some hw
1133 * might want to perform and HDP flush through MMIO as it seems that
1134 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1135 * through ring.
1136 */
1137 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1138 /* check if 3D engine is idle */
1139 bool (*gui_idle)(struct radeon_device *rdev);
1140 /* wait for mc_idle */
1141 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1142 /* gart */
1143 struct {
1144 void (*tlb_flush)(struct radeon_device *rdev);
1145 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1146 } gart;
1147 struct {
1148 int (*init)(struct radeon_device *rdev);
1149 void (*fini)(struct radeon_device *rdev);
1150
1151 u32 pt_ring_index;
1152 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
1153 uint64_t addr, unsigned count,
1154 uint32_t incr, uint32_t flags);
1155 } vm;
1156 /* ring specific callbacks */
1157 struct {
1158 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1159 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1160 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1161 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1162 struct radeon_semaphore *semaphore, bool emit_wait);
1163 int (*cs_parse)(struct radeon_cs_parser *p);
1164 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1165 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1166 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1167 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1168 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1169 } ring[RADEON_NUM_RINGS];
1170 /* irqs */
1171 struct {
1172 int (*set)(struct radeon_device *rdev);
1173 int (*process)(struct radeon_device *rdev);
1174 } irq;
1175 /* displays */
1176 struct {
1177 /* display watermarks */
1178 void (*bandwidth_update)(struct radeon_device *rdev);
1179 /* get frame count */
1180 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1181 /* wait for vblank */
1182 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1183 /* set backlight level */
1184 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1185 /* get backlight level */
1186 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1187 } display;
1188 /* copy functions for bo handling */
1189 struct {
1190 int (*blit)(struct radeon_device *rdev,
1191 uint64_t src_offset,
1192 uint64_t dst_offset,
1193 unsigned num_gpu_pages,
1194 struct radeon_fence **fence);
1195 u32 blit_ring_index;
1196 int (*dma)(struct radeon_device *rdev,
1197 uint64_t src_offset,
1198 uint64_t dst_offset,
1199 unsigned num_gpu_pages,
1200 struct radeon_fence **fence);
1201 u32 dma_ring_index;
1202 /* method used for bo copy */
1203 int (*copy)(struct radeon_device *rdev,
1204 uint64_t src_offset,
1205 uint64_t dst_offset,
1206 unsigned num_gpu_pages,
1207 struct radeon_fence **fence);
1208 /* ring used for bo copies */
1209 u32 copy_ring_index;
1210 } copy;
1211 /* surfaces */
1212 struct {
1213 int (*set_reg)(struct radeon_device *rdev, int reg,
1214 uint32_t tiling_flags, uint32_t pitch,
1215 uint32_t offset, uint32_t obj_size);
1216 void (*clear_reg)(struct radeon_device *rdev, int reg);
1217 } surface;
1218 /* hotplug detect */
1219 struct {
1220 void (*init)(struct radeon_device *rdev);
1221 void (*fini)(struct radeon_device *rdev);
1222 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1223 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1224 } hpd;
1225 /* power management */
1226 struct {
1227 void (*misc)(struct radeon_device *rdev);
1228 void (*prepare)(struct radeon_device *rdev);
1229 void (*finish)(struct radeon_device *rdev);
1230 void (*init_profile)(struct radeon_device *rdev);
1231 void (*get_dynpm_state)(struct radeon_device *rdev);
1232 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1233 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1234 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1235 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1236 int (*get_pcie_lanes)(struct radeon_device *rdev);
1237 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1238 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1239 } pm;
1240 /* pageflipping */
1241 struct {
1242 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1243 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1244 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1245 } pflip;
1246 };
1247
1248 /*
1249 * Asic structures
1250 */
1251 struct r100_asic {
1252 const unsigned *reg_safe_bm;
1253 unsigned reg_safe_bm_size;
1254 u32 hdp_cntl;
1255 };
1256
1257 struct r300_asic {
1258 const unsigned *reg_safe_bm;
1259 unsigned reg_safe_bm_size;
1260 u32 resync_scratch;
1261 u32 hdp_cntl;
1262 };
1263
1264 struct r600_asic {
1265 unsigned max_pipes;
1266 unsigned max_tile_pipes;
1267 unsigned max_simds;
1268 unsigned max_backends;
1269 unsigned max_gprs;
1270 unsigned max_threads;
1271 unsigned max_stack_entries;
1272 unsigned max_hw_contexts;
1273 unsigned max_gs_threads;
1274 unsigned sx_max_export_size;
1275 unsigned sx_max_export_pos_size;
1276 unsigned sx_max_export_smx_size;
1277 unsigned sq_num_cf_insts;
1278 unsigned tiling_nbanks;
1279 unsigned tiling_npipes;
1280 unsigned tiling_group_size;
1281 unsigned tile_config;
1282 unsigned backend_map;
1283 };
1284
1285 struct rv770_asic {
1286 unsigned max_pipes;
1287 unsigned max_tile_pipes;
1288 unsigned max_simds;
1289 unsigned max_backends;
1290 unsigned max_gprs;
1291 unsigned max_threads;
1292 unsigned max_stack_entries;
1293 unsigned max_hw_contexts;
1294 unsigned max_gs_threads;
1295 unsigned sx_max_export_size;
1296 unsigned sx_max_export_pos_size;
1297 unsigned sx_max_export_smx_size;
1298 unsigned sq_num_cf_insts;
1299 unsigned sx_num_of_sets;
1300 unsigned sc_prim_fifo_size;
1301 unsigned sc_hiz_tile_fifo_size;
1302 unsigned sc_earlyz_tile_fifo_fize;
1303 unsigned tiling_nbanks;
1304 unsigned tiling_npipes;
1305 unsigned tiling_group_size;
1306 unsigned tile_config;
1307 unsigned backend_map;
1308 };
1309
1310 struct evergreen_asic {
1311 unsigned num_ses;
1312 unsigned max_pipes;
1313 unsigned max_tile_pipes;
1314 unsigned max_simds;
1315 unsigned max_backends;
1316 unsigned max_gprs;
1317 unsigned max_threads;
1318 unsigned max_stack_entries;
1319 unsigned max_hw_contexts;
1320 unsigned max_gs_threads;
1321 unsigned sx_max_export_size;
1322 unsigned sx_max_export_pos_size;
1323 unsigned sx_max_export_smx_size;
1324 unsigned sq_num_cf_insts;
1325 unsigned sx_num_of_sets;
1326 unsigned sc_prim_fifo_size;
1327 unsigned sc_hiz_tile_fifo_size;
1328 unsigned sc_earlyz_tile_fifo_size;
1329 unsigned tiling_nbanks;
1330 unsigned tiling_npipes;
1331 unsigned tiling_group_size;
1332 unsigned tile_config;
1333 unsigned backend_map;
1334 };
1335
1336 struct cayman_asic {
1337 unsigned max_shader_engines;
1338 unsigned max_pipes_per_simd;
1339 unsigned max_tile_pipes;
1340 unsigned max_simds_per_se;
1341 unsigned max_backends_per_se;
1342 unsigned max_texture_channel_caches;
1343 unsigned max_gprs;
1344 unsigned max_threads;
1345 unsigned max_gs_threads;
1346 unsigned max_stack_entries;
1347 unsigned sx_num_of_sets;
1348 unsigned sx_max_export_size;
1349 unsigned sx_max_export_pos_size;
1350 unsigned sx_max_export_smx_size;
1351 unsigned max_hw_contexts;
1352 unsigned sq_num_cf_insts;
1353 unsigned sc_prim_fifo_size;
1354 unsigned sc_hiz_tile_fifo_size;
1355 unsigned sc_earlyz_tile_fifo_size;
1356
1357 unsigned num_shader_engines;
1358 unsigned num_shader_pipes_per_simd;
1359 unsigned num_tile_pipes;
1360 unsigned num_simds_per_se;
1361 unsigned num_backends_per_se;
1362 unsigned backend_disable_mask_per_asic;
1363 unsigned backend_map;
1364 unsigned num_texture_channel_caches;
1365 unsigned mem_max_burst_length_bytes;
1366 unsigned mem_row_size_in_kb;
1367 unsigned shader_engine_tile_size;
1368 unsigned num_gpus;
1369 unsigned multi_gpu_tile_size;
1370
1371 unsigned tile_config;
1372 };
1373
1374 struct si_asic {
1375 unsigned max_shader_engines;
1376 unsigned max_tile_pipes;
1377 unsigned max_cu_per_sh;
1378 unsigned max_sh_per_se;
1379 unsigned max_backends_per_se;
1380 unsigned max_texture_channel_caches;
1381 unsigned max_gprs;
1382 unsigned max_gs_threads;
1383 unsigned max_hw_contexts;
1384 unsigned sc_prim_fifo_size_frontend;
1385 unsigned sc_prim_fifo_size_backend;
1386 unsigned sc_hiz_tile_fifo_size;
1387 unsigned sc_earlyz_tile_fifo_size;
1388
1389 unsigned num_tile_pipes;
1390 unsigned num_backends_per_se;
1391 unsigned backend_disable_mask_per_asic;
1392 unsigned backend_map;
1393 unsigned num_texture_channel_caches;
1394 unsigned mem_max_burst_length_bytes;
1395 unsigned mem_row_size_in_kb;
1396 unsigned shader_engine_tile_size;
1397 unsigned num_gpus;
1398 unsigned multi_gpu_tile_size;
1399
1400 unsigned tile_config;
1401 };
1402
1403 union radeon_asic_config {
1404 struct r300_asic r300;
1405 struct r100_asic r100;
1406 struct r600_asic r600;
1407 struct rv770_asic rv770;
1408 struct evergreen_asic evergreen;
1409 struct cayman_asic cayman;
1410 struct si_asic si;
1411 };
1412
1413 /*
1414 * asic initizalization from radeon_asic.c
1415 */
1416 void radeon_agp_disable(struct radeon_device *rdev);
1417 int radeon_asic_init(struct radeon_device *rdev);
1418
1419
1420 /*
1421 * IOCTL.
1422 */
1423 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1424 struct drm_file *filp);
1425 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1426 struct drm_file *filp);
1427 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1428 struct drm_file *file_priv);
1429 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1430 struct drm_file *file_priv);
1431 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1432 struct drm_file *file_priv);
1433 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1434 struct drm_file *file_priv);
1435 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1436 struct drm_file *filp);
1437 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1438 struct drm_file *filp);
1439 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1440 struct drm_file *filp);
1441 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1442 struct drm_file *filp);
1443 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1444 struct drm_file *filp);
1445 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1446 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1447 struct drm_file *filp);
1448 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1449 struct drm_file *filp);
1450
1451 /* VRAM scratch page for HDP bug, default vram page */
1452 struct r600_vram_scratch {
1453 struct radeon_bo *robj;
1454 volatile uint32_t *ptr;
1455 u64 gpu_addr;
1456 };
1457
1458 /*
1459 * ACPI
1460 */
1461 struct radeon_atif_notification_cfg {
1462 bool enabled;
1463 int command_code;
1464 };
1465
1466 struct radeon_atif_notifications {
1467 bool display_switch;
1468 bool expansion_mode_change;
1469 bool thermal_state;
1470 bool forced_power_state;
1471 bool system_power_state;
1472 bool display_conf_change;
1473 bool px_gfx_switch;
1474 bool brightness_change;
1475 bool dgpu_display_event;
1476 };
1477
1478 struct radeon_atif_functions {
1479 bool system_params;
1480 bool sbios_requests;
1481 bool select_active_disp;
1482 bool lid_state;
1483 bool get_tv_standard;
1484 bool set_tv_standard;
1485 bool get_panel_expansion_mode;
1486 bool set_panel_expansion_mode;
1487 bool temperature_change;
1488 bool graphics_device_types;
1489 };
1490
1491 struct radeon_atif {
1492 struct radeon_atif_notifications notifications;
1493 struct radeon_atif_functions functions;
1494 struct radeon_atif_notification_cfg notification_cfg;
1495 struct radeon_encoder *encoder_for_bl;
1496 };
1497
1498 struct radeon_atcs_functions {
1499 bool get_ext_state;
1500 bool pcie_perf_req;
1501 bool pcie_dev_rdy;
1502 bool pcie_bus_width;
1503 };
1504
1505 struct radeon_atcs {
1506 struct radeon_atcs_functions functions;
1507 };
1508
1509 /*
1510 * Core structure, functions and helpers.
1511 */
1512 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1513 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1514
1515 struct radeon_device {
1516 struct device *dev;
1517 struct drm_device *ddev;
1518 struct pci_dev *pdev;
1519 struct rw_semaphore exclusive_lock;
1520 /* ASIC */
1521 union radeon_asic_config config;
1522 enum radeon_family family;
1523 unsigned long flags;
1524 int usec_timeout;
1525 enum radeon_pll_errata pll_errata;
1526 int num_gb_pipes;
1527 int num_z_pipes;
1528 int disp_priority;
1529 /* BIOS */
1530 uint8_t *bios;
1531 bool is_atom_bios;
1532 uint16_t bios_header_start;
1533 struct radeon_bo *stollen_vga_memory;
1534 /* Register mmio */
1535 resource_size_t rmmio_base;
1536 resource_size_t rmmio_size;
1537 void __iomem *rmmio;
1538 radeon_rreg_t mc_rreg;
1539 radeon_wreg_t mc_wreg;
1540 radeon_rreg_t pll_rreg;
1541 radeon_wreg_t pll_wreg;
1542 uint32_t pcie_reg_mask;
1543 radeon_rreg_t pciep_rreg;
1544 radeon_wreg_t pciep_wreg;
1545 /* io port */
1546 void __iomem *rio_mem;
1547 resource_size_t rio_mem_size;
1548 struct radeon_clock clock;
1549 struct radeon_mc mc;
1550 struct radeon_gart gart;
1551 struct radeon_mode_info mode_info;
1552 struct radeon_scratch scratch;
1553 struct radeon_mman mman;
1554 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1555 wait_queue_head_t fence_queue;
1556 struct mutex ring_lock;
1557 struct radeon_ring ring[RADEON_NUM_RINGS];
1558 bool ib_pool_ready;
1559 struct radeon_sa_manager ring_tmp_bo;
1560 struct radeon_irq irq;
1561 struct radeon_asic *asic;
1562 struct radeon_gem gem;
1563 struct radeon_pm pm;
1564 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1565 struct radeon_wb wb;
1566 struct radeon_dummy_page dummy_page;
1567 bool shutdown;
1568 bool suspend;
1569 bool need_dma32;
1570 bool accel_working;
1571 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1572 const struct firmware *me_fw; /* all family ME firmware */
1573 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1574 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1575 const struct firmware *mc_fw; /* NI MC firmware */
1576 const struct firmware *ce_fw; /* SI CE firmware */
1577 struct r600_blit r600_blit;
1578 struct r600_vram_scratch vram_scratch;
1579 int msi_enabled; /* msi enabled */
1580 struct r600_ih ih; /* r6/700 interrupt ring */
1581 struct si_rlc rlc;
1582 struct work_struct hotplug_work;
1583 struct work_struct audio_work;
1584 int num_crtc; /* number of crtcs */
1585 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1586 bool audio_enabled;
1587 struct r600_audio audio_status; /* audio stuff */
1588 struct notifier_block acpi_nb;
1589 /* only one userspace can use Hyperz features or CMASK at a time */
1590 struct drm_file *hyperz_filp;
1591 struct drm_file *cmask_filp;
1592 /* i2c buses */
1593 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1594 /* debugfs */
1595 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1596 unsigned debugfs_count;
1597 /* virtual memory */
1598 struct radeon_vm_manager vm_manager;
1599 struct mutex gpu_clock_mutex;
1600 /* ACPI interface */
1601 struct radeon_atif atif;
1602 struct radeon_atcs atcs;
1603 };
1604
1605 int radeon_device_init(struct radeon_device *rdev,
1606 struct drm_device *ddev,
1607 struct pci_dev *pdev,
1608 uint32_t flags);
1609 void radeon_device_fini(struct radeon_device *rdev);
1610 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1611
1612 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1613 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1614 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1615 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1616
1617 /*
1618 * Cast helper
1619 */
1620 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1621
1622 /*
1623 * Registers read & write functions.
1624 */
1625 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1626 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1627 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1628 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1629 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1630 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1631 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1632 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1633 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1634 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1635 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1636 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1637 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1638 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1639 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1640 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1641 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1642 #define WREG32_P(reg, val, mask) \
1643 do { \
1644 uint32_t tmp_ = RREG32(reg); \
1645 tmp_ &= (mask); \
1646 tmp_ |= ((val) & ~(mask)); \
1647 WREG32(reg, tmp_); \
1648 } while (0)
1649 #define WREG32_PLL_P(reg, val, mask) \
1650 do { \
1651 uint32_t tmp_ = RREG32_PLL(reg); \
1652 tmp_ &= (mask); \
1653 tmp_ |= ((val) & ~(mask)); \
1654 WREG32_PLL(reg, tmp_); \
1655 } while (0)
1656 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1657 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1658 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1659
1660 /*
1661 * Indirect registers accessor
1662 */
1663 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1664 {
1665 uint32_t r;
1666
1667 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1668 r = RREG32(RADEON_PCIE_DATA);
1669 return r;
1670 }
1671
1672 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1673 {
1674 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1675 WREG32(RADEON_PCIE_DATA, (v));
1676 }
1677
1678 void r100_pll_errata_after_index(struct radeon_device *rdev);
1679
1680
1681 /*
1682 * ASICs helpers.
1683 */
1684 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1685 (rdev->pdev->device == 0x5969))
1686 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1687 (rdev->family == CHIP_RV200) || \
1688 (rdev->family == CHIP_RS100) || \
1689 (rdev->family == CHIP_RS200) || \
1690 (rdev->family == CHIP_RV250) || \
1691 (rdev->family == CHIP_RV280) || \
1692 (rdev->family == CHIP_RS300))
1693 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1694 (rdev->family == CHIP_RV350) || \
1695 (rdev->family == CHIP_R350) || \
1696 (rdev->family == CHIP_RV380) || \
1697 (rdev->family == CHIP_R420) || \
1698 (rdev->family == CHIP_R423) || \
1699 (rdev->family == CHIP_RV410) || \
1700 (rdev->family == CHIP_RS400) || \
1701 (rdev->family == CHIP_RS480))
1702 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1703 (rdev->ddev->pdev->device == 0x9443) || \
1704 (rdev->ddev->pdev->device == 0x944B) || \
1705 (rdev->ddev->pdev->device == 0x9506) || \
1706 (rdev->ddev->pdev->device == 0x9509) || \
1707 (rdev->ddev->pdev->device == 0x950F) || \
1708 (rdev->ddev->pdev->device == 0x689C) || \
1709 (rdev->ddev->pdev->device == 0x689D))
1710 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1711 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1712 (rdev->family == CHIP_RS690) || \
1713 (rdev->family == CHIP_RS740) || \
1714 (rdev->family >= CHIP_R600))
1715 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1716 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1717 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1718 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1719 (rdev->flags & RADEON_IS_IGP))
1720 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1721 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1722 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1723 (rdev->flags & RADEON_IS_IGP))
1724
1725 /*
1726 * BIOS helpers.
1727 */
1728 #define RBIOS8(i) (rdev->bios[i])
1729 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1730 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1731
1732 int radeon_combios_init(struct radeon_device *rdev);
1733 void radeon_combios_fini(struct radeon_device *rdev);
1734 int radeon_atombios_init(struct radeon_device *rdev);
1735 void radeon_atombios_fini(struct radeon_device *rdev);
1736
1737
1738 /*
1739 * RING helpers.
1740 */
1741 #if DRM_DEBUG_CODE == 0
1742 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1743 {
1744 ring->ring[ring->wptr++] = v;
1745 ring->wptr &= ring->ptr_mask;
1746 ring->count_dw--;
1747 ring->ring_free_dw--;
1748 }
1749 #else
1750 /* With debugging this is just too big to inline */
1751 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1752 #endif
1753
1754 /*
1755 * ASICs macro.
1756 */
1757 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1758 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1759 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1760 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1761 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1762 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1763 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1764 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1765 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1766 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1767 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1768 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
1769 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1770 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1771 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1772 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1773 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1774 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1775 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1776 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1777 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1778 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1779 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1780 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1781 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1782 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1783 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1784 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1785 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1786 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1787 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1788 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1789 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1790 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1791 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1792 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1793 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1794 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1795 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1796 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1797 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1798 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1799 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1800 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1801 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1802 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1803 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1804 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1805 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1806 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1807 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1808 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1809 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1810 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1811 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1812 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1813 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1814
1815 /* Common functions */
1816 /* AGP */
1817 extern int radeon_gpu_reset(struct radeon_device *rdev);
1818 extern void radeon_agp_disable(struct radeon_device *rdev);
1819 extern int radeon_modeset_init(struct radeon_device *rdev);
1820 extern void radeon_modeset_fini(struct radeon_device *rdev);
1821 extern bool radeon_card_posted(struct radeon_device *rdev);
1822 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1823 extern void radeon_update_display_priority(struct radeon_device *rdev);
1824 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1825 extern void radeon_scratch_init(struct radeon_device *rdev);
1826 extern void radeon_wb_fini(struct radeon_device *rdev);
1827 extern int radeon_wb_init(struct radeon_device *rdev);
1828 extern void radeon_wb_disable(struct radeon_device *rdev);
1829 extern void radeon_surface_init(struct radeon_device *rdev);
1830 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1831 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1832 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1833 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1834 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1835 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1836 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1837 extern int radeon_resume_kms(struct drm_device *dev);
1838 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1839 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1840
1841 /*
1842 * vm
1843 */
1844 int radeon_vm_manager_init(struct radeon_device *rdev);
1845 void radeon_vm_manager_fini(struct radeon_device *rdev);
1846 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1847 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1848 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1849 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1850 struct radeon_vm *vm, int ring);
1851 void radeon_vm_fence(struct radeon_device *rdev,
1852 struct radeon_vm *vm,
1853 struct radeon_fence *fence);
1854 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1855 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1856 struct radeon_vm *vm,
1857 struct radeon_bo *bo,
1858 struct ttm_mem_reg *mem);
1859 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1860 struct radeon_bo *bo);
1861 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1862 struct radeon_bo *bo);
1863 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1864 struct radeon_vm *vm,
1865 struct radeon_bo *bo);
1866 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1867 struct radeon_bo_va *bo_va,
1868 uint64_t offset,
1869 uint32_t flags);
1870 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1871 struct radeon_bo_va *bo_va);
1872
1873 /* audio */
1874 void r600_audio_update_hdmi(struct work_struct *work);
1875
1876 /*
1877 * R600 vram scratch functions
1878 */
1879 int r600_vram_scratch_init(struct radeon_device *rdev);
1880 void r600_vram_scratch_fini(struct radeon_device *rdev);
1881
1882 /*
1883 * r600 cs checking helper
1884 */
1885 unsigned r600_mip_minify(unsigned size, unsigned level);
1886 bool r600_fmt_is_valid_color(u32 format);
1887 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1888 int r600_fmt_get_blocksize(u32 format);
1889 int r600_fmt_get_nblocksx(u32 format, u32 w);
1890 int r600_fmt_get_nblocksy(u32 format, u32 h);
1891
1892 /*
1893 * r600 functions used by radeon_encoder.c
1894 */
1895 struct radeon_hdmi_acr {
1896 u32 clock;
1897
1898 int n_32khz;
1899 int cts_32khz;
1900
1901 int n_44_1khz;
1902 int cts_44_1khz;
1903
1904 int n_48khz;
1905 int cts_48khz;
1906
1907 };
1908
1909 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1910
1911 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1912 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1913 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1914 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1915 u32 tiling_pipe_num,
1916 u32 max_rb_num,
1917 u32 total_max_rb_num,
1918 u32 enabled_rb_mask);
1919
1920 /*
1921 * evergreen functions used by radeon_encoder.c
1922 */
1923
1924 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1925
1926 extern int ni_init_microcode(struct radeon_device *rdev);
1927 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1928
1929 /* radeon_acpi.c */
1930 #if defined(CONFIG_ACPI)
1931 extern int radeon_acpi_init(struct radeon_device *rdev);
1932 extern void radeon_acpi_fini(struct radeon_device *rdev);
1933 #else
1934 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1935 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1936 #endif
1937
1938 #include "radeon_object.h"
1939
1940 #endif
Linux kernel - Deliverables
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