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drm/radeon/kms: add support for per-ring fence interrupts
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
112
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
116
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
120
121 /*
122 * Errata workarounds.
123 */
124 enum radeon_pll_errata {
125 CHIP_ERRATA_R300_CG = 0x00000001,
126 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
127 CHIP_ERRATA_PLL_DELAY = 0x00000004
128 };
129
130
131 struct radeon_device;
132
133
134 /*
135 * BIOS.
136 */
137 #define ATRM_BIOS_PAGE 4096
138
139 #if defined(CONFIG_VGA_SWITCHEROO)
140 bool radeon_atrm_supported(struct pci_dev *pdev);
141 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
142 #else
143 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
144 {
145 return false;
146 }
147
148 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
149 return -EINVAL;
150 }
151 #endif
152 bool radeon_get_bios(struct radeon_device *rdev);
153
154
155 /*
156 * Dummy page
157 */
158 struct radeon_dummy_page {
159 struct page *page;
160 dma_addr_t addr;
161 };
162 int radeon_dummy_page_init(struct radeon_device *rdev);
163 void radeon_dummy_page_fini(struct radeon_device *rdev);
164
165
166 /*
167 * Clocks
168 */
169 struct radeon_clock {
170 struct radeon_pll p1pll;
171 struct radeon_pll p2pll;
172 struct radeon_pll dcpll;
173 struct radeon_pll spll;
174 struct radeon_pll mpll;
175 /* 10 Khz units */
176 uint32_t default_mclk;
177 uint32_t default_sclk;
178 uint32_t default_dispclk;
179 uint32_t dp_extclk;
180 uint32_t max_pixel_clock;
181 };
182
183 /*
184 * Power management
185 */
186 int radeon_pm_init(struct radeon_device *rdev);
187 void radeon_pm_fini(struct radeon_device *rdev);
188 void radeon_pm_compute_clocks(struct radeon_device *rdev);
189 void radeon_pm_suspend(struct radeon_device *rdev);
190 void radeon_pm_resume(struct radeon_device *rdev);
191 void radeon_combios_get_power_modes(struct radeon_device *rdev);
192 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
193 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
194 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
195 void rs690_pm_info(struct radeon_device *rdev);
196 extern int rv6xx_get_temp(struct radeon_device *rdev);
197 extern int rv770_get_temp(struct radeon_device *rdev);
198 extern int evergreen_get_temp(struct radeon_device *rdev);
199 extern int sumo_get_temp(struct radeon_device *rdev);
200
201 /*
202 * Fences.
203 */
204 struct radeon_fence_driver {
205 uint32_t scratch_reg;
206 uint64_t gpu_addr;
207 volatile uint32_t *cpu_addr;
208 atomic_t seq;
209 uint32_t last_seq;
210 unsigned long last_jiffies;
211 unsigned long last_timeout;
212 wait_queue_head_t queue;
213 struct list_head created;
214 struct list_head emitted;
215 struct list_head signaled;
216 bool initialized;
217 };
218
219 struct radeon_fence {
220 struct radeon_device *rdev;
221 struct kref kref;
222 struct list_head list;
223 /* protected by radeon_fence.lock */
224 uint32_t seq;
225 bool emitted;
226 bool signaled;
227 /* RB, DMA, etc. */
228 int ring;
229 };
230
231 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
232 int radeon_fence_driver_init(struct radeon_device *rdev);
233 void radeon_fence_driver_fini(struct radeon_device *rdev);
234 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
235 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
236 void radeon_fence_process(struct radeon_device *rdev, int ring);
237 bool radeon_fence_signaled(struct radeon_fence *fence);
238 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
239 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
240 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
241 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
242 void radeon_fence_unref(struct radeon_fence **fence);
243 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
244
245 /*
246 * Semaphores.
247 */
248 struct radeon_ring;
249
250 struct radeon_semaphore_driver {
251 rwlock_t lock;
252 struct list_head free;
253 };
254
255 struct radeon_semaphore {
256 struct radeon_bo *robj;
257 struct list_head list;
258 uint64_t gpu_addr;
259 };
260
261 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
262 int radeon_semaphore_create(struct radeon_device *rdev,
263 struct radeon_semaphore **semaphore);
264 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
265 struct radeon_semaphore *semaphore);
266 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
267 struct radeon_semaphore *semaphore);
268 void radeon_semaphore_free(struct radeon_device *rdev,
269 struct radeon_semaphore *semaphore);
270
271 /*
272 * Tiling registers
273 */
274 struct radeon_surface_reg {
275 struct radeon_bo *bo;
276 };
277
278 #define RADEON_GEM_MAX_SURFACES 8
279
280 /*
281 * TTM.
282 */
283 struct radeon_mman {
284 struct ttm_bo_global_ref bo_global_ref;
285 struct drm_global_reference mem_global_ref;
286 struct ttm_bo_device bdev;
287 bool mem_global_referenced;
288 bool initialized;
289 };
290
291 struct radeon_bo {
292 /* Protected by gem.mutex */
293 struct list_head list;
294 /* Protected by tbo.reserved */
295 u32 placements[3];
296 struct ttm_placement placement;
297 struct ttm_buffer_object tbo;
298 struct ttm_bo_kmap_obj kmap;
299 unsigned pin_count;
300 void *kptr;
301 u32 tiling_flags;
302 u32 pitch;
303 int surface_reg;
304 /* Constant after initialization */
305 struct radeon_device *rdev;
306 struct drm_gem_object gem_base;
307 };
308 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
309
310 struct radeon_bo_list {
311 struct ttm_validate_buffer tv;
312 struct radeon_bo *bo;
313 uint64_t gpu_offset;
314 unsigned rdomain;
315 unsigned wdomain;
316 u32 tiling_flags;
317 };
318
319 /*
320 * GEM objects.
321 */
322 struct radeon_gem {
323 struct mutex mutex;
324 struct list_head objects;
325 };
326
327 int radeon_gem_init(struct radeon_device *rdev);
328 void radeon_gem_fini(struct radeon_device *rdev);
329 int radeon_gem_object_create(struct radeon_device *rdev, int size,
330 int alignment, int initial_domain,
331 bool discardable, bool kernel,
332 struct drm_gem_object **obj);
333 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
334 uint64_t *gpu_addr);
335 void radeon_gem_object_unpin(struct drm_gem_object *obj);
336
337 int radeon_mode_dumb_create(struct drm_file *file_priv,
338 struct drm_device *dev,
339 struct drm_mode_create_dumb *args);
340 int radeon_mode_dumb_mmap(struct drm_file *filp,
341 struct drm_device *dev,
342 uint32_t handle, uint64_t *offset_p);
343 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
344 struct drm_device *dev,
345 uint32_t handle);
346
347 /*
348 * GART structures, functions & helpers
349 */
350 struct radeon_mc;
351
352 #define RADEON_GPU_PAGE_SIZE 4096
353 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
354 #define RADEON_GPU_PAGE_SHIFT 12
355
356 struct radeon_gart {
357 dma_addr_t table_addr;
358 struct radeon_bo *robj;
359 void *ptr;
360 unsigned num_gpu_pages;
361 unsigned num_cpu_pages;
362 unsigned table_size;
363 struct page **pages;
364 dma_addr_t *pages_addr;
365 bool ready;
366 };
367
368 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
369 void radeon_gart_table_ram_free(struct radeon_device *rdev);
370 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
371 void radeon_gart_table_vram_free(struct radeon_device *rdev);
372 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
373 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
374 int radeon_gart_init(struct radeon_device *rdev);
375 void radeon_gart_fini(struct radeon_device *rdev);
376 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
377 int pages);
378 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
379 int pages, struct page **pagelist,
380 dma_addr_t *dma_addr);
381 void radeon_gart_restore(struct radeon_device *rdev);
382
383
384 /*
385 * GPU MC structures, functions & helpers
386 */
387 struct radeon_mc {
388 resource_size_t aper_size;
389 resource_size_t aper_base;
390 resource_size_t agp_base;
391 /* for some chips with <= 32MB we need to lie
392 * about vram size near mc fb location */
393 u64 mc_vram_size;
394 u64 visible_vram_size;
395 u64 gtt_size;
396 u64 gtt_start;
397 u64 gtt_end;
398 u64 vram_start;
399 u64 vram_end;
400 unsigned vram_width;
401 u64 real_vram_size;
402 int vram_mtrr;
403 bool vram_is_ddr;
404 bool igp_sideport_enabled;
405 u64 gtt_base_align;
406 };
407
408 bool radeon_combios_sideport_present(struct radeon_device *rdev);
409 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
410
411 /*
412 * GPU scratch registers structures, functions & helpers
413 */
414 struct radeon_scratch {
415 unsigned num_reg;
416 uint32_t reg_base;
417 bool free[32];
418 uint32_t reg[32];
419 };
420
421 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
422 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
423
424
425 /*
426 * IRQS.
427 */
428
429 struct radeon_unpin_work {
430 struct work_struct work;
431 struct radeon_device *rdev;
432 int crtc_id;
433 struct radeon_fence *fence;
434 struct drm_pending_vblank_event *event;
435 struct radeon_bo *old_rbo;
436 u64 new_crtc_base;
437 };
438
439 struct r500_irq_stat_regs {
440 u32 disp_int;
441 };
442
443 struct r600_irq_stat_regs {
444 u32 disp_int;
445 u32 disp_int_cont;
446 u32 disp_int_cont2;
447 u32 d1grph_int;
448 u32 d2grph_int;
449 };
450
451 struct evergreen_irq_stat_regs {
452 u32 disp_int;
453 u32 disp_int_cont;
454 u32 disp_int_cont2;
455 u32 disp_int_cont3;
456 u32 disp_int_cont4;
457 u32 disp_int_cont5;
458 u32 d1grph_int;
459 u32 d2grph_int;
460 u32 d3grph_int;
461 u32 d4grph_int;
462 u32 d5grph_int;
463 u32 d6grph_int;
464 };
465
466 union radeon_irq_stat_regs {
467 struct r500_irq_stat_regs r500;
468 struct r600_irq_stat_regs r600;
469 struct evergreen_irq_stat_regs evergreen;
470 };
471
472 #define RADEON_MAX_HPD_PINS 6
473 #define RADEON_MAX_CRTCS 6
474 #define RADEON_MAX_HDMI_BLOCKS 2
475
476 struct radeon_irq {
477 bool installed;
478 bool sw_int[RADEON_NUM_RINGS];
479 bool crtc_vblank_int[RADEON_MAX_CRTCS];
480 bool pflip[RADEON_MAX_CRTCS];
481 wait_queue_head_t vblank_queue;
482 bool hpd[RADEON_MAX_HPD_PINS];
483 bool gui_idle;
484 bool gui_idle_acked;
485 wait_queue_head_t idle_queue;
486 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
487 spinlock_t sw_lock;
488 int sw_refcount[RADEON_NUM_RINGS];
489 union radeon_irq_stat_regs stat_regs;
490 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
491 int pflip_refcount[RADEON_MAX_CRTCS];
492 };
493
494 int radeon_irq_kms_init(struct radeon_device *rdev);
495 void radeon_irq_kms_fini(struct radeon_device *rdev);
496 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
497 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
498 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
499 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
500
501 /*
502 * CP & rings.
503 */
504
505 struct radeon_ib {
506 struct list_head list;
507 unsigned idx;
508 uint64_t gpu_addr;
509 struct radeon_fence *fence;
510 uint32_t *ptr;
511 uint32_t length_dw;
512 bool free;
513 };
514
515 /*
516 * locking -
517 * mutex protects scheduled_ibs, ready, alloc_bm
518 */
519 struct radeon_ib_pool {
520 struct mutex mutex;
521 struct radeon_bo *robj;
522 struct list_head bogus_ib;
523 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
524 bool ready;
525 unsigned head_id;
526 };
527
528 struct radeon_ring {
529 struct radeon_bo *ring_obj;
530 volatile uint32_t *ring;
531 unsigned rptr;
532 unsigned rptr_offs;
533 unsigned rptr_reg;
534 unsigned wptr;
535 unsigned wptr_old;
536 unsigned wptr_reg;
537 unsigned ring_size;
538 unsigned ring_free_dw;
539 int count_dw;
540 uint64_t gpu_addr;
541 uint32_t align_mask;
542 uint32_t ptr_mask;
543 struct mutex mutex;
544 bool ready;
545 u32 ptr_reg_shift;
546 u32 ptr_reg_mask;
547 u32 nop;
548 };
549
550 /*
551 * R6xx+ IH ring
552 */
553 struct r600_ih {
554 struct radeon_bo *ring_obj;
555 volatile uint32_t *ring;
556 unsigned rptr;
557 unsigned rptr_offs;
558 unsigned wptr;
559 unsigned wptr_old;
560 unsigned ring_size;
561 uint64_t gpu_addr;
562 uint32_t ptr_mask;
563 spinlock_t lock;
564 bool enabled;
565 };
566
567 struct r600_blit_cp_primitives {
568 void (*set_render_target)(struct radeon_device *rdev, int format,
569 int w, int h, u64 gpu_addr);
570 void (*cp_set_surface_sync)(struct radeon_device *rdev,
571 u32 sync_type, u32 size,
572 u64 mc_addr);
573 void (*set_shaders)(struct radeon_device *rdev);
574 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
575 void (*set_tex_resource)(struct radeon_device *rdev,
576 int format, int w, int h, int pitch,
577 u64 gpu_addr, u32 size);
578 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
579 int x2, int y2);
580 void (*draw_auto)(struct radeon_device *rdev);
581 void (*set_default_state)(struct radeon_device *rdev);
582 };
583
584 struct r600_blit {
585 struct mutex mutex;
586 struct radeon_bo *shader_obj;
587 struct r600_blit_cp_primitives primitives;
588 int max_dim;
589 int ring_size_common;
590 int ring_size_per_loop;
591 u64 shader_gpu_addr;
592 u32 vs_offset, ps_offset;
593 u32 state_offset;
594 u32 state_len;
595 u32 vb_used, vb_total;
596 struct radeon_ib *vb_ib;
597 };
598
599 void r600_blit_suspend(struct radeon_device *rdev);
600
601 int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
602 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
603 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
604 int radeon_ib_pool_init(struct radeon_device *rdev);
605 void radeon_ib_pool_fini(struct radeon_device *rdev);
606 int radeon_ib_test(struct radeon_device *rdev);
607 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
608 /* Ring access between begin & end cannot sleep */
609 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
610 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
611 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
612 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
613 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
614 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
615 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
616 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
617 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
618 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
619 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
620 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
621
622
623 /*
624 * CS.
625 */
626 struct radeon_cs_reloc {
627 struct drm_gem_object *gobj;
628 struct radeon_bo *robj;
629 struct radeon_bo_list lobj;
630 uint32_t handle;
631 uint32_t flags;
632 };
633
634 struct radeon_cs_chunk {
635 uint32_t chunk_id;
636 uint32_t length_dw;
637 int kpage_idx[2];
638 uint32_t *kpage[2];
639 uint32_t *kdata;
640 void __user *user_ptr;
641 int last_copied_page;
642 int last_page_index;
643 };
644
645 struct radeon_cs_parser {
646 struct device *dev;
647 struct radeon_device *rdev;
648 struct drm_file *filp;
649 /* chunks */
650 unsigned nchunks;
651 struct radeon_cs_chunk *chunks;
652 uint64_t *chunks_array;
653 /* IB */
654 unsigned idx;
655 /* relocations */
656 unsigned nrelocs;
657 struct radeon_cs_reloc *relocs;
658 struct radeon_cs_reloc **relocs_ptr;
659 struct list_head validated;
660 /* indices of various chunks */
661 int chunk_ib_idx;
662 int chunk_relocs_idx;
663 struct radeon_ib *ib;
664 void *track;
665 unsigned family;
666 int parser_error;
667 bool keep_tiling_flags;
668 };
669
670 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
671 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
672 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
673
674 struct radeon_cs_packet {
675 unsigned idx;
676 unsigned type;
677 unsigned reg;
678 unsigned opcode;
679 int count;
680 unsigned one_reg_wr;
681 };
682
683 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
684 struct radeon_cs_packet *pkt,
685 unsigned idx, unsigned reg);
686 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
687 struct radeon_cs_packet *pkt);
688
689
690 /*
691 * AGP
692 */
693 int radeon_agp_init(struct radeon_device *rdev);
694 void radeon_agp_resume(struct radeon_device *rdev);
695 void radeon_agp_suspend(struct radeon_device *rdev);
696 void radeon_agp_fini(struct radeon_device *rdev);
697
698
699 /*
700 * Writeback
701 */
702 struct radeon_wb {
703 struct radeon_bo *wb_obj;
704 volatile uint32_t *wb;
705 uint64_t gpu_addr;
706 bool enabled;
707 bool use_event;
708 };
709
710 #define RADEON_WB_SCRATCH_OFFSET 0
711 #define RADEON_WB_CP_RPTR_OFFSET 1024
712 #define RADEON_WB_CP1_RPTR_OFFSET 1280
713 #define RADEON_WB_CP2_RPTR_OFFSET 1536
714 #define R600_WB_IH_WPTR_OFFSET 2048
715 #define R600_WB_EVENT_OFFSET 3072
716
717 /**
718 * struct radeon_pm - power management datas
719 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
720 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
721 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
722 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
723 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
724 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
725 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
726 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
727 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
728 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
729 * @needed_bandwidth: current bandwidth needs
730 *
731 * It keeps track of various data needed to take powermanagement decision.
732 * Bandwidth need is used to determine minimun clock of the GPU and memory.
733 * Equation between gpu/memory clock and available bandwidth is hw dependent
734 * (type of memory, bus size, efficiency, ...)
735 */
736
737 enum radeon_pm_method {
738 PM_METHOD_PROFILE,
739 PM_METHOD_DYNPM,
740 };
741
742 enum radeon_dynpm_state {
743 DYNPM_STATE_DISABLED,
744 DYNPM_STATE_MINIMUM,
745 DYNPM_STATE_PAUSED,
746 DYNPM_STATE_ACTIVE,
747 DYNPM_STATE_SUSPENDED,
748 };
749 enum radeon_dynpm_action {
750 DYNPM_ACTION_NONE,
751 DYNPM_ACTION_MINIMUM,
752 DYNPM_ACTION_DOWNCLOCK,
753 DYNPM_ACTION_UPCLOCK,
754 DYNPM_ACTION_DEFAULT
755 };
756
757 enum radeon_voltage_type {
758 VOLTAGE_NONE = 0,
759 VOLTAGE_GPIO,
760 VOLTAGE_VDDC,
761 VOLTAGE_SW
762 };
763
764 enum radeon_pm_state_type {
765 POWER_STATE_TYPE_DEFAULT,
766 POWER_STATE_TYPE_POWERSAVE,
767 POWER_STATE_TYPE_BATTERY,
768 POWER_STATE_TYPE_BALANCED,
769 POWER_STATE_TYPE_PERFORMANCE,
770 };
771
772 enum radeon_pm_profile_type {
773 PM_PROFILE_DEFAULT,
774 PM_PROFILE_AUTO,
775 PM_PROFILE_LOW,
776 PM_PROFILE_MID,
777 PM_PROFILE_HIGH,
778 };
779
780 #define PM_PROFILE_DEFAULT_IDX 0
781 #define PM_PROFILE_LOW_SH_IDX 1
782 #define PM_PROFILE_MID_SH_IDX 2
783 #define PM_PROFILE_HIGH_SH_IDX 3
784 #define PM_PROFILE_LOW_MH_IDX 4
785 #define PM_PROFILE_MID_MH_IDX 5
786 #define PM_PROFILE_HIGH_MH_IDX 6
787 #define PM_PROFILE_MAX 7
788
789 struct radeon_pm_profile {
790 int dpms_off_ps_idx;
791 int dpms_on_ps_idx;
792 int dpms_off_cm_idx;
793 int dpms_on_cm_idx;
794 };
795
796 enum radeon_int_thermal_type {
797 THERMAL_TYPE_NONE,
798 THERMAL_TYPE_RV6XX,
799 THERMAL_TYPE_RV770,
800 THERMAL_TYPE_EVERGREEN,
801 THERMAL_TYPE_SUMO,
802 THERMAL_TYPE_NI,
803 };
804
805 struct radeon_voltage {
806 enum radeon_voltage_type type;
807 /* gpio voltage */
808 struct radeon_gpio_rec gpio;
809 u32 delay; /* delay in usec from voltage drop to sclk change */
810 bool active_high; /* voltage drop is active when bit is high */
811 /* VDDC voltage */
812 u8 vddc_id; /* index into vddc voltage table */
813 u8 vddci_id; /* index into vddci voltage table */
814 bool vddci_enabled;
815 /* r6xx+ sw */
816 u16 voltage;
817 /* evergreen+ vddci */
818 u16 vddci;
819 };
820
821 /* clock mode flags */
822 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
823
824 struct radeon_pm_clock_info {
825 /* memory clock */
826 u32 mclk;
827 /* engine clock */
828 u32 sclk;
829 /* voltage info */
830 struct radeon_voltage voltage;
831 /* standardized clock flags */
832 u32 flags;
833 };
834
835 /* state flags */
836 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
837
838 struct radeon_power_state {
839 enum radeon_pm_state_type type;
840 struct radeon_pm_clock_info *clock_info;
841 /* number of valid clock modes in this power state */
842 int num_clock_modes;
843 struct radeon_pm_clock_info *default_clock_mode;
844 /* standardized state flags */
845 u32 flags;
846 u32 misc; /* vbios specific flags */
847 u32 misc2; /* vbios specific flags */
848 int pcie_lanes; /* pcie lanes */
849 };
850
851 /*
852 * Some modes are overclocked by very low value, accept them
853 */
854 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
855
856 struct radeon_pm {
857 struct mutex mutex;
858 u32 active_crtcs;
859 int active_crtc_count;
860 int req_vblank;
861 bool vblank_sync;
862 bool gui_idle;
863 fixed20_12 max_bandwidth;
864 fixed20_12 igp_sideport_mclk;
865 fixed20_12 igp_system_mclk;
866 fixed20_12 igp_ht_link_clk;
867 fixed20_12 igp_ht_link_width;
868 fixed20_12 k8_bandwidth;
869 fixed20_12 sideport_bandwidth;
870 fixed20_12 ht_bandwidth;
871 fixed20_12 core_bandwidth;
872 fixed20_12 sclk;
873 fixed20_12 mclk;
874 fixed20_12 needed_bandwidth;
875 struct radeon_power_state *power_state;
876 /* number of valid power states */
877 int num_power_states;
878 int current_power_state_index;
879 int current_clock_mode_index;
880 int requested_power_state_index;
881 int requested_clock_mode_index;
882 int default_power_state_index;
883 u32 current_sclk;
884 u32 current_mclk;
885 u16 current_vddc;
886 u16 current_vddci;
887 u32 default_sclk;
888 u32 default_mclk;
889 u16 default_vddc;
890 u16 default_vddci;
891 struct radeon_i2c_chan *i2c_bus;
892 /* selected pm method */
893 enum radeon_pm_method pm_method;
894 /* dynpm power management */
895 struct delayed_work dynpm_idle_work;
896 enum radeon_dynpm_state dynpm_state;
897 enum radeon_dynpm_action dynpm_planned_action;
898 unsigned long dynpm_action_timeout;
899 bool dynpm_can_upclock;
900 bool dynpm_can_downclock;
901 /* profile-based power management */
902 enum radeon_pm_profile_type profile;
903 int profile_index;
904 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
905 /* internal thermal controller on rv6xx+ */
906 enum radeon_int_thermal_type int_thermal_type;
907 struct device *int_hwmon_dev;
908 };
909
910 int radeon_pm_get_type_index(struct radeon_device *rdev,
911 enum radeon_pm_state_type ps_type,
912 int instance);
913
914 /*
915 * Benchmarking
916 */
917 void radeon_benchmark(struct radeon_device *rdev, int test_number);
918
919
920 /*
921 * Testing
922 */
923 void radeon_test_moves(struct radeon_device *rdev);
924 void radeon_test_ring_sync(struct radeon_device *rdev,
925 struct radeon_ring *cpA,
926 struct radeon_ring *cpB);
927 void radeon_test_syncing(struct radeon_device *rdev);
928
929
930 /*
931 * Debugfs
932 */
933 struct radeon_debugfs {
934 struct drm_info_list *files;
935 unsigned num_files;
936 };
937
938 int radeon_debugfs_add_files(struct radeon_device *rdev,
939 struct drm_info_list *files,
940 unsigned nfiles);
941 int radeon_debugfs_fence_init(struct radeon_device *rdev);
942
943
944 /*
945 * ASIC specific functions.
946 */
947 struct radeon_asic {
948 int (*init)(struct radeon_device *rdev);
949 void (*fini)(struct radeon_device *rdev);
950 int (*resume)(struct radeon_device *rdev);
951 int (*suspend)(struct radeon_device *rdev);
952 void (*vga_set_state)(struct radeon_device *rdev, bool state);
953 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
954 int (*asic_reset)(struct radeon_device *rdev);
955 void (*gart_tlb_flush)(struct radeon_device *rdev);
956 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
957 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
958 void (*cp_fini)(struct radeon_device *rdev);
959 void (*cp_disable)(struct radeon_device *rdev);
960 void (*ring_start)(struct radeon_device *rdev);
961
962 struct {
963 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
964 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
965 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
966 struct radeon_semaphore *semaphore, bool emit_wait);
967 } ring[RADEON_NUM_RINGS];
968
969 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
970 int (*irq_set)(struct radeon_device *rdev);
971 int (*irq_process)(struct radeon_device *rdev);
972 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
973 int (*cs_parse)(struct radeon_cs_parser *p);
974 int (*copy_blit)(struct radeon_device *rdev,
975 uint64_t src_offset,
976 uint64_t dst_offset,
977 unsigned num_gpu_pages,
978 struct radeon_fence *fence);
979 int (*copy_dma)(struct radeon_device *rdev,
980 uint64_t src_offset,
981 uint64_t dst_offset,
982 unsigned num_gpu_pages,
983 struct radeon_fence *fence);
984 int (*copy)(struct radeon_device *rdev,
985 uint64_t src_offset,
986 uint64_t dst_offset,
987 unsigned num_gpu_pages,
988 struct radeon_fence *fence);
989 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
990 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
991 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
992 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
993 int (*get_pcie_lanes)(struct radeon_device *rdev);
994 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
995 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
996 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
997 uint32_t tiling_flags, uint32_t pitch,
998 uint32_t offset, uint32_t obj_size);
999 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
1000 void (*bandwidth_update)(struct radeon_device *rdev);
1001 void (*hpd_init)(struct radeon_device *rdev);
1002 void (*hpd_fini)(struct radeon_device *rdev);
1003 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1004 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1005 /* ioctl hw specific callback. Some hw might want to perform special
1006 * operation on specific ioctl. For instance on wait idle some hw
1007 * might want to perform and HDP flush through MMIO as it seems that
1008 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1009 * through ring.
1010 */
1011 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1012 bool (*gui_idle)(struct radeon_device *rdev);
1013 /* power management */
1014 void (*pm_misc)(struct radeon_device *rdev);
1015 void (*pm_prepare)(struct radeon_device *rdev);
1016 void (*pm_finish)(struct radeon_device *rdev);
1017 void (*pm_init_profile)(struct radeon_device *rdev);
1018 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
1019 /* pageflipping */
1020 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1021 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1022 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1023 };
1024
1025 /*
1026 * Asic structures
1027 */
1028 struct r100_gpu_lockup {
1029 unsigned long last_jiffies;
1030 u32 last_cp_rptr;
1031 };
1032
1033 struct r100_asic {
1034 const unsigned *reg_safe_bm;
1035 unsigned reg_safe_bm_size;
1036 u32 hdp_cntl;
1037 struct r100_gpu_lockup lockup;
1038 };
1039
1040 struct r300_asic {
1041 const unsigned *reg_safe_bm;
1042 unsigned reg_safe_bm_size;
1043 u32 resync_scratch;
1044 u32 hdp_cntl;
1045 struct r100_gpu_lockup lockup;
1046 };
1047
1048 struct r600_asic {
1049 unsigned max_pipes;
1050 unsigned max_tile_pipes;
1051 unsigned max_simds;
1052 unsigned max_backends;
1053 unsigned max_gprs;
1054 unsigned max_threads;
1055 unsigned max_stack_entries;
1056 unsigned max_hw_contexts;
1057 unsigned max_gs_threads;
1058 unsigned sx_max_export_size;
1059 unsigned sx_max_export_pos_size;
1060 unsigned sx_max_export_smx_size;
1061 unsigned sq_num_cf_insts;
1062 unsigned tiling_nbanks;
1063 unsigned tiling_npipes;
1064 unsigned tiling_group_size;
1065 unsigned tile_config;
1066 unsigned backend_map;
1067 struct r100_gpu_lockup lockup;
1068 };
1069
1070 struct rv770_asic {
1071 unsigned max_pipes;
1072 unsigned max_tile_pipes;
1073 unsigned max_simds;
1074 unsigned max_backends;
1075 unsigned max_gprs;
1076 unsigned max_threads;
1077 unsigned max_stack_entries;
1078 unsigned max_hw_contexts;
1079 unsigned max_gs_threads;
1080 unsigned sx_max_export_size;
1081 unsigned sx_max_export_pos_size;
1082 unsigned sx_max_export_smx_size;
1083 unsigned sq_num_cf_insts;
1084 unsigned sx_num_of_sets;
1085 unsigned sc_prim_fifo_size;
1086 unsigned sc_hiz_tile_fifo_size;
1087 unsigned sc_earlyz_tile_fifo_fize;
1088 unsigned tiling_nbanks;
1089 unsigned tiling_npipes;
1090 unsigned tiling_group_size;
1091 unsigned tile_config;
1092 unsigned backend_map;
1093 struct r100_gpu_lockup lockup;
1094 };
1095
1096 struct evergreen_asic {
1097 unsigned num_ses;
1098 unsigned max_pipes;
1099 unsigned max_tile_pipes;
1100 unsigned max_simds;
1101 unsigned max_backends;
1102 unsigned max_gprs;
1103 unsigned max_threads;
1104 unsigned max_stack_entries;
1105 unsigned max_hw_contexts;
1106 unsigned max_gs_threads;
1107 unsigned sx_max_export_size;
1108 unsigned sx_max_export_pos_size;
1109 unsigned sx_max_export_smx_size;
1110 unsigned sq_num_cf_insts;
1111 unsigned sx_num_of_sets;
1112 unsigned sc_prim_fifo_size;
1113 unsigned sc_hiz_tile_fifo_size;
1114 unsigned sc_earlyz_tile_fifo_size;
1115 unsigned tiling_nbanks;
1116 unsigned tiling_npipes;
1117 unsigned tiling_group_size;
1118 unsigned tile_config;
1119 unsigned backend_map;
1120 struct r100_gpu_lockup lockup;
1121 };
1122
1123 struct cayman_asic {
1124 unsigned max_shader_engines;
1125 unsigned max_pipes_per_simd;
1126 unsigned max_tile_pipes;
1127 unsigned max_simds_per_se;
1128 unsigned max_backends_per_se;
1129 unsigned max_texture_channel_caches;
1130 unsigned max_gprs;
1131 unsigned max_threads;
1132 unsigned max_gs_threads;
1133 unsigned max_stack_entries;
1134 unsigned sx_num_of_sets;
1135 unsigned sx_max_export_size;
1136 unsigned sx_max_export_pos_size;
1137 unsigned sx_max_export_smx_size;
1138 unsigned max_hw_contexts;
1139 unsigned sq_num_cf_insts;
1140 unsigned sc_prim_fifo_size;
1141 unsigned sc_hiz_tile_fifo_size;
1142 unsigned sc_earlyz_tile_fifo_size;
1143
1144 unsigned num_shader_engines;
1145 unsigned num_shader_pipes_per_simd;
1146 unsigned num_tile_pipes;
1147 unsigned num_simds_per_se;
1148 unsigned num_backends_per_se;
1149 unsigned backend_disable_mask_per_asic;
1150 unsigned backend_map;
1151 unsigned num_texture_channel_caches;
1152 unsigned mem_max_burst_length_bytes;
1153 unsigned mem_row_size_in_kb;
1154 unsigned shader_engine_tile_size;
1155 unsigned num_gpus;
1156 unsigned multi_gpu_tile_size;
1157
1158 unsigned tile_config;
1159 struct r100_gpu_lockup lockup;
1160 };
1161
1162 union radeon_asic_config {
1163 struct r300_asic r300;
1164 struct r100_asic r100;
1165 struct r600_asic r600;
1166 struct rv770_asic rv770;
1167 struct evergreen_asic evergreen;
1168 struct cayman_asic cayman;
1169 };
1170
1171 /*
1172 * asic initizalization from radeon_asic.c
1173 */
1174 void radeon_agp_disable(struct radeon_device *rdev);
1175 int radeon_asic_init(struct radeon_device *rdev);
1176
1177
1178 /*
1179 * IOCTL.
1180 */
1181 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1182 struct drm_file *filp);
1183 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1184 struct drm_file *filp);
1185 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1186 struct drm_file *file_priv);
1187 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file_priv);
1189 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1190 struct drm_file *file_priv);
1191 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1192 struct drm_file *file_priv);
1193 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1194 struct drm_file *filp);
1195 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1196 struct drm_file *filp);
1197 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1198 struct drm_file *filp);
1199 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1200 struct drm_file *filp);
1201 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1202 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1203 struct drm_file *filp);
1204 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1205 struct drm_file *filp);
1206
1207 /* VRAM scratch page for HDP bug, default vram page */
1208 struct r600_vram_scratch {
1209 struct radeon_bo *robj;
1210 volatile uint32_t *ptr;
1211 u64 gpu_addr;
1212 };
1213
1214
1215 /*
1216 * Mutex which allows recursive locking from the same process.
1217 */
1218 struct radeon_mutex {
1219 struct mutex mutex;
1220 struct task_struct *owner;
1221 int level;
1222 };
1223
1224 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1225 {
1226 mutex_init(&mutex->mutex);
1227 mutex->owner = NULL;
1228 mutex->level = 0;
1229 }
1230
1231 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1232 {
1233 if (mutex_trylock(&mutex->mutex)) {
1234 /* The mutex was unlocked before, so it's ours now */
1235 mutex->owner = current;
1236 } else if (mutex->owner != current) {
1237 /* Another process locked the mutex, take it */
1238 mutex_lock(&mutex->mutex);
1239 mutex->owner = current;
1240 }
1241 /* Otherwise the mutex was already locked by this process */
1242
1243 mutex->level++;
1244 }
1245
1246 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1247 {
1248 if (--mutex->level > 0)
1249 return;
1250
1251 mutex->owner = NULL;
1252 mutex_unlock(&mutex->mutex);
1253 }
1254
1255
1256 /*
1257 * Core structure, functions and helpers.
1258 */
1259 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1260 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1261
1262 struct radeon_device {
1263 struct device *dev;
1264 struct drm_device *ddev;
1265 struct pci_dev *pdev;
1266 /* ASIC */
1267 union radeon_asic_config config;
1268 enum radeon_family family;
1269 unsigned long flags;
1270 int usec_timeout;
1271 enum radeon_pll_errata pll_errata;
1272 int num_gb_pipes;
1273 int num_z_pipes;
1274 int disp_priority;
1275 /* BIOS */
1276 uint8_t *bios;
1277 bool is_atom_bios;
1278 uint16_t bios_header_start;
1279 struct radeon_bo *stollen_vga_memory;
1280 /* Register mmio */
1281 resource_size_t rmmio_base;
1282 resource_size_t rmmio_size;
1283 void __iomem *rmmio;
1284 radeon_rreg_t mc_rreg;
1285 radeon_wreg_t mc_wreg;
1286 radeon_rreg_t pll_rreg;
1287 radeon_wreg_t pll_wreg;
1288 uint32_t pcie_reg_mask;
1289 radeon_rreg_t pciep_rreg;
1290 radeon_wreg_t pciep_wreg;
1291 /* io port */
1292 void __iomem *rio_mem;
1293 resource_size_t rio_mem_size;
1294 struct radeon_clock clock;
1295 struct radeon_mc mc;
1296 struct radeon_gart gart;
1297 struct radeon_mode_info mode_info;
1298 struct radeon_scratch scratch;
1299 struct radeon_mman mman;
1300 rwlock_t fence_lock;
1301 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1302 struct radeon_semaphore_driver semaphore_drv;
1303 struct radeon_ring ring[RADEON_NUM_RINGS];
1304 struct radeon_ib_pool ib_pool;
1305 struct radeon_irq irq;
1306 struct radeon_asic *asic;
1307 struct radeon_gem gem;
1308 struct radeon_pm pm;
1309 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1310 struct radeon_mutex cs_mutex;
1311 struct radeon_wb wb;
1312 struct radeon_dummy_page dummy_page;
1313 bool gpu_lockup;
1314 bool shutdown;
1315 bool suspend;
1316 bool need_dma32;
1317 bool accel_working;
1318 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1319 const struct firmware *me_fw; /* all family ME firmware */
1320 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1321 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1322 const struct firmware *mc_fw; /* NI MC firmware */
1323 struct r600_blit r600_blit;
1324 struct r600_vram_scratch vram_scratch;
1325 int msi_enabled; /* msi enabled */
1326 struct r600_ih ih; /* r6/700 interrupt ring */
1327 struct work_struct hotplug_work;
1328 int num_crtc; /* number of crtcs */
1329 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1330 struct mutex vram_mutex;
1331
1332 /* audio stuff */
1333 bool audio_enabled;
1334 struct timer_list audio_timer;
1335 int audio_channels;
1336 int audio_rate;
1337 int audio_bits_per_sample;
1338 uint8_t audio_status_bits;
1339 uint8_t audio_category_code;
1340
1341 struct notifier_block acpi_nb;
1342 /* only one userspace can use Hyperz features or CMASK at a time */
1343 struct drm_file *hyperz_filp;
1344 struct drm_file *cmask_filp;
1345 /* i2c buses */
1346 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1347 /* debugfs */
1348 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1349 unsigned debugfs_count;
1350 };
1351
1352 int radeon_device_init(struct radeon_device *rdev,
1353 struct drm_device *ddev,
1354 struct pci_dev *pdev,
1355 uint32_t flags);
1356 void radeon_device_fini(struct radeon_device *rdev);
1357 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1358
1359 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1360 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1361 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1362 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1363
1364 /*
1365 * Cast helper
1366 */
1367 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1368
1369 /*
1370 * Registers read & write functions.
1371 */
1372 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1373 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1374 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1375 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1376 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1377 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1378 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1379 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1380 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1381 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1382 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1383 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1384 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1385 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1386 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1387 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1388 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1389 #define WREG32_P(reg, val, mask) \
1390 do { \
1391 uint32_t tmp_ = RREG32(reg); \
1392 tmp_ &= (mask); \
1393 tmp_ |= ((val) & ~(mask)); \
1394 WREG32(reg, tmp_); \
1395 } while (0)
1396 #define WREG32_PLL_P(reg, val, mask) \
1397 do { \
1398 uint32_t tmp_ = RREG32_PLL(reg); \
1399 tmp_ &= (mask); \
1400 tmp_ |= ((val) & ~(mask)); \
1401 WREG32_PLL(reg, tmp_); \
1402 } while (0)
1403 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1404 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1405 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1406
1407 /*
1408 * Indirect registers accessor
1409 */
1410 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1411 {
1412 uint32_t r;
1413
1414 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1415 r = RREG32(RADEON_PCIE_DATA);
1416 return r;
1417 }
1418
1419 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1420 {
1421 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1422 WREG32(RADEON_PCIE_DATA, (v));
1423 }
1424
1425 void r100_pll_errata_after_index(struct radeon_device *rdev);
1426
1427
1428 /*
1429 * ASICs helpers.
1430 */
1431 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1432 (rdev->pdev->device == 0x5969))
1433 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1434 (rdev->family == CHIP_RV200) || \
1435 (rdev->family == CHIP_RS100) || \
1436 (rdev->family == CHIP_RS200) || \
1437 (rdev->family == CHIP_RV250) || \
1438 (rdev->family == CHIP_RV280) || \
1439 (rdev->family == CHIP_RS300))
1440 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1441 (rdev->family == CHIP_RV350) || \
1442 (rdev->family == CHIP_R350) || \
1443 (rdev->family == CHIP_RV380) || \
1444 (rdev->family == CHIP_R420) || \
1445 (rdev->family == CHIP_R423) || \
1446 (rdev->family == CHIP_RV410) || \
1447 (rdev->family == CHIP_RS400) || \
1448 (rdev->family == CHIP_RS480))
1449 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1450 (rdev->ddev->pdev->device == 0x9443) || \
1451 (rdev->ddev->pdev->device == 0x944B) || \
1452 (rdev->ddev->pdev->device == 0x9506) || \
1453 (rdev->ddev->pdev->device == 0x9509) || \
1454 (rdev->ddev->pdev->device == 0x950F) || \
1455 (rdev->ddev->pdev->device == 0x689C) || \
1456 (rdev->ddev->pdev->device == 0x689D))
1457 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1458 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1459 (rdev->family == CHIP_RS690) || \
1460 (rdev->family == CHIP_RS740) || \
1461 (rdev->family >= CHIP_R600))
1462 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1463 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1464 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1465 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1466 (rdev->flags & RADEON_IS_IGP))
1467 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1468
1469 /*
1470 * BIOS helpers.
1471 */
1472 #define RBIOS8(i) (rdev->bios[i])
1473 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1474 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1475
1476 int radeon_combios_init(struct radeon_device *rdev);
1477 void radeon_combios_fini(struct radeon_device *rdev);
1478 int radeon_atombios_init(struct radeon_device *rdev);
1479 void radeon_atombios_fini(struct radeon_device *rdev);
1480
1481
1482 /*
1483 * RING helpers.
1484 */
1485 #if DRM_DEBUG_CODE == 0
1486 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1487 {
1488 ring->ring[ring->wptr++] = v;
1489 ring->wptr &= ring->ptr_mask;
1490 ring->count_dw--;
1491 ring->ring_free_dw--;
1492 }
1493 #else
1494 /* With debugging this is just too big to inline */
1495 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1496 #endif
1497
1498 /*
1499 * ASICs macro.
1500 */
1501 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1502 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1503 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1504 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1505 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1506 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1507 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1508 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1509 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1510 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1511 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1512 #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1513 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1514 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1515 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1516 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1517 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1518 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1519 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1520 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1521 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1522 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1523 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1524 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1525 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1526 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1527 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1528 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1529 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1530 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1531 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1532 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1533 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1534 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1535 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1536 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1537 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1538 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1539 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1540 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1541 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1542 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1543 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1544 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1545
1546 /* Common functions */
1547 /* AGP */
1548 extern int radeon_gpu_reset(struct radeon_device *rdev);
1549 extern void radeon_agp_disable(struct radeon_device *rdev);
1550 extern int radeon_modeset_init(struct radeon_device *rdev);
1551 extern void radeon_modeset_fini(struct radeon_device *rdev);
1552 extern bool radeon_card_posted(struct radeon_device *rdev);
1553 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1554 extern void radeon_update_display_priority(struct radeon_device *rdev);
1555 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1556 extern void radeon_scratch_init(struct radeon_device *rdev);
1557 extern void radeon_wb_fini(struct radeon_device *rdev);
1558 extern int radeon_wb_init(struct radeon_device *rdev);
1559 extern void radeon_wb_disable(struct radeon_device *rdev);
1560 extern void radeon_surface_init(struct radeon_device *rdev);
1561 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1562 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1563 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1564 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1565 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1566 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1567 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1568 extern int radeon_resume_kms(struct drm_device *dev);
1569 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1570 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1571
1572 /*
1573 * R600 vram scratch functions
1574 */
1575 int r600_vram_scratch_init(struct radeon_device *rdev);
1576 void r600_vram_scratch_fini(struct radeon_device *rdev);
1577
1578 /*
1579 * r600 functions used by radeon_encoder.c
1580 */
1581 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1582 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1583 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1584
1585 extern int ni_init_microcode(struct radeon_device *rdev);
1586 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1587
1588 /* radeon_acpi.c */
1589 #if defined(CONFIG_ACPI)
1590 extern int radeon_acpi_init(struct radeon_device *rdev);
1591 #else
1592 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1593 #endif
1594
1595 #include "radeon_object.h"
1596
1597 #endif
Linux kernel - Deliverables
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