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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98
99 /*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
110
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 3
113
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
116
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
120
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
124
125 /* hardcode those limit for now */
126 #define RADEON_VA_RESERVED_SIZE (8 << 20)
127 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
128
129 /*
130 * Errata workarounds.
131 */
132 enum radeon_pll_errata {
133 CHIP_ERRATA_R300_CG = 0x00000001,
134 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
135 CHIP_ERRATA_PLL_DELAY = 0x00000004
136 };
137
138
139 struct radeon_device;
140
141
142 /*
143 * BIOS.
144 */
145 bool radeon_get_bios(struct radeon_device *rdev);
146
147 /*
148 * Dummy page
149 */
150 struct radeon_dummy_page {
151 struct page *page;
152 dma_addr_t addr;
153 };
154 int radeon_dummy_page_init(struct radeon_device *rdev);
155 void radeon_dummy_page_fini(struct radeon_device *rdev);
156
157
158 /*
159 * Clocks
160 */
161 struct radeon_clock {
162 struct radeon_pll p1pll;
163 struct radeon_pll p2pll;
164 struct radeon_pll dcpll;
165 struct radeon_pll spll;
166 struct radeon_pll mpll;
167 /* 10 Khz units */
168 uint32_t default_mclk;
169 uint32_t default_sclk;
170 uint32_t default_dispclk;
171 uint32_t dp_extclk;
172 uint32_t max_pixel_clock;
173 };
174
175 /*
176 * Power management
177 */
178 int radeon_pm_init(struct radeon_device *rdev);
179 void radeon_pm_fini(struct radeon_device *rdev);
180 void radeon_pm_compute_clocks(struct radeon_device *rdev);
181 void radeon_pm_suspend(struct radeon_device *rdev);
182 void radeon_pm_resume(struct radeon_device *rdev);
183 void radeon_combios_get_power_modes(struct radeon_device *rdev);
184 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
185 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
186 void rs690_pm_info(struct radeon_device *rdev);
187 extern int rv6xx_get_temp(struct radeon_device *rdev);
188 extern int rv770_get_temp(struct radeon_device *rdev);
189 extern int evergreen_get_temp(struct radeon_device *rdev);
190 extern int sumo_get_temp(struct radeon_device *rdev);
191 extern int si_get_temp(struct radeon_device *rdev);
192 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
193 unsigned *bankh, unsigned *mtaspect,
194 unsigned *tile_split);
195
196 /*
197 * Fences.
198 */
199 struct radeon_fence_driver {
200 uint32_t scratch_reg;
201 uint64_t gpu_addr;
202 volatile uint32_t *cpu_addr;
203 /* sync_seq is protected by ring emission lock */
204 uint64_t sync_seq[RADEON_NUM_RINGS];
205 atomic64_t last_seq;
206 unsigned long last_activity;
207 bool initialized;
208 };
209
210 struct radeon_fence {
211 struct radeon_device *rdev;
212 struct kref kref;
213 /* protected by radeon_fence.lock */
214 uint64_t seq;
215 /* RB, DMA, etc. */
216 unsigned ring;
217 };
218
219 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
220 int radeon_fence_driver_init(struct radeon_device *rdev);
221 void radeon_fence_driver_fini(struct radeon_device *rdev);
222 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
223 void radeon_fence_process(struct radeon_device *rdev, int ring);
224 bool radeon_fence_signaled(struct radeon_fence *fence);
225 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
226 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
227 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
228 int radeon_fence_wait_any(struct radeon_device *rdev,
229 struct radeon_fence **fences,
230 bool intr);
231 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
232 void radeon_fence_unref(struct radeon_fence **fence);
233 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
234 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
235 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
236 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
237 struct radeon_fence *b)
238 {
239 if (!a) {
240 return b;
241 }
242
243 if (!b) {
244 return a;
245 }
246
247 BUG_ON(a->ring != b->ring);
248
249 if (a->seq > b->seq) {
250 return a;
251 } else {
252 return b;
253 }
254 }
255
256 /*
257 * Tiling registers
258 */
259 struct radeon_surface_reg {
260 struct radeon_bo *bo;
261 };
262
263 #define RADEON_GEM_MAX_SURFACES 8
264
265 /*
266 * TTM.
267 */
268 struct radeon_mman {
269 struct ttm_bo_global_ref bo_global_ref;
270 struct drm_global_reference mem_global_ref;
271 struct ttm_bo_device bdev;
272 bool mem_global_referenced;
273 bool initialized;
274 };
275
276 /* bo virtual address in a specific vm */
277 struct radeon_bo_va {
278 /* bo list is protected by bo being reserved */
279 struct list_head bo_list;
280 /* vm list is protected by vm mutex */
281 struct list_head vm_list;
282 /* constant after initialization */
283 struct radeon_vm *vm;
284 struct radeon_bo *bo;
285 uint64_t soffset;
286 uint64_t eoffset;
287 uint32_t flags;
288 struct radeon_fence *fence;
289 bool valid;
290 };
291
292 struct radeon_bo {
293 /* Protected by gem.mutex */
294 struct list_head list;
295 /* Protected by tbo.reserved */
296 u32 placements[3];
297 struct ttm_placement placement;
298 struct ttm_buffer_object tbo;
299 struct ttm_bo_kmap_obj kmap;
300 unsigned pin_count;
301 void *kptr;
302 u32 tiling_flags;
303 u32 pitch;
304 int surface_reg;
305 /* list of all virtual address to which this bo
306 * is associated to
307 */
308 struct list_head va;
309 /* Constant after initialization */
310 struct radeon_device *rdev;
311 struct drm_gem_object gem_base;
312
313 struct ttm_bo_kmap_obj dma_buf_vmap;
314 int vmapping_count;
315 };
316 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
317
318 struct radeon_bo_list {
319 struct ttm_validate_buffer tv;
320 struct radeon_bo *bo;
321 uint64_t gpu_offset;
322 unsigned rdomain;
323 unsigned wdomain;
324 u32 tiling_flags;
325 };
326
327 /* sub-allocation manager, it has to be protected by another lock.
328 * By conception this is an helper for other part of the driver
329 * like the indirect buffer or semaphore, which both have their
330 * locking.
331 *
332 * Principe is simple, we keep a list of sub allocation in offset
333 * order (first entry has offset == 0, last entry has the highest
334 * offset).
335 *
336 * When allocating new object we first check if there is room at
337 * the end total_size - (last_object_offset + last_object_size) >=
338 * alloc_size. If so we allocate new object there.
339 *
340 * When there is not enough room at the end, we start waiting for
341 * each sub object until we reach object_offset+object_size >=
342 * alloc_size, this object then become the sub object we return.
343 *
344 * Alignment can't be bigger than page size.
345 *
346 * Hole are not considered for allocation to keep things simple.
347 * Assumption is that there won't be hole (all object on same
348 * alignment).
349 */
350 struct radeon_sa_manager {
351 wait_queue_head_t wq;
352 struct radeon_bo *bo;
353 struct list_head *hole;
354 struct list_head flist[RADEON_NUM_RINGS];
355 struct list_head olist;
356 unsigned size;
357 uint64_t gpu_addr;
358 void *cpu_ptr;
359 uint32_t domain;
360 };
361
362 struct radeon_sa_bo;
363
364 /* sub-allocation buffer */
365 struct radeon_sa_bo {
366 struct list_head olist;
367 struct list_head flist;
368 struct radeon_sa_manager *manager;
369 unsigned soffset;
370 unsigned eoffset;
371 struct radeon_fence *fence;
372 };
373
374 /*
375 * GEM objects.
376 */
377 struct radeon_gem {
378 struct mutex mutex;
379 struct list_head objects;
380 };
381
382 int radeon_gem_init(struct radeon_device *rdev);
383 void radeon_gem_fini(struct radeon_device *rdev);
384 int radeon_gem_object_create(struct radeon_device *rdev, int size,
385 int alignment, int initial_domain,
386 bool discardable, bool kernel,
387 struct drm_gem_object **obj);
388
389 int radeon_mode_dumb_create(struct drm_file *file_priv,
390 struct drm_device *dev,
391 struct drm_mode_create_dumb *args);
392 int radeon_mode_dumb_mmap(struct drm_file *filp,
393 struct drm_device *dev,
394 uint32_t handle, uint64_t *offset_p);
395 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
396 struct drm_device *dev,
397 uint32_t handle);
398
399 /*
400 * Semaphores.
401 */
402 /* everything here is constant */
403 struct radeon_semaphore {
404 struct radeon_sa_bo *sa_bo;
405 signed waiters;
406 uint64_t gpu_addr;
407 };
408
409 int radeon_semaphore_create(struct radeon_device *rdev,
410 struct radeon_semaphore **semaphore);
411 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
412 struct radeon_semaphore *semaphore);
413 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
414 struct radeon_semaphore *semaphore);
415 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
416 struct radeon_semaphore *semaphore,
417 int signaler, int waiter);
418 void radeon_semaphore_free(struct radeon_device *rdev,
419 struct radeon_semaphore **semaphore,
420 struct radeon_fence *fence);
421
422 /*
423 * GART structures, functions & helpers
424 */
425 struct radeon_mc;
426
427 #define RADEON_GPU_PAGE_SIZE 4096
428 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
429 #define RADEON_GPU_PAGE_SHIFT 12
430 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
431
432 struct radeon_gart {
433 dma_addr_t table_addr;
434 struct radeon_bo *robj;
435 void *ptr;
436 unsigned num_gpu_pages;
437 unsigned num_cpu_pages;
438 unsigned table_size;
439 struct page **pages;
440 dma_addr_t *pages_addr;
441 bool ready;
442 };
443
444 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
445 void radeon_gart_table_ram_free(struct radeon_device *rdev);
446 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
447 void radeon_gart_table_vram_free(struct radeon_device *rdev);
448 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
449 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
450 int radeon_gart_init(struct radeon_device *rdev);
451 void radeon_gart_fini(struct radeon_device *rdev);
452 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
453 int pages);
454 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
455 int pages, struct page **pagelist,
456 dma_addr_t *dma_addr);
457 void radeon_gart_restore(struct radeon_device *rdev);
458
459
460 /*
461 * GPU MC structures, functions & helpers
462 */
463 struct radeon_mc {
464 resource_size_t aper_size;
465 resource_size_t aper_base;
466 resource_size_t agp_base;
467 /* for some chips with <= 32MB we need to lie
468 * about vram size near mc fb location */
469 u64 mc_vram_size;
470 u64 visible_vram_size;
471 u64 gtt_size;
472 u64 gtt_start;
473 u64 gtt_end;
474 u64 vram_start;
475 u64 vram_end;
476 unsigned vram_width;
477 u64 real_vram_size;
478 int vram_mtrr;
479 bool vram_is_ddr;
480 bool igp_sideport_enabled;
481 u64 gtt_base_align;
482 };
483
484 bool radeon_combios_sideport_present(struct radeon_device *rdev);
485 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
486
487 /*
488 * GPU scratch registers structures, functions & helpers
489 */
490 struct radeon_scratch {
491 unsigned num_reg;
492 uint32_t reg_base;
493 bool free[32];
494 uint32_t reg[32];
495 };
496
497 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
498 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
499
500
501 /*
502 * IRQS.
503 */
504
505 struct radeon_unpin_work {
506 struct work_struct work;
507 struct radeon_device *rdev;
508 int crtc_id;
509 struct radeon_fence *fence;
510 struct drm_pending_vblank_event *event;
511 struct radeon_bo *old_rbo;
512 u64 new_crtc_base;
513 };
514
515 struct r500_irq_stat_regs {
516 u32 disp_int;
517 u32 hdmi0_status;
518 };
519
520 struct r600_irq_stat_regs {
521 u32 disp_int;
522 u32 disp_int_cont;
523 u32 disp_int_cont2;
524 u32 d1grph_int;
525 u32 d2grph_int;
526 u32 hdmi0_status;
527 u32 hdmi1_status;
528 };
529
530 struct evergreen_irq_stat_regs {
531 u32 disp_int;
532 u32 disp_int_cont;
533 u32 disp_int_cont2;
534 u32 disp_int_cont3;
535 u32 disp_int_cont4;
536 u32 disp_int_cont5;
537 u32 d1grph_int;
538 u32 d2grph_int;
539 u32 d3grph_int;
540 u32 d4grph_int;
541 u32 d5grph_int;
542 u32 d6grph_int;
543 u32 afmt_status1;
544 u32 afmt_status2;
545 u32 afmt_status3;
546 u32 afmt_status4;
547 u32 afmt_status5;
548 u32 afmt_status6;
549 };
550
551 union radeon_irq_stat_regs {
552 struct r500_irq_stat_regs r500;
553 struct r600_irq_stat_regs r600;
554 struct evergreen_irq_stat_regs evergreen;
555 };
556
557 #define RADEON_MAX_HPD_PINS 6
558 #define RADEON_MAX_CRTCS 6
559 #define RADEON_MAX_AFMT_BLOCKS 6
560
561 struct radeon_irq {
562 bool installed;
563 spinlock_t lock;
564 atomic_t ring_int[RADEON_NUM_RINGS];
565 bool crtc_vblank_int[RADEON_MAX_CRTCS];
566 atomic_t pflip[RADEON_MAX_CRTCS];
567 wait_queue_head_t vblank_queue;
568 bool hpd[RADEON_MAX_HPD_PINS];
569 bool afmt[RADEON_MAX_AFMT_BLOCKS];
570 union radeon_irq_stat_regs stat_regs;
571 };
572
573 int radeon_irq_kms_init(struct radeon_device *rdev);
574 void radeon_irq_kms_fini(struct radeon_device *rdev);
575 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
576 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
577 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
578 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
579 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
580 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
581 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
582 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
583
584 /*
585 * CP & rings.
586 */
587
588 struct radeon_ib {
589 struct radeon_sa_bo *sa_bo;
590 uint32_t length_dw;
591 uint64_t gpu_addr;
592 uint32_t *ptr;
593 int ring;
594 struct radeon_fence *fence;
595 unsigned vm_id;
596 bool is_const_ib;
597 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
598 struct radeon_semaphore *semaphore;
599 };
600
601 struct radeon_ring {
602 struct radeon_bo *ring_obj;
603 volatile uint32_t *ring;
604 unsigned rptr;
605 unsigned rptr_offs;
606 unsigned rptr_reg;
607 unsigned rptr_save_reg;
608 u64 next_rptr_gpu_addr;
609 volatile u32 *next_rptr_cpu_addr;
610 unsigned wptr;
611 unsigned wptr_old;
612 unsigned wptr_reg;
613 unsigned ring_size;
614 unsigned ring_free_dw;
615 int count_dw;
616 unsigned long last_activity;
617 unsigned last_rptr;
618 uint64_t gpu_addr;
619 uint32_t align_mask;
620 uint32_t ptr_mask;
621 bool ready;
622 u32 ptr_reg_shift;
623 u32 ptr_reg_mask;
624 u32 nop;
625 u32 idx;
626 };
627
628 /*
629 * VM
630 */
631 struct radeon_vm {
632 struct list_head list;
633 struct list_head va;
634 int id;
635 unsigned last_pfn;
636 u64 pt_gpu_addr;
637 u64 *pt;
638 struct radeon_sa_bo *sa_bo;
639 struct mutex mutex;
640 /* last fence for cs using this vm */
641 struct radeon_fence *fence;
642 };
643
644 struct radeon_vm_funcs {
645 int (*init)(struct radeon_device *rdev);
646 void (*fini)(struct radeon_device *rdev);
647 /* cs mutex must be lock for schedule_ib */
648 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
649 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
650 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
651 uint32_t (*page_flags)(struct radeon_device *rdev,
652 struct radeon_vm *vm,
653 uint32_t flags);
654 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
655 unsigned pfn, uint64_t addr, uint32_t flags);
656 };
657
658 struct radeon_vm_manager {
659 struct mutex lock;
660 struct list_head lru_vm;
661 uint32_t use_bitmap;
662 struct radeon_sa_manager sa_manager;
663 uint32_t max_pfn;
664 /* fields constant after init */
665 const struct radeon_vm_funcs *funcs;
666 /* number of VMIDs */
667 unsigned nvm;
668 /* vram base address for page table entry */
669 u64 vram_base_offset;
670 /* is vm enabled? */
671 bool enabled;
672 };
673
674 /*
675 * file private structure
676 */
677 struct radeon_fpriv {
678 struct radeon_vm vm;
679 };
680
681 /*
682 * R6xx+ IH ring
683 */
684 struct r600_ih {
685 struct radeon_bo *ring_obj;
686 volatile uint32_t *ring;
687 unsigned rptr;
688 unsigned ring_size;
689 uint64_t gpu_addr;
690 uint32_t ptr_mask;
691 atomic_t lock;
692 bool enabled;
693 };
694
695 struct r600_blit_cp_primitives {
696 void (*set_render_target)(struct radeon_device *rdev, int format,
697 int w, int h, u64 gpu_addr);
698 void (*cp_set_surface_sync)(struct radeon_device *rdev,
699 u32 sync_type, u32 size,
700 u64 mc_addr);
701 void (*set_shaders)(struct radeon_device *rdev);
702 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
703 void (*set_tex_resource)(struct radeon_device *rdev,
704 int format, int w, int h, int pitch,
705 u64 gpu_addr, u32 size);
706 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
707 int x2, int y2);
708 void (*draw_auto)(struct radeon_device *rdev);
709 void (*set_default_state)(struct radeon_device *rdev);
710 };
711
712 struct r600_blit {
713 struct radeon_bo *shader_obj;
714 struct r600_blit_cp_primitives primitives;
715 int max_dim;
716 int ring_size_common;
717 int ring_size_per_loop;
718 u64 shader_gpu_addr;
719 u32 vs_offset, ps_offset;
720 u32 state_offset;
721 u32 state_len;
722 };
723
724 /*
725 * SI RLC stuff
726 */
727 struct si_rlc {
728 /* for power gating */
729 struct radeon_bo *save_restore_obj;
730 uint64_t save_restore_gpu_addr;
731 /* for clear state */
732 struct radeon_bo *clear_state_obj;
733 uint64_t clear_state_gpu_addr;
734 };
735
736 int radeon_ib_get(struct radeon_device *rdev, int ring,
737 struct radeon_ib *ib, unsigned size);
738 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
739 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
740 struct radeon_ib *const_ib);
741 int radeon_ib_pool_init(struct radeon_device *rdev);
742 void radeon_ib_pool_fini(struct radeon_device *rdev);
743 int radeon_ib_ring_tests(struct radeon_device *rdev);
744 /* Ring access between begin & end cannot sleep */
745 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
746 struct radeon_ring *ring);
747 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
748 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
749 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
750 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
751 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
752 void radeon_ring_undo(struct radeon_ring *ring);
753 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
754 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
755 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
756 void radeon_ring_lockup_update(struct radeon_ring *ring);
757 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
758 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
759 uint32_t **data);
760 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
761 unsigned size, uint32_t *data);
762 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
763 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
764 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
765 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
766
767
768 /*
769 * CS.
770 */
771 struct radeon_cs_reloc {
772 struct drm_gem_object *gobj;
773 struct radeon_bo *robj;
774 struct radeon_bo_list lobj;
775 uint32_t handle;
776 uint32_t flags;
777 };
778
779 struct radeon_cs_chunk {
780 uint32_t chunk_id;
781 uint32_t length_dw;
782 int kpage_idx[2];
783 uint32_t *kpage[2];
784 uint32_t *kdata;
785 void __user *user_ptr;
786 int last_copied_page;
787 int last_page_index;
788 };
789
790 struct radeon_cs_parser {
791 struct device *dev;
792 struct radeon_device *rdev;
793 struct drm_file *filp;
794 /* chunks */
795 unsigned nchunks;
796 struct radeon_cs_chunk *chunks;
797 uint64_t *chunks_array;
798 /* IB */
799 unsigned idx;
800 /* relocations */
801 unsigned nrelocs;
802 struct radeon_cs_reloc *relocs;
803 struct radeon_cs_reloc **relocs_ptr;
804 struct list_head validated;
805 /* indices of various chunks */
806 int chunk_ib_idx;
807 int chunk_relocs_idx;
808 int chunk_flags_idx;
809 int chunk_const_ib_idx;
810 struct radeon_ib ib;
811 struct radeon_ib const_ib;
812 void *track;
813 unsigned family;
814 int parser_error;
815 u32 cs_flags;
816 u32 ring;
817 s32 priority;
818 };
819
820 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
821 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
822
823 struct radeon_cs_packet {
824 unsigned idx;
825 unsigned type;
826 unsigned reg;
827 unsigned opcode;
828 int count;
829 unsigned one_reg_wr;
830 };
831
832 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
833 struct radeon_cs_packet *pkt,
834 unsigned idx, unsigned reg);
835 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
836 struct radeon_cs_packet *pkt);
837
838
839 /*
840 * AGP
841 */
842 int radeon_agp_init(struct radeon_device *rdev);
843 void radeon_agp_resume(struct radeon_device *rdev);
844 void radeon_agp_suspend(struct radeon_device *rdev);
845 void radeon_agp_fini(struct radeon_device *rdev);
846
847
848 /*
849 * Writeback
850 */
851 struct radeon_wb {
852 struct radeon_bo *wb_obj;
853 volatile uint32_t *wb;
854 uint64_t gpu_addr;
855 bool enabled;
856 bool use_event;
857 };
858
859 #define RADEON_WB_SCRATCH_OFFSET 0
860 #define RADEON_WB_RING0_NEXT_RPTR 256
861 #define RADEON_WB_CP_RPTR_OFFSET 1024
862 #define RADEON_WB_CP1_RPTR_OFFSET 1280
863 #define RADEON_WB_CP2_RPTR_OFFSET 1536
864 #define R600_WB_IH_WPTR_OFFSET 2048
865 #define R600_WB_EVENT_OFFSET 3072
866
867 /**
868 * struct radeon_pm - power management datas
869 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
870 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
871 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
872 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
873 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
874 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
875 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
876 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
877 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
878 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
879 * @needed_bandwidth: current bandwidth needs
880 *
881 * It keeps track of various data needed to take powermanagement decision.
882 * Bandwidth need is used to determine minimun clock of the GPU and memory.
883 * Equation between gpu/memory clock and available bandwidth is hw dependent
884 * (type of memory, bus size, efficiency, ...)
885 */
886
887 enum radeon_pm_method {
888 PM_METHOD_PROFILE,
889 PM_METHOD_DYNPM,
890 };
891
892 enum radeon_dynpm_state {
893 DYNPM_STATE_DISABLED,
894 DYNPM_STATE_MINIMUM,
895 DYNPM_STATE_PAUSED,
896 DYNPM_STATE_ACTIVE,
897 DYNPM_STATE_SUSPENDED,
898 };
899 enum radeon_dynpm_action {
900 DYNPM_ACTION_NONE,
901 DYNPM_ACTION_MINIMUM,
902 DYNPM_ACTION_DOWNCLOCK,
903 DYNPM_ACTION_UPCLOCK,
904 DYNPM_ACTION_DEFAULT
905 };
906
907 enum radeon_voltage_type {
908 VOLTAGE_NONE = 0,
909 VOLTAGE_GPIO,
910 VOLTAGE_VDDC,
911 VOLTAGE_SW
912 };
913
914 enum radeon_pm_state_type {
915 POWER_STATE_TYPE_DEFAULT,
916 POWER_STATE_TYPE_POWERSAVE,
917 POWER_STATE_TYPE_BATTERY,
918 POWER_STATE_TYPE_BALANCED,
919 POWER_STATE_TYPE_PERFORMANCE,
920 };
921
922 enum radeon_pm_profile_type {
923 PM_PROFILE_DEFAULT,
924 PM_PROFILE_AUTO,
925 PM_PROFILE_LOW,
926 PM_PROFILE_MID,
927 PM_PROFILE_HIGH,
928 };
929
930 #define PM_PROFILE_DEFAULT_IDX 0
931 #define PM_PROFILE_LOW_SH_IDX 1
932 #define PM_PROFILE_MID_SH_IDX 2
933 #define PM_PROFILE_HIGH_SH_IDX 3
934 #define PM_PROFILE_LOW_MH_IDX 4
935 #define PM_PROFILE_MID_MH_IDX 5
936 #define PM_PROFILE_HIGH_MH_IDX 6
937 #define PM_PROFILE_MAX 7
938
939 struct radeon_pm_profile {
940 int dpms_off_ps_idx;
941 int dpms_on_ps_idx;
942 int dpms_off_cm_idx;
943 int dpms_on_cm_idx;
944 };
945
946 enum radeon_int_thermal_type {
947 THERMAL_TYPE_NONE,
948 THERMAL_TYPE_RV6XX,
949 THERMAL_TYPE_RV770,
950 THERMAL_TYPE_EVERGREEN,
951 THERMAL_TYPE_SUMO,
952 THERMAL_TYPE_NI,
953 THERMAL_TYPE_SI,
954 };
955
956 struct radeon_voltage {
957 enum radeon_voltage_type type;
958 /* gpio voltage */
959 struct radeon_gpio_rec gpio;
960 u32 delay; /* delay in usec from voltage drop to sclk change */
961 bool active_high; /* voltage drop is active when bit is high */
962 /* VDDC voltage */
963 u8 vddc_id; /* index into vddc voltage table */
964 u8 vddci_id; /* index into vddci voltage table */
965 bool vddci_enabled;
966 /* r6xx+ sw */
967 u16 voltage;
968 /* evergreen+ vddci */
969 u16 vddci;
970 };
971
972 /* clock mode flags */
973 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
974
975 struct radeon_pm_clock_info {
976 /* memory clock */
977 u32 mclk;
978 /* engine clock */
979 u32 sclk;
980 /* voltage info */
981 struct radeon_voltage voltage;
982 /* standardized clock flags */
983 u32 flags;
984 };
985
986 /* state flags */
987 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
988
989 struct radeon_power_state {
990 enum radeon_pm_state_type type;
991 struct radeon_pm_clock_info *clock_info;
992 /* number of valid clock modes in this power state */
993 int num_clock_modes;
994 struct radeon_pm_clock_info *default_clock_mode;
995 /* standardized state flags */
996 u32 flags;
997 u32 misc; /* vbios specific flags */
998 u32 misc2; /* vbios specific flags */
999 int pcie_lanes; /* pcie lanes */
1000 };
1001
1002 /*
1003 * Some modes are overclocked by very low value, accept them
1004 */
1005 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1006
1007 struct radeon_pm {
1008 struct mutex mutex;
1009 /* write locked while reprogramming mclk */
1010 struct rw_semaphore mclk_lock;
1011 u32 active_crtcs;
1012 int active_crtc_count;
1013 int req_vblank;
1014 bool vblank_sync;
1015 fixed20_12 max_bandwidth;
1016 fixed20_12 igp_sideport_mclk;
1017 fixed20_12 igp_system_mclk;
1018 fixed20_12 igp_ht_link_clk;
1019 fixed20_12 igp_ht_link_width;
1020 fixed20_12 k8_bandwidth;
1021 fixed20_12 sideport_bandwidth;
1022 fixed20_12 ht_bandwidth;
1023 fixed20_12 core_bandwidth;
1024 fixed20_12 sclk;
1025 fixed20_12 mclk;
1026 fixed20_12 needed_bandwidth;
1027 struct radeon_power_state *power_state;
1028 /* number of valid power states */
1029 int num_power_states;
1030 int current_power_state_index;
1031 int current_clock_mode_index;
1032 int requested_power_state_index;
1033 int requested_clock_mode_index;
1034 int default_power_state_index;
1035 u32 current_sclk;
1036 u32 current_mclk;
1037 u16 current_vddc;
1038 u16 current_vddci;
1039 u32 default_sclk;
1040 u32 default_mclk;
1041 u16 default_vddc;
1042 u16 default_vddci;
1043 struct radeon_i2c_chan *i2c_bus;
1044 /* selected pm method */
1045 enum radeon_pm_method pm_method;
1046 /* dynpm power management */
1047 struct delayed_work dynpm_idle_work;
1048 enum radeon_dynpm_state dynpm_state;
1049 enum radeon_dynpm_action dynpm_planned_action;
1050 unsigned long dynpm_action_timeout;
1051 bool dynpm_can_upclock;
1052 bool dynpm_can_downclock;
1053 /* profile-based power management */
1054 enum radeon_pm_profile_type profile;
1055 int profile_index;
1056 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1057 /* internal thermal controller on rv6xx+ */
1058 enum radeon_int_thermal_type int_thermal_type;
1059 struct device *int_hwmon_dev;
1060 };
1061
1062 int radeon_pm_get_type_index(struct radeon_device *rdev,
1063 enum radeon_pm_state_type ps_type,
1064 int instance);
1065
1066 struct r600_audio {
1067 int channels;
1068 int rate;
1069 int bits_per_sample;
1070 u8 status_bits;
1071 u8 category_code;
1072 };
1073
1074 /*
1075 * Benchmarking
1076 */
1077 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1078
1079
1080 /*
1081 * Testing
1082 */
1083 void radeon_test_moves(struct radeon_device *rdev);
1084 void radeon_test_ring_sync(struct radeon_device *rdev,
1085 struct radeon_ring *cpA,
1086 struct radeon_ring *cpB);
1087 void radeon_test_syncing(struct radeon_device *rdev);
1088
1089
1090 /*
1091 * Debugfs
1092 */
1093 struct radeon_debugfs {
1094 struct drm_info_list *files;
1095 unsigned num_files;
1096 };
1097
1098 int radeon_debugfs_add_files(struct radeon_device *rdev,
1099 struct drm_info_list *files,
1100 unsigned nfiles);
1101 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1102
1103
1104 /*
1105 * ASIC specific functions.
1106 */
1107 struct radeon_asic {
1108 int (*init)(struct radeon_device *rdev);
1109 void (*fini)(struct radeon_device *rdev);
1110 int (*resume)(struct radeon_device *rdev);
1111 int (*suspend)(struct radeon_device *rdev);
1112 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1113 int (*asic_reset)(struct radeon_device *rdev);
1114 /* ioctl hw specific callback. Some hw might want to perform special
1115 * operation on specific ioctl. For instance on wait idle some hw
1116 * might want to perform and HDP flush through MMIO as it seems that
1117 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1118 * through ring.
1119 */
1120 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1121 /* check if 3D engine is idle */
1122 bool (*gui_idle)(struct radeon_device *rdev);
1123 /* wait for mc_idle */
1124 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1125 /* gart */
1126 struct {
1127 void (*tlb_flush)(struct radeon_device *rdev);
1128 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1129 } gart;
1130 /* ring specific callbacks */
1131 struct {
1132 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1133 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1134 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1135 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1136 struct radeon_semaphore *semaphore, bool emit_wait);
1137 int (*cs_parse)(struct radeon_cs_parser *p);
1138 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1139 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1140 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1141 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1142 } ring[RADEON_NUM_RINGS];
1143 /* irqs */
1144 struct {
1145 int (*set)(struct radeon_device *rdev);
1146 int (*process)(struct radeon_device *rdev);
1147 } irq;
1148 /* displays */
1149 struct {
1150 /* display watermarks */
1151 void (*bandwidth_update)(struct radeon_device *rdev);
1152 /* get frame count */
1153 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1154 /* wait for vblank */
1155 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1156 } display;
1157 /* copy functions for bo handling */
1158 struct {
1159 int (*blit)(struct radeon_device *rdev,
1160 uint64_t src_offset,
1161 uint64_t dst_offset,
1162 unsigned num_gpu_pages,
1163 struct radeon_fence **fence);
1164 u32 blit_ring_index;
1165 int (*dma)(struct radeon_device *rdev,
1166 uint64_t src_offset,
1167 uint64_t dst_offset,
1168 unsigned num_gpu_pages,
1169 struct radeon_fence **fence);
1170 u32 dma_ring_index;
1171 /* method used for bo copy */
1172 int (*copy)(struct radeon_device *rdev,
1173 uint64_t src_offset,
1174 uint64_t dst_offset,
1175 unsigned num_gpu_pages,
1176 struct radeon_fence **fence);
1177 /* ring used for bo copies */
1178 u32 copy_ring_index;
1179 } copy;
1180 /* surfaces */
1181 struct {
1182 int (*set_reg)(struct radeon_device *rdev, int reg,
1183 uint32_t tiling_flags, uint32_t pitch,
1184 uint32_t offset, uint32_t obj_size);
1185 void (*clear_reg)(struct radeon_device *rdev, int reg);
1186 } surface;
1187 /* hotplug detect */
1188 struct {
1189 void (*init)(struct radeon_device *rdev);
1190 void (*fini)(struct radeon_device *rdev);
1191 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1192 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1193 } hpd;
1194 /* power management */
1195 struct {
1196 void (*misc)(struct radeon_device *rdev);
1197 void (*prepare)(struct radeon_device *rdev);
1198 void (*finish)(struct radeon_device *rdev);
1199 void (*init_profile)(struct radeon_device *rdev);
1200 void (*get_dynpm_state)(struct radeon_device *rdev);
1201 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1202 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1203 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1204 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1205 int (*get_pcie_lanes)(struct radeon_device *rdev);
1206 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1207 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1208 } pm;
1209 /* pageflipping */
1210 struct {
1211 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1212 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1213 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1214 } pflip;
1215 };
1216
1217 /*
1218 * Asic structures
1219 */
1220 struct r100_asic {
1221 const unsigned *reg_safe_bm;
1222 unsigned reg_safe_bm_size;
1223 u32 hdp_cntl;
1224 };
1225
1226 struct r300_asic {
1227 const unsigned *reg_safe_bm;
1228 unsigned reg_safe_bm_size;
1229 u32 resync_scratch;
1230 u32 hdp_cntl;
1231 };
1232
1233 struct r600_asic {
1234 unsigned max_pipes;
1235 unsigned max_tile_pipes;
1236 unsigned max_simds;
1237 unsigned max_backends;
1238 unsigned max_gprs;
1239 unsigned max_threads;
1240 unsigned max_stack_entries;
1241 unsigned max_hw_contexts;
1242 unsigned max_gs_threads;
1243 unsigned sx_max_export_size;
1244 unsigned sx_max_export_pos_size;
1245 unsigned sx_max_export_smx_size;
1246 unsigned sq_num_cf_insts;
1247 unsigned tiling_nbanks;
1248 unsigned tiling_npipes;
1249 unsigned tiling_group_size;
1250 unsigned tile_config;
1251 unsigned backend_map;
1252 };
1253
1254 struct rv770_asic {
1255 unsigned max_pipes;
1256 unsigned max_tile_pipes;
1257 unsigned max_simds;
1258 unsigned max_backends;
1259 unsigned max_gprs;
1260 unsigned max_threads;
1261 unsigned max_stack_entries;
1262 unsigned max_hw_contexts;
1263 unsigned max_gs_threads;
1264 unsigned sx_max_export_size;
1265 unsigned sx_max_export_pos_size;
1266 unsigned sx_max_export_smx_size;
1267 unsigned sq_num_cf_insts;
1268 unsigned sx_num_of_sets;
1269 unsigned sc_prim_fifo_size;
1270 unsigned sc_hiz_tile_fifo_size;
1271 unsigned sc_earlyz_tile_fifo_fize;
1272 unsigned tiling_nbanks;
1273 unsigned tiling_npipes;
1274 unsigned tiling_group_size;
1275 unsigned tile_config;
1276 unsigned backend_map;
1277 };
1278
1279 struct evergreen_asic {
1280 unsigned num_ses;
1281 unsigned max_pipes;
1282 unsigned max_tile_pipes;
1283 unsigned max_simds;
1284 unsigned max_backends;
1285 unsigned max_gprs;
1286 unsigned max_threads;
1287 unsigned max_stack_entries;
1288 unsigned max_hw_contexts;
1289 unsigned max_gs_threads;
1290 unsigned sx_max_export_size;
1291 unsigned sx_max_export_pos_size;
1292 unsigned sx_max_export_smx_size;
1293 unsigned sq_num_cf_insts;
1294 unsigned sx_num_of_sets;
1295 unsigned sc_prim_fifo_size;
1296 unsigned sc_hiz_tile_fifo_size;
1297 unsigned sc_earlyz_tile_fifo_size;
1298 unsigned tiling_nbanks;
1299 unsigned tiling_npipes;
1300 unsigned tiling_group_size;
1301 unsigned tile_config;
1302 unsigned backend_map;
1303 };
1304
1305 struct cayman_asic {
1306 unsigned max_shader_engines;
1307 unsigned max_pipes_per_simd;
1308 unsigned max_tile_pipes;
1309 unsigned max_simds_per_se;
1310 unsigned max_backends_per_se;
1311 unsigned max_texture_channel_caches;
1312 unsigned max_gprs;
1313 unsigned max_threads;
1314 unsigned max_gs_threads;
1315 unsigned max_stack_entries;
1316 unsigned sx_num_of_sets;
1317 unsigned sx_max_export_size;
1318 unsigned sx_max_export_pos_size;
1319 unsigned sx_max_export_smx_size;
1320 unsigned max_hw_contexts;
1321 unsigned sq_num_cf_insts;
1322 unsigned sc_prim_fifo_size;
1323 unsigned sc_hiz_tile_fifo_size;
1324 unsigned sc_earlyz_tile_fifo_size;
1325
1326 unsigned num_shader_engines;
1327 unsigned num_shader_pipes_per_simd;
1328 unsigned num_tile_pipes;
1329 unsigned num_simds_per_se;
1330 unsigned num_backends_per_se;
1331 unsigned backend_disable_mask_per_asic;
1332 unsigned backend_map;
1333 unsigned num_texture_channel_caches;
1334 unsigned mem_max_burst_length_bytes;
1335 unsigned mem_row_size_in_kb;
1336 unsigned shader_engine_tile_size;
1337 unsigned num_gpus;
1338 unsigned multi_gpu_tile_size;
1339
1340 unsigned tile_config;
1341 };
1342
1343 struct si_asic {
1344 unsigned max_shader_engines;
1345 unsigned max_tile_pipes;
1346 unsigned max_cu_per_sh;
1347 unsigned max_sh_per_se;
1348 unsigned max_backends_per_se;
1349 unsigned max_texture_channel_caches;
1350 unsigned max_gprs;
1351 unsigned max_gs_threads;
1352 unsigned max_hw_contexts;
1353 unsigned sc_prim_fifo_size_frontend;
1354 unsigned sc_prim_fifo_size_backend;
1355 unsigned sc_hiz_tile_fifo_size;
1356 unsigned sc_earlyz_tile_fifo_size;
1357
1358 unsigned num_tile_pipes;
1359 unsigned num_backends_per_se;
1360 unsigned backend_disable_mask_per_asic;
1361 unsigned backend_map;
1362 unsigned num_texture_channel_caches;
1363 unsigned mem_max_burst_length_bytes;
1364 unsigned mem_row_size_in_kb;
1365 unsigned shader_engine_tile_size;
1366 unsigned num_gpus;
1367 unsigned multi_gpu_tile_size;
1368
1369 unsigned tile_config;
1370 };
1371
1372 union radeon_asic_config {
1373 struct r300_asic r300;
1374 struct r100_asic r100;
1375 struct r600_asic r600;
1376 struct rv770_asic rv770;
1377 struct evergreen_asic evergreen;
1378 struct cayman_asic cayman;
1379 struct si_asic si;
1380 };
1381
1382 /*
1383 * asic initizalization from radeon_asic.c
1384 */
1385 void radeon_agp_disable(struct radeon_device *rdev);
1386 int radeon_asic_init(struct radeon_device *rdev);
1387
1388
1389 /*
1390 * IOCTL.
1391 */
1392 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *filp);
1394 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *filp);
1396 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1397 struct drm_file *file_priv);
1398 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1399 struct drm_file *file_priv);
1400 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1401 struct drm_file *file_priv);
1402 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1403 struct drm_file *file_priv);
1404 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1405 struct drm_file *filp);
1406 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1407 struct drm_file *filp);
1408 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1409 struct drm_file *filp);
1410 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1411 struct drm_file *filp);
1412 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1413 struct drm_file *filp);
1414 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1415 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1416 struct drm_file *filp);
1417 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1418 struct drm_file *filp);
1419
1420 /* VRAM scratch page for HDP bug, default vram page */
1421 struct r600_vram_scratch {
1422 struct radeon_bo *robj;
1423 volatile uint32_t *ptr;
1424 u64 gpu_addr;
1425 };
1426
1427 /*
1428 * ACPI
1429 */
1430 struct radeon_atif_notification_cfg {
1431 bool enabled;
1432 int command_code;
1433 };
1434
1435 struct radeon_atif_notifications {
1436 bool display_switch;
1437 bool expansion_mode_change;
1438 bool thermal_state;
1439 bool forced_power_state;
1440 bool system_power_state;
1441 bool display_conf_change;
1442 bool px_gfx_switch;
1443 bool brightness_change;
1444 bool dgpu_display_event;
1445 };
1446
1447 struct radeon_atif_functions {
1448 bool system_params;
1449 bool sbios_requests;
1450 bool select_active_disp;
1451 bool lid_state;
1452 bool get_tv_standard;
1453 bool set_tv_standard;
1454 bool get_panel_expansion_mode;
1455 bool set_panel_expansion_mode;
1456 bool temperature_change;
1457 bool graphics_device_types;
1458 };
1459
1460 struct radeon_atif {
1461 struct radeon_atif_notifications notifications;
1462 struct radeon_atif_functions functions;
1463 struct radeon_atif_notification_cfg notification_cfg;
1464 struct radeon_encoder *backlight_ctl;
1465 };
1466
1467 /*
1468 * Core structure, functions and helpers.
1469 */
1470 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1471 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1472
1473 struct radeon_device {
1474 struct device *dev;
1475 struct drm_device *ddev;
1476 struct pci_dev *pdev;
1477 struct rw_semaphore exclusive_lock;
1478 /* ASIC */
1479 union radeon_asic_config config;
1480 enum radeon_family family;
1481 unsigned long flags;
1482 int usec_timeout;
1483 enum radeon_pll_errata pll_errata;
1484 int num_gb_pipes;
1485 int num_z_pipes;
1486 int disp_priority;
1487 /* BIOS */
1488 uint8_t *bios;
1489 bool is_atom_bios;
1490 uint16_t bios_header_start;
1491 struct radeon_bo *stollen_vga_memory;
1492 /* Register mmio */
1493 resource_size_t rmmio_base;
1494 resource_size_t rmmio_size;
1495 void __iomem *rmmio;
1496 radeon_rreg_t mc_rreg;
1497 radeon_wreg_t mc_wreg;
1498 radeon_rreg_t pll_rreg;
1499 radeon_wreg_t pll_wreg;
1500 uint32_t pcie_reg_mask;
1501 radeon_rreg_t pciep_rreg;
1502 radeon_wreg_t pciep_wreg;
1503 /* io port */
1504 void __iomem *rio_mem;
1505 resource_size_t rio_mem_size;
1506 struct radeon_clock clock;
1507 struct radeon_mc mc;
1508 struct radeon_gart gart;
1509 struct radeon_mode_info mode_info;
1510 struct radeon_scratch scratch;
1511 struct radeon_mman mman;
1512 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1513 wait_queue_head_t fence_queue;
1514 struct mutex ring_lock;
1515 struct radeon_ring ring[RADEON_NUM_RINGS];
1516 bool ib_pool_ready;
1517 struct radeon_sa_manager ring_tmp_bo;
1518 struct radeon_irq irq;
1519 struct radeon_asic *asic;
1520 struct radeon_gem gem;
1521 struct radeon_pm pm;
1522 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1523 struct radeon_wb wb;
1524 struct radeon_dummy_page dummy_page;
1525 bool shutdown;
1526 bool suspend;
1527 bool need_dma32;
1528 bool accel_working;
1529 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1530 const struct firmware *me_fw; /* all family ME firmware */
1531 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1532 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1533 const struct firmware *mc_fw; /* NI MC firmware */
1534 const struct firmware *ce_fw; /* SI CE firmware */
1535 struct r600_blit r600_blit;
1536 struct r600_vram_scratch vram_scratch;
1537 int msi_enabled; /* msi enabled */
1538 struct r600_ih ih; /* r6/700 interrupt ring */
1539 struct si_rlc rlc;
1540 struct work_struct hotplug_work;
1541 struct work_struct audio_work;
1542 int num_crtc; /* number of crtcs */
1543 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1544 bool audio_enabled;
1545 struct r600_audio audio_status; /* audio stuff */
1546 struct notifier_block acpi_nb;
1547 /* only one userspace can use Hyperz features or CMASK at a time */
1548 struct drm_file *hyperz_filp;
1549 struct drm_file *cmask_filp;
1550 /* i2c buses */
1551 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1552 /* debugfs */
1553 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1554 unsigned debugfs_count;
1555 /* virtual memory */
1556 struct radeon_vm_manager vm_manager;
1557 struct mutex gpu_clock_mutex;
1558 /* ACPI interface */
1559 struct radeon_atif atif;
1560 };
1561
1562 int radeon_device_init(struct radeon_device *rdev,
1563 struct drm_device *ddev,
1564 struct pci_dev *pdev,
1565 uint32_t flags);
1566 void radeon_device_fini(struct radeon_device *rdev);
1567 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1568
1569 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1570 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1571 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1572 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1573
1574 /*
1575 * Cast helper
1576 */
1577 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1578
1579 /*
1580 * Registers read & write functions.
1581 */
1582 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1583 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1584 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1585 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1586 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1587 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1588 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1589 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1590 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1591 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1592 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1593 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1594 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1595 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1596 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1597 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1598 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1599 #define WREG32_P(reg, val, mask) \
1600 do { \
1601 uint32_t tmp_ = RREG32(reg); \
1602 tmp_ &= (mask); \
1603 tmp_ |= ((val) & ~(mask)); \
1604 WREG32(reg, tmp_); \
1605 } while (0)
1606 #define WREG32_PLL_P(reg, val, mask) \
1607 do { \
1608 uint32_t tmp_ = RREG32_PLL(reg); \
1609 tmp_ &= (mask); \
1610 tmp_ |= ((val) & ~(mask)); \
1611 WREG32_PLL(reg, tmp_); \
1612 } while (0)
1613 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1614 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1615 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1616
1617 /*
1618 * Indirect registers accessor
1619 */
1620 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1621 {
1622 uint32_t r;
1623
1624 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1625 r = RREG32(RADEON_PCIE_DATA);
1626 return r;
1627 }
1628
1629 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1630 {
1631 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1632 WREG32(RADEON_PCIE_DATA, (v));
1633 }
1634
1635 void r100_pll_errata_after_index(struct radeon_device *rdev);
1636
1637
1638 /*
1639 * ASICs helpers.
1640 */
1641 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1642 (rdev->pdev->device == 0x5969))
1643 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1644 (rdev->family == CHIP_RV200) || \
1645 (rdev->family == CHIP_RS100) || \
1646 (rdev->family == CHIP_RS200) || \
1647 (rdev->family == CHIP_RV250) || \
1648 (rdev->family == CHIP_RV280) || \
1649 (rdev->family == CHIP_RS300))
1650 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1651 (rdev->family == CHIP_RV350) || \
1652 (rdev->family == CHIP_R350) || \
1653 (rdev->family == CHIP_RV380) || \
1654 (rdev->family == CHIP_R420) || \
1655 (rdev->family == CHIP_R423) || \
1656 (rdev->family == CHIP_RV410) || \
1657 (rdev->family == CHIP_RS400) || \
1658 (rdev->family == CHIP_RS480))
1659 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1660 (rdev->ddev->pdev->device == 0x9443) || \
1661 (rdev->ddev->pdev->device == 0x944B) || \
1662 (rdev->ddev->pdev->device == 0x9506) || \
1663 (rdev->ddev->pdev->device == 0x9509) || \
1664 (rdev->ddev->pdev->device == 0x950F) || \
1665 (rdev->ddev->pdev->device == 0x689C) || \
1666 (rdev->ddev->pdev->device == 0x689D))
1667 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1668 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1669 (rdev->family == CHIP_RS690) || \
1670 (rdev->family == CHIP_RS740) || \
1671 (rdev->family >= CHIP_R600))
1672 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1673 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1674 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1675 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1676 (rdev->flags & RADEON_IS_IGP))
1677 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1678 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1679 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1680 (rdev->flags & RADEON_IS_IGP))
1681
1682 /*
1683 * BIOS helpers.
1684 */
1685 #define RBIOS8(i) (rdev->bios[i])
1686 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1687 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1688
1689 int radeon_combios_init(struct radeon_device *rdev);
1690 void radeon_combios_fini(struct radeon_device *rdev);
1691 int radeon_atombios_init(struct radeon_device *rdev);
1692 void radeon_atombios_fini(struct radeon_device *rdev);
1693
1694
1695 /*
1696 * RING helpers.
1697 */
1698 #if DRM_DEBUG_CODE == 0
1699 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1700 {
1701 ring->ring[ring->wptr++] = v;
1702 ring->wptr &= ring->ptr_mask;
1703 ring->count_dw--;
1704 ring->ring_free_dw--;
1705 }
1706 #else
1707 /* With debugging this is just too big to inline */
1708 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1709 #endif
1710
1711 /*
1712 * ASICs macro.
1713 */
1714 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1715 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1716 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1717 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1718 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1719 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1720 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1721 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1722 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1723 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1724 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1725 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1726 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1727 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1728 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1729 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1730 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1731 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1732 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1733 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1734 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1735 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1736 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1737 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1738 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1739 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1740 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1741 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1742 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1743 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1744 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1745 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1746 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1747 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1748 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1749 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1750 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1751 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1752 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1753 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1754 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1755 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1756 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1757 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1758 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1759 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1760 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1761 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1762 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1763 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1764 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1765
1766 /* Common functions */
1767 /* AGP */
1768 extern int radeon_gpu_reset(struct radeon_device *rdev);
1769 extern void radeon_agp_disable(struct radeon_device *rdev);
1770 extern int radeon_modeset_init(struct radeon_device *rdev);
1771 extern void radeon_modeset_fini(struct radeon_device *rdev);
1772 extern bool radeon_card_posted(struct radeon_device *rdev);
1773 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1774 extern void radeon_update_display_priority(struct radeon_device *rdev);
1775 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1776 extern void radeon_scratch_init(struct radeon_device *rdev);
1777 extern void radeon_wb_fini(struct radeon_device *rdev);
1778 extern int radeon_wb_init(struct radeon_device *rdev);
1779 extern void radeon_wb_disable(struct radeon_device *rdev);
1780 extern void radeon_surface_init(struct radeon_device *rdev);
1781 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1782 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1783 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1784 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1785 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1786 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1787 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1788 extern int radeon_resume_kms(struct drm_device *dev);
1789 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1790 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1791
1792 /*
1793 * vm
1794 */
1795 int radeon_vm_manager_init(struct radeon_device *rdev);
1796 void radeon_vm_manager_fini(struct radeon_device *rdev);
1797 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1798 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1799 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1800 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1801 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1802 struct radeon_vm *vm,
1803 struct radeon_bo *bo,
1804 struct ttm_mem_reg *mem);
1805 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1806 struct radeon_bo *bo);
1807 int radeon_vm_bo_add(struct radeon_device *rdev,
1808 struct radeon_vm *vm,
1809 struct radeon_bo *bo,
1810 uint64_t offset,
1811 uint32_t flags);
1812 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1813 struct radeon_vm *vm,
1814 struct radeon_bo *bo);
1815
1816 /* audio */
1817 void r600_audio_update_hdmi(struct work_struct *work);
1818
1819 /*
1820 * R600 vram scratch functions
1821 */
1822 int r600_vram_scratch_init(struct radeon_device *rdev);
1823 void r600_vram_scratch_fini(struct radeon_device *rdev);
1824
1825 /*
1826 * r600 cs checking helper
1827 */
1828 unsigned r600_mip_minify(unsigned size, unsigned level);
1829 bool r600_fmt_is_valid_color(u32 format);
1830 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1831 int r600_fmt_get_blocksize(u32 format);
1832 int r600_fmt_get_nblocksx(u32 format, u32 w);
1833 int r600_fmt_get_nblocksy(u32 format, u32 h);
1834
1835 /*
1836 * r600 functions used by radeon_encoder.c
1837 */
1838 struct radeon_hdmi_acr {
1839 u32 clock;
1840
1841 int n_32khz;
1842 int cts_32khz;
1843
1844 int n_44_1khz;
1845 int cts_44_1khz;
1846
1847 int n_48khz;
1848 int cts_48khz;
1849
1850 };
1851
1852 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1853
1854 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1855 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1856 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1857 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1858 u32 tiling_pipe_num,
1859 u32 max_rb_num,
1860 u32 total_max_rb_num,
1861 u32 enabled_rb_mask);
1862
1863 /*
1864 * evergreen functions used by radeon_encoder.c
1865 */
1866
1867 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1868
1869 extern int ni_init_microcode(struct radeon_device *rdev);
1870 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1871
1872 /* radeon_acpi.c */
1873 #if defined(CONFIG_ACPI)
1874 extern int radeon_acpi_init(struct radeon_device *rdev);
1875 extern void radeon_acpi_fini(struct radeon_device *rdev);
1876 #else
1877 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1878 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1879 #endif
1880
1881 #include "radeon_object.h"
1882
1883 #endif
Linux kernel - Deliverables
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