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drm/radeon: use common fence implementation for fences, v4
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
70
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
76
77 #include "radeon_family.h"
78 #include "radeon_mode.h"
79 #include "radeon_reg.h"
80
81 /*
82 * Modules parameters.
83 */
84 extern int radeon_no_wb;
85 extern int radeon_modeset;
86 extern int radeon_dynclks;
87 extern int radeon_r4xx_atom;
88 extern int radeon_agpmode;
89 extern int radeon_vram_limit;
90 extern int radeon_gart_size;
91 extern int radeon_benchmarking;
92 extern int radeon_testing;
93 extern int radeon_connector_table;
94 extern int radeon_tv;
95 extern int radeon_audio;
96 extern int radeon_disp_priority;
97 extern int radeon_hw_i2c;
98 extern int radeon_pcie_gen2;
99 extern int radeon_msi;
100 extern int radeon_lockup_timeout;
101 extern int radeon_fastfb;
102 extern int radeon_dpm;
103 extern int radeon_aspm;
104 extern int radeon_runtime_pm;
105 extern int radeon_hard_reset;
106 extern int radeon_vm_size;
107 extern int radeon_vm_block_size;
108 extern int radeon_deep_color;
109 extern int radeon_use_pflipirq;
110 extern int radeon_bapm;
111
112 /*
113 * Copy from radeon_drv.h so we don't have to include both and have conflicting
114 * symbol;
115 */
116 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
117 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
118 /* RADEON_IB_POOL_SIZE must be a power of 2 */
119 #define RADEON_IB_POOL_SIZE 16
120 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
121 #define RADEONFB_CONN_LIMIT 4
122 #define RADEON_BIOS_NUM_SCRATCH 8
123
124 /* internal ring indices */
125 /* r1xx+ has gfx CP ring */
126 #define RADEON_RING_TYPE_GFX_INDEX 0
127
128 /* cayman has 2 compute CP rings */
129 #define CAYMAN_RING_TYPE_CP1_INDEX 1
130 #define CAYMAN_RING_TYPE_CP2_INDEX 2
131
132 /* R600+ has an async dma ring */
133 #define R600_RING_TYPE_DMA_INDEX 3
134 /* cayman add a second async dma ring */
135 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
136
137 /* R600+ */
138 #define R600_RING_TYPE_UVD_INDEX 5
139
140 /* TN+ */
141 #define TN_RING_TYPE_VCE1_INDEX 6
142 #define TN_RING_TYPE_VCE2_INDEX 7
143
144 /* max number of rings */
145 #define RADEON_NUM_RINGS 8
146
147 /* number of hw syncs before falling back on blocking */
148 #define RADEON_NUM_SYNCS 4
149
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
152
153 /* hardcode those limit for now */
154 #define RADEON_VA_IB_OFFSET (1 << 20)
155 #define RADEON_VA_RESERVED_SIZE (8 << 20)
156 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
157
158 /* hard reset data */
159 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
160
161 /* reset flags */
162 #define RADEON_RESET_GFX (1 << 0)
163 #define RADEON_RESET_COMPUTE (1 << 1)
164 #define RADEON_RESET_DMA (1 << 2)
165 #define RADEON_RESET_CP (1 << 3)
166 #define RADEON_RESET_GRBM (1 << 4)
167 #define RADEON_RESET_DMA1 (1 << 5)
168 #define RADEON_RESET_RLC (1 << 6)
169 #define RADEON_RESET_SEM (1 << 7)
170 #define RADEON_RESET_IH (1 << 8)
171 #define RADEON_RESET_VMC (1 << 9)
172 #define RADEON_RESET_MC (1 << 10)
173 #define RADEON_RESET_DISPLAY (1 << 11)
174
175 /* CG block flags */
176 #define RADEON_CG_BLOCK_GFX (1 << 0)
177 #define RADEON_CG_BLOCK_MC (1 << 1)
178 #define RADEON_CG_BLOCK_SDMA (1 << 2)
179 #define RADEON_CG_BLOCK_UVD (1 << 3)
180 #define RADEON_CG_BLOCK_VCE (1 << 4)
181 #define RADEON_CG_BLOCK_HDP (1 << 5)
182 #define RADEON_CG_BLOCK_BIF (1 << 6)
183
184 /* CG flags */
185 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
186 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
187 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
188 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
189 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
190 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
191 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
192 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
193 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
194 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
195 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
196 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
197 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
198 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
199 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
200 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
201 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
202
203 /* PG flags */
204 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
205 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
206 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
207 #define RADEON_PG_SUPPORT_UVD (1 << 3)
208 #define RADEON_PG_SUPPORT_VCE (1 << 4)
209 #define RADEON_PG_SUPPORT_CP (1 << 5)
210 #define RADEON_PG_SUPPORT_GDS (1 << 6)
211 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
212 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
213 #define RADEON_PG_SUPPORT_ACP (1 << 9)
214 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
215
216 /* max cursor sizes (in pixels) */
217 #define CURSOR_WIDTH 64
218 #define CURSOR_HEIGHT 64
219
220 #define CIK_CURSOR_WIDTH 128
221 #define CIK_CURSOR_HEIGHT 128
222
223 /*
224 * Errata workarounds.
225 */
226 enum radeon_pll_errata {
227 CHIP_ERRATA_R300_CG = 0x00000001,
228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
229 CHIP_ERRATA_PLL_DELAY = 0x00000004
230 };
231
232
233 struct radeon_device;
234
235
236 /*
237 * BIOS.
238 */
239 bool radeon_get_bios(struct radeon_device *rdev);
240
241 /*
242 * Dummy page
243 */
244 struct radeon_dummy_page {
245 struct page *page;
246 dma_addr_t addr;
247 };
248 int radeon_dummy_page_init(struct radeon_device *rdev);
249 void radeon_dummy_page_fini(struct radeon_device *rdev);
250
251
252 /*
253 * Clocks
254 */
255 struct radeon_clock {
256 struct radeon_pll p1pll;
257 struct radeon_pll p2pll;
258 struct radeon_pll dcpll;
259 struct radeon_pll spll;
260 struct radeon_pll mpll;
261 /* 10 Khz units */
262 uint32_t default_mclk;
263 uint32_t default_sclk;
264 uint32_t default_dispclk;
265 uint32_t current_dispclk;
266 uint32_t dp_extclk;
267 uint32_t max_pixel_clock;
268 };
269
270 /*
271 * Power management
272 */
273 int radeon_pm_init(struct radeon_device *rdev);
274 int radeon_pm_late_init(struct radeon_device *rdev);
275 void radeon_pm_fini(struct radeon_device *rdev);
276 void radeon_pm_compute_clocks(struct radeon_device *rdev);
277 void radeon_pm_suspend(struct radeon_device *rdev);
278 void radeon_pm_resume(struct radeon_device *rdev);
279 void radeon_combios_get_power_modes(struct radeon_device *rdev);
280 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
281 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
282 u8 clock_type,
283 u32 clock,
284 bool strobe_mode,
285 struct atom_clock_dividers *dividers);
286 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
287 u32 clock,
288 bool strobe_mode,
289 struct atom_mpll_param *mpll_param);
290 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
291 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
292 u16 voltage_level, u8 voltage_type,
293 u32 *gpio_value, u32 *gpio_mask);
294 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
295 u32 eng_clock, u32 mem_clock);
296 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
297 u8 voltage_type, u16 *voltage_step);
298 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
299 u16 voltage_id, u16 *voltage);
300 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
301 u16 *voltage,
302 u16 leakage_idx);
303 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
304 u16 *leakage_id);
305 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
306 u16 *vddc, u16 *vddci,
307 u16 virtual_voltage_id,
308 u16 vbios_voltage_id);
309 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
310 u16 virtual_voltage_id,
311 u16 *voltage);
312 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
313 u8 voltage_type,
314 u16 nominal_voltage,
315 u16 *true_voltage);
316 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
317 u8 voltage_type, u16 *min_voltage);
318 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *max_voltage);
320 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
321 u8 voltage_type, u8 voltage_mode,
322 struct atom_voltage_table *voltage_table);
323 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode);
325 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
326 u8 voltage_type,
327 u8 *svd_gpio_id, u8 *svc_gpio_id);
328 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
329 u32 mem_clock);
330 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
331 u32 mem_clock);
332 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
333 u8 module_index,
334 struct atom_mc_reg_table *reg_table);
335 int radeon_atom_get_memory_info(struct radeon_device *rdev,
336 u8 module_index, struct atom_memory_info *mem_info);
337 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
338 bool gddr5, u8 module_index,
339 struct atom_memory_clock_range_table *mclk_range_table);
340 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
341 u16 voltage_id, u16 *voltage);
342 void rs690_pm_info(struct radeon_device *rdev);
343 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 unsigned *bankh, unsigned *mtaspect,
345 unsigned *tile_split);
346
347 /*
348 * Fences.
349 */
350 struct radeon_fence_driver {
351 struct radeon_device *rdev;
352 uint32_t scratch_reg;
353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
357 atomic64_t last_seq;
358 bool initialized, delayed_irq;
359 struct delayed_work lockup_work;
360 };
361
362 struct radeon_fence {
363 struct fence base;
364
365 struct radeon_device *rdev;
366 uint64_t seq;
367 /* RB, DMA, etc. */
368 unsigned ring;
369
370 wait_queue_t fence_wake;
371 };
372
373 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
374 int radeon_fence_driver_init(struct radeon_device *rdev);
375 void radeon_fence_driver_fini(struct radeon_device *rdev);
376 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
377 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
378 void radeon_fence_process(struct radeon_device *rdev, int ring);
379 bool radeon_fence_signaled(struct radeon_fence *fence);
380 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
381 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
382 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
383 int radeon_fence_wait_any(struct radeon_device *rdev,
384 struct radeon_fence **fences,
385 bool intr);
386 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
387 void radeon_fence_unref(struct radeon_fence **fence);
388 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
389 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
390 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
391 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
392 struct radeon_fence *b)
393 {
394 if (!a) {
395 return b;
396 }
397
398 if (!b) {
399 return a;
400 }
401
402 BUG_ON(a->ring != b->ring);
403
404 if (a->seq > b->seq) {
405 return a;
406 } else {
407 return b;
408 }
409 }
410
411 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
412 struct radeon_fence *b)
413 {
414 if (!a) {
415 return false;
416 }
417
418 if (!b) {
419 return true;
420 }
421
422 BUG_ON(a->ring != b->ring);
423
424 return a->seq < b->seq;
425 }
426
427 /*
428 * Tiling registers
429 */
430 struct radeon_surface_reg {
431 struct radeon_bo *bo;
432 };
433
434 #define RADEON_GEM_MAX_SURFACES 8
435
436 /*
437 * TTM.
438 */
439 struct radeon_mman {
440 struct ttm_bo_global_ref bo_global_ref;
441 struct drm_global_reference mem_global_ref;
442 struct ttm_bo_device bdev;
443 bool mem_global_referenced;
444 bool initialized;
445
446 #if defined(CONFIG_DEBUG_FS)
447 struct dentry *vram;
448 struct dentry *gtt;
449 #endif
450 };
451
452 /* bo virtual address in a specific vm */
453 struct radeon_bo_va {
454 /* protected by bo being reserved */
455 struct list_head bo_list;
456 uint32_t flags;
457 uint64_t addr;
458 unsigned ref_count;
459
460 /* protected by vm mutex */
461 struct interval_tree_node it;
462 struct list_head vm_status;
463
464 /* constant after initialization */
465 struct radeon_vm *vm;
466 struct radeon_bo *bo;
467 };
468
469 struct radeon_bo {
470 /* Protected by gem.mutex */
471 struct list_head list;
472 /* Protected by tbo.reserved */
473 u32 initial_domain;
474 struct ttm_place placements[3];
475 struct ttm_placement placement;
476 struct ttm_buffer_object tbo;
477 struct ttm_bo_kmap_obj kmap;
478 u32 flags;
479 unsigned pin_count;
480 void *kptr;
481 u32 tiling_flags;
482 u32 pitch;
483 int surface_reg;
484 /* list of all virtual address to which this bo
485 * is associated to
486 */
487 struct list_head va;
488 /* Constant after initialization */
489 struct radeon_device *rdev;
490 struct drm_gem_object gem_base;
491
492 struct ttm_bo_kmap_obj dma_buf_vmap;
493 pid_t pid;
494
495 struct radeon_mn *mn;
496 struct interval_tree_node mn_it;
497 };
498 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
499
500 int radeon_gem_debugfs_init(struct radeon_device *rdev);
501
502 /* sub-allocation manager, it has to be protected by another lock.
503 * By conception this is an helper for other part of the driver
504 * like the indirect buffer or semaphore, which both have their
505 * locking.
506 *
507 * Principe is simple, we keep a list of sub allocation in offset
508 * order (first entry has offset == 0, last entry has the highest
509 * offset).
510 *
511 * When allocating new object we first check if there is room at
512 * the end total_size - (last_object_offset + last_object_size) >=
513 * alloc_size. If so we allocate new object there.
514 *
515 * When there is not enough room at the end, we start waiting for
516 * each sub object until we reach object_offset+object_size >=
517 * alloc_size, this object then become the sub object we return.
518 *
519 * Alignment can't be bigger than page size.
520 *
521 * Hole are not considered for allocation to keep things simple.
522 * Assumption is that there won't be hole (all object on same
523 * alignment).
524 */
525 struct radeon_sa_manager {
526 wait_queue_head_t wq;
527 struct radeon_bo *bo;
528 struct list_head *hole;
529 struct list_head flist[RADEON_NUM_RINGS];
530 struct list_head olist;
531 unsigned size;
532 uint64_t gpu_addr;
533 void *cpu_ptr;
534 uint32_t domain;
535 uint32_t align;
536 };
537
538 struct radeon_sa_bo;
539
540 /* sub-allocation buffer */
541 struct radeon_sa_bo {
542 struct list_head olist;
543 struct list_head flist;
544 struct radeon_sa_manager *manager;
545 unsigned soffset;
546 unsigned eoffset;
547 struct radeon_fence *fence;
548 };
549
550 /*
551 * GEM objects.
552 */
553 struct radeon_gem {
554 struct mutex mutex;
555 struct list_head objects;
556 };
557
558 int radeon_gem_init(struct radeon_device *rdev);
559 void radeon_gem_fini(struct radeon_device *rdev);
560 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
561 int alignment, int initial_domain,
562 u32 flags, bool kernel,
563 struct drm_gem_object **obj);
564
565 int radeon_mode_dumb_create(struct drm_file *file_priv,
566 struct drm_device *dev,
567 struct drm_mode_create_dumb *args);
568 int radeon_mode_dumb_mmap(struct drm_file *filp,
569 struct drm_device *dev,
570 uint32_t handle, uint64_t *offset_p);
571
572 /*
573 * Semaphores.
574 */
575 struct radeon_semaphore {
576 struct radeon_sa_bo *sa_bo;
577 signed waiters;
578 uint64_t gpu_addr;
579 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
580 };
581
582 int radeon_semaphore_create(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore);
584 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
585 struct radeon_semaphore *semaphore);
586 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
587 struct radeon_semaphore *semaphore);
588 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
589 struct radeon_fence *fence);
590 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
591 struct radeon_semaphore *semaphore,
592 int waiting_ring);
593 void radeon_semaphore_free(struct radeon_device *rdev,
594 struct radeon_semaphore **semaphore,
595 struct radeon_fence *fence);
596
597 /*
598 * GART structures, functions & helpers
599 */
600 struct radeon_mc;
601
602 #define RADEON_GPU_PAGE_SIZE 4096
603 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
604 #define RADEON_GPU_PAGE_SHIFT 12
605 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
606
607 #define RADEON_GART_PAGE_DUMMY 0
608 #define RADEON_GART_PAGE_VALID (1 << 0)
609 #define RADEON_GART_PAGE_READ (1 << 1)
610 #define RADEON_GART_PAGE_WRITE (1 << 2)
611 #define RADEON_GART_PAGE_SNOOP (1 << 3)
612
613 struct radeon_gart {
614 dma_addr_t table_addr;
615 struct radeon_bo *robj;
616 void *ptr;
617 unsigned num_gpu_pages;
618 unsigned num_cpu_pages;
619 unsigned table_size;
620 struct page **pages;
621 dma_addr_t *pages_addr;
622 bool ready;
623 };
624
625 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
626 void radeon_gart_table_ram_free(struct radeon_device *rdev);
627 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
628 void radeon_gart_table_vram_free(struct radeon_device *rdev);
629 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
630 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
631 int radeon_gart_init(struct radeon_device *rdev);
632 void radeon_gart_fini(struct radeon_device *rdev);
633 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
634 int pages);
635 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
636 int pages, struct page **pagelist,
637 dma_addr_t *dma_addr, uint32_t flags);
638
639
640 /*
641 * GPU MC structures, functions & helpers
642 */
643 struct radeon_mc {
644 resource_size_t aper_size;
645 resource_size_t aper_base;
646 resource_size_t agp_base;
647 /* for some chips with <= 32MB we need to lie
648 * about vram size near mc fb location */
649 u64 mc_vram_size;
650 u64 visible_vram_size;
651 u64 gtt_size;
652 u64 gtt_start;
653 u64 gtt_end;
654 u64 vram_start;
655 u64 vram_end;
656 unsigned vram_width;
657 u64 real_vram_size;
658 int vram_mtrr;
659 bool vram_is_ddr;
660 bool igp_sideport_enabled;
661 u64 gtt_base_align;
662 u64 mc_mask;
663 };
664
665 bool radeon_combios_sideport_present(struct radeon_device *rdev);
666 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
667
668 /*
669 * GPU scratch registers structures, functions & helpers
670 */
671 struct radeon_scratch {
672 unsigned num_reg;
673 uint32_t reg_base;
674 bool free[32];
675 uint32_t reg[32];
676 };
677
678 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
679 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
680
681 /*
682 * GPU doorbell structures, functions & helpers
683 */
684 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
685
686 struct radeon_doorbell {
687 /* doorbell mmio */
688 resource_size_t base;
689 resource_size_t size;
690 u32 __iomem *ptr;
691 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
692 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
693 };
694
695 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
696 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
697
698 /*
699 * IRQS.
700 */
701
702 struct radeon_flip_work {
703 struct work_struct flip_work;
704 struct work_struct unpin_work;
705 struct radeon_device *rdev;
706 int crtc_id;
707 uint64_t base;
708 struct drm_pending_vblank_event *event;
709 struct radeon_bo *old_rbo;
710 struct radeon_fence *fence;
711 };
712
713 struct r500_irq_stat_regs {
714 u32 disp_int;
715 u32 hdmi0_status;
716 };
717
718 struct r600_irq_stat_regs {
719 u32 disp_int;
720 u32 disp_int_cont;
721 u32 disp_int_cont2;
722 u32 d1grph_int;
723 u32 d2grph_int;
724 u32 hdmi0_status;
725 u32 hdmi1_status;
726 };
727
728 struct evergreen_irq_stat_regs {
729 u32 disp_int;
730 u32 disp_int_cont;
731 u32 disp_int_cont2;
732 u32 disp_int_cont3;
733 u32 disp_int_cont4;
734 u32 disp_int_cont5;
735 u32 d1grph_int;
736 u32 d2grph_int;
737 u32 d3grph_int;
738 u32 d4grph_int;
739 u32 d5grph_int;
740 u32 d6grph_int;
741 u32 afmt_status1;
742 u32 afmt_status2;
743 u32 afmt_status3;
744 u32 afmt_status4;
745 u32 afmt_status5;
746 u32 afmt_status6;
747 };
748
749 struct cik_irq_stat_regs {
750 u32 disp_int;
751 u32 disp_int_cont;
752 u32 disp_int_cont2;
753 u32 disp_int_cont3;
754 u32 disp_int_cont4;
755 u32 disp_int_cont5;
756 u32 disp_int_cont6;
757 u32 d1grph_int;
758 u32 d2grph_int;
759 u32 d3grph_int;
760 u32 d4grph_int;
761 u32 d5grph_int;
762 u32 d6grph_int;
763 };
764
765 union radeon_irq_stat_regs {
766 struct r500_irq_stat_regs r500;
767 struct r600_irq_stat_regs r600;
768 struct evergreen_irq_stat_regs evergreen;
769 struct cik_irq_stat_regs cik;
770 };
771
772 struct radeon_irq {
773 bool installed;
774 spinlock_t lock;
775 atomic_t ring_int[RADEON_NUM_RINGS];
776 bool crtc_vblank_int[RADEON_MAX_CRTCS];
777 atomic_t pflip[RADEON_MAX_CRTCS];
778 wait_queue_head_t vblank_queue;
779 bool hpd[RADEON_MAX_HPD_PINS];
780 bool afmt[RADEON_MAX_AFMT_BLOCKS];
781 union radeon_irq_stat_regs stat_regs;
782 bool dpm_thermal;
783 };
784
785 int radeon_irq_kms_init(struct radeon_device *rdev);
786 void radeon_irq_kms_fini(struct radeon_device *rdev);
787 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
788 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
789 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
790 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
791 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
792 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
793 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
794 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
795 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
796
797 /*
798 * CP & rings.
799 */
800
801 struct radeon_ib {
802 struct radeon_sa_bo *sa_bo;
803 uint32_t length_dw;
804 uint64_t gpu_addr;
805 uint32_t *ptr;
806 int ring;
807 struct radeon_fence *fence;
808 struct radeon_vm *vm;
809 bool is_const_ib;
810 struct radeon_semaphore *semaphore;
811 };
812
813 struct radeon_ring {
814 struct radeon_bo *ring_obj;
815 volatile uint32_t *ring;
816 unsigned rptr_offs;
817 unsigned rptr_save_reg;
818 u64 next_rptr_gpu_addr;
819 volatile u32 *next_rptr_cpu_addr;
820 unsigned wptr;
821 unsigned wptr_old;
822 unsigned ring_size;
823 unsigned ring_free_dw;
824 int count_dw;
825 atomic_t last_rptr;
826 atomic64_t last_activity;
827 uint64_t gpu_addr;
828 uint32_t align_mask;
829 uint32_t ptr_mask;
830 bool ready;
831 u32 nop;
832 u32 idx;
833 u64 last_semaphore_signal_addr;
834 u64 last_semaphore_wait_addr;
835 /* for CIK queues */
836 u32 me;
837 u32 pipe;
838 u32 queue;
839 struct radeon_bo *mqd_obj;
840 u32 doorbell_index;
841 unsigned wptr_offs;
842 };
843
844 struct radeon_mec {
845 struct radeon_bo *hpd_eop_obj;
846 u64 hpd_eop_gpu_addr;
847 u32 num_pipe;
848 u32 num_mec;
849 u32 num_queue;
850 };
851
852 /*
853 * VM
854 */
855
856 /* maximum number of VMIDs */
857 #define RADEON_NUM_VM 16
858
859 /* number of entries in page table */
860 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
861
862 /* PTBs (Page Table Blocks) need to be aligned to 32K */
863 #define RADEON_VM_PTB_ALIGN_SIZE 32768
864 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
865 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
866
867 #define R600_PTE_VALID (1 << 0)
868 #define R600_PTE_SYSTEM (1 << 1)
869 #define R600_PTE_SNOOPED (1 << 2)
870 #define R600_PTE_READABLE (1 << 5)
871 #define R600_PTE_WRITEABLE (1 << 6)
872
873 /* PTE (Page Table Entry) fragment field for different page sizes */
874 #define R600_PTE_FRAG_4KB (0 << 7)
875 #define R600_PTE_FRAG_64KB (4 << 7)
876 #define R600_PTE_FRAG_256KB (6 << 7)
877
878 /* flags needed to be set so we can copy directly from the GART table */
879 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
880 R600_PTE_SYSTEM | R600_PTE_VALID )
881
882 struct radeon_vm_pt {
883 struct radeon_bo *bo;
884 uint64_t addr;
885 };
886
887 struct radeon_vm {
888 struct rb_root va;
889 unsigned id;
890
891 /* BOs moved, but not yet updated in the PT */
892 struct list_head invalidated;
893
894 /* BOs freed, but not yet updated in the PT */
895 struct list_head freed;
896
897 /* contains the page directory */
898 struct radeon_bo *page_directory;
899 uint64_t pd_gpu_addr;
900 unsigned max_pde_used;
901
902 /* array of page tables, one for each page directory entry */
903 struct radeon_vm_pt *page_tables;
904
905 struct radeon_bo_va *ib_bo_va;
906
907 struct mutex mutex;
908 /* last fence for cs using this vm */
909 struct radeon_fence *fence;
910 /* last flush or NULL if we still need to flush */
911 struct radeon_fence *last_flush;
912 /* last use of vmid */
913 struct radeon_fence *last_id_use;
914 };
915
916 struct radeon_vm_manager {
917 struct radeon_fence *active[RADEON_NUM_VM];
918 uint32_t max_pfn;
919 /* number of VMIDs */
920 unsigned nvm;
921 /* vram base address for page table entry */
922 u64 vram_base_offset;
923 /* is vm enabled? */
924 bool enabled;
925 };
926
927 /*
928 * file private structure
929 */
930 struct radeon_fpriv {
931 struct radeon_vm vm;
932 };
933
934 /*
935 * R6xx+ IH ring
936 */
937 struct r600_ih {
938 struct radeon_bo *ring_obj;
939 volatile uint32_t *ring;
940 unsigned rptr;
941 unsigned ring_size;
942 uint64_t gpu_addr;
943 uint32_t ptr_mask;
944 atomic_t lock;
945 bool enabled;
946 };
947
948 /*
949 * RLC stuff
950 */
951 #include "clearstate_defs.h"
952
953 struct radeon_rlc {
954 /* for power gating */
955 struct radeon_bo *save_restore_obj;
956 uint64_t save_restore_gpu_addr;
957 volatile uint32_t *sr_ptr;
958 const u32 *reg_list;
959 u32 reg_list_size;
960 /* for clear state */
961 struct radeon_bo *clear_state_obj;
962 uint64_t clear_state_gpu_addr;
963 volatile uint32_t *cs_ptr;
964 const struct cs_section_def *cs_data;
965 u32 clear_state_size;
966 /* for cp tables */
967 struct radeon_bo *cp_table_obj;
968 uint64_t cp_table_gpu_addr;
969 volatile uint32_t *cp_table_ptr;
970 u32 cp_table_size;
971 };
972
973 int radeon_ib_get(struct radeon_device *rdev, int ring,
974 struct radeon_ib *ib, struct radeon_vm *vm,
975 unsigned size);
976 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
977 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
978 struct radeon_ib *const_ib, bool hdp_flush);
979 int radeon_ib_pool_init(struct radeon_device *rdev);
980 void radeon_ib_pool_fini(struct radeon_device *rdev);
981 int radeon_ib_ring_tests(struct radeon_device *rdev);
982 /* Ring access between begin & end cannot sleep */
983 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
984 struct radeon_ring *ring);
985 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
986 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
987 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
988 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
989 bool hdp_flush);
990 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
991 bool hdp_flush);
992 void radeon_ring_undo(struct radeon_ring *ring);
993 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
994 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
995 void radeon_ring_lockup_update(struct radeon_device *rdev,
996 struct radeon_ring *ring);
997 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
998 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
999 uint32_t **data);
1000 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1001 unsigned size, uint32_t *data);
1002 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1003 unsigned rptr_offs, u32 nop);
1004 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1005
1006
1007 /* r600 async dma */
1008 void r600_dma_stop(struct radeon_device *rdev);
1009 int r600_dma_resume(struct radeon_device *rdev);
1010 void r600_dma_fini(struct radeon_device *rdev);
1011
1012 void cayman_dma_stop(struct radeon_device *rdev);
1013 int cayman_dma_resume(struct radeon_device *rdev);
1014 void cayman_dma_fini(struct radeon_device *rdev);
1015
1016 /*
1017 * CS.
1018 */
1019 struct radeon_cs_reloc {
1020 struct drm_gem_object *gobj;
1021 struct radeon_bo *robj;
1022 struct ttm_validate_buffer tv;
1023 uint64_t gpu_offset;
1024 unsigned prefered_domains;
1025 unsigned allowed_domains;
1026 uint32_t tiling_flags;
1027 uint32_t handle;
1028 };
1029
1030 struct radeon_cs_chunk {
1031 uint32_t chunk_id;
1032 uint32_t length_dw;
1033 uint32_t *kdata;
1034 void __user *user_ptr;
1035 };
1036
1037 struct radeon_cs_parser {
1038 struct device *dev;
1039 struct radeon_device *rdev;
1040 struct drm_file *filp;
1041 /* chunks */
1042 unsigned nchunks;
1043 struct radeon_cs_chunk *chunks;
1044 uint64_t *chunks_array;
1045 /* IB */
1046 unsigned idx;
1047 /* relocations */
1048 unsigned nrelocs;
1049 struct radeon_cs_reloc *relocs;
1050 struct radeon_cs_reloc **relocs_ptr;
1051 struct radeon_cs_reloc *vm_bos;
1052 struct list_head validated;
1053 unsigned dma_reloc_idx;
1054 /* indices of various chunks */
1055 int chunk_ib_idx;
1056 int chunk_relocs_idx;
1057 int chunk_flags_idx;
1058 int chunk_const_ib_idx;
1059 struct radeon_ib ib;
1060 struct radeon_ib const_ib;
1061 void *track;
1062 unsigned family;
1063 int parser_error;
1064 u32 cs_flags;
1065 u32 ring;
1066 s32 priority;
1067 struct ww_acquire_ctx ticket;
1068 };
1069
1070 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1071 {
1072 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1073
1074 if (ibc->kdata)
1075 return ibc->kdata[idx];
1076 return p->ib.ptr[idx];
1077 }
1078
1079
1080 struct radeon_cs_packet {
1081 unsigned idx;
1082 unsigned type;
1083 unsigned reg;
1084 unsigned opcode;
1085 int count;
1086 unsigned one_reg_wr;
1087 };
1088
1089 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1090 struct radeon_cs_packet *pkt,
1091 unsigned idx, unsigned reg);
1092 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1093 struct radeon_cs_packet *pkt);
1094
1095
1096 /*
1097 * AGP
1098 */
1099 int radeon_agp_init(struct radeon_device *rdev);
1100 void radeon_agp_resume(struct radeon_device *rdev);
1101 void radeon_agp_suspend(struct radeon_device *rdev);
1102 void radeon_agp_fini(struct radeon_device *rdev);
1103
1104
1105 /*
1106 * Writeback
1107 */
1108 struct radeon_wb {
1109 struct radeon_bo *wb_obj;
1110 volatile uint32_t *wb;
1111 uint64_t gpu_addr;
1112 bool enabled;
1113 bool use_event;
1114 };
1115
1116 #define RADEON_WB_SCRATCH_OFFSET 0
1117 #define RADEON_WB_RING0_NEXT_RPTR 256
1118 #define RADEON_WB_CP_RPTR_OFFSET 1024
1119 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1120 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1121 #define R600_WB_DMA_RPTR_OFFSET 1792
1122 #define R600_WB_IH_WPTR_OFFSET 2048
1123 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1124 #define R600_WB_EVENT_OFFSET 3072
1125 #define CIK_WB_CP1_WPTR_OFFSET 3328
1126 #define CIK_WB_CP2_WPTR_OFFSET 3584
1127
1128 /**
1129 * struct radeon_pm - power management datas
1130 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1131 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1132 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1133 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1134 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1135 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1136 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1137 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1138 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1139 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1140 * @needed_bandwidth: current bandwidth needs
1141 *
1142 * It keeps track of various data needed to take powermanagement decision.
1143 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1144 * Equation between gpu/memory clock and available bandwidth is hw dependent
1145 * (type of memory, bus size, efficiency, ...)
1146 */
1147
1148 enum radeon_pm_method {
1149 PM_METHOD_PROFILE,
1150 PM_METHOD_DYNPM,
1151 PM_METHOD_DPM,
1152 };
1153
1154 enum radeon_dynpm_state {
1155 DYNPM_STATE_DISABLED,
1156 DYNPM_STATE_MINIMUM,
1157 DYNPM_STATE_PAUSED,
1158 DYNPM_STATE_ACTIVE,
1159 DYNPM_STATE_SUSPENDED,
1160 };
1161 enum radeon_dynpm_action {
1162 DYNPM_ACTION_NONE,
1163 DYNPM_ACTION_MINIMUM,
1164 DYNPM_ACTION_DOWNCLOCK,
1165 DYNPM_ACTION_UPCLOCK,
1166 DYNPM_ACTION_DEFAULT
1167 };
1168
1169 enum radeon_voltage_type {
1170 VOLTAGE_NONE = 0,
1171 VOLTAGE_GPIO,
1172 VOLTAGE_VDDC,
1173 VOLTAGE_SW
1174 };
1175
1176 enum radeon_pm_state_type {
1177 /* not used for dpm */
1178 POWER_STATE_TYPE_DEFAULT,
1179 POWER_STATE_TYPE_POWERSAVE,
1180 /* user selectable states */
1181 POWER_STATE_TYPE_BATTERY,
1182 POWER_STATE_TYPE_BALANCED,
1183 POWER_STATE_TYPE_PERFORMANCE,
1184 /* internal states */
1185 POWER_STATE_TYPE_INTERNAL_UVD,
1186 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1187 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1188 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1189 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1190 POWER_STATE_TYPE_INTERNAL_BOOT,
1191 POWER_STATE_TYPE_INTERNAL_THERMAL,
1192 POWER_STATE_TYPE_INTERNAL_ACPI,
1193 POWER_STATE_TYPE_INTERNAL_ULV,
1194 POWER_STATE_TYPE_INTERNAL_3DPERF,
1195 };
1196
1197 enum radeon_pm_profile_type {
1198 PM_PROFILE_DEFAULT,
1199 PM_PROFILE_AUTO,
1200 PM_PROFILE_LOW,
1201 PM_PROFILE_MID,
1202 PM_PROFILE_HIGH,
1203 };
1204
1205 #define PM_PROFILE_DEFAULT_IDX 0
1206 #define PM_PROFILE_LOW_SH_IDX 1
1207 #define PM_PROFILE_MID_SH_IDX 2
1208 #define PM_PROFILE_HIGH_SH_IDX 3
1209 #define PM_PROFILE_LOW_MH_IDX 4
1210 #define PM_PROFILE_MID_MH_IDX 5
1211 #define PM_PROFILE_HIGH_MH_IDX 6
1212 #define PM_PROFILE_MAX 7
1213
1214 struct radeon_pm_profile {
1215 int dpms_off_ps_idx;
1216 int dpms_on_ps_idx;
1217 int dpms_off_cm_idx;
1218 int dpms_on_cm_idx;
1219 };
1220
1221 enum radeon_int_thermal_type {
1222 THERMAL_TYPE_NONE,
1223 THERMAL_TYPE_EXTERNAL,
1224 THERMAL_TYPE_EXTERNAL_GPIO,
1225 THERMAL_TYPE_RV6XX,
1226 THERMAL_TYPE_RV770,
1227 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1228 THERMAL_TYPE_EVERGREEN,
1229 THERMAL_TYPE_SUMO,
1230 THERMAL_TYPE_NI,
1231 THERMAL_TYPE_SI,
1232 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1233 THERMAL_TYPE_CI,
1234 THERMAL_TYPE_KV,
1235 };
1236
1237 struct radeon_voltage {
1238 enum radeon_voltage_type type;
1239 /* gpio voltage */
1240 struct radeon_gpio_rec gpio;
1241 u32 delay; /* delay in usec from voltage drop to sclk change */
1242 bool active_high; /* voltage drop is active when bit is high */
1243 /* VDDC voltage */
1244 u8 vddc_id; /* index into vddc voltage table */
1245 u8 vddci_id; /* index into vddci voltage table */
1246 bool vddci_enabled;
1247 /* r6xx+ sw */
1248 u16 voltage;
1249 /* evergreen+ vddci */
1250 u16 vddci;
1251 };
1252
1253 /* clock mode flags */
1254 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1255
1256 struct radeon_pm_clock_info {
1257 /* memory clock */
1258 u32 mclk;
1259 /* engine clock */
1260 u32 sclk;
1261 /* voltage info */
1262 struct radeon_voltage voltage;
1263 /* standardized clock flags */
1264 u32 flags;
1265 };
1266
1267 /* state flags */
1268 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1269
1270 struct radeon_power_state {
1271 enum radeon_pm_state_type type;
1272 struct radeon_pm_clock_info *clock_info;
1273 /* number of valid clock modes in this power state */
1274 int num_clock_modes;
1275 struct radeon_pm_clock_info *default_clock_mode;
1276 /* standardized state flags */
1277 u32 flags;
1278 u32 misc; /* vbios specific flags */
1279 u32 misc2; /* vbios specific flags */
1280 int pcie_lanes; /* pcie lanes */
1281 };
1282
1283 /*
1284 * Some modes are overclocked by very low value, accept them
1285 */
1286 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1287
1288 enum radeon_dpm_auto_throttle_src {
1289 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1290 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1291 };
1292
1293 enum radeon_dpm_event_src {
1294 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1295 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1296 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1297 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1298 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1299 };
1300
1301 #define RADEON_MAX_VCE_LEVELS 6
1302
1303 enum radeon_vce_level {
1304 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1305 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1306 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1307 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1308 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1309 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1310 };
1311
1312 struct radeon_ps {
1313 u32 caps; /* vbios flags */
1314 u32 class; /* vbios flags */
1315 u32 class2; /* vbios flags */
1316 /* UVD clocks */
1317 u32 vclk;
1318 u32 dclk;
1319 /* VCE clocks */
1320 u32 evclk;
1321 u32 ecclk;
1322 bool vce_active;
1323 enum radeon_vce_level vce_level;
1324 /* asic priv */
1325 void *ps_priv;
1326 };
1327
1328 struct radeon_dpm_thermal {
1329 /* thermal interrupt work */
1330 struct work_struct work;
1331 /* low temperature threshold */
1332 int min_temp;
1333 /* high temperature threshold */
1334 int max_temp;
1335 /* was interrupt low to high or high to low */
1336 bool high_to_low;
1337 };
1338
1339 enum radeon_clk_action
1340 {
1341 RADEON_SCLK_UP = 1,
1342 RADEON_SCLK_DOWN
1343 };
1344
1345 struct radeon_blacklist_clocks
1346 {
1347 u32 sclk;
1348 u32 mclk;
1349 enum radeon_clk_action action;
1350 };
1351
1352 struct radeon_clock_and_voltage_limits {
1353 u32 sclk;
1354 u32 mclk;
1355 u16 vddc;
1356 u16 vddci;
1357 };
1358
1359 struct radeon_clock_array {
1360 u32 count;
1361 u32 *values;
1362 };
1363
1364 struct radeon_clock_voltage_dependency_entry {
1365 u32 clk;
1366 u16 v;
1367 };
1368
1369 struct radeon_clock_voltage_dependency_table {
1370 u32 count;
1371 struct radeon_clock_voltage_dependency_entry *entries;
1372 };
1373
1374 union radeon_cac_leakage_entry {
1375 struct {
1376 u16 vddc;
1377 u32 leakage;
1378 };
1379 struct {
1380 u16 vddc1;
1381 u16 vddc2;
1382 u16 vddc3;
1383 };
1384 };
1385
1386 struct radeon_cac_leakage_table {
1387 u32 count;
1388 union radeon_cac_leakage_entry *entries;
1389 };
1390
1391 struct radeon_phase_shedding_limits_entry {
1392 u16 voltage;
1393 u32 sclk;
1394 u32 mclk;
1395 };
1396
1397 struct radeon_phase_shedding_limits_table {
1398 u32 count;
1399 struct radeon_phase_shedding_limits_entry *entries;
1400 };
1401
1402 struct radeon_uvd_clock_voltage_dependency_entry {
1403 u32 vclk;
1404 u32 dclk;
1405 u16 v;
1406 };
1407
1408 struct radeon_uvd_clock_voltage_dependency_table {
1409 u8 count;
1410 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1411 };
1412
1413 struct radeon_vce_clock_voltage_dependency_entry {
1414 u32 ecclk;
1415 u32 evclk;
1416 u16 v;
1417 };
1418
1419 struct radeon_vce_clock_voltage_dependency_table {
1420 u8 count;
1421 struct radeon_vce_clock_voltage_dependency_entry *entries;
1422 };
1423
1424 struct radeon_ppm_table {
1425 u8 ppm_design;
1426 u16 cpu_core_number;
1427 u32 platform_tdp;
1428 u32 small_ac_platform_tdp;
1429 u32 platform_tdc;
1430 u32 small_ac_platform_tdc;
1431 u32 apu_tdp;
1432 u32 dgpu_tdp;
1433 u32 dgpu_ulv_power;
1434 u32 tj_max;
1435 };
1436
1437 struct radeon_cac_tdp_table {
1438 u16 tdp;
1439 u16 configurable_tdp;
1440 u16 tdc;
1441 u16 battery_power_limit;
1442 u16 small_power_limit;
1443 u16 low_cac_leakage;
1444 u16 high_cac_leakage;
1445 u16 maximum_power_delivery_limit;
1446 };
1447
1448 struct radeon_dpm_dynamic_state {
1449 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1450 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1451 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1452 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1453 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1454 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1455 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1456 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1457 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1458 struct radeon_clock_array valid_sclk_values;
1459 struct radeon_clock_array valid_mclk_values;
1460 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1461 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1462 u32 mclk_sclk_ratio;
1463 u32 sclk_mclk_delta;
1464 u16 vddc_vddci_delta;
1465 u16 min_vddc_for_pcie_gen2;
1466 struct radeon_cac_leakage_table cac_leakage_table;
1467 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1468 struct radeon_ppm_table *ppm_table;
1469 struct radeon_cac_tdp_table *cac_tdp_table;
1470 };
1471
1472 struct radeon_dpm_fan {
1473 u16 t_min;
1474 u16 t_med;
1475 u16 t_high;
1476 u16 pwm_min;
1477 u16 pwm_med;
1478 u16 pwm_high;
1479 u8 t_hyst;
1480 u32 cycle_delay;
1481 u16 t_max;
1482 bool ucode_fan_control;
1483 };
1484
1485 enum radeon_pcie_gen {
1486 RADEON_PCIE_GEN1 = 0,
1487 RADEON_PCIE_GEN2 = 1,
1488 RADEON_PCIE_GEN3 = 2,
1489 RADEON_PCIE_GEN_INVALID = 0xffff
1490 };
1491
1492 enum radeon_dpm_forced_level {
1493 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1494 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1495 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1496 };
1497
1498 struct radeon_vce_state {
1499 /* vce clocks */
1500 u32 evclk;
1501 u32 ecclk;
1502 /* gpu clocks */
1503 u32 sclk;
1504 u32 mclk;
1505 u8 clk_idx;
1506 u8 pstate;
1507 };
1508
1509 struct radeon_dpm {
1510 struct radeon_ps *ps;
1511 /* number of valid power states */
1512 int num_ps;
1513 /* current power state that is active */
1514 struct radeon_ps *current_ps;
1515 /* requested power state */
1516 struct radeon_ps *requested_ps;
1517 /* boot up power state */
1518 struct radeon_ps *boot_ps;
1519 /* default uvd power state */
1520 struct radeon_ps *uvd_ps;
1521 /* vce requirements */
1522 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1523 enum radeon_vce_level vce_level;
1524 enum radeon_pm_state_type state;
1525 enum radeon_pm_state_type user_state;
1526 u32 platform_caps;
1527 u32 voltage_response_time;
1528 u32 backbias_response_time;
1529 void *priv;
1530 u32 new_active_crtcs;
1531 int new_active_crtc_count;
1532 u32 current_active_crtcs;
1533 int current_active_crtc_count;
1534 struct radeon_dpm_dynamic_state dyn_state;
1535 struct radeon_dpm_fan fan;
1536 u32 tdp_limit;
1537 u32 near_tdp_limit;
1538 u32 near_tdp_limit_adjusted;
1539 u32 sq_ramping_threshold;
1540 u32 cac_leakage;
1541 u16 tdp_od_limit;
1542 u32 tdp_adjustment;
1543 u16 load_line_slope;
1544 bool power_control;
1545 bool ac_power;
1546 /* special states active */
1547 bool thermal_active;
1548 bool uvd_active;
1549 bool vce_active;
1550 /* thermal handling */
1551 struct radeon_dpm_thermal thermal;
1552 /* forced levels */
1553 enum radeon_dpm_forced_level forced_level;
1554 /* track UVD streams */
1555 unsigned sd;
1556 unsigned hd;
1557 };
1558
1559 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1560 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1561
1562 struct radeon_pm {
1563 struct mutex mutex;
1564 /* write locked while reprogramming mclk */
1565 struct rw_semaphore mclk_lock;
1566 u32 active_crtcs;
1567 int active_crtc_count;
1568 int req_vblank;
1569 bool vblank_sync;
1570 fixed20_12 max_bandwidth;
1571 fixed20_12 igp_sideport_mclk;
1572 fixed20_12 igp_system_mclk;
1573 fixed20_12 igp_ht_link_clk;
1574 fixed20_12 igp_ht_link_width;
1575 fixed20_12 k8_bandwidth;
1576 fixed20_12 sideport_bandwidth;
1577 fixed20_12 ht_bandwidth;
1578 fixed20_12 core_bandwidth;
1579 fixed20_12 sclk;
1580 fixed20_12 mclk;
1581 fixed20_12 needed_bandwidth;
1582 struct radeon_power_state *power_state;
1583 /* number of valid power states */
1584 int num_power_states;
1585 int current_power_state_index;
1586 int current_clock_mode_index;
1587 int requested_power_state_index;
1588 int requested_clock_mode_index;
1589 int default_power_state_index;
1590 u32 current_sclk;
1591 u32 current_mclk;
1592 u16 current_vddc;
1593 u16 current_vddci;
1594 u32 default_sclk;
1595 u32 default_mclk;
1596 u16 default_vddc;
1597 u16 default_vddci;
1598 struct radeon_i2c_chan *i2c_bus;
1599 /* selected pm method */
1600 enum radeon_pm_method pm_method;
1601 /* dynpm power management */
1602 struct delayed_work dynpm_idle_work;
1603 enum radeon_dynpm_state dynpm_state;
1604 enum radeon_dynpm_action dynpm_planned_action;
1605 unsigned long dynpm_action_timeout;
1606 bool dynpm_can_upclock;
1607 bool dynpm_can_downclock;
1608 /* profile-based power management */
1609 enum radeon_pm_profile_type profile;
1610 int profile_index;
1611 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1612 /* internal thermal controller on rv6xx+ */
1613 enum radeon_int_thermal_type int_thermal_type;
1614 struct device *int_hwmon_dev;
1615 /* dpm */
1616 bool dpm_enabled;
1617 struct radeon_dpm dpm;
1618 };
1619
1620 int radeon_pm_get_type_index(struct radeon_device *rdev,
1621 enum radeon_pm_state_type ps_type,
1622 int instance);
1623 /*
1624 * UVD
1625 */
1626 #define RADEON_MAX_UVD_HANDLES 10
1627 #define RADEON_UVD_STACK_SIZE (1024*1024)
1628 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1629
1630 struct radeon_uvd {
1631 struct radeon_bo *vcpu_bo;
1632 void *cpu_addr;
1633 uint64_t gpu_addr;
1634 void *saved_bo;
1635 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1636 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1637 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1638 struct delayed_work idle_work;
1639 };
1640
1641 int radeon_uvd_init(struct radeon_device *rdev);
1642 void radeon_uvd_fini(struct radeon_device *rdev);
1643 int radeon_uvd_suspend(struct radeon_device *rdev);
1644 int radeon_uvd_resume(struct radeon_device *rdev);
1645 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1646 uint32_t handle, struct radeon_fence **fence);
1647 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1648 uint32_t handle, struct radeon_fence **fence);
1649 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1650 uint32_t allowed_domains);
1651 void radeon_uvd_free_handles(struct radeon_device *rdev,
1652 struct drm_file *filp);
1653 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1654 void radeon_uvd_note_usage(struct radeon_device *rdev);
1655 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1656 unsigned vclk, unsigned dclk,
1657 unsigned vco_min, unsigned vco_max,
1658 unsigned fb_factor, unsigned fb_mask,
1659 unsigned pd_min, unsigned pd_max,
1660 unsigned pd_even,
1661 unsigned *optimal_fb_div,
1662 unsigned *optimal_vclk_div,
1663 unsigned *optimal_dclk_div);
1664 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1665 unsigned cg_upll_func_cntl);
1666
1667 /*
1668 * VCE
1669 */
1670 #define RADEON_MAX_VCE_HANDLES 16
1671 #define RADEON_VCE_STACK_SIZE (1024*1024)
1672 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1673
1674 struct radeon_vce {
1675 struct radeon_bo *vcpu_bo;
1676 uint64_t gpu_addr;
1677 unsigned fw_version;
1678 unsigned fb_version;
1679 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1680 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1681 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1682 struct delayed_work idle_work;
1683 };
1684
1685 int radeon_vce_init(struct radeon_device *rdev);
1686 void radeon_vce_fini(struct radeon_device *rdev);
1687 int radeon_vce_suspend(struct radeon_device *rdev);
1688 int radeon_vce_resume(struct radeon_device *rdev);
1689 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1690 uint32_t handle, struct radeon_fence **fence);
1691 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1692 uint32_t handle, struct radeon_fence **fence);
1693 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1694 void radeon_vce_note_usage(struct radeon_device *rdev);
1695 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1696 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1697 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1698 struct radeon_ring *ring,
1699 struct radeon_semaphore *semaphore,
1700 bool emit_wait);
1701 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1702 void radeon_vce_fence_emit(struct radeon_device *rdev,
1703 struct radeon_fence *fence);
1704 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1705 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1706
1707 struct r600_audio_pin {
1708 int channels;
1709 int rate;
1710 int bits_per_sample;
1711 u8 status_bits;
1712 u8 category_code;
1713 u32 offset;
1714 bool connected;
1715 u32 id;
1716 };
1717
1718 struct r600_audio {
1719 bool enabled;
1720 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1721 int num_pins;
1722 };
1723
1724 /*
1725 * Benchmarking
1726 */
1727 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1728
1729
1730 /*
1731 * Testing
1732 */
1733 void radeon_test_moves(struct radeon_device *rdev);
1734 void radeon_test_ring_sync(struct radeon_device *rdev,
1735 struct radeon_ring *cpA,
1736 struct radeon_ring *cpB);
1737 void radeon_test_syncing(struct radeon_device *rdev);
1738
1739 /*
1740 * MMU Notifier
1741 */
1742 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1743 void radeon_mn_unregister(struct radeon_bo *bo);
1744
1745 /*
1746 * Debugfs
1747 */
1748 struct radeon_debugfs {
1749 struct drm_info_list *files;
1750 unsigned num_files;
1751 };
1752
1753 int radeon_debugfs_add_files(struct radeon_device *rdev,
1754 struct drm_info_list *files,
1755 unsigned nfiles);
1756 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1757
1758 /*
1759 * ASIC ring specific functions.
1760 */
1761 struct radeon_asic_ring {
1762 /* ring read/write ptr handling */
1763 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1764 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1765 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1766
1767 /* validating and patching of IBs */
1768 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1769 int (*cs_parse)(struct radeon_cs_parser *p);
1770
1771 /* command emmit functions */
1772 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1773 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1774 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1775 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1776 struct radeon_semaphore *semaphore, bool emit_wait);
1777 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1778
1779 /* testing functions */
1780 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1781 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1782 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1783
1784 /* deprecated */
1785 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1786 };
1787
1788 /*
1789 * ASIC specific functions.
1790 */
1791 struct radeon_asic {
1792 int (*init)(struct radeon_device *rdev);
1793 void (*fini)(struct radeon_device *rdev);
1794 int (*resume)(struct radeon_device *rdev);
1795 int (*suspend)(struct radeon_device *rdev);
1796 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1797 int (*asic_reset)(struct radeon_device *rdev);
1798 /* Flush the HDP cache via MMIO */
1799 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1800 /* check if 3D engine is idle */
1801 bool (*gui_idle)(struct radeon_device *rdev);
1802 /* wait for mc_idle */
1803 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1804 /* get the reference clock */
1805 u32 (*get_xclk)(struct radeon_device *rdev);
1806 /* get the gpu clock counter */
1807 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1808 /* gart */
1809 struct {
1810 void (*tlb_flush)(struct radeon_device *rdev);
1811 void (*set_page)(struct radeon_device *rdev, unsigned i,
1812 uint64_t addr, uint32_t flags);
1813 } gart;
1814 struct {
1815 int (*init)(struct radeon_device *rdev);
1816 void (*fini)(struct radeon_device *rdev);
1817 void (*copy_pages)(struct radeon_device *rdev,
1818 struct radeon_ib *ib,
1819 uint64_t pe, uint64_t src,
1820 unsigned count);
1821 void (*write_pages)(struct radeon_device *rdev,
1822 struct radeon_ib *ib,
1823 uint64_t pe,
1824 uint64_t addr, unsigned count,
1825 uint32_t incr, uint32_t flags);
1826 void (*set_pages)(struct radeon_device *rdev,
1827 struct radeon_ib *ib,
1828 uint64_t pe,
1829 uint64_t addr, unsigned count,
1830 uint32_t incr, uint32_t flags);
1831 void (*pad_ib)(struct radeon_ib *ib);
1832 } vm;
1833 /* ring specific callbacks */
1834 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1835 /* irqs */
1836 struct {
1837 int (*set)(struct radeon_device *rdev);
1838 int (*process)(struct radeon_device *rdev);
1839 } irq;
1840 /* displays */
1841 struct {
1842 /* display watermarks */
1843 void (*bandwidth_update)(struct radeon_device *rdev);
1844 /* get frame count */
1845 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1846 /* wait for vblank */
1847 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1848 /* set backlight level */
1849 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1850 /* get backlight level */
1851 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1852 /* audio callbacks */
1853 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1854 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1855 } display;
1856 /* copy functions for bo handling */
1857 struct {
1858 int (*blit)(struct radeon_device *rdev,
1859 uint64_t src_offset,
1860 uint64_t dst_offset,
1861 unsigned num_gpu_pages,
1862 struct radeon_fence **fence);
1863 u32 blit_ring_index;
1864 int (*dma)(struct radeon_device *rdev,
1865 uint64_t src_offset,
1866 uint64_t dst_offset,
1867 unsigned num_gpu_pages,
1868 struct radeon_fence **fence);
1869 u32 dma_ring_index;
1870 /* method used for bo copy */
1871 int (*copy)(struct radeon_device *rdev,
1872 uint64_t src_offset,
1873 uint64_t dst_offset,
1874 unsigned num_gpu_pages,
1875 struct radeon_fence **fence);
1876 /* ring used for bo copies */
1877 u32 copy_ring_index;
1878 } copy;
1879 /* surfaces */
1880 struct {
1881 int (*set_reg)(struct radeon_device *rdev, int reg,
1882 uint32_t tiling_flags, uint32_t pitch,
1883 uint32_t offset, uint32_t obj_size);
1884 void (*clear_reg)(struct radeon_device *rdev, int reg);
1885 } surface;
1886 /* hotplug detect */
1887 struct {
1888 void (*init)(struct radeon_device *rdev);
1889 void (*fini)(struct radeon_device *rdev);
1890 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1891 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1892 } hpd;
1893 /* static power management */
1894 struct {
1895 void (*misc)(struct radeon_device *rdev);
1896 void (*prepare)(struct radeon_device *rdev);
1897 void (*finish)(struct radeon_device *rdev);
1898 void (*init_profile)(struct radeon_device *rdev);
1899 void (*get_dynpm_state)(struct radeon_device *rdev);
1900 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1901 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1902 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1903 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1904 int (*get_pcie_lanes)(struct radeon_device *rdev);
1905 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1906 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1907 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1908 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1909 int (*get_temperature)(struct radeon_device *rdev);
1910 } pm;
1911 /* dynamic power management */
1912 struct {
1913 int (*init)(struct radeon_device *rdev);
1914 void (*setup_asic)(struct radeon_device *rdev);
1915 int (*enable)(struct radeon_device *rdev);
1916 int (*late_enable)(struct radeon_device *rdev);
1917 void (*disable)(struct radeon_device *rdev);
1918 int (*pre_set_power_state)(struct radeon_device *rdev);
1919 int (*set_power_state)(struct radeon_device *rdev);
1920 void (*post_set_power_state)(struct radeon_device *rdev);
1921 void (*display_configuration_changed)(struct radeon_device *rdev);
1922 void (*fini)(struct radeon_device *rdev);
1923 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1924 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1925 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1926 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1927 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1928 bool (*vblank_too_short)(struct radeon_device *rdev);
1929 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1930 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1931 } dpm;
1932 /* pageflipping */
1933 struct {
1934 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1935 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1936 } pflip;
1937 };
1938
1939 /*
1940 * Asic structures
1941 */
1942 struct r100_asic {
1943 const unsigned *reg_safe_bm;
1944 unsigned reg_safe_bm_size;
1945 u32 hdp_cntl;
1946 };
1947
1948 struct r300_asic {
1949 const unsigned *reg_safe_bm;
1950 unsigned reg_safe_bm_size;
1951 u32 resync_scratch;
1952 u32 hdp_cntl;
1953 };
1954
1955 struct r600_asic {
1956 unsigned max_pipes;
1957 unsigned max_tile_pipes;
1958 unsigned max_simds;
1959 unsigned max_backends;
1960 unsigned max_gprs;
1961 unsigned max_threads;
1962 unsigned max_stack_entries;
1963 unsigned max_hw_contexts;
1964 unsigned max_gs_threads;
1965 unsigned sx_max_export_size;
1966 unsigned sx_max_export_pos_size;
1967 unsigned sx_max_export_smx_size;
1968 unsigned sq_num_cf_insts;
1969 unsigned tiling_nbanks;
1970 unsigned tiling_npipes;
1971 unsigned tiling_group_size;
1972 unsigned tile_config;
1973 unsigned backend_map;
1974 unsigned active_simds;
1975 };
1976
1977 struct rv770_asic {
1978 unsigned max_pipes;
1979 unsigned max_tile_pipes;
1980 unsigned max_simds;
1981 unsigned max_backends;
1982 unsigned max_gprs;
1983 unsigned max_threads;
1984 unsigned max_stack_entries;
1985 unsigned max_hw_contexts;
1986 unsigned max_gs_threads;
1987 unsigned sx_max_export_size;
1988 unsigned sx_max_export_pos_size;
1989 unsigned sx_max_export_smx_size;
1990 unsigned sq_num_cf_insts;
1991 unsigned sx_num_of_sets;
1992 unsigned sc_prim_fifo_size;
1993 unsigned sc_hiz_tile_fifo_size;
1994 unsigned sc_earlyz_tile_fifo_fize;
1995 unsigned tiling_nbanks;
1996 unsigned tiling_npipes;
1997 unsigned tiling_group_size;
1998 unsigned tile_config;
1999 unsigned backend_map;
2000 unsigned active_simds;
2001 };
2002
2003 struct evergreen_asic {
2004 unsigned num_ses;
2005 unsigned max_pipes;
2006 unsigned max_tile_pipes;
2007 unsigned max_simds;
2008 unsigned max_backends;
2009 unsigned max_gprs;
2010 unsigned max_threads;
2011 unsigned max_stack_entries;
2012 unsigned max_hw_contexts;
2013 unsigned max_gs_threads;
2014 unsigned sx_max_export_size;
2015 unsigned sx_max_export_pos_size;
2016 unsigned sx_max_export_smx_size;
2017 unsigned sq_num_cf_insts;
2018 unsigned sx_num_of_sets;
2019 unsigned sc_prim_fifo_size;
2020 unsigned sc_hiz_tile_fifo_size;
2021 unsigned sc_earlyz_tile_fifo_size;
2022 unsigned tiling_nbanks;
2023 unsigned tiling_npipes;
2024 unsigned tiling_group_size;
2025 unsigned tile_config;
2026 unsigned backend_map;
2027 unsigned active_simds;
2028 };
2029
2030 struct cayman_asic {
2031 unsigned max_shader_engines;
2032 unsigned max_pipes_per_simd;
2033 unsigned max_tile_pipes;
2034 unsigned max_simds_per_se;
2035 unsigned max_backends_per_se;
2036 unsigned max_texture_channel_caches;
2037 unsigned max_gprs;
2038 unsigned max_threads;
2039 unsigned max_gs_threads;
2040 unsigned max_stack_entries;
2041 unsigned sx_num_of_sets;
2042 unsigned sx_max_export_size;
2043 unsigned sx_max_export_pos_size;
2044 unsigned sx_max_export_smx_size;
2045 unsigned max_hw_contexts;
2046 unsigned sq_num_cf_insts;
2047 unsigned sc_prim_fifo_size;
2048 unsigned sc_hiz_tile_fifo_size;
2049 unsigned sc_earlyz_tile_fifo_size;
2050
2051 unsigned num_shader_engines;
2052 unsigned num_shader_pipes_per_simd;
2053 unsigned num_tile_pipes;
2054 unsigned num_simds_per_se;
2055 unsigned num_backends_per_se;
2056 unsigned backend_disable_mask_per_asic;
2057 unsigned backend_map;
2058 unsigned num_texture_channel_caches;
2059 unsigned mem_max_burst_length_bytes;
2060 unsigned mem_row_size_in_kb;
2061 unsigned shader_engine_tile_size;
2062 unsigned num_gpus;
2063 unsigned multi_gpu_tile_size;
2064
2065 unsigned tile_config;
2066 unsigned active_simds;
2067 };
2068
2069 struct si_asic {
2070 unsigned max_shader_engines;
2071 unsigned max_tile_pipes;
2072 unsigned max_cu_per_sh;
2073 unsigned max_sh_per_se;
2074 unsigned max_backends_per_se;
2075 unsigned max_texture_channel_caches;
2076 unsigned max_gprs;
2077 unsigned max_gs_threads;
2078 unsigned max_hw_contexts;
2079 unsigned sc_prim_fifo_size_frontend;
2080 unsigned sc_prim_fifo_size_backend;
2081 unsigned sc_hiz_tile_fifo_size;
2082 unsigned sc_earlyz_tile_fifo_size;
2083
2084 unsigned num_tile_pipes;
2085 unsigned backend_enable_mask;
2086 unsigned backend_disable_mask_per_asic;
2087 unsigned backend_map;
2088 unsigned num_texture_channel_caches;
2089 unsigned mem_max_burst_length_bytes;
2090 unsigned mem_row_size_in_kb;
2091 unsigned shader_engine_tile_size;
2092 unsigned num_gpus;
2093 unsigned multi_gpu_tile_size;
2094
2095 unsigned tile_config;
2096 uint32_t tile_mode_array[32];
2097 uint32_t active_cus;
2098 };
2099
2100 struct cik_asic {
2101 unsigned max_shader_engines;
2102 unsigned max_tile_pipes;
2103 unsigned max_cu_per_sh;
2104 unsigned max_sh_per_se;
2105 unsigned max_backends_per_se;
2106 unsigned max_texture_channel_caches;
2107 unsigned max_gprs;
2108 unsigned max_gs_threads;
2109 unsigned max_hw_contexts;
2110 unsigned sc_prim_fifo_size_frontend;
2111 unsigned sc_prim_fifo_size_backend;
2112 unsigned sc_hiz_tile_fifo_size;
2113 unsigned sc_earlyz_tile_fifo_size;
2114
2115 unsigned num_tile_pipes;
2116 unsigned backend_enable_mask;
2117 unsigned backend_disable_mask_per_asic;
2118 unsigned backend_map;
2119 unsigned num_texture_channel_caches;
2120 unsigned mem_max_burst_length_bytes;
2121 unsigned mem_row_size_in_kb;
2122 unsigned shader_engine_tile_size;
2123 unsigned num_gpus;
2124 unsigned multi_gpu_tile_size;
2125
2126 unsigned tile_config;
2127 uint32_t tile_mode_array[32];
2128 uint32_t macrotile_mode_array[16];
2129 uint32_t active_cus;
2130 };
2131
2132 union radeon_asic_config {
2133 struct r300_asic r300;
2134 struct r100_asic r100;
2135 struct r600_asic r600;
2136 struct rv770_asic rv770;
2137 struct evergreen_asic evergreen;
2138 struct cayman_asic cayman;
2139 struct si_asic si;
2140 struct cik_asic cik;
2141 };
2142
2143 /*
2144 * asic initizalization from radeon_asic.c
2145 */
2146 void radeon_agp_disable(struct radeon_device *rdev);
2147 int radeon_asic_init(struct radeon_device *rdev);
2148
2149
2150 /*
2151 * IOCTL.
2152 */
2153 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *filp);
2155 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *filp);
2157 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *filp);
2159 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *file_priv);
2161 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file_priv);
2163 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file_priv);
2165 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *file_priv);
2167 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *filp);
2169 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
2171 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *filp);
2173 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
2175 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *filp);
2177 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *filp);
2179 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2180 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *filp);
2182 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2183 struct drm_file *filp);
2184
2185 /* VRAM scratch page for HDP bug, default vram page */
2186 struct r600_vram_scratch {
2187 struct radeon_bo *robj;
2188 volatile uint32_t *ptr;
2189 u64 gpu_addr;
2190 };
2191
2192 /*
2193 * ACPI
2194 */
2195 struct radeon_atif_notification_cfg {
2196 bool enabled;
2197 int command_code;
2198 };
2199
2200 struct radeon_atif_notifications {
2201 bool display_switch;
2202 bool expansion_mode_change;
2203 bool thermal_state;
2204 bool forced_power_state;
2205 bool system_power_state;
2206 bool display_conf_change;
2207 bool px_gfx_switch;
2208 bool brightness_change;
2209 bool dgpu_display_event;
2210 };
2211
2212 struct radeon_atif_functions {
2213 bool system_params;
2214 bool sbios_requests;
2215 bool select_active_disp;
2216 bool lid_state;
2217 bool get_tv_standard;
2218 bool set_tv_standard;
2219 bool get_panel_expansion_mode;
2220 bool set_panel_expansion_mode;
2221 bool temperature_change;
2222 bool graphics_device_types;
2223 };
2224
2225 struct radeon_atif {
2226 struct radeon_atif_notifications notifications;
2227 struct radeon_atif_functions functions;
2228 struct radeon_atif_notification_cfg notification_cfg;
2229 struct radeon_encoder *encoder_for_bl;
2230 };
2231
2232 struct radeon_atcs_functions {
2233 bool get_ext_state;
2234 bool pcie_perf_req;
2235 bool pcie_dev_rdy;
2236 bool pcie_bus_width;
2237 };
2238
2239 struct radeon_atcs {
2240 struct radeon_atcs_functions functions;
2241 };
2242
2243 /*
2244 * Core structure, functions and helpers.
2245 */
2246 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2247 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2248
2249 struct radeon_device {
2250 struct device *dev;
2251 struct drm_device *ddev;
2252 struct pci_dev *pdev;
2253 struct rw_semaphore exclusive_lock;
2254 /* ASIC */
2255 union radeon_asic_config config;
2256 enum radeon_family family;
2257 unsigned long flags;
2258 int usec_timeout;
2259 enum radeon_pll_errata pll_errata;
2260 int num_gb_pipes;
2261 int num_z_pipes;
2262 int disp_priority;
2263 /* BIOS */
2264 uint8_t *bios;
2265 bool is_atom_bios;
2266 uint16_t bios_header_start;
2267 struct radeon_bo *stollen_vga_memory;
2268 /* Register mmio */
2269 resource_size_t rmmio_base;
2270 resource_size_t rmmio_size;
2271 /* protects concurrent MM_INDEX/DATA based register access */
2272 spinlock_t mmio_idx_lock;
2273 /* protects concurrent SMC based register access */
2274 spinlock_t smc_idx_lock;
2275 /* protects concurrent PLL register access */
2276 spinlock_t pll_idx_lock;
2277 /* protects concurrent MC register access */
2278 spinlock_t mc_idx_lock;
2279 /* protects concurrent PCIE register access */
2280 spinlock_t pcie_idx_lock;
2281 /* protects concurrent PCIE_PORT register access */
2282 spinlock_t pciep_idx_lock;
2283 /* protects concurrent PIF register access */
2284 spinlock_t pif_idx_lock;
2285 /* protects concurrent CG register access */
2286 spinlock_t cg_idx_lock;
2287 /* protects concurrent UVD register access */
2288 spinlock_t uvd_idx_lock;
2289 /* protects concurrent RCU register access */
2290 spinlock_t rcu_idx_lock;
2291 /* protects concurrent DIDT register access */
2292 spinlock_t didt_idx_lock;
2293 /* protects concurrent ENDPOINT (audio) register access */
2294 spinlock_t end_idx_lock;
2295 void __iomem *rmmio;
2296 radeon_rreg_t mc_rreg;
2297 radeon_wreg_t mc_wreg;
2298 radeon_rreg_t pll_rreg;
2299 radeon_wreg_t pll_wreg;
2300 uint32_t pcie_reg_mask;
2301 radeon_rreg_t pciep_rreg;
2302 radeon_wreg_t pciep_wreg;
2303 /* io port */
2304 void __iomem *rio_mem;
2305 resource_size_t rio_mem_size;
2306 struct radeon_clock clock;
2307 struct radeon_mc mc;
2308 struct radeon_gart gart;
2309 struct radeon_mode_info mode_info;
2310 struct radeon_scratch scratch;
2311 struct radeon_doorbell doorbell;
2312 struct radeon_mman mman;
2313 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2314 wait_queue_head_t fence_queue;
2315 unsigned fence_context;
2316 struct mutex ring_lock;
2317 struct radeon_ring ring[RADEON_NUM_RINGS];
2318 bool ib_pool_ready;
2319 struct radeon_sa_manager ring_tmp_bo;
2320 struct radeon_irq irq;
2321 struct radeon_asic *asic;
2322 struct radeon_gem gem;
2323 struct radeon_pm pm;
2324 struct radeon_uvd uvd;
2325 struct radeon_vce vce;
2326 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2327 struct radeon_wb wb;
2328 struct radeon_dummy_page dummy_page;
2329 bool shutdown;
2330 bool suspend;
2331 bool need_dma32;
2332 bool accel_working;
2333 bool fastfb_working; /* IGP feature*/
2334 bool needs_reset, in_reset;
2335 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2336 const struct firmware *me_fw; /* all family ME firmware */
2337 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2338 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2339 const struct firmware *mc_fw; /* NI MC firmware */
2340 const struct firmware *ce_fw; /* SI CE firmware */
2341 const struct firmware *mec_fw; /* CIK MEC firmware */
2342 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2343 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2344 const struct firmware *smc_fw; /* SMC firmware */
2345 const struct firmware *uvd_fw; /* UVD firmware */
2346 const struct firmware *vce_fw; /* VCE firmware */
2347 bool new_fw;
2348 struct r600_vram_scratch vram_scratch;
2349 int msi_enabled; /* msi enabled */
2350 struct r600_ih ih; /* r6/700 interrupt ring */
2351 struct radeon_rlc rlc;
2352 struct radeon_mec mec;
2353 struct work_struct hotplug_work;
2354 struct work_struct audio_work;
2355 int num_crtc; /* number of crtcs */
2356 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2357 bool has_uvd;
2358 struct r600_audio audio; /* audio stuff */
2359 struct notifier_block acpi_nb;
2360 /* only one userspace can use Hyperz features or CMASK at a time */
2361 struct drm_file *hyperz_filp;
2362 struct drm_file *cmask_filp;
2363 /* i2c buses */
2364 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2365 /* debugfs */
2366 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2367 unsigned debugfs_count;
2368 /* virtual memory */
2369 struct radeon_vm_manager vm_manager;
2370 struct mutex gpu_clock_mutex;
2371 /* memory stats */
2372 atomic64_t vram_usage;
2373 atomic64_t gtt_usage;
2374 atomic64_t num_bytes_moved;
2375 /* ACPI interface */
2376 struct radeon_atif atif;
2377 struct radeon_atcs atcs;
2378 /* srbm instance registers */
2379 struct mutex srbm_mutex;
2380 /* clock, powergating flags */
2381 u32 cg_flags;
2382 u32 pg_flags;
2383
2384 struct dev_pm_domain vga_pm_domain;
2385 bool have_disp_power_ref;
2386 u32 px_quirk_flags;
2387
2388 /* tracking pinned memory */
2389 u64 vram_pin_size;
2390 u64 gart_pin_size;
2391
2392 struct mutex mn_lock;
2393 DECLARE_HASHTABLE(mn_hash, 7);
2394 };
2395
2396 bool radeon_is_px(struct drm_device *dev);
2397 int radeon_device_init(struct radeon_device *rdev,
2398 struct drm_device *ddev,
2399 struct pci_dev *pdev,
2400 uint32_t flags);
2401 void radeon_device_fini(struct radeon_device *rdev);
2402 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2403
2404 #define RADEON_MIN_MMIO_SIZE 0x10000
2405
2406 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2407 bool always_indirect)
2408 {
2409 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2410 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2411 return readl(((void __iomem *)rdev->rmmio) + reg);
2412 else {
2413 unsigned long flags;
2414 uint32_t ret;
2415
2416 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2417 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2418 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2419 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2420
2421 return ret;
2422 }
2423 }
2424
2425 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2426 bool always_indirect)
2427 {
2428 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2429 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2430 else {
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2434 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2435 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2436 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2437 }
2438 }
2439
2440 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2441 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2442
2443 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2444 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2445
2446 /*
2447 * Cast helper
2448 */
2449 extern const struct fence_ops radeon_fence_ops;
2450
2451 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2452 {
2453 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2454
2455 if (__f->base.ops == &radeon_fence_ops)
2456 return __f;
2457
2458 return NULL;
2459 }
2460
2461 /*
2462 * Registers read & write functions.
2463 */
2464 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2465 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2466 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2467 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2468 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2469 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2470 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2471 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2472 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2473 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2474 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2475 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2476 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2477 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2478 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2479 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2480 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2481 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2482 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2483 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2484 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2485 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2486 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2487 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2488 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2489 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2490 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2491 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2492 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2493 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2494 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2495 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2496 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2497 #define WREG32_P(reg, val, mask) \
2498 do { \
2499 uint32_t tmp_ = RREG32(reg); \
2500 tmp_ &= (mask); \
2501 tmp_ |= ((val) & ~(mask)); \
2502 WREG32(reg, tmp_); \
2503 } while (0)
2504 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2505 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2506 #define WREG32_PLL_P(reg, val, mask) \
2507 do { \
2508 uint32_t tmp_ = RREG32_PLL(reg); \
2509 tmp_ &= (mask); \
2510 tmp_ |= ((val) & ~(mask)); \
2511 WREG32_PLL(reg, tmp_); \
2512 } while (0)
2513 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2514 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2515 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2516
2517 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2518 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2519
2520 /*
2521 * Indirect registers accessor
2522 */
2523 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2524 {
2525 unsigned long flags;
2526 uint32_t r;
2527
2528 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2529 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2530 r = RREG32(RADEON_PCIE_DATA);
2531 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2532 return r;
2533 }
2534
2535 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2536 {
2537 unsigned long flags;
2538
2539 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2540 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2541 WREG32(RADEON_PCIE_DATA, (v));
2542 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2543 }
2544
2545 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2546 {
2547 unsigned long flags;
2548 u32 r;
2549
2550 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2551 WREG32(TN_SMC_IND_INDEX_0, (reg));
2552 r = RREG32(TN_SMC_IND_DATA_0);
2553 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2554 return r;
2555 }
2556
2557 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2558 {
2559 unsigned long flags;
2560
2561 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2562 WREG32(TN_SMC_IND_INDEX_0, (reg));
2563 WREG32(TN_SMC_IND_DATA_0, (v));
2564 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2565 }
2566
2567 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2568 {
2569 unsigned long flags;
2570 u32 r;
2571
2572 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2573 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2574 r = RREG32(R600_RCU_DATA);
2575 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2576 return r;
2577 }
2578
2579 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2580 {
2581 unsigned long flags;
2582
2583 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2584 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2585 WREG32(R600_RCU_DATA, (v));
2586 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2587 }
2588
2589 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2590 {
2591 unsigned long flags;
2592 u32 r;
2593
2594 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2595 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2596 r = RREG32(EVERGREEN_CG_IND_DATA);
2597 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2598 return r;
2599 }
2600
2601 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2602 {
2603 unsigned long flags;
2604
2605 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2606 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2607 WREG32(EVERGREEN_CG_IND_DATA, (v));
2608 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2609 }
2610
2611 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2612 {
2613 unsigned long flags;
2614 u32 r;
2615
2616 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2617 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2618 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2619 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2620 return r;
2621 }
2622
2623 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2624 {
2625 unsigned long flags;
2626
2627 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2628 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2629 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2630 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2631 }
2632
2633 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2634 {
2635 unsigned long flags;
2636 u32 r;
2637
2638 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2639 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2640 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2641 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2642 return r;
2643 }
2644
2645 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2646 {
2647 unsigned long flags;
2648
2649 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2650 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2651 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2652 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2653 }
2654
2655 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2656 {
2657 unsigned long flags;
2658 u32 r;
2659
2660 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2661 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2662 r = RREG32(R600_UVD_CTX_DATA);
2663 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2664 return r;
2665 }
2666
2667 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2668 {
2669 unsigned long flags;
2670
2671 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2672 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2673 WREG32(R600_UVD_CTX_DATA, (v));
2674 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2675 }
2676
2677
2678 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2679 {
2680 unsigned long flags;
2681 u32 r;
2682
2683 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2684 WREG32(CIK_DIDT_IND_INDEX, (reg));
2685 r = RREG32(CIK_DIDT_IND_DATA);
2686 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2687 return r;
2688 }
2689
2690 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2691 {
2692 unsigned long flags;
2693
2694 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2695 WREG32(CIK_DIDT_IND_INDEX, (reg));
2696 WREG32(CIK_DIDT_IND_DATA, (v));
2697 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2698 }
2699
2700 void r100_pll_errata_after_index(struct radeon_device *rdev);
2701
2702
2703 /*
2704 * ASICs helpers.
2705 */
2706 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2707 (rdev->pdev->device == 0x5969))
2708 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2709 (rdev->family == CHIP_RV200) || \
2710 (rdev->family == CHIP_RS100) || \
2711 (rdev->family == CHIP_RS200) || \
2712 (rdev->family == CHIP_RV250) || \
2713 (rdev->family == CHIP_RV280) || \
2714 (rdev->family == CHIP_RS300))
2715 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2716 (rdev->family == CHIP_RV350) || \
2717 (rdev->family == CHIP_R350) || \
2718 (rdev->family == CHIP_RV380) || \
2719 (rdev->family == CHIP_R420) || \
2720 (rdev->family == CHIP_R423) || \
2721 (rdev->family == CHIP_RV410) || \
2722 (rdev->family == CHIP_RS400) || \
2723 (rdev->family == CHIP_RS480))
2724 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2725 (rdev->ddev->pdev->device == 0x9443) || \
2726 (rdev->ddev->pdev->device == 0x944B) || \
2727 (rdev->ddev->pdev->device == 0x9506) || \
2728 (rdev->ddev->pdev->device == 0x9509) || \
2729 (rdev->ddev->pdev->device == 0x950F) || \
2730 (rdev->ddev->pdev->device == 0x689C) || \
2731 (rdev->ddev->pdev->device == 0x689D))
2732 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2733 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2734 (rdev->family == CHIP_RS690) || \
2735 (rdev->family == CHIP_RS740) || \
2736 (rdev->family >= CHIP_R600))
2737 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2738 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2739 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2740 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2741 (rdev->flags & RADEON_IS_IGP))
2742 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2743 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2744 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2745 (rdev->flags & RADEON_IS_IGP))
2746 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2747 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2748 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2749 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2750 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2751 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2752 (rdev->family == CHIP_MULLINS))
2753
2754 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2755 (rdev->ddev->pdev->device == 0x6850) || \
2756 (rdev->ddev->pdev->device == 0x6858) || \
2757 (rdev->ddev->pdev->device == 0x6859) || \
2758 (rdev->ddev->pdev->device == 0x6840) || \
2759 (rdev->ddev->pdev->device == 0x6841) || \
2760 (rdev->ddev->pdev->device == 0x6842) || \
2761 (rdev->ddev->pdev->device == 0x6843))
2762
2763 /*
2764 * BIOS helpers.
2765 */
2766 #define RBIOS8(i) (rdev->bios[i])
2767 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2768 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2769
2770 int radeon_combios_init(struct radeon_device *rdev);
2771 void radeon_combios_fini(struct radeon_device *rdev);
2772 int radeon_atombios_init(struct radeon_device *rdev);
2773 void radeon_atombios_fini(struct radeon_device *rdev);
2774
2775
2776 /*
2777 * RING helpers.
2778 */
2779 #if DRM_DEBUG_CODE == 0
2780 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2781 {
2782 ring->ring[ring->wptr++] = v;
2783 ring->wptr &= ring->ptr_mask;
2784 ring->count_dw--;
2785 ring->ring_free_dw--;
2786 }
2787 #else
2788 /* With debugging this is just too big to inline */
2789 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2790 #endif
2791
2792 /*
2793 * ASICs macro.
2794 */
2795 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2796 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2797 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2798 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2799 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2800 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2801 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2802 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2803 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2804 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2805 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2806 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2807 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2808 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2809 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2810 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2811 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2812 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2813 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2814 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2815 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2816 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2817 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2818 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2819 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2820 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2821 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2822 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2823 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2824 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2825 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2826 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2827 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2828 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2829 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2830 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2831 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2832 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2833 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2834 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2835 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2836 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2837 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2838 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2839 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2840 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2841 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2842 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2843 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2844 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2845 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2846 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2847 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2848 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2849 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2850 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2851 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2852 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2853 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2854 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2855 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2856 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2857 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2858 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2859 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2860 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2861 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2862 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2863 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2864 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2865 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2866 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2867 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2868 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2869 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2870 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2871 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2872 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2873 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2874 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2875 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2876 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2877 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2878 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2879 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2880 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2881 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2882
2883 /* Common functions */
2884 /* AGP */
2885 extern int radeon_gpu_reset(struct radeon_device *rdev);
2886 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2887 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2888 extern void radeon_agp_disable(struct radeon_device *rdev);
2889 extern int radeon_modeset_init(struct radeon_device *rdev);
2890 extern void radeon_modeset_fini(struct radeon_device *rdev);
2891 extern bool radeon_card_posted(struct radeon_device *rdev);
2892 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2893 extern void radeon_update_display_priority(struct radeon_device *rdev);
2894 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2895 extern void radeon_scratch_init(struct radeon_device *rdev);
2896 extern void radeon_wb_fini(struct radeon_device *rdev);
2897 extern int radeon_wb_init(struct radeon_device *rdev);
2898 extern void radeon_wb_disable(struct radeon_device *rdev);
2899 extern void radeon_surface_init(struct radeon_device *rdev);
2900 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2901 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2902 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2903 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2904 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2905 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2906 uint32_t flags);
2907 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2908 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2909 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2910 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2911 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2912 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2913 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2914 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2915 const u32 *registers,
2916 const u32 array_size);
2917
2918 /*
2919 * vm
2920 */
2921 int radeon_vm_manager_init(struct radeon_device *rdev);
2922 void radeon_vm_manager_fini(struct radeon_device *rdev);
2923 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2924 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2925 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2926 struct radeon_vm *vm,
2927 struct list_head *head);
2928 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2929 struct radeon_vm *vm, int ring);
2930 void radeon_vm_flush(struct radeon_device *rdev,
2931 struct radeon_vm *vm,
2932 int ring);
2933 void radeon_vm_fence(struct radeon_device *rdev,
2934 struct radeon_vm *vm,
2935 struct radeon_fence *fence);
2936 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2937 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2938 struct radeon_vm *vm);
2939 int radeon_vm_clear_freed(struct radeon_device *rdev,
2940 struct radeon_vm *vm);
2941 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2942 struct radeon_vm *vm);
2943 int radeon_vm_bo_update(struct radeon_device *rdev,
2944 struct radeon_bo_va *bo_va,
2945 struct ttm_mem_reg *mem);
2946 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2947 struct radeon_bo *bo);
2948 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2949 struct radeon_bo *bo);
2950 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2951 struct radeon_vm *vm,
2952 struct radeon_bo *bo);
2953 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2954 struct radeon_bo_va *bo_va,
2955 uint64_t offset,
2956 uint32_t flags);
2957 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2958 struct radeon_bo_va *bo_va);
2959
2960 /* audio */
2961 void r600_audio_update_hdmi(struct work_struct *work);
2962 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2963 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2964 void r600_audio_enable(struct radeon_device *rdev,
2965 struct r600_audio_pin *pin,
2966 bool enable);
2967 void dce6_audio_enable(struct radeon_device *rdev,
2968 struct r600_audio_pin *pin,
2969 bool enable);
2970
2971 /*
2972 * R600 vram scratch functions
2973 */
2974 int r600_vram_scratch_init(struct radeon_device *rdev);
2975 void r600_vram_scratch_fini(struct radeon_device *rdev);
2976
2977 /*
2978 * r600 cs checking helper
2979 */
2980 unsigned r600_mip_minify(unsigned size, unsigned level);
2981 bool r600_fmt_is_valid_color(u32 format);
2982 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2983 int r600_fmt_get_blocksize(u32 format);
2984 int r600_fmt_get_nblocksx(u32 format, u32 w);
2985 int r600_fmt_get_nblocksy(u32 format, u32 h);
2986
2987 /*
2988 * r600 functions used by radeon_encoder.c
2989 */
2990 struct radeon_hdmi_acr {
2991 u32 clock;
2992
2993 int n_32khz;
2994 int cts_32khz;
2995
2996 int n_44_1khz;
2997 int cts_44_1khz;
2998
2999 int n_48khz;
3000 int cts_48khz;
3001
3002 };
3003
3004 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3005
3006 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3007 u32 tiling_pipe_num,
3008 u32 max_rb_num,
3009 u32 total_max_rb_num,
3010 u32 enabled_rb_mask);
3011
3012 /*
3013 * evergreen functions used by radeon_encoder.c
3014 */
3015
3016 extern int ni_init_microcode(struct radeon_device *rdev);
3017 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3018
3019 /* radeon_acpi.c */
3020 #if defined(CONFIG_ACPI)
3021 extern int radeon_acpi_init(struct radeon_device *rdev);
3022 extern void radeon_acpi_fini(struct radeon_device *rdev);
3023 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3024 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3025 u8 perf_req, bool advertise);
3026 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3027 #else
3028 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3029 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3030 #endif
3031
3032 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3033 struct radeon_cs_packet *pkt,
3034 unsigned idx);
3035 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3036 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3037 struct radeon_cs_packet *pkt);
3038 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3039 struct radeon_cs_reloc **cs_reloc,
3040 int nomm);
3041 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3042 uint32_t *vline_start_end,
3043 uint32_t *vline_status);
3044
3045 #include "radeon_object.h"
3046
3047 #endif
Linux kernel - Deliverables
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