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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
94
95 /*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
97 * symbol;
98 */
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 #define RADEON_IB_POOL_SIZE 16
101 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
102 #define RADEONFB_CONN_LIMIT 4
103 #define RADEON_BIOS_NUM_SCRATCH 8
104
105 /*
106 * Errata workarounds.
107 */
108 enum radeon_pll_errata {
109 CHIP_ERRATA_R300_CG = 0x00000001,
110 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
111 CHIP_ERRATA_PLL_DELAY = 0x00000004
112 };
113
114
115 struct radeon_device;
116
117
118 /*
119 * BIOS.
120 */
121 bool radeon_get_bios(struct radeon_device *rdev);
122
123
124 /*
125 * Dummy page
126 */
127 struct radeon_dummy_page {
128 struct page *page;
129 dma_addr_t addr;
130 };
131 int radeon_dummy_page_init(struct radeon_device *rdev);
132 void radeon_dummy_page_fini(struct radeon_device *rdev);
133
134
135 /*
136 * Clocks
137 */
138 struct radeon_clock {
139 struct radeon_pll p1pll;
140 struct radeon_pll p2pll;
141 struct radeon_pll spll;
142 struct radeon_pll mpll;
143 /* 10 Khz units */
144 uint32_t default_mclk;
145 uint32_t default_sclk;
146 };
147
148 /*
149 * Power management
150 */
151 int radeon_pm_init(struct radeon_device *rdev);
152 void radeon_pm_compute_clocks(struct radeon_device *rdev);
153 void radeon_combios_get_power_modes(struct radeon_device *rdev);
154 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
155
156 /*
157 * Fences.
158 */
159 struct radeon_fence_driver {
160 uint32_t scratch_reg;
161 atomic_t seq;
162 uint32_t last_seq;
163 unsigned long count_timeout;
164 wait_queue_head_t queue;
165 rwlock_t lock;
166 struct list_head created;
167 struct list_head emited;
168 struct list_head signaled;
169 bool initialized;
170 };
171
172 struct radeon_fence {
173 struct radeon_device *rdev;
174 struct kref kref;
175 struct list_head list;
176 /* protected by radeon_fence.lock */
177 uint32_t seq;
178 unsigned long timeout;
179 bool emited;
180 bool signaled;
181 };
182
183 int radeon_fence_driver_init(struct radeon_device *rdev);
184 void radeon_fence_driver_fini(struct radeon_device *rdev);
185 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
186 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
187 void radeon_fence_process(struct radeon_device *rdev);
188 bool radeon_fence_signaled(struct radeon_fence *fence);
189 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
190 int radeon_fence_wait_next(struct radeon_device *rdev);
191 int radeon_fence_wait_last(struct radeon_device *rdev);
192 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
193 void radeon_fence_unref(struct radeon_fence **fence);
194
195 /*
196 * Tiling registers
197 */
198 struct radeon_surface_reg {
199 struct radeon_bo *bo;
200 };
201
202 #define RADEON_GEM_MAX_SURFACES 8
203
204 /*
205 * TTM.
206 */
207 struct radeon_mman {
208 struct ttm_bo_global_ref bo_global_ref;
209 struct ttm_global_reference mem_global_ref;
210 struct ttm_bo_device bdev;
211 bool mem_global_referenced;
212 bool initialized;
213 };
214
215 struct radeon_bo {
216 /* Protected by gem.mutex */
217 struct list_head list;
218 /* Protected by tbo.reserved */
219 u32 placements[3];
220 struct ttm_placement placement;
221 struct ttm_buffer_object tbo;
222 struct ttm_bo_kmap_obj kmap;
223 unsigned pin_count;
224 void *kptr;
225 u32 tiling_flags;
226 u32 pitch;
227 int surface_reg;
228 /* Constant after initialization */
229 struct radeon_device *rdev;
230 struct drm_gem_object *gobj;
231 };
232
233 struct radeon_bo_list {
234 struct list_head list;
235 struct radeon_bo *bo;
236 uint64_t gpu_offset;
237 unsigned rdomain;
238 unsigned wdomain;
239 u32 tiling_flags;
240 };
241
242 /*
243 * GEM objects.
244 */
245 struct radeon_gem {
246 struct mutex mutex;
247 struct list_head objects;
248 };
249
250 int radeon_gem_init(struct radeon_device *rdev);
251 void radeon_gem_fini(struct radeon_device *rdev);
252 int radeon_gem_object_create(struct radeon_device *rdev, int size,
253 int alignment, int initial_domain,
254 bool discardable, bool kernel,
255 struct drm_gem_object **obj);
256 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
257 uint64_t *gpu_addr);
258 void radeon_gem_object_unpin(struct drm_gem_object *obj);
259
260
261 /*
262 * GART structures, functions & helpers
263 */
264 struct radeon_mc;
265
266 struct radeon_gart_table_ram {
267 volatile uint32_t *ptr;
268 };
269
270 struct radeon_gart_table_vram {
271 struct radeon_bo *robj;
272 volatile uint32_t *ptr;
273 };
274
275 union radeon_gart_table {
276 struct radeon_gart_table_ram ram;
277 struct radeon_gart_table_vram vram;
278 };
279
280 #define RADEON_GPU_PAGE_SIZE 4096
281
282 struct radeon_gart {
283 dma_addr_t table_addr;
284 unsigned num_gpu_pages;
285 unsigned num_cpu_pages;
286 unsigned table_size;
287 union radeon_gart_table table;
288 struct page **pages;
289 dma_addr_t *pages_addr;
290 bool ready;
291 };
292
293 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
294 void radeon_gart_table_ram_free(struct radeon_device *rdev);
295 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
296 void radeon_gart_table_vram_free(struct radeon_device *rdev);
297 int radeon_gart_init(struct radeon_device *rdev);
298 void radeon_gart_fini(struct radeon_device *rdev);
299 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
300 int pages);
301 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
302 int pages, struct page **pagelist);
303
304
305 /*
306 * GPU MC structures, functions & helpers
307 */
308 struct radeon_mc {
309 resource_size_t aper_size;
310 resource_size_t aper_base;
311 resource_size_t agp_base;
312 /* for some chips with <= 32MB we need to lie
313 * about vram size near mc fb location */
314 u64 mc_vram_size;
315 u64 gtt_location;
316 u64 gtt_size;
317 u64 gtt_start;
318 u64 gtt_end;
319 u64 vram_location;
320 u64 vram_start;
321 u64 vram_end;
322 unsigned vram_width;
323 u64 real_vram_size;
324 int vram_mtrr;
325 bool vram_is_ddr;
326 bool igp_sideport_enabled;
327 };
328
329 int radeon_mc_setup(struct radeon_device *rdev);
330 bool radeon_combios_sideport_present(struct radeon_device *rdev);
331 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
332
333 /*
334 * GPU scratch registers structures, functions & helpers
335 */
336 struct radeon_scratch {
337 unsigned num_reg;
338 bool free[32];
339 uint32_t reg[32];
340 };
341
342 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
343 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
344
345
346 /*
347 * IRQS.
348 */
349 struct radeon_irq {
350 bool installed;
351 bool sw_int;
352 /* FIXME: use a define max crtc rather than hardcode it */
353 bool crtc_vblank_int[2];
354 /* FIXME: use defines for max hpd/dacs */
355 bool hpd[6];
356 spinlock_t sw_lock;
357 int sw_refcount;
358 };
359
360 int radeon_irq_kms_init(struct radeon_device *rdev);
361 void radeon_irq_kms_fini(struct radeon_device *rdev);
362 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
363 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
364
365 /*
366 * CP & ring.
367 */
368 struct radeon_ib {
369 struct list_head list;
370 unsigned long idx;
371 uint64_t gpu_addr;
372 struct radeon_fence *fence;
373 uint32_t *ptr;
374 uint32_t length_dw;
375 };
376
377 /*
378 * locking -
379 * mutex protects scheduled_ibs, ready, alloc_bm
380 */
381 struct radeon_ib_pool {
382 struct mutex mutex;
383 struct radeon_bo *robj;
384 struct list_head scheduled_ibs;
385 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
386 bool ready;
387 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
388 };
389
390 struct radeon_cp {
391 struct radeon_bo *ring_obj;
392 volatile uint32_t *ring;
393 unsigned rptr;
394 unsigned wptr;
395 unsigned wptr_old;
396 unsigned ring_size;
397 unsigned ring_free_dw;
398 int count_dw;
399 uint64_t gpu_addr;
400 uint32_t align_mask;
401 uint32_t ptr_mask;
402 struct mutex mutex;
403 bool ready;
404 };
405
406 /*
407 * R6xx+ IH ring
408 */
409 struct r600_ih {
410 struct radeon_bo *ring_obj;
411 volatile uint32_t *ring;
412 unsigned rptr;
413 unsigned wptr;
414 unsigned wptr_old;
415 unsigned ring_size;
416 uint64_t gpu_addr;
417 uint32_t ptr_mask;
418 spinlock_t lock;
419 bool enabled;
420 };
421
422 struct r600_blit {
423 struct mutex mutex;
424 struct radeon_bo *shader_obj;
425 u64 shader_gpu_addr;
426 u32 vs_offset, ps_offset;
427 u32 state_offset;
428 u32 state_len;
429 u32 vb_used, vb_total;
430 struct radeon_ib *vb_ib;
431 };
432
433 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
434 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
435 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
436 int radeon_ib_pool_init(struct radeon_device *rdev);
437 void radeon_ib_pool_fini(struct radeon_device *rdev);
438 int radeon_ib_test(struct radeon_device *rdev);
439 /* Ring access between begin & end cannot sleep */
440 void radeon_ring_free_size(struct radeon_device *rdev);
441 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
442 void radeon_ring_unlock_commit(struct radeon_device *rdev);
443 void radeon_ring_unlock_undo(struct radeon_device *rdev);
444 int radeon_ring_test(struct radeon_device *rdev);
445 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
446 void radeon_ring_fini(struct radeon_device *rdev);
447
448
449 /*
450 * CS.
451 */
452 struct radeon_cs_reloc {
453 struct drm_gem_object *gobj;
454 struct radeon_bo *robj;
455 struct radeon_bo_list lobj;
456 uint32_t handle;
457 uint32_t flags;
458 };
459
460 struct radeon_cs_chunk {
461 uint32_t chunk_id;
462 uint32_t length_dw;
463 int kpage_idx[2];
464 uint32_t *kpage[2];
465 uint32_t *kdata;
466 void __user *user_ptr;
467 int last_copied_page;
468 int last_page_index;
469 };
470
471 struct radeon_cs_parser {
472 struct device *dev;
473 struct radeon_device *rdev;
474 struct drm_file *filp;
475 /* chunks */
476 unsigned nchunks;
477 struct radeon_cs_chunk *chunks;
478 uint64_t *chunks_array;
479 /* IB */
480 unsigned idx;
481 /* relocations */
482 unsigned nrelocs;
483 struct radeon_cs_reloc *relocs;
484 struct radeon_cs_reloc **relocs_ptr;
485 struct list_head validated;
486 /* indices of various chunks */
487 int chunk_ib_idx;
488 int chunk_relocs_idx;
489 struct radeon_ib *ib;
490 void *track;
491 unsigned family;
492 int parser_error;
493 };
494
495 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
496 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
497
498
499 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
500 {
501 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
502 u32 pg_idx, pg_offset;
503 u32 idx_value = 0;
504 int new_page;
505
506 pg_idx = (idx * 4) / PAGE_SIZE;
507 pg_offset = (idx * 4) % PAGE_SIZE;
508
509 if (ibc->kpage_idx[0] == pg_idx)
510 return ibc->kpage[0][pg_offset/4];
511 if (ibc->kpage_idx[1] == pg_idx)
512 return ibc->kpage[1][pg_offset/4];
513
514 new_page = radeon_cs_update_pages(p, pg_idx);
515 if (new_page < 0) {
516 p->parser_error = new_page;
517 return 0;
518 }
519
520 idx_value = ibc->kpage[new_page][pg_offset/4];
521 return idx_value;
522 }
523
524 struct radeon_cs_packet {
525 unsigned idx;
526 unsigned type;
527 unsigned reg;
528 unsigned opcode;
529 int count;
530 unsigned one_reg_wr;
531 };
532
533 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
534 struct radeon_cs_packet *pkt,
535 unsigned idx, unsigned reg);
536 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
537 struct radeon_cs_packet *pkt);
538
539
540 /*
541 * AGP
542 */
543 int radeon_agp_init(struct radeon_device *rdev);
544 void radeon_agp_resume(struct radeon_device *rdev);
545 void radeon_agp_fini(struct radeon_device *rdev);
546
547
548 /*
549 * Writeback
550 */
551 struct radeon_wb {
552 struct radeon_bo *wb_obj;
553 volatile uint32_t *wb;
554 uint64_t gpu_addr;
555 };
556
557 /**
558 * struct radeon_pm - power management datas
559 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
560 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
562 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
563 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
564 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
565 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
566 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
567 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
568 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
569 * @needed_bandwidth: current bandwidth needs
570 *
571 * It keeps track of various data needed to take powermanagement decision.
572 * Bandwith need is used to determine minimun clock of the GPU and memory.
573 * Equation between gpu/memory clock and available bandwidth is hw dependent
574 * (type of memory, bus size, efficiency, ...)
575 */
576 enum radeon_pm_state {
577 PM_STATE_DISABLED,
578 PM_STATE_MINIMUM,
579 PM_STATE_PAUSED,
580 PM_STATE_ACTIVE
581 };
582 enum radeon_pm_action {
583 PM_ACTION_NONE,
584 PM_ACTION_MINIMUM,
585 PM_ACTION_DOWNCLOCK,
586 PM_ACTION_UPCLOCK
587 };
588
589 enum radeon_voltage_type {
590 VOLTAGE_NONE = 0,
591 VOLTAGE_GPIO,
592 VOLTAGE_VDDC,
593 VOLTAGE_SW
594 };
595
596 enum radeon_pm_state_type {
597 POWER_STATE_TYPE_DEFAULT,
598 POWER_STATE_TYPE_POWERSAVE,
599 POWER_STATE_TYPE_BATTERY,
600 POWER_STATE_TYPE_BALANCED,
601 POWER_STATE_TYPE_PERFORMANCE,
602 };
603
604 enum radeon_pm_clock_mode_type {
605 POWER_MODE_TYPE_DEFAULT,
606 POWER_MODE_TYPE_LOW,
607 POWER_MODE_TYPE_MID,
608 POWER_MODE_TYPE_HIGH,
609 };
610
611 struct radeon_voltage {
612 enum radeon_voltage_type type;
613 /* gpio voltage */
614 struct radeon_gpio_rec gpio;
615 u32 delay; /* delay in usec from voltage drop to sclk change */
616 bool active_high; /* voltage drop is active when bit is high */
617 /* VDDC voltage */
618 u8 vddc_id; /* index into vddc voltage table */
619 u8 vddci_id; /* index into vddci voltage table */
620 bool vddci_enabled;
621 /* r6xx+ sw */
622 u32 voltage;
623 };
624
625 struct radeon_pm_non_clock_info {
626 /* pcie lanes */
627 int pcie_lanes;
628 /* standardized non-clock flags */
629 u32 flags;
630 };
631
632 struct radeon_pm_clock_info {
633 /* memory clock */
634 u32 mclk;
635 /* engine clock */
636 u32 sclk;
637 /* voltage info */
638 struct radeon_voltage voltage;
639 /* standardized clock flags - not sure we'll need these */
640 u32 flags;
641 };
642
643 struct radeon_power_state {
644 enum radeon_pm_state_type type;
645 /* XXX: use a define for num clock modes */
646 struct radeon_pm_clock_info clock_info[8];
647 /* number of valid clock modes in this power state */
648 int num_clock_modes;
649 /* currently selected clock mode */
650 struct radeon_pm_clock_info *current_clock_mode;
651 struct radeon_pm_clock_info *requested_clock_mode;
652 struct radeon_pm_clock_info *default_clock_mode;
653 /* non clock info about this state */
654 struct radeon_pm_non_clock_info non_clock_info;
655 bool voltage_drop_active;
656 };
657
658 struct radeon_pm {
659 struct mutex mutex;
660 struct work_struct reclock_work;
661 struct delayed_work idle_work;
662 enum radeon_pm_state state;
663 enum radeon_pm_action planned_action;
664 unsigned long action_timeout;
665 bool downclocked;
666 bool vblank_callback;
667 int active_crtcs;
668 int req_vblank;
669 fixed20_12 max_bandwidth;
670 fixed20_12 igp_sideport_mclk;
671 fixed20_12 igp_system_mclk;
672 fixed20_12 igp_ht_link_clk;
673 fixed20_12 igp_ht_link_width;
674 fixed20_12 k8_bandwidth;
675 fixed20_12 sideport_bandwidth;
676 fixed20_12 ht_bandwidth;
677 fixed20_12 core_bandwidth;
678 fixed20_12 sclk;
679 fixed20_12 needed_bandwidth;
680 /* XXX: use a define for num power modes */
681 struct radeon_power_state power_state[8];
682 /* number of valid power states */
683 int num_power_states;
684 struct radeon_power_state *current_power_state;
685 struct radeon_power_state *requested_power_state;
686 struct radeon_power_state *default_power_state;
687 };
688
689
690 /*
691 * Benchmarking
692 */
693 void radeon_benchmark(struct radeon_device *rdev);
694
695
696 /*
697 * Testing
698 */
699 void radeon_test_moves(struct radeon_device *rdev);
700
701
702 /*
703 * Debugfs
704 */
705 int radeon_debugfs_add_files(struct radeon_device *rdev,
706 struct drm_info_list *files,
707 unsigned nfiles);
708 int radeon_debugfs_fence_init(struct radeon_device *rdev);
709 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
710 int r100_debugfs_cp_init(struct radeon_device *rdev);
711
712
713 /*
714 * ASIC specific functions.
715 */
716 struct radeon_asic {
717 int (*init)(struct radeon_device *rdev);
718 void (*fini)(struct radeon_device *rdev);
719 int (*resume)(struct radeon_device *rdev);
720 int (*suspend)(struct radeon_device *rdev);
721 void (*vga_set_state)(struct radeon_device *rdev, bool state);
722 int (*gpu_reset)(struct radeon_device *rdev);
723 void (*gart_tlb_flush)(struct radeon_device *rdev);
724 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
725 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
726 void (*cp_fini)(struct radeon_device *rdev);
727 void (*cp_disable)(struct radeon_device *rdev);
728 void (*cp_commit)(struct radeon_device *rdev);
729 void (*ring_start)(struct radeon_device *rdev);
730 int (*ring_test)(struct radeon_device *rdev);
731 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
732 int (*irq_set)(struct radeon_device *rdev);
733 int (*irq_process)(struct radeon_device *rdev);
734 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
735 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
736 int (*cs_parse)(struct radeon_cs_parser *p);
737 int (*copy_blit)(struct radeon_device *rdev,
738 uint64_t src_offset,
739 uint64_t dst_offset,
740 unsigned num_pages,
741 struct radeon_fence *fence);
742 int (*copy_dma)(struct radeon_device *rdev,
743 uint64_t src_offset,
744 uint64_t dst_offset,
745 unsigned num_pages,
746 struct radeon_fence *fence);
747 int (*copy)(struct radeon_device *rdev,
748 uint64_t src_offset,
749 uint64_t dst_offset,
750 unsigned num_pages,
751 struct radeon_fence *fence);
752 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
753 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
754 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
755 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
756 int (*get_pcie_lanes)(struct radeon_device *rdev);
757 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
758 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
759 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
760 uint32_t tiling_flags, uint32_t pitch,
761 uint32_t offset, uint32_t obj_size);
762 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
763 void (*bandwidth_update)(struct radeon_device *rdev);
764 void (*hpd_init)(struct radeon_device *rdev);
765 void (*hpd_fini)(struct radeon_device *rdev);
766 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
767 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
768 /* ioctl hw specific callback. Some hw might want to perform special
769 * operation on specific ioctl. For instance on wait idle some hw
770 * might want to perform and HDP flush through MMIO as it seems that
771 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
772 * through ring.
773 */
774 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
775 };
776
777 /*
778 * Asic structures
779 */
780 struct r100_asic {
781 const unsigned *reg_safe_bm;
782 unsigned reg_safe_bm_size;
783 u32 hdp_cntl;
784 };
785
786 struct r300_asic {
787 const unsigned *reg_safe_bm;
788 unsigned reg_safe_bm_size;
789 u32 resync_scratch;
790 u32 hdp_cntl;
791 };
792
793 struct r600_asic {
794 unsigned max_pipes;
795 unsigned max_tile_pipes;
796 unsigned max_simds;
797 unsigned max_backends;
798 unsigned max_gprs;
799 unsigned max_threads;
800 unsigned max_stack_entries;
801 unsigned max_hw_contexts;
802 unsigned max_gs_threads;
803 unsigned sx_max_export_size;
804 unsigned sx_max_export_pos_size;
805 unsigned sx_max_export_smx_size;
806 unsigned sq_num_cf_insts;
807 };
808
809 struct rv770_asic {
810 unsigned max_pipes;
811 unsigned max_tile_pipes;
812 unsigned max_simds;
813 unsigned max_backends;
814 unsigned max_gprs;
815 unsigned max_threads;
816 unsigned max_stack_entries;
817 unsigned max_hw_contexts;
818 unsigned max_gs_threads;
819 unsigned sx_max_export_size;
820 unsigned sx_max_export_pos_size;
821 unsigned sx_max_export_smx_size;
822 unsigned sq_num_cf_insts;
823 unsigned sx_num_of_sets;
824 unsigned sc_prim_fifo_size;
825 unsigned sc_hiz_tile_fifo_size;
826 unsigned sc_earlyz_tile_fifo_fize;
827 };
828
829 union radeon_asic_config {
830 struct r300_asic r300;
831 struct r100_asic r100;
832 struct r600_asic r600;
833 struct rv770_asic rv770;
834 };
835
836
837 /*
838 * IOCTL.
839 */
840 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
841 struct drm_file *filp);
842 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
843 struct drm_file *filp);
844 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
845 struct drm_file *file_priv);
846 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);
848 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file_priv);
850 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
851 struct drm_file *file_priv);
852 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
853 struct drm_file *filp);
854 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
855 struct drm_file *filp);
856 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *filp);
858 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
859 struct drm_file *filp);
860 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
861 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *filp);
863 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
864 struct drm_file *filp);
865
866
867 /*
868 * Core structure, functions and helpers.
869 */
870 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
871 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
872
873 struct radeon_device {
874 struct device *dev;
875 struct drm_device *ddev;
876 struct pci_dev *pdev;
877 /* ASIC */
878 union radeon_asic_config config;
879 enum radeon_family family;
880 unsigned long flags;
881 int usec_timeout;
882 enum radeon_pll_errata pll_errata;
883 int num_gb_pipes;
884 int num_z_pipes;
885 int disp_priority;
886 /* BIOS */
887 uint8_t *bios;
888 bool is_atom_bios;
889 uint16_t bios_header_start;
890 struct radeon_bo *stollen_vga_memory;
891 struct fb_info *fbdev_info;
892 struct radeon_bo *fbdev_rbo;
893 struct radeon_framebuffer *fbdev_rfb;
894 /* Register mmio */
895 resource_size_t rmmio_base;
896 resource_size_t rmmio_size;
897 void *rmmio;
898 radeon_rreg_t mc_rreg;
899 radeon_wreg_t mc_wreg;
900 radeon_rreg_t pll_rreg;
901 radeon_wreg_t pll_wreg;
902 uint32_t pcie_reg_mask;
903 radeon_rreg_t pciep_rreg;
904 radeon_wreg_t pciep_wreg;
905 struct radeon_clock clock;
906 struct radeon_mc mc;
907 struct radeon_gart gart;
908 struct radeon_mode_info mode_info;
909 struct radeon_scratch scratch;
910 struct radeon_mman mman;
911 struct radeon_fence_driver fence_drv;
912 struct radeon_cp cp;
913 struct radeon_ib_pool ib_pool;
914 struct radeon_irq irq;
915 struct radeon_asic *asic;
916 struct radeon_gem gem;
917 struct radeon_pm pm;
918 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
919 struct mutex cs_mutex;
920 struct radeon_wb wb;
921 struct radeon_dummy_page dummy_page;
922 bool gpu_lockup;
923 bool shutdown;
924 bool suspend;
925 bool need_dma32;
926 bool accel_working;
927 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
928 const struct firmware *me_fw; /* all family ME firmware */
929 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
930 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
931 struct r600_blit r600_blit;
932 int msi_enabled; /* msi enabled */
933 struct r600_ih ih; /* r6/700 interrupt ring */
934 struct workqueue_struct *wq;
935 struct work_struct hotplug_work;
936 int num_crtc; /* number of crtcs */
937 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
938
939 /* audio stuff */
940 struct timer_list audio_timer;
941 int audio_channels;
942 int audio_rate;
943 int audio_bits_per_sample;
944 uint8_t audio_status_bits;
945 uint8_t audio_category_code;
946 };
947
948 int radeon_device_init(struct radeon_device *rdev,
949 struct drm_device *ddev,
950 struct pci_dev *pdev,
951 uint32_t flags);
952 void radeon_device_fini(struct radeon_device *rdev);
953 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
954
955 /* r600 blit */
956 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
957 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
958 void r600_kms_blit_copy(struct radeon_device *rdev,
959 u64 src_gpu_addr, u64 dst_gpu_addr,
960 int size_bytes);
961
962 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
963 {
964 if (reg < rdev->rmmio_size)
965 return readl(((void __iomem *)rdev->rmmio) + reg);
966 else {
967 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
968 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
969 }
970 }
971
972 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
973 {
974 if (reg < rdev->rmmio_size)
975 writel(v, ((void __iomem *)rdev->rmmio) + reg);
976 else {
977 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
978 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
979 }
980 }
981
982 /*
983 * Cast helper
984 */
985 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
986
987 /*
988 * Registers read & write functions.
989 */
990 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
991 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
992 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
993 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
994 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
995 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
996 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
997 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
998 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
999 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1000 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1001 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1002 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1003 #define WREG32_P(reg, val, mask) \
1004 do { \
1005 uint32_t tmp_ = RREG32(reg); \
1006 tmp_ &= (mask); \
1007 tmp_ |= ((val) & ~(mask)); \
1008 WREG32(reg, tmp_); \
1009 } while (0)
1010 #define WREG32_PLL_P(reg, val, mask) \
1011 do { \
1012 uint32_t tmp_ = RREG32_PLL(reg); \
1013 tmp_ &= (mask); \
1014 tmp_ |= ((val) & ~(mask)); \
1015 WREG32_PLL(reg, tmp_); \
1016 } while (0)
1017 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1018
1019 /*
1020 * Indirect registers accessor
1021 */
1022 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1023 {
1024 uint32_t r;
1025
1026 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1027 r = RREG32(RADEON_PCIE_DATA);
1028 return r;
1029 }
1030
1031 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1032 {
1033 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1034 WREG32(RADEON_PCIE_DATA, (v));
1035 }
1036
1037 void r100_pll_errata_after_index(struct radeon_device *rdev);
1038
1039
1040 /*
1041 * ASICs helpers.
1042 */
1043 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1044 (rdev->pdev->device == 0x5969))
1045 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1046 (rdev->family == CHIP_RV200) || \
1047 (rdev->family == CHIP_RS100) || \
1048 (rdev->family == CHIP_RS200) || \
1049 (rdev->family == CHIP_RV250) || \
1050 (rdev->family == CHIP_RV280) || \
1051 (rdev->family == CHIP_RS300))
1052 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1053 (rdev->family == CHIP_RV350) || \
1054 (rdev->family == CHIP_R350) || \
1055 (rdev->family == CHIP_RV380) || \
1056 (rdev->family == CHIP_R420) || \
1057 (rdev->family == CHIP_R423) || \
1058 (rdev->family == CHIP_RV410) || \
1059 (rdev->family == CHIP_RS400) || \
1060 (rdev->family == CHIP_RS480))
1061 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1062 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1063 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1064
1065
1066 /*
1067 * BIOS helpers.
1068 */
1069 #define RBIOS8(i) (rdev->bios[i])
1070 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1071 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1072
1073 int radeon_combios_init(struct radeon_device *rdev);
1074 void radeon_combios_fini(struct radeon_device *rdev);
1075 int radeon_atombios_init(struct radeon_device *rdev);
1076 void radeon_atombios_fini(struct radeon_device *rdev);
1077
1078
1079 /*
1080 * RING helpers.
1081 */
1082 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1083 {
1084 #if DRM_DEBUG_CODE
1085 if (rdev->cp.count_dw <= 0) {
1086 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1087 }
1088 #endif
1089 rdev->cp.ring[rdev->cp.wptr++] = v;
1090 rdev->cp.wptr &= rdev->cp.ptr_mask;
1091 rdev->cp.count_dw--;
1092 rdev->cp.ring_free_dw--;
1093 }
1094
1095
1096 /*
1097 * ASICs macro.
1098 */
1099 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1100 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1101 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1102 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1103 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1104 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1105 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1106 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1107 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1108 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1109 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1110 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1111 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1112 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1113 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1114 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1115 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1116 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1117 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1118 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1119 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1120 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1121 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1122 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1123 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1124 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1125 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1126 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1127 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1128 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1129 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1130 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1131 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1132 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1133
1134 /* Common functions */
1135 /* AGP */
1136 extern void radeon_agp_disable(struct radeon_device *rdev);
1137 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1138 extern int radeon_modeset_init(struct radeon_device *rdev);
1139 extern void radeon_modeset_fini(struct radeon_device *rdev);
1140 extern bool radeon_card_posted(struct radeon_device *rdev);
1141 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1142 extern int radeon_clocks_init(struct radeon_device *rdev);
1143 extern void radeon_clocks_fini(struct radeon_device *rdev);
1144 extern void radeon_scratch_init(struct radeon_device *rdev);
1145 extern void radeon_surface_init(struct radeon_device *rdev);
1146 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1147 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1148 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1149 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1150 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1151
1152 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1153 struct r100_mc_save {
1154 u32 GENMO_WT;
1155 u32 CRTC_EXT_CNTL;
1156 u32 CRTC_GEN_CNTL;
1157 u32 CRTC2_GEN_CNTL;
1158 u32 CUR_OFFSET;
1159 u32 CUR2_OFFSET;
1160 };
1161 extern void r100_cp_disable(struct radeon_device *rdev);
1162 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1163 extern void r100_cp_fini(struct radeon_device *rdev);
1164 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1165 extern int r100_pci_gart_init(struct radeon_device *rdev);
1166 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1167 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1168 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1169 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1170 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1171 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1172 extern void r100_ib_fini(struct radeon_device *rdev);
1173 extern int r100_ib_init(struct radeon_device *rdev);
1174 extern void r100_irq_disable(struct radeon_device *rdev);
1175 extern int r100_irq_set(struct radeon_device *rdev);
1176 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1177 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1178 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1179 extern void r100_wb_disable(struct radeon_device *rdev);
1180 extern void r100_wb_fini(struct radeon_device *rdev);
1181 extern int r100_wb_init(struct radeon_device *rdev);
1182 extern void r100_hdp_reset(struct radeon_device *rdev);
1183 extern int r100_rb2d_reset(struct radeon_device *rdev);
1184 extern int r100_cp_reset(struct radeon_device *rdev);
1185 extern void r100_vga_render_disable(struct radeon_device *rdev);
1186 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1187 struct radeon_cs_packet *pkt,
1188 struct radeon_bo *robj);
1189 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1190 struct radeon_cs_packet *pkt,
1191 const unsigned *auth, unsigned n,
1192 radeon_packet0_check_t check);
1193 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1194 struct radeon_cs_packet *pkt,
1195 unsigned idx);
1196 extern void r100_enable_bm(struct radeon_device *rdev);
1197 extern void r100_set_common_regs(struct radeon_device *rdev);
1198
1199 /* rv200,rv250,rv280 */
1200 extern void r200_set_safe_registers(struct radeon_device *rdev);
1201
1202 /* r300,r350,rv350,rv370,rv380 */
1203 extern void r300_set_reg_safe(struct radeon_device *rdev);
1204 extern void r300_mc_program(struct radeon_device *rdev);
1205 extern void r300_vram_info(struct radeon_device *rdev);
1206 extern void r300_clock_startup(struct radeon_device *rdev);
1207 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1208 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1209 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1210 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1211 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1212
1213 /* r420,r423,rv410 */
1214 extern int r420_mc_init(struct radeon_device *rdev);
1215 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1216 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1217 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1218 extern void r420_pipes_init(struct radeon_device *rdev);
1219
1220 /* rv515 */
1221 struct rv515_mc_save {
1222 u32 d1vga_control;
1223 u32 d2vga_control;
1224 u32 vga_render_control;
1225 u32 vga_hdp_control;
1226 u32 d1crtc_control;
1227 u32 d2crtc_control;
1228 };
1229 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1230 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1231 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1232 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1233 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1234 extern void rv515_clock_startup(struct radeon_device *rdev);
1235 extern void rv515_debugfs(struct radeon_device *rdev);
1236 extern int rv515_suspend(struct radeon_device *rdev);
1237
1238 /* rs400 */
1239 extern int rs400_gart_init(struct radeon_device *rdev);
1240 extern int rs400_gart_enable(struct radeon_device *rdev);
1241 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1242 extern void rs400_gart_disable(struct radeon_device *rdev);
1243 extern void rs400_gart_fini(struct radeon_device *rdev);
1244
1245 /* rs600 */
1246 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1247 extern int rs600_irq_set(struct radeon_device *rdev);
1248 extern void rs600_irq_disable(struct radeon_device *rdev);
1249
1250 /* rs690, rs740 */
1251 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1252 struct drm_display_mode *mode1,
1253 struct drm_display_mode *mode2);
1254
1255 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1256 extern bool r600_card_posted(struct radeon_device *rdev);
1257 extern void r600_cp_stop(struct radeon_device *rdev);
1258 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1259 extern int r600_cp_resume(struct radeon_device *rdev);
1260 extern void r600_cp_fini(struct radeon_device *rdev);
1261 extern int r600_count_pipe_bits(uint32_t val);
1262 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1263 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1264 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1265 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1266 extern int r600_ib_test(struct radeon_device *rdev);
1267 extern int r600_ring_test(struct radeon_device *rdev);
1268 extern void r600_wb_fini(struct radeon_device *rdev);
1269 extern int r600_wb_enable(struct radeon_device *rdev);
1270 extern void r600_wb_disable(struct radeon_device *rdev);
1271 extern void r600_scratch_init(struct radeon_device *rdev);
1272 extern int r600_blit_init(struct radeon_device *rdev);
1273 extern void r600_blit_fini(struct radeon_device *rdev);
1274 extern int r600_init_microcode(struct radeon_device *rdev);
1275 extern int r600_gpu_reset(struct radeon_device *rdev);
1276 /* r600 irq */
1277 extern int r600_irq_init(struct radeon_device *rdev);
1278 extern void r600_irq_fini(struct radeon_device *rdev);
1279 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1280 extern int r600_irq_set(struct radeon_device *rdev);
1281 extern void r600_irq_suspend(struct radeon_device *rdev);
1282 /* r600 audio */
1283 extern int r600_audio_init(struct radeon_device *rdev);
1284 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1285 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1286 extern void r600_audio_fini(struct radeon_device *rdev);
1287 extern void r600_hdmi_init(struct drm_encoder *encoder);
1288 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1289 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1290 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1291 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1292 int channels,
1293 int rate,
1294 int bps,
1295 uint8_t status_bits,
1296 uint8_t category_code);
1297
1298 #include "radeon_object.h"
1299
1300 #endif
Linux kernel - Deliverables
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