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drm/radeon: add a asic callback to get the xclk
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98
99 /*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
110
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 5
113
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
116
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
120
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
124
125 /* R600+ has an async dma ring */
126 #define R600_RING_TYPE_DMA_INDEX 3
127 /* cayman add a second async dma ring */
128 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
129
130 /* hardcode those limit for now */
131 #define RADEON_VA_IB_OFFSET (1 << 20)
132 #define RADEON_VA_RESERVED_SIZE (8 << 20)
133 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
134
135 /* reset flags */
136 #define RADEON_RESET_GFX (1 << 0)
137 #define RADEON_RESET_COMPUTE (1 << 1)
138 #define RADEON_RESET_DMA (1 << 2)
139 #define RADEON_RESET_CP (1 << 3)
140 #define RADEON_RESET_GRBM (1 << 4)
141 #define RADEON_RESET_DMA1 (1 << 5)
142 #define RADEON_RESET_RLC (1 << 6)
143 #define RADEON_RESET_SEM (1 << 7)
144 #define RADEON_RESET_IH (1 << 8)
145 #define RADEON_RESET_VMC (1 << 9)
146 #define RADEON_RESET_MC (1 << 10)
147 #define RADEON_RESET_DISPLAY (1 << 11)
148
149 /*
150 * Errata workarounds.
151 */
152 enum radeon_pll_errata {
153 CHIP_ERRATA_R300_CG = 0x00000001,
154 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
155 CHIP_ERRATA_PLL_DELAY = 0x00000004
156 };
157
158
159 struct radeon_device;
160
161
162 /*
163 * BIOS.
164 */
165 bool radeon_get_bios(struct radeon_device *rdev);
166
167 /*
168 * Dummy page
169 */
170 struct radeon_dummy_page {
171 struct page *page;
172 dma_addr_t addr;
173 };
174 int radeon_dummy_page_init(struct radeon_device *rdev);
175 void radeon_dummy_page_fini(struct radeon_device *rdev);
176
177
178 /*
179 * Clocks
180 */
181 struct radeon_clock {
182 struct radeon_pll p1pll;
183 struct radeon_pll p2pll;
184 struct radeon_pll dcpll;
185 struct radeon_pll spll;
186 struct radeon_pll mpll;
187 /* 10 Khz units */
188 uint32_t default_mclk;
189 uint32_t default_sclk;
190 uint32_t default_dispclk;
191 uint32_t dp_extclk;
192 uint32_t max_pixel_clock;
193 };
194
195 /*
196 * Power management
197 */
198 int radeon_pm_init(struct radeon_device *rdev);
199 void radeon_pm_fini(struct radeon_device *rdev);
200 void radeon_pm_compute_clocks(struct radeon_device *rdev);
201 void radeon_pm_suspend(struct radeon_device *rdev);
202 void radeon_pm_resume(struct radeon_device *rdev);
203 void radeon_combios_get_power_modes(struct radeon_device *rdev);
204 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
205 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
206 void rs690_pm_info(struct radeon_device *rdev);
207 extern int rv6xx_get_temp(struct radeon_device *rdev);
208 extern int rv770_get_temp(struct radeon_device *rdev);
209 extern int evergreen_get_temp(struct radeon_device *rdev);
210 extern int sumo_get_temp(struct radeon_device *rdev);
211 extern int si_get_temp(struct radeon_device *rdev);
212 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
213 unsigned *bankh, unsigned *mtaspect,
214 unsigned *tile_split);
215
216 /*
217 * Fences.
218 */
219 struct radeon_fence_driver {
220 uint32_t scratch_reg;
221 uint64_t gpu_addr;
222 volatile uint32_t *cpu_addr;
223 /* sync_seq is protected by ring emission lock */
224 uint64_t sync_seq[RADEON_NUM_RINGS];
225 atomic64_t last_seq;
226 unsigned long last_activity;
227 bool initialized;
228 };
229
230 struct radeon_fence {
231 struct radeon_device *rdev;
232 struct kref kref;
233 /* protected by radeon_fence.lock */
234 uint64_t seq;
235 /* RB, DMA, etc. */
236 unsigned ring;
237 };
238
239 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
240 int radeon_fence_driver_init(struct radeon_device *rdev);
241 void radeon_fence_driver_fini(struct radeon_device *rdev);
242 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
243 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
244 void radeon_fence_process(struct radeon_device *rdev, int ring);
245 bool radeon_fence_signaled(struct radeon_fence *fence);
246 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
247 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
248 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
249 int radeon_fence_wait_any(struct radeon_device *rdev,
250 struct radeon_fence **fences,
251 bool intr);
252 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
253 void radeon_fence_unref(struct radeon_fence **fence);
254 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
255 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
256 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
257 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
258 struct radeon_fence *b)
259 {
260 if (!a) {
261 return b;
262 }
263
264 if (!b) {
265 return a;
266 }
267
268 BUG_ON(a->ring != b->ring);
269
270 if (a->seq > b->seq) {
271 return a;
272 } else {
273 return b;
274 }
275 }
276
277 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
278 struct radeon_fence *b)
279 {
280 if (!a) {
281 return false;
282 }
283
284 if (!b) {
285 return true;
286 }
287
288 BUG_ON(a->ring != b->ring);
289
290 return a->seq < b->seq;
291 }
292
293 /*
294 * Tiling registers
295 */
296 struct radeon_surface_reg {
297 struct radeon_bo *bo;
298 };
299
300 #define RADEON_GEM_MAX_SURFACES 8
301
302 /*
303 * TTM.
304 */
305 struct radeon_mman {
306 struct ttm_bo_global_ref bo_global_ref;
307 struct drm_global_reference mem_global_ref;
308 struct ttm_bo_device bdev;
309 bool mem_global_referenced;
310 bool initialized;
311 };
312
313 /* bo virtual address in a specific vm */
314 struct radeon_bo_va {
315 /* protected by bo being reserved */
316 struct list_head bo_list;
317 uint64_t soffset;
318 uint64_t eoffset;
319 uint32_t flags;
320 bool valid;
321 unsigned ref_count;
322
323 /* protected by vm mutex */
324 struct list_head vm_list;
325
326 /* constant after initialization */
327 struct radeon_vm *vm;
328 struct radeon_bo *bo;
329 };
330
331 struct radeon_bo {
332 /* Protected by gem.mutex */
333 struct list_head list;
334 /* Protected by tbo.reserved */
335 u32 placements[3];
336 struct ttm_placement placement;
337 struct ttm_buffer_object tbo;
338 struct ttm_bo_kmap_obj kmap;
339 unsigned pin_count;
340 void *kptr;
341 u32 tiling_flags;
342 u32 pitch;
343 int surface_reg;
344 /* list of all virtual address to which this bo
345 * is associated to
346 */
347 struct list_head va;
348 /* Constant after initialization */
349 struct radeon_device *rdev;
350 struct drm_gem_object gem_base;
351
352 struct ttm_bo_kmap_obj dma_buf_vmap;
353 int vmapping_count;
354 };
355 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
356
357 struct radeon_bo_list {
358 struct ttm_validate_buffer tv;
359 struct radeon_bo *bo;
360 uint64_t gpu_offset;
361 unsigned rdomain;
362 unsigned wdomain;
363 u32 tiling_flags;
364 };
365
366 /* sub-allocation manager, it has to be protected by another lock.
367 * By conception this is an helper for other part of the driver
368 * like the indirect buffer or semaphore, which both have their
369 * locking.
370 *
371 * Principe is simple, we keep a list of sub allocation in offset
372 * order (first entry has offset == 0, last entry has the highest
373 * offset).
374 *
375 * When allocating new object we first check if there is room at
376 * the end total_size - (last_object_offset + last_object_size) >=
377 * alloc_size. If so we allocate new object there.
378 *
379 * When there is not enough room at the end, we start waiting for
380 * each sub object until we reach object_offset+object_size >=
381 * alloc_size, this object then become the sub object we return.
382 *
383 * Alignment can't be bigger than page size.
384 *
385 * Hole are not considered for allocation to keep things simple.
386 * Assumption is that there won't be hole (all object on same
387 * alignment).
388 */
389 struct radeon_sa_manager {
390 wait_queue_head_t wq;
391 struct radeon_bo *bo;
392 struct list_head *hole;
393 struct list_head flist[RADEON_NUM_RINGS];
394 struct list_head olist;
395 unsigned size;
396 uint64_t gpu_addr;
397 void *cpu_ptr;
398 uint32_t domain;
399 };
400
401 struct radeon_sa_bo;
402
403 /* sub-allocation buffer */
404 struct radeon_sa_bo {
405 struct list_head olist;
406 struct list_head flist;
407 struct radeon_sa_manager *manager;
408 unsigned soffset;
409 unsigned eoffset;
410 struct radeon_fence *fence;
411 };
412
413 /*
414 * GEM objects.
415 */
416 struct radeon_gem {
417 struct mutex mutex;
418 struct list_head objects;
419 };
420
421 int radeon_gem_init(struct radeon_device *rdev);
422 void radeon_gem_fini(struct radeon_device *rdev);
423 int radeon_gem_object_create(struct radeon_device *rdev, int size,
424 int alignment, int initial_domain,
425 bool discardable, bool kernel,
426 struct drm_gem_object **obj);
427
428 int radeon_mode_dumb_create(struct drm_file *file_priv,
429 struct drm_device *dev,
430 struct drm_mode_create_dumb *args);
431 int radeon_mode_dumb_mmap(struct drm_file *filp,
432 struct drm_device *dev,
433 uint32_t handle, uint64_t *offset_p);
434 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
435 struct drm_device *dev,
436 uint32_t handle);
437
438 /*
439 * Semaphores.
440 */
441 /* everything here is constant */
442 struct radeon_semaphore {
443 struct radeon_sa_bo *sa_bo;
444 signed waiters;
445 uint64_t gpu_addr;
446 };
447
448 int radeon_semaphore_create(struct radeon_device *rdev,
449 struct radeon_semaphore **semaphore);
450 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
451 struct radeon_semaphore *semaphore);
452 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
453 struct radeon_semaphore *semaphore);
454 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
455 struct radeon_semaphore *semaphore,
456 int signaler, int waiter);
457 void radeon_semaphore_free(struct radeon_device *rdev,
458 struct radeon_semaphore **semaphore,
459 struct radeon_fence *fence);
460
461 /*
462 * GART structures, functions & helpers
463 */
464 struct radeon_mc;
465
466 #define RADEON_GPU_PAGE_SIZE 4096
467 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
468 #define RADEON_GPU_PAGE_SHIFT 12
469 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
470
471 struct radeon_gart {
472 dma_addr_t table_addr;
473 struct radeon_bo *robj;
474 void *ptr;
475 unsigned num_gpu_pages;
476 unsigned num_cpu_pages;
477 unsigned table_size;
478 struct page **pages;
479 dma_addr_t *pages_addr;
480 bool ready;
481 };
482
483 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
484 void radeon_gart_table_ram_free(struct radeon_device *rdev);
485 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
486 void radeon_gart_table_vram_free(struct radeon_device *rdev);
487 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
488 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
489 int radeon_gart_init(struct radeon_device *rdev);
490 void radeon_gart_fini(struct radeon_device *rdev);
491 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
492 int pages);
493 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
494 int pages, struct page **pagelist,
495 dma_addr_t *dma_addr);
496 void radeon_gart_restore(struct radeon_device *rdev);
497
498
499 /*
500 * GPU MC structures, functions & helpers
501 */
502 struct radeon_mc {
503 resource_size_t aper_size;
504 resource_size_t aper_base;
505 resource_size_t agp_base;
506 /* for some chips with <= 32MB we need to lie
507 * about vram size near mc fb location */
508 u64 mc_vram_size;
509 u64 visible_vram_size;
510 u64 gtt_size;
511 u64 gtt_start;
512 u64 gtt_end;
513 u64 vram_start;
514 u64 vram_end;
515 unsigned vram_width;
516 u64 real_vram_size;
517 int vram_mtrr;
518 bool vram_is_ddr;
519 bool igp_sideport_enabled;
520 u64 gtt_base_align;
521 };
522
523 bool radeon_combios_sideport_present(struct radeon_device *rdev);
524 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
525
526 /*
527 * GPU scratch registers structures, functions & helpers
528 */
529 struct radeon_scratch {
530 unsigned num_reg;
531 uint32_t reg_base;
532 bool free[32];
533 uint32_t reg[32];
534 };
535
536 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
537 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
538
539
540 /*
541 * IRQS.
542 */
543
544 struct radeon_unpin_work {
545 struct work_struct work;
546 struct radeon_device *rdev;
547 int crtc_id;
548 struct radeon_fence *fence;
549 struct drm_pending_vblank_event *event;
550 struct radeon_bo *old_rbo;
551 u64 new_crtc_base;
552 };
553
554 struct r500_irq_stat_regs {
555 u32 disp_int;
556 u32 hdmi0_status;
557 };
558
559 struct r600_irq_stat_regs {
560 u32 disp_int;
561 u32 disp_int_cont;
562 u32 disp_int_cont2;
563 u32 d1grph_int;
564 u32 d2grph_int;
565 u32 hdmi0_status;
566 u32 hdmi1_status;
567 };
568
569 struct evergreen_irq_stat_regs {
570 u32 disp_int;
571 u32 disp_int_cont;
572 u32 disp_int_cont2;
573 u32 disp_int_cont3;
574 u32 disp_int_cont4;
575 u32 disp_int_cont5;
576 u32 d1grph_int;
577 u32 d2grph_int;
578 u32 d3grph_int;
579 u32 d4grph_int;
580 u32 d5grph_int;
581 u32 d6grph_int;
582 u32 afmt_status1;
583 u32 afmt_status2;
584 u32 afmt_status3;
585 u32 afmt_status4;
586 u32 afmt_status5;
587 u32 afmt_status6;
588 };
589
590 union radeon_irq_stat_regs {
591 struct r500_irq_stat_regs r500;
592 struct r600_irq_stat_regs r600;
593 struct evergreen_irq_stat_regs evergreen;
594 };
595
596 #define RADEON_MAX_HPD_PINS 6
597 #define RADEON_MAX_CRTCS 6
598 #define RADEON_MAX_AFMT_BLOCKS 6
599
600 struct radeon_irq {
601 bool installed;
602 spinlock_t lock;
603 atomic_t ring_int[RADEON_NUM_RINGS];
604 bool crtc_vblank_int[RADEON_MAX_CRTCS];
605 atomic_t pflip[RADEON_MAX_CRTCS];
606 wait_queue_head_t vblank_queue;
607 bool hpd[RADEON_MAX_HPD_PINS];
608 bool afmt[RADEON_MAX_AFMT_BLOCKS];
609 union radeon_irq_stat_regs stat_regs;
610 };
611
612 int radeon_irq_kms_init(struct radeon_device *rdev);
613 void radeon_irq_kms_fini(struct radeon_device *rdev);
614 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
615 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
616 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
617 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
618 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
619 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
620 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
621 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
622
623 /*
624 * CP & rings.
625 */
626
627 struct radeon_ib {
628 struct radeon_sa_bo *sa_bo;
629 uint32_t length_dw;
630 uint64_t gpu_addr;
631 uint32_t *ptr;
632 int ring;
633 struct radeon_fence *fence;
634 struct radeon_vm *vm;
635 bool is_const_ib;
636 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
637 struct radeon_semaphore *semaphore;
638 };
639
640 struct radeon_ring {
641 struct radeon_bo *ring_obj;
642 volatile uint32_t *ring;
643 unsigned rptr;
644 unsigned rptr_offs;
645 unsigned rptr_reg;
646 unsigned rptr_save_reg;
647 u64 next_rptr_gpu_addr;
648 volatile u32 *next_rptr_cpu_addr;
649 unsigned wptr;
650 unsigned wptr_old;
651 unsigned wptr_reg;
652 unsigned ring_size;
653 unsigned ring_free_dw;
654 int count_dw;
655 unsigned long last_activity;
656 unsigned last_rptr;
657 uint64_t gpu_addr;
658 uint32_t align_mask;
659 uint32_t ptr_mask;
660 bool ready;
661 u32 ptr_reg_shift;
662 u32 ptr_reg_mask;
663 u32 nop;
664 u32 idx;
665 u64 last_semaphore_signal_addr;
666 u64 last_semaphore_wait_addr;
667 };
668
669 /*
670 * VM
671 */
672
673 /* maximum number of VMIDs */
674 #define RADEON_NUM_VM 16
675
676 /* defines number of bits in page table versus page directory,
677 * a page is 4KB so we have 12 bits offset, 9 bits in the page
678 * table and the remaining 19 bits are in the page directory */
679 #define RADEON_VM_BLOCK_SIZE 9
680
681 /* number of entries in page table */
682 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
683
684 struct radeon_vm {
685 struct list_head list;
686 struct list_head va;
687 unsigned id;
688
689 /* contains the page directory */
690 struct radeon_sa_bo *page_directory;
691 uint64_t pd_gpu_addr;
692
693 /* array of page tables, one for each page directory entry */
694 struct radeon_sa_bo **page_tables;
695
696 struct mutex mutex;
697 /* last fence for cs using this vm */
698 struct radeon_fence *fence;
699 /* last flush or NULL if we still need to flush */
700 struct radeon_fence *last_flush;
701 };
702
703 struct radeon_vm_manager {
704 struct mutex lock;
705 struct list_head lru_vm;
706 struct radeon_fence *active[RADEON_NUM_VM];
707 struct radeon_sa_manager sa_manager;
708 uint32_t max_pfn;
709 /* number of VMIDs */
710 unsigned nvm;
711 /* vram base address for page table entry */
712 u64 vram_base_offset;
713 /* is vm enabled? */
714 bool enabled;
715 };
716
717 /*
718 * file private structure
719 */
720 struct radeon_fpriv {
721 struct radeon_vm vm;
722 };
723
724 /*
725 * R6xx+ IH ring
726 */
727 struct r600_ih {
728 struct radeon_bo *ring_obj;
729 volatile uint32_t *ring;
730 unsigned rptr;
731 unsigned ring_size;
732 uint64_t gpu_addr;
733 uint32_t ptr_mask;
734 atomic_t lock;
735 bool enabled;
736 };
737
738 struct r600_blit_cp_primitives {
739 void (*set_render_target)(struct radeon_device *rdev, int format,
740 int w, int h, u64 gpu_addr);
741 void (*cp_set_surface_sync)(struct radeon_device *rdev,
742 u32 sync_type, u32 size,
743 u64 mc_addr);
744 void (*set_shaders)(struct radeon_device *rdev);
745 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
746 void (*set_tex_resource)(struct radeon_device *rdev,
747 int format, int w, int h, int pitch,
748 u64 gpu_addr, u32 size);
749 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
750 int x2, int y2);
751 void (*draw_auto)(struct radeon_device *rdev);
752 void (*set_default_state)(struct radeon_device *rdev);
753 };
754
755 struct r600_blit {
756 struct radeon_bo *shader_obj;
757 struct r600_blit_cp_primitives primitives;
758 int max_dim;
759 int ring_size_common;
760 int ring_size_per_loop;
761 u64 shader_gpu_addr;
762 u32 vs_offset, ps_offset;
763 u32 state_offset;
764 u32 state_len;
765 };
766
767 /*
768 * SI RLC stuff
769 */
770 struct si_rlc {
771 /* for power gating */
772 struct radeon_bo *save_restore_obj;
773 uint64_t save_restore_gpu_addr;
774 /* for clear state */
775 struct radeon_bo *clear_state_obj;
776 uint64_t clear_state_gpu_addr;
777 };
778
779 int radeon_ib_get(struct radeon_device *rdev, int ring,
780 struct radeon_ib *ib, struct radeon_vm *vm,
781 unsigned size);
782 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
783 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
784 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
785 struct radeon_ib *const_ib);
786 int radeon_ib_pool_init(struct radeon_device *rdev);
787 void radeon_ib_pool_fini(struct radeon_device *rdev);
788 int radeon_ib_ring_tests(struct radeon_device *rdev);
789 /* Ring access between begin & end cannot sleep */
790 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
791 struct radeon_ring *ring);
792 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
793 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
794 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
795 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
796 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
797 void radeon_ring_undo(struct radeon_ring *ring);
798 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
799 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
800 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
801 void radeon_ring_lockup_update(struct radeon_ring *ring);
802 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
803 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
804 uint32_t **data);
805 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
806 unsigned size, uint32_t *data);
807 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
808 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
809 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
810 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
811
812
813 /* r600 async dma */
814 void r600_dma_stop(struct radeon_device *rdev);
815 int r600_dma_resume(struct radeon_device *rdev);
816 void r600_dma_fini(struct radeon_device *rdev);
817
818 void cayman_dma_stop(struct radeon_device *rdev);
819 int cayman_dma_resume(struct radeon_device *rdev);
820 void cayman_dma_fini(struct radeon_device *rdev);
821
822 /*
823 * CS.
824 */
825 struct radeon_cs_reloc {
826 struct drm_gem_object *gobj;
827 struct radeon_bo *robj;
828 struct radeon_bo_list lobj;
829 uint32_t handle;
830 uint32_t flags;
831 };
832
833 struct radeon_cs_chunk {
834 uint32_t chunk_id;
835 uint32_t length_dw;
836 int kpage_idx[2];
837 uint32_t *kpage[2];
838 uint32_t *kdata;
839 void __user *user_ptr;
840 int last_copied_page;
841 int last_page_index;
842 };
843
844 struct radeon_cs_parser {
845 struct device *dev;
846 struct radeon_device *rdev;
847 struct drm_file *filp;
848 /* chunks */
849 unsigned nchunks;
850 struct radeon_cs_chunk *chunks;
851 uint64_t *chunks_array;
852 /* IB */
853 unsigned idx;
854 /* relocations */
855 unsigned nrelocs;
856 struct radeon_cs_reloc *relocs;
857 struct radeon_cs_reloc **relocs_ptr;
858 struct list_head validated;
859 unsigned dma_reloc_idx;
860 /* indices of various chunks */
861 int chunk_ib_idx;
862 int chunk_relocs_idx;
863 int chunk_flags_idx;
864 int chunk_const_ib_idx;
865 struct radeon_ib ib;
866 struct radeon_ib const_ib;
867 void *track;
868 unsigned family;
869 int parser_error;
870 u32 cs_flags;
871 u32 ring;
872 s32 priority;
873 };
874
875 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
876 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
877
878 struct radeon_cs_packet {
879 unsigned idx;
880 unsigned type;
881 unsigned reg;
882 unsigned opcode;
883 int count;
884 unsigned one_reg_wr;
885 };
886
887 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
888 struct radeon_cs_packet *pkt,
889 unsigned idx, unsigned reg);
890 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
891 struct radeon_cs_packet *pkt);
892
893
894 /*
895 * AGP
896 */
897 int radeon_agp_init(struct radeon_device *rdev);
898 void radeon_agp_resume(struct radeon_device *rdev);
899 void radeon_agp_suspend(struct radeon_device *rdev);
900 void radeon_agp_fini(struct radeon_device *rdev);
901
902
903 /*
904 * Writeback
905 */
906 struct radeon_wb {
907 struct radeon_bo *wb_obj;
908 volatile uint32_t *wb;
909 uint64_t gpu_addr;
910 bool enabled;
911 bool use_event;
912 };
913
914 #define RADEON_WB_SCRATCH_OFFSET 0
915 #define RADEON_WB_RING0_NEXT_RPTR 256
916 #define RADEON_WB_CP_RPTR_OFFSET 1024
917 #define RADEON_WB_CP1_RPTR_OFFSET 1280
918 #define RADEON_WB_CP2_RPTR_OFFSET 1536
919 #define R600_WB_DMA_RPTR_OFFSET 1792
920 #define R600_WB_IH_WPTR_OFFSET 2048
921 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
922 #define R600_WB_EVENT_OFFSET 3072
923
924 /**
925 * struct radeon_pm - power management datas
926 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
927 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
928 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
929 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
930 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
931 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
932 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
933 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
934 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
935 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
936 * @needed_bandwidth: current bandwidth needs
937 *
938 * It keeps track of various data needed to take powermanagement decision.
939 * Bandwidth need is used to determine minimun clock of the GPU and memory.
940 * Equation between gpu/memory clock and available bandwidth is hw dependent
941 * (type of memory, bus size, efficiency, ...)
942 */
943
944 enum radeon_pm_method {
945 PM_METHOD_PROFILE,
946 PM_METHOD_DYNPM,
947 };
948
949 enum radeon_dynpm_state {
950 DYNPM_STATE_DISABLED,
951 DYNPM_STATE_MINIMUM,
952 DYNPM_STATE_PAUSED,
953 DYNPM_STATE_ACTIVE,
954 DYNPM_STATE_SUSPENDED,
955 };
956 enum radeon_dynpm_action {
957 DYNPM_ACTION_NONE,
958 DYNPM_ACTION_MINIMUM,
959 DYNPM_ACTION_DOWNCLOCK,
960 DYNPM_ACTION_UPCLOCK,
961 DYNPM_ACTION_DEFAULT
962 };
963
964 enum radeon_voltage_type {
965 VOLTAGE_NONE = 0,
966 VOLTAGE_GPIO,
967 VOLTAGE_VDDC,
968 VOLTAGE_SW
969 };
970
971 enum radeon_pm_state_type {
972 POWER_STATE_TYPE_DEFAULT,
973 POWER_STATE_TYPE_POWERSAVE,
974 POWER_STATE_TYPE_BATTERY,
975 POWER_STATE_TYPE_BALANCED,
976 POWER_STATE_TYPE_PERFORMANCE,
977 };
978
979 enum radeon_pm_profile_type {
980 PM_PROFILE_DEFAULT,
981 PM_PROFILE_AUTO,
982 PM_PROFILE_LOW,
983 PM_PROFILE_MID,
984 PM_PROFILE_HIGH,
985 };
986
987 #define PM_PROFILE_DEFAULT_IDX 0
988 #define PM_PROFILE_LOW_SH_IDX 1
989 #define PM_PROFILE_MID_SH_IDX 2
990 #define PM_PROFILE_HIGH_SH_IDX 3
991 #define PM_PROFILE_LOW_MH_IDX 4
992 #define PM_PROFILE_MID_MH_IDX 5
993 #define PM_PROFILE_HIGH_MH_IDX 6
994 #define PM_PROFILE_MAX 7
995
996 struct radeon_pm_profile {
997 int dpms_off_ps_idx;
998 int dpms_on_ps_idx;
999 int dpms_off_cm_idx;
1000 int dpms_on_cm_idx;
1001 };
1002
1003 enum radeon_int_thermal_type {
1004 THERMAL_TYPE_NONE,
1005 THERMAL_TYPE_RV6XX,
1006 THERMAL_TYPE_RV770,
1007 THERMAL_TYPE_EVERGREEN,
1008 THERMAL_TYPE_SUMO,
1009 THERMAL_TYPE_NI,
1010 THERMAL_TYPE_SI,
1011 };
1012
1013 struct radeon_voltage {
1014 enum radeon_voltage_type type;
1015 /* gpio voltage */
1016 struct radeon_gpio_rec gpio;
1017 u32 delay; /* delay in usec from voltage drop to sclk change */
1018 bool active_high; /* voltage drop is active when bit is high */
1019 /* VDDC voltage */
1020 u8 vddc_id; /* index into vddc voltage table */
1021 u8 vddci_id; /* index into vddci voltage table */
1022 bool vddci_enabled;
1023 /* r6xx+ sw */
1024 u16 voltage;
1025 /* evergreen+ vddci */
1026 u16 vddci;
1027 };
1028
1029 /* clock mode flags */
1030 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1031
1032 struct radeon_pm_clock_info {
1033 /* memory clock */
1034 u32 mclk;
1035 /* engine clock */
1036 u32 sclk;
1037 /* voltage info */
1038 struct radeon_voltage voltage;
1039 /* standardized clock flags */
1040 u32 flags;
1041 };
1042
1043 /* state flags */
1044 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1045
1046 struct radeon_power_state {
1047 enum radeon_pm_state_type type;
1048 struct radeon_pm_clock_info *clock_info;
1049 /* number of valid clock modes in this power state */
1050 int num_clock_modes;
1051 struct radeon_pm_clock_info *default_clock_mode;
1052 /* standardized state flags */
1053 u32 flags;
1054 u32 misc; /* vbios specific flags */
1055 u32 misc2; /* vbios specific flags */
1056 int pcie_lanes; /* pcie lanes */
1057 };
1058
1059 /*
1060 * Some modes are overclocked by very low value, accept them
1061 */
1062 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1063
1064 struct radeon_pm {
1065 struct mutex mutex;
1066 /* write locked while reprogramming mclk */
1067 struct rw_semaphore mclk_lock;
1068 u32 active_crtcs;
1069 int active_crtc_count;
1070 int req_vblank;
1071 bool vblank_sync;
1072 fixed20_12 max_bandwidth;
1073 fixed20_12 igp_sideport_mclk;
1074 fixed20_12 igp_system_mclk;
1075 fixed20_12 igp_ht_link_clk;
1076 fixed20_12 igp_ht_link_width;
1077 fixed20_12 k8_bandwidth;
1078 fixed20_12 sideport_bandwidth;
1079 fixed20_12 ht_bandwidth;
1080 fixed20_12 core_bandwidth;
1081 fixed20_12 sclk;
1082 fixed20_12 mclk;
1083 fixed20_12 needed_bandwidth;
1084 struct radeon_power_state *power_state;
1085 /* number of valid power states */
1086 int num_power_states;
1087 int current_power_state_index;
1088 int current_clock_mode_index;
1089 int requested_power_state_index;
1090 int requested_clock_mode_index;
1091 int default_power_state_index;
1092 u32 current_sclk;
1093 u32 current_mclk;
1094 u16 current_vddc;
1095 u16 current_vddci;
1096 u32 default_sclk;
1097 u32 default_mclk;
1098 u16 default_vddc;
1099 u16 default_vddci;
1100 struct radeon_i2c_chan *i2c_bus;
1101 /* selected pm method */
1102 enum radeon_pm_method pm_method;
1103 /* dynpm power management */
1104 struct delayed_work dynpm_idle_work;
1105 enum radeon_dynpm_state dynpm_state;
1106 enum radeon_dynpm_action dynpm_planned_action;
1107 unsigned long dynpm_action_timeout;
1108 bool dynpm_can_upclock;
1109 bool dynpm_can_downclock;
1110 /* profile-based power management */
1111 enum radeon_pm_profile_type profile;
1112 int profile_index;
1113 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1114 /* internal thermal controller on rv6xx+ */
1115 enum radeon_int_thermal_type int_thermal_type;
1116 struct device *int_hwmon_dev;
1117 };
1118
1119 int radeon_pm_get_type_index(struct radeon_device *rdev,
1120 enum radeon_pm_state_type ps_type,
1121 int instance);
1122
1123 struct r600_audio {
1124 int channels;
1125 int rate;
1126 int bits_per_sample;
1127 u8 status_bits;
1128 u8 category_code;
1129 };
1130
1131 /*
1132 * Benchmarking
1133 */
1134 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1135
1136
1137 /*
1138 * Testing
1139 */
1140 void radeon_test_moves(struct radeon_device *rdev);
1141 void radeon_test_ring_sync(struct radeon_device *rdev,
1142 struct radeon_ring *cpA,
1143 struct radeon_ring *cpB);
1144 void radeon_test_syncing(struct radeon_device *rdev);
1145
1146
1147 /*
1148 * Debugfs
1149 */
1150 struct radeon_debugfs {
1151 struct drm_info_list *files;
1152 unsigned num_files;
1153 };
1154
1155 int radeon_debugfs_add_files(struct radeon_device *rdev,
1156 struct drm_info_list *files,
1157 unsigned nfiles);
1158 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1159
1160
1161 /*
1162 * ASIC specific functions.
1163 */
1164 struct radeon_asic {
1165 int (*init)(struct radeon_device *rdev);
1166 void (*fini)(struct radeon_device *rdev);
1167 int (*resume)(struct radeon_device *rdev);
1168 int (*suspend)(struct radeon_device *rdev);
1169 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1170 int (*asic_reset)(struct radeon_device *rdev);
1171 /* ioctl hw specific callback. Some hw might want to perform special
1172 * operation on specific ioctl. For instance on wait idle some hw
1173 * might want to perform and HDP flush through MMIO as it seems that
1174 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1175 * through ring.
1176 */
1177 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1178 /* check if 3D engine is idle */
1179 bool (*gui_idle)(struct radeon_device *rdev);
1180 /* wait for mc_idle */
1181 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1182 /* get the reference clock */
1183 u32 (*get_xclk)(struct radeon_device *rdev);
1184 /* gart */
1185 struct {
1186 void (*tlb_flush)(struct radeon_device *rdev);
1187 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1188 } gart;
1189 struct {
1190 int (*init)(struct radeon_device *rdev);
1191 void (*fini)(struct radeon_device *rdev);
1192
1193 u32 pt_ring_index;
1194 void (*set_page)(struct radeon_device *rdev,
1195 struct radeon_ib *ib,
1196 uint64_t pe,
1197 uint64_t addr, unsigned count,
1198 uint32_t incr, uint32_t flags);
1199 } vm;
1200 /* ring specific callbacks */
1201 struct {
1202 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1203 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1204 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1205 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1206 struct radeon_semaphore *semaphore, bool emit_wait);
1207 int (*cs_parse)(struct radeon_cs_parser *p);
1208 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1209 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1210 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1211 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1212 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1213 } ring[RADEON_NUM_RINGS];
1214 /* irqs */
1215 struct {
1216 int (*set)(struct radeon_device *rdev);
1217 int (*process)(struct radeon_device *rdev);
1218 } irq;
1219 /* displays */
1220 struct {
1221 /* display watermarks */
1222 void (*bandwidth_update)(struct radeon_device *rdev);
1223 /* get frame count */
1224 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1225 /* wait for vblank */
1226 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1227 /* set backlight level */
1228 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1229 /* get backlight level */
1230 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1231 } display;
1232 /* copy functions for bo handling */
1233 struct {
1234 int (*blit)(struct radeon_device *rdev,
1235 uint64_t src_offset,
1236 uint64_t dst_offset,
1237 unsigned num_gpu_pages,
1238 struct radeon_fence **fence);
1239 u32 blit_ring_index;
1240 int (*dma)(struct radeon_device *rdev,
1241 uint64_t src_offset,
1242 uint64_t dst_offset,
1243 unsigned num_gpu_pages,
1244 struct radeon_fence **fence);
1245 u32 dma_ring_index;
1246 /* method used for bo copy */
1247 int (*copy)(struct radeon_device *rdev,
1248 uint64_t src_offset,
1249 uint64_t dst_offset,
1250 unsigned num_gpu_pages,
1251 struct radeon_fence **fence);
1252 /* ring used for bo copies */
1253 u32 copy_ring_index;
1254 } copy;
1255 /* surfaces */
1256 struct {
1257 int (*set_reg)(struct radeon_device *rdev, int reg,
1258 uint32_t tiling_flags, uint32_t pitch,
1259 uint32_t offset, uint32_t obj_size);
1260 void (*clear_reg)(struct radeon_device *rdev, int reg);
1261 } surface;
1262 /* hotplug detect */
1263 struct {
1264 void (*init)(struct radeon_device *rdev);
1265 void (*fini)(struct radeon_device *rdev);
1266 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1267 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1268 } hpd;
1269 /* power management */
1270 struct {
1271 void (*misc)(struct radeon_device *rdev);
1272 void (*prepare)(struct radeon_device *rdev);
1273 void (*finish)(struct radeon_device *rdev);
1274 void (*init_profile)(struct radeon_device *rdev);
1275 void (*get_dynpm_state)(struct radeon_device *rdev);
1276 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1277 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1278 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1279 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1280 int (*get_pcie_lanes)(struct radeon_device *rdev);
1281 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1282 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1283 } pm;
1284 /* pageflipping */
1285 struct {
1286 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1287 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1288 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1289 } pflip;
1290 };
1291
1292 /*
1293 * Asic structures
1294 */
1295 struct r100_asic {
1296 const unsigned *reg_safe_bm;
1297 unsigned reg_safe_bm_size;
1298 u32 hdp_cntl;
1299 };
1300
1301 struct r300_asic {
1302 const unsigned *reg_safe_bm;
1303 unsigned reg_safe_bm_size;
1304 u32 resync_scratch;
1305 u32 hdp_cntl;
1306 };
1307
1308 struct r600_asic {
1309 unsigned max_pipes;
1310 unsigned max_tile_pipes;
1311 unsigned max_simds;
1312 unsigned max_backends;
1313 unsigned max_gprs;
1314 unsigned max_threads;
1315 unsigned max_stack_entries;
1316 unsigned max_hw_contexts;
1317 unsigned max_gs_threads;
1318 unsigned sx_max_export_size;
1319 unsigned sx_max_export_pos_size;
1320 unsigned sx_max_export_smx_size;
1321 unsigned sq_num_cf_insts;
1322 unsigned tiling_nbanks;
1323 unsigned tiling_npipes;
1324 unsigned tiling_group_size;
1325 unsigned tile_config;
1326 unsigned backend_map;
1327 };
1328
1329 struct rv770_asic {
1330 unsigned max_pipes;
1331 unsigned max_tile_pipes;
1332 unsigned max_simds;
1333 unsigned max_backends;
1334 unsigned max_gprs;
1335 unsigned max_threads;
1336 unsigned max_stack_entries;
1337 unsigned max_hw_contexts;
1338 unsigned max_gs_threads;
1339 unsigned sx_max_export_size;
1340 unsigned sx_max_export_pos_size;
1341 unsigned sx_max_export_smx_size;
1342 unsigned sq_num_cf_insts;
1343 unsigned sx_num_of_sets;
1344 unsigned sc_prim_fifo_size;
1345 unsigned sc_hiz_tile_fifo_size;
1346 unsigned sc_earlyz_tile_fifo_fize;
1347 unsigned tiling_nbanks;
1348 unsigned tiling_npipes;
1349 unsigned tiling_group_size;
1350 unsigned tile_config;
1351 unsigned backend_map;
1352 };
1353
1354 struct evergreen_asic {
1355 unsigned num_ses;
1356 unsigned max_pipes;
1357 unsigned max_tile_pipes;
1358 unsigned max_simds;
1359 unsigned max_backends;
1360 unsigned max_gprs;
1361 unsigned max_threads;
1362 unsigned max_stack_entries;
1363 unsigned max_hw_contexts;
1364 unsigned max_gs_threads;
1365 unsigned sx_max_export_size;
1366 unsigned sx_max_export_pos_size;
1367 unsigned sx_max_export_smx_size;
1368 unsigned sq_num_cf_insts;
1369 unsigned sx_num_of_sets;
1370 unsigned sc_prim_fifo_size;
1371 unsigned sc_hiz_tile_fifo_size;
1372 unsigned sc_earlyz_tile_fifo_size;
1373 unsigned tiling_nbanks;
1374 unsigned tiling_npipes;
1375 unsigned tiling_group_size;
1376 unsigned tile_config;
1377 unsigned backend_map;
1378 };
1379
1380 struct cayman_asic {
1381 unsigned max_shader_engines;
1382 unsigned max_pipes_per_simd;
1383 unsigned max_tile_pipes;
1384 unsigned max_simds_per_se;
1385 unsigned max_backends_per_se;
1386 unsigned max_texture_channel_caches;
1387 unsigned max_gprs;
1388 unsigned max_threads;
1389 unsigned max_gs_threads;
1390 unsigned max_stack_entries;
1391 unsigned sx_num_of_sets;
1392 unsigned sx_max_export_size;
1393 unsigned sx_max_export_pos_size;
1394 unsigned sx_max_export_smx_size;
1395 unsigned max_hw_contexts;
1396 unsigned sq_num_cf_insts;
1397 unsigned sc_prim_fifo_size;
1398 unsigned sc_hiz_tile_fifo_size;
1399 unsigned sc_earlyz_tile_fifo_size;
1400
1401 unsigned num_shader_engines;
1402 unsigned num_shader_pipes_per_simd;
1403 unsigned num_tile_pipes;
1404 unsigned num_simds_per_se;
1405 unsigned num_backends_per_se;
1406 unsigned backend_disable_mask_per_asic;
1407 unsigned backend_map;
1408 unsigned num_texture_channel_caches;
1409 unsigned mem_max_burst_length_bytes;
1410 unsigned mem_row_size_in_kb;
1411 unsigned shader_engine_tile_size;
1412 unsigned num_gpus;
1413 unsigned multi_gpu_tile_size;
1414
1415 unsigned tile_config;
1416 };
1417
1418 struct si_asic {
1419 unsigned max_shader_engines;
1420 unsigned max_tile_pipes;
1421 unsigned max_cu_per_sh;
1422 unsigned max_sh_per_se;
1423 unsigned max_backends_per_se;
1424 unsigned max_texture_channel_caches;
1425 unsigned max_gprs;
1426 unsigned max_gs_threads;
1427 unsigned max_hw_contexts;
1428 unsigned sc_prim_fifo_size_frontend;
1429 unsigned sc_prim_fifo_size_backend;
1430 unsigned sc_hiz_tile_fifo_size;
1431 unsigned sc_earlyz_tile_fifo_size;
1432
1433 unsigned num_tile_pipes;
1434 unsigned num_backends_per_se;
1435 unsigned backend_disable_mask_per_asic;
1436 unsigned backend_map;
1437 unsigned num_texture_channel_caches;
1438 unsigned mem_max_burst_length_bytes;
1439 unsigned mem_row_size_in_kb;
1440 unsigned shader_engine_tile_size;
1441 unsigned num_gpus;
1442 unsigned multi_gpu_tile_size;
1443
1444 unsigned tile_config;
1445 };
1446
1447 union radeon_asic_config {
1448 struct r300_asic r300;
1449 struct r100_asic r100;
1450 struct r600_asic r600;
1451 struct rv770_asic rv770;
1452 struct evergreen_asic evergreen;
1453 struct cayman_asic cayman;
1454 struct si_asic si;
1455 };
1456
1457 /*
1458 * asic initizalization from radeon_asic.c
1459 */
1460 void radeon_agp_disable(struct radeon_device *rdev);
1461 int radeon_asic_init(struct radeon_device *rdev);
1462
1463
1464 /*
1465 * IOCTL.
1466 */
1467 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *filp);
1469 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1470 struct drm_file *filp);
1471 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1472 struct drm_file *file_priv);
1473 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1474 struct drm_file *file_priv);
1475 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1476 struct drm_file *file_priv);
1477 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1478 struct drm_file *file_priv);
1479 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1480 struct drm_file *filp);
1481 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1482 struct drm_file *filp);
1483 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1484 struct drm_file *filp);
1485 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1486 struct drm_file *filp);
1487 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1488 struct drm_file *filp);
1489 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1490 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *filp);
1492 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1493 struct drm_file *filp);
1494
1495 /* VRAM scratch page for HDP bug, default vram page */
1496 struct r600_vram_scratch {
1497 struct radeon_bo *robj;
1498 volatile uint32_t *ptr;
1499 u64 gpu_addr;
1500 };
1501
1502 /*
1503 * ACPI
1504 */
1505 struct radeon_atif_notification_cfg {
1506 bool enabled;
1507 int command_code;
1508 };
1509
1510 struct radeon_atif_notifications {
1511 bool display_switch;
1512 bool expansion_mode_change;
1513 bool thermal_state;
1514 bool forced_power_state;
1515 bool system_power_state;
1516 bool display_conf_change;
1517 bool px_gfx_switch;
1518 bool brightness_change;
1519 bool dgpu_display_event;
1520 };
1521
1522 struct radeon_atif_functions {
1523 bool system_params;
1524 bool sbios_requests;
1525 bool select_active_disp;
1526 bool lid_state;
1527 bool get_tv_standard;
1528 bool set_tv_standard;
1529 bool get_panel_expansion_mode;
1530 bool set_panel_expansion_mode;
1531 bool temperature_change;
1532 bool graphics_device_types;
1533 };
1534
1535 struct radeon_atif {
1536 struct radeon_atif_notifications notifications;
1537 struct radeon_atif_functions functions;
1538 struct radeon_atif_notification_cfg notification_cfg;
1539 struct radeon_encoder *encoder_for_bl;
1540 };
1541
1542 struct radeon_atcs_functions {
1543 bool get_ext_state;
1544 bool pcie_perf_req;
1545 bool pcie_dev_rdy;
1546 bool pcie_bus_width;
1547 };
1548
1549 struct radeon_atcs {
1550 struct radeon_atcs_functions functions;
1551 };
1552
1553 /*
1554 * Core structure, functions and helpers.
1555 */
1556 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1557 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1558
1559 struct radeon_device {
1560 struct device *dev;
1561 struct drm_device *ddev;
1562 struct pci_dev *pdev;
1563 struct rw_semaphore exclusive_lock;
1564 /* ASIC */
1565 union radeon_asic_config config;
1566 enum radeon_family family;
1567 unsigned long flags;
1568 int usec_timeout;
1569 enum radeon_pll_errata pll_errata;
1570 int num_gb_pipes;
1571 int num_z_pipes;
1572 int disp_priority;
1573 /* BIOS */
1574 uint8_t *bios;
1575 bool is_atom_bios;
1576 uint16_t bios_header_start;
1577 struct radeon_bo *stollen_vga_memory;
1578 /* Register mmio */
1579 resource_size_t rmmio_base;
1580 resource_size_t rmmio_size;
1581 /* protects concurrent MM_INDEX/DATA based register access */
1582 spinlock_t mmio_idx_lock;
1583 void __iomem *rmmio;
1584 radeon_rreg_t mc_rreg;
1585 radeon_wreg_t mc_wreg;
1586 radeon_rreg_t pll_rreg;
1587 radeon_wreg_t pll_wreg;
1588 uint32_t pcie_reg_mask;
1589 radeon_rreg_t pciep_rreg;
1590 radeon_wreg_t pciep_wreg;
1591 /* io port */
1592 void __iomem *rio_mem;
1593 resource_size_t rio_mem_size;
1594 struct radeon_clock clock;
1595 struct radeon_mc mc;
1596 struct radeon_gart gart;
1597 struct radeon_mode_info mode_info;
1598 struct radeon_scratch scratch;
1599 struct radeon_mman mman;
1600 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1601 wait_queue_head_t fence_queue;
1602 struct mutex ring_lock;
1603 struct radeon_ring ring[RADEON_NUM_RINGS];
1604 bool ib_pool_ready;
1605 struct radeon_sa_manager ring_tmp_bo;
1606 struct radeon_irq irq;
1607 struct radeon_asic *asic;
1608 struct radeon_gem gem;
1609 struct radeon_pm pm;
1610 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1611 struct radeon_wb wb;
1612 struct radeon_dummy_page dummy_page;
1613 bool shutdown;
1614 bool suspend;
1615 bool need_dma32;
1616 bool accel_working;
1617 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1618 const struct firmware *me_fw; /* all family ME firmware */
1619 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1620 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1621 const struct firmware *mc_fw; /* NI MC firmware */
1622 const struct firmware *ce_fw; /* SI CE firmware */
1623 struct r600_blit r600_blit;
1624 struct r600_vram_scratch vram_scratch;
1625 int msi_enabled; /* msi enabled */
1626 struct r600_ih ih; /* r6/700 interrupt ring */
1627 struct si_rlc rlc;
1628 struct work_struct hotplug_work;
1629 struct work_struct audio_work;
1630 int num_crtc; /* number of crtcs */
1631 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1632 bool audio_enabled;
1633 struct r600_audio audio_status; /* audio stuff */
1634 struct notifier_block acpi_nb;
1635 /* only one userspace can use Hyperz features or CMASK at a time */
1636 struct drm_file *hyperz_filp;
1637 struct drm_file *cmask_filp;
1638 /* i2c buses */
1639 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1640 /* debugfs */
1641 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1642 unsigned debugfs_count;
1643 /* virtual memory */
1644 struct radeon_vm_manager vm_manager;
1645 struct mutex gpu_clock_mutex;
1646 /* ACPI interface */
1647 struct radeon_atif atif;
1648 struct radeon_atcs atcs;
1649 };
1650
1651 int radeon_device_init(struct radeon_device *rdev,
1652 struct drm_device *ddev,
1653 struct pci_dev *pdev,
1654 uint32_t flags);
1655 void radeon_device_fini(struct radeon_device *rdev);
1656 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1657
1658 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1659 bool always_indirect);
1660 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1661 bool always_indirect);
1662 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1663 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1664
1665 /*
1666 * Cast helper
1667 */
1668 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1669
1670 /*
1671 * Registers read & write functions.
1672 */
1673 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1674 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1675 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1676 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1677 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1678 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1679 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1680 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1681 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1682 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1683 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1684 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1685 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1686 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1687 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1688 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1689 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1690 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1691 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1692 #define WREG32_P(reg, val, mask) \
1693 do { \
1694 uint32_t tmp_ = RREG32(reg); \
1695 tmp_ &= (mask); \
1696 tmp_ |= ((val) & ~(mask)); \
1697 WREG32(reg, tmp_); \
1698 } while (0)
1699 #define WREG32_PLL_P(reg, val, mask) \
1700 do { \
1701 uint32_t tmp_ = RREG32_PLL(reg); \
1702 tmp_ &= (mask); \
1703 tmp_ |= ((val) & ~(mask)); \
1704 WREG32_PLL(reg, tmp_); \
1705 } while (0)
1706 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1707 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1708 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1709
1710 /*
1711 * Indirect registers accessor
1712 */
1713 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1714 {
1715 uint32_t r;
1716
1717 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1718 r = RREG32(RADEON_PCIE_DATA);
1719 return r;
1720 }
1721
1722 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1723 {
1724 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1725 WREG32(RADEON_PCIE_DATA, (v));
1726 }
1727
1728 void r100_pll_errata_after_index(struct radeon_device *rdev);
1729
1730
1731 /*
1732 * ASICs helpers.
1733 */
1734 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1735 (rdev->pdev->device == 0x5969))
1736 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1737 (rdev->family == CHIP_RV200) || \
1738 (rdev->family == CHIP_RS100) || \
1739 (rdev->family == CHIP_RS200) || \
1740 (rdev->family == CHIP_RV250) || \
1741 (rdev->family == CHIP_RV280) || \
1742 (rdev->family == CHIP_RS300))
1743 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1744 (rdev->family == CHIP_RV350) || \
1745 (rdev->family == CHIP_R350) || \
1746 (rdev->family == CHIP_RV380) || \
1747 (rdev->family == CHIP_R420) || \
1748 (rdev->family == CHIP_R423) || \
1749 (rdev->family == CHIP_RV410) || \
1750 (rdev->family == CHIP_RS400) || \
1751 (rdev->family == CHIP_RS480))
1752 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1753 (rdev->ddev->pdev->device == 0x9443) || \
1754 (rdev->ddev->pdev->device == 0x944B) || \
1755 (rdev->ddev->pdev->device == 0x9506) || \
1756 (rdev->ddev->pdev->device == 0x9509) || \
1757 (rdev->ddev->pdev->device == 0x950F) || \
1758 (rdev->ddev->pdev->device == 0x689C) || \
1759 (rdev->ddev->pdev->device == 0x689D))
1760 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1761 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1762 (rdev->family == CHIP_RS690) || \
1763 (rdev->family == CHIP_RS740) || \
1764 (rdev->family >= CHIP_R600))
1765 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1766 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1767 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1768 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1769 (rdev->flags & RADEON_IS_IGP))
1770 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1771 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1772 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1773 (rdev->flags & RADEON_IS_IGP))
1774 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1775
1776 /*
1777 * BIOS helpers.
1778 */
1779 #define RBIOS8(i) (rdev->bios[i])
1780 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1781 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1782
1783 int radeon_combios_init(struct radeon_device *rdev);
1784 void radeon_combios_fini(struct radeon_device *rdev);
1785 int radeon_atombios_init(struct radeon_device *rdev);
1786 void radeon_atombios_fini(struct radeon_device *rdev);
1787
1788
1789 /*
1790 * RING helpers.
1791 */
1792 #if DRM_DEBUG_CODE == 0
1793 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1794 {
1795 ring->ring[ring->wptr++] = v;
1796 ring->wptr &= ring->ptr_mask;
1797 ring->count_dw--;
1798 ring->ring_free_dw--;
1799 }
1800 #else
1801 /* With debugging this is just too big to inline */
1802 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1803 #endif
1804
1805 /*
1806 * ASICs macro.
1807 */
1808 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1809 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1810 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1811 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1812 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1813 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1814 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1815 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1816 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1817 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1818 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1819 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1820 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1821 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1822 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1823 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1824 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1825 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1826 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1827 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1828 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1829 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1830 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1831 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1832 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1833 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1834 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1835 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1836 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1837 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1838 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1839 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1840 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1841 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1842 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1843 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1844 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1845 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1846 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1847 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1848 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1849 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1850 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1851 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1852 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1853 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1854 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1855 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1856 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1857 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1858 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1859 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1860 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1861 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1862 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1863 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1864 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1865 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1866
1867 /* Common functions */
1868 /* AGP */
1869 extern int radeon_gpu_reset(struct radeon_device *rdev);
1870 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1871 extern void radeon_agp_disable(struct radeon_device *rdev);
1872 extern int radeon_modeset_init(struct radeon_device *rdev);
1873 extern void radeon_modeset_fini(struct radeon_device *rdev);
1874 extern bool radeon_card_posted(struct radeon_device *rdev);
1875 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1876 extern void radeon_update_display_priority(struct radeon_device *rdev);
1877 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1878 extern void radeon_scratch_init(struct radeon_device *rdev);
1879 extern void radeon_wb_fini(struct radeon_device *rdev);
1880 extern int radeon_wb_init(struct radeon_device *rdev);
1881 extern void radeon_wb_disable(struct radeon_device *rdev);
1882 extern void radeon_surface_init(struct radeon_device *rdev);
1883 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1884 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1885 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1886 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1887 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1888 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1889 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1890 extern int radeon_resume_kms(struct drm_device *dev);
1891 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1892 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1893
1894 /*
1895 * vm
1896 */
1897 int radeon_vm_manager_init(struct radeon_device *rdev);
1898 void radeon_vm_manager_fini(struct radeon_device *rdev);
1899 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1900 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1901 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1902 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1903 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1904 struct radeon_vm *vm, int ring);
1905 void radeon_vm_fence(struct radeon_device *rdev,
1906 struct radeon_vm *vm,
1907 struct radeon_fence *fence);
1908 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1909 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1910 struct radeon_vm *vm,
1911 struct radeon_bo *bo,
1912 struct ttm_mem_reg *mem);
1913 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1914 struct radeon_bo *bo);
1915 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1916 struct radeon_bo *bo);
1917 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1918 struct radeon_vm *vm,
1919 struct radeon_bo *bo);
1920 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1921 struct radeon_bo_va *bo_va,
1922 uint64_t offset,
1923 uint32_t flags);
1924 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1925 struct radeon_bo_va *bo_va);
1926
1927 /* audio */
1928 void r600_audio_update_hdmi(struct work_struct *work);
1929
1930 /*
1931 * R600 vram scratch functions
1932 */
1933 int r600_vram_scratch_init(struct radeon_device *rdev);
1934 void r600_vram_scratch_fini(struct radeon_device *rdev);
1935
1936 /*
1937 * r600 cs checking helper
1938 */
1939 unsigned r600_mip_minify(unsigned size, unsigned level);
1940 bool r600_fmt_is_valid_color(u32 format);
1941 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1942 int r600_fmt_get_blocksize(u32 format);
1943 int r600_fmt_get_nblocksx(u32 format, u32 w);
1944 int r600_fmt_get_nblocksy(u32 format, u32 h);
1945
1946 /*
1947 * r600 functions used by radeon_encoder.c
1948 */
1949 struct radeon_hdmi_acr {
1950 u32 clock;
1951
1952 int n_32khz;
1953 int cts_32khz;
1954
1955 int n_44_1khz;
1956 int cts_44_1khz;
1957
1958 int n_48khz;
1959 int cts_48khz;
1960
1961 };
1962
1963 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1964
1965 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1966 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1967 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1968 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1969 u32 tiling_pipe_num,
1970 u32 max_rb_num,
1971 u32 total_max_rb_num,
1972 u32 enabled_rb_mask);
1973
1974 /*
1975 * evergreen functions used by radeon_encoder.c
1976 */
1977
1978 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1979
1980 extern int ni_init_microcode(struct radeon_device *rdev);
1981 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1982
1983 /* radeon_acpi.c */
1984 #if defined(CONFIG_ACPI)
1985 extern int radeon_acpi_init(struct radeon_device *rdev);
1986 extern void radeon_acpi_fini(struct radeon_device *rdev);
1987 #else
1988 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1989 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1990 #endif
1991
1992 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
1993 struct radeon_cs_packet *pkt,
1994 unsigned idx);
1995 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
1996 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
1997 struct radeon_cs_packet *pkt);
1998 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1999 struct radeon_cs_reloc **cs_reloc,
2000 int nomm);
2001 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2002 uint32_t *vline_start_end,
2003 uint32_t *vline_status);
2004
2005 #include "radeon_object.h"
2006
2007 #endif
Linux kernel - Deliverables
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