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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99
100 /*
101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 * symbol;
103 */
104 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
105 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
106 /* RADEON_IB_POOL_SIZE must be a power of 2 */
107 #define RADEON_IB_POOL_SIZE 16
108 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
109 #define RADEONFB_CONN_LIMIT 4
110 #define RADEON_BIOS_NUM_SCRATCH 8
111
112 /* max number of rings */
113 #define RADEON_NUM_RINGS 6
114
115 /* fence seq are set to this number when signaled */
116 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117
118 /* internal ring indices */
119 /* r1xx+ has gfx CP ring */
120 #define RADEON_RING_TYPE_GFX_INDEX 0
121
122 /* cayman has 2 compute CP rings */
123 #define CAYMAN_RING_TYPE_CP1_INDEX 1
124 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125
126 /* R600+ has an async dma ring */
127 #define R600_RING_TYPE_DMA_INDEX 3
128 /* cayman add a second async dma ring */
129 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
130
131 /* R600+ */
132 #define R600_RING_TYPE_UVD_INDEX 5
133
134 /* hardcode those limit for now */
135 #define RADEON_VA_IB_OFFSET (1 << 20)
136 #define RADEON_VA_RESERVED_SIZE (8 << 20)
137 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
138
139 /* reset flags */
140 #define RADEON_RESET_GFX (1 << 0)
141 #define RADEON_RESET_COMPUTE (1 << 1)
142 #define RADEON_RESET_DMA (1 << 2)
143 #define RADEON_RESET_CP (1 << 3)
144 #define RADEON_RESET_GRBM (1 << 4)
145 #define RADEON_RESET_DMA1 (1 << 5)
146 #define RADEON_RESET_RLC (1 << 6)
147 #define RADEON_RESET_SEM (1 << 7)
148 #define RADEON_RESET_IH (1 << 8)
149 #define RADEON_RESET_VMC (1 << 9)
150 #define RADEON_RESET_MC (1 << 10)
151 #define RADEON_RESET_DISPLAY (1 << 11)
152
153 /* max cursor sizes (in pixels) */
154 #define CURSOR_WIDTH 64
155 #define CURSOR_HEIGHT 64
156
157 #define CIK_CURSOR_WIDTH 128
158 #define CIK_CURSOR_HEIGHT 128
159
160 /*
161 * Errata workarounds.
162 */
163 enum radeon_pll_errata {
164 CHIP_ERRATA_R300_CG = 0x00000001,
165 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
166 CHIP_ERRATA_PLL_DELAY = 0x00000004
167 };
168
169
170 struct radeon_device;
171
172
173 /*
174 * BIOS.
175 */
176 bool radeon_get_bios(struct radeon_device *rdev);
177
178 /*
179 * Dummy page
180 */
181 struct radeon_dummy_page {
182 struct page *page;
183 dma_addr_t addr;
184 };
185 int radeon_dummy_page_init(struct radeon_device *rdev);
186 void radeon_dummy_page_fini(struct radeon_device *rdev);
187
188
189 /*
190 * Clocks
191 */
192 struct radeon_clock {
193 struct radeon_pll p1pll;
194 struct radeon_pll p2pll;
195 struct radeon_pll dcpll;
196 struct radeon_pll spll;
197 struct radeon_pll mpll;
198 /* 10 Khz units */
199 uint32_t default_mclk;
200 uint32_t default_sclk;
201 uint32_t default_dispclk;
202 uint32_t dp_extclk;
203 uint32_t max_pixel_clock;
204 };
205
206 /*
207 * Power management
208 */
209 int radeon_pm_init(struct radeon_device *rdev);
210 void radeon_pm_fini(struct radeon_device *rdev);
211 void radeon_pm_compute_clocks(struct radeon_device *rdev);
212 void radeon_pm_suspend(struct radeon_device *rdev);
213 void radeon_pm_resume(struct radeon_device *rdev);
214 void radeon_combios_get_power_modes(struct radeon_device *rdev);
215 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
216 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
217 u8 clock_type,
218 u32 clock,
219 bool strobe_mode,
220 struct atom_clock_dividers *dividers);
221 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
222 void rs690_pm_info(struct radeon_device *rdev);
223 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
224 unsigned *bankh, unsigned *mtaspect,
225 unsigned *tile_split);
226
227 /*
228 * Fences.
229 */
230 struct radeon_fence_driver {
231 uint32_t scratch_reg;
232 uint64_t gpu_addr;
233 volatile uint32_t *cpu_addr;
234 /* sync_seq is protected by ring emission lock */
235 uint64_t sync_seq[RADEON_NUM_RINGS];
236 atomic64_t last_seq;
237 unsigned long last_activity;
238 bool initialized;
239 };
240
241 struct radeon_fence {
242 struct radeon_device *rdev;
243 struct kref kref;
244 /* protected by radeon_fence.lock */
245 uint64_t seq;
246 /* RB, DMA, etc. */
247 unsigned ring;
248 };
249
250 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
251 int radeon_fence_driver_init(struct radeon_device *rdev);
252 void radeon_fence_driver_fini(struct radeon_device *rdev);
253 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
254 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
255 void radeon_fence_process(struct radeon_device *rdev, int ring);
256 bool radeon_fence_signaled(struct radeon_fence *fence);
257 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
258 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
259 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
260 int radeon_fence_wait_any(struct radeon_device *rdev,
261 struct radeon_fence **fences,
262 bool intr);
263 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
264 void radeon_fence_unref(struct radeon_fence **fence);
265 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
266 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
267 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
268 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
269 struct radeon_fence *b)
270 {
271 if (!a) {
272 return b;
273 }
274
275 if (!b) {
276 return a;
277 }
278
279 BUG_ON(a->ring != b->ring);
280
281 if (a->seq > b->seq) {
282 return a;
283 } else {
284 return b;
285 }
286 }
287
288 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
289 struct radeon_fence *b)
290 {
291 if (!a) {
292 return false;
293 }
294
295 if (!b) {
296 return true;
297 }
298
299 BUG_ON(a->ring != b->ring);
300
301 return a->seq < b->seq;
302 }
303
304 /*
305 * Tiling registers
306 */
307 struct radeon_surface_reg {
308 struct radeon_bo *bo;
309 };
310
311 #define RADEON_GEM_MAX_SURFACES 8
312
313 /*
314 * TTM.
315 */
316 struct radeon_mman {
317 struct ttm_bo_global_ref bo_global_ref;
318 struct drm_global_reference mem_global_ref;
319 struct ttm_bo_device bdev;
320 bool mem_global_referenced;
321 bool initialized;
322 };
323
324 /* bo virtual address in a specific vm */
325 struct radeon_bo_va {
326 /* protected by bo being reserved */
327 struct list_head bo_list;
328 uint64_t soffset;
329 uint64_t eoffset;
330 uint32_t flags;
331 bool valid;
332 unsigned ref_count;
333
334 /* protected by vm mutex */
335 struct list_head vm_list;
336
337 /* constant after initialization */
338 struct radeon_vm *vm;
339 struct radeon_bo *bo;
340 };
341
342 struct radeon_bo {
343 /* Protected by gem.mutex */
344 struct list_head list;
345 /* Protected by tbo.reserved */
346 u32 placements[3];
347 struct ttm_placement placement;
348 struct ttm_buffer_object tbo;
349 struct ttm_bo_kmap_obj kmap;
350 unsigned pin_count;
351 void *kptr;
352 u32 tiling_flags;
353 u32 pitch;
354 int surface_reg;
355 /* list of all virtual address to which this bo
356 * is associated to
357 */
358 struct list_head va;
359 /* Constant after initialization */
360 struct radeon_device *rdev;
361 struct drm_gem_object gem_base;
362
363 struct ttm_bo_kmap_obj dma_buf_vmap;
364 pid_t pid;
365 };
366 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
367
368 struct radeon_bo_list {
369 struct ttm_validate_buffer tv;
370 struct radeon_bo *bo;
371 uint64_t gpu_offset;
372 bool written;
373 unsigned domain;
374 unsigned alt_domain;
375 u32 tiling_flags;
376 };
377
378 int radeon_gem_debugfs_init(struct radeon_device *rdev);
379
380 /* sub-allocation manager, it has to be protected by another lock.
381 * By conception this is an helper for other part of the driver
382 * like the indirect buffer or semaphore, which both have their
383 * locking.
384 *
385 * Principe is simple, we keep a list of sub allocation in offset
386 * order (first entry has offset == 0, last entry has the highest
387 * offset).
388 *
389 * When allocating new object we first check if there is room at
390 * the end total_size - (last_object_offset + last_object_size) >=
391 * alloc_size. If so we allocate new object there.
392 *
393 * When there is not enough room at the end, we start waiting for
394 * each sub object until we reach object_offset+object_size >=
395 * alloc_size, this object then become the sub object we return.
396 *
397 * Alignment can't be bigger than page size.
398 *
399 * Hole are not considered for allocation to keep things simple.
400 * Assumption is that there won't be hole (all object on same
401 * alignment).
402 */
403 struct radeon_sa_manager {
404 wait_queue_head_t wq;
405 struct radeon_bo *bo;
406 struct list_head *hole;
407 struct list_head flist[RADEON_NUM_RINGS];
408 struct list_head olist;
409 unsigned size;
410 uint64_t gpu_addr;
411 void *cpu_ptr;
412 uint32_t domain;
413 };
414
415 struct radeon_sa_bo;
416
417 /* sub-allocation buffer */
418 struct radeon_sa_bo {
419 struct list_head olist;
420 struct list_head flist;
421 struct radeon_sa_manager *manager;
422 unsigned soffset;
423 unsigned eoffset;
424 struct radeon_fence *fence;
425 };
426
427 /*
428 * GEM objects.
429 */
430 struct radeon_gem {
431 struct mutex mutex;
432 struct list_head objects;
433 };
434
435 int radeon_gem_init(struct radeon_device *rdev);
436 void radeon_gem_fini(struct radeon_device *rdev);
437 int radeon_gem_object_create(struct radeon_device *rdev, int size,
438 int alignment, int initial_domain,
439 bool discardable, bool kernel,
440 struct drm_gem_object **obj);
441
442 int radeon_mode_dumb_create(struct drm_file *file_priv,
443 struct drm_device *dev,
444 struct drm_mode_create_dumb *args);
445 int radeon_mode_dumb_mmap(struct drm_file *filp,
446 struct drm_device *dev,
447 uint32_t handle, uint64_t *offset_p);
448 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
449 struct drm_device *dev,
450 uint32_t handle);
451
452 /*
453 * Semaphores.
454 */
455 /* everything here is constant */
456 struct radeon_semaphore {
457 struct radeon_sa_bo *sa_bo;
458 signed waiters;
459 uint64_t gpu_addr;
460 };
461
462 int radeon_semaphore_create(struct radeon_device *rdev,
463 struct radeon_semaphore **semaphore);
464 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
465 struct radeon_semaphore *semaphore);
466 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
467 struct radeon_semaphore *semaphore);
468 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
469 struct radeon_semaphore *semaphore,
470 int signaler, int waiter);
471 void radeon_semaphore_free(struct radeon_device *rdev,
472 struct radeon_semaphore **semaphore,
473 struct radeon_fence *fence);
474
475 /*
476 * GART structures, functions & helpers
477 */
478 struct radeon_mc;
479
480 #define RADEON_GPU_PAGE_SIZE 4096
481 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
482 #define RADEON_GPU_PAGE_SHIFT 12
483 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
484
485 struct radeon_gart {
486 dma_addr_t table_addr;
487 struct radeon_bo *robj;
488 void *ptr;
489 unsigned num_gpu_pages;
490 unsigned num_cpu_pages;
491 unsigned table_size;
492 struct page **pages;
493 dma_addr_t *pages_addr;
494 bool ready;
495 };
496
497 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
498 void radeon_gart_table_ram_free(struct radeon_device *rdev);
499 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
500 void radeon_gart_table_vram_free(struct radeon_device *rdev);
501 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
502 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
503 int radeon_gart_init(struct radeon_device *rdev);
504 void radeon_gart_fini(struct radeon_device *rdev);
505 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
506 int pages);
507 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
508 int pages, struct page **pagelist,
509 dma_addr_t *dma_addr);
510 void radeon_gart_restore(struct radeon_device *rdev);
511
512
513 /*
514 * GPU MC structures, functions & helpers
515 */
516 struct radeon_mc {
517 resource_size_t aper_size;
518 resource_size_t aper_base;
519 resource_size_t agp_base;
520 /* for some chips with <= 32MB we need to lie
521 * about vram size near mc fb location */
522 u64 mc_vram_size;
523 u64 visible_vram_size;
524 u64 gtt_size;
525 u64 gtt_start;
526 u64 gtt_end;
527 u64 vram_start;
528 u64 vram_end;
529 unsigned vram_width;
530 u64 real_vram_size;
531 int vram_mtrr;
532 bool vram_is_ddr;
533 bool igp_sideport_enabled;
534 u64 gtt_base_align;
535 u64 mc_mask;
536 };
537
538 bool radeon_combios_sideport_present(struct radeon_device *rdev);
539 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
540
541 /*
542 * GPU scratch registers structures, functions & helpers
543 */
544 struct radeon_scratch {
545 unsigned num_reg;
546 uint32_t reg_base;
547 bool free[32];
548 uint32_t reg[32];
549 };
550
551 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
552 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
553
554 /*
555 * GPU doorbell structures, functions & helpers
556 */
557 struct radeon_doorbell {
558 u32 num_pages;
559 bool free[1024];
560 /* doorbell mmio */
561 resource_size_t base;
562 resource_size_t size;
563 void __iomem *ptr;
564 };
565
566 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
567 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
568
569 /*
570 * IRQS.
571 */
572
573 struct radeon_unpin_work {
574 struct work_struct work;
575 struct radeon_device *rdev;
576 int crtc_id;
577 struct radeon_fence *fence;
578 struct drm_pending_vblank_event *event;
579 struct radeon_bo *old_rbo;
580 u64 new_crtc_base;
581 };
582
583 struct r500_irq_stat_regs {
584 u32 disp_int;
585 u32 hdmi0_status;
586 };
587
588 struct r600_irq_stat_regs {
589 u32 disp_int;
590 u32 disp_int_cont;
591 u32 disp_int_cont2;
592 u32 d1grph_int;
593 u32 d2grph_int;
594 u32 hdmi0_status;
595 u32 hdmi1_status;
596 };
597
598 struct evergreen_irq_stat_regs {
599 u32 disp_int;
600 u32 disp_int_cont;
601 u32 disp_int_cont2;
602 u32 disp_int_cont3;
603 u32 disp_int_cont4;
604 u32 disp_int_cont5;
605 u32 d1grph_int;
606 u32 d2grph_int;
607 u32 d3grph_int;
608 u32 d4grph_int;
609 u32 d5grph_int;
610 u32 d6grph_int;
611 u32 afmt_status1;
612 u32 afmt_status2;
613 u32 afmt_status3;
614 u32 afmt_status4;
615 u32 afmt_status5;
616 u32 afmt_status6;
617 };
618
619 struct cik_irq_stat_regs {
620 u32 disp_int;
621 u32 disp_int_cont;
622 u32 disp_int_cont2;
623 u32 disp_int_cont3;
624 u32 disp_int_cont4;
625 u32 disp_int_cont5;
626 u32 disp_int_cont6;
627 };
628
629 union radeon_irq_stat_regs {
630 struct r500_irq_stat_regs r500;
631 struct r600_irq_stat_regs r600;
632 struct evergreen_irq_stat_regs evergreen;
633 struct cik_irq_stat_regs cik;
634 };
635
636 #define RADEON_MAX_HPD_PINS 6
637 #define RADEON_MAX_CRTCS 6
638 #define RADEON_MAX_AFMT_BLOCKS 6
639
640 struct radeon_irq {
641 bool installed;
642 spinlock_t lock;
643 atomic_t ring_int[RADEON_NUM_RINGS];
644 bool crtc_vblank_int[RADEON_MAX_CRTCS];
645 atomic_t pflip[RADEON_MAX_CRTCS];
646 wait_queue_head_t vblank_queue;
647 bool hpd[RADEON_MAX_HPD_PINS];
648 bool afmt[RADEON_MAX_AFMT_BLOCKS];
649 union radeon_irq_stat_regs stat_regs;
650 };
651
652 int radeon_irq_kms_init(struct radeon_device *rdev);
653 void radeon_irq_kms_fini(struct radeon_device *rdev);
654 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
655 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
656 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
657 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
658 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
659 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
660 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
661 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
662
663 /*
664 * CP & rings.
665 */
666
667 struct radeon_ib {
668 struct radeon_sa_bo *sa_bo;
669 uint32_t length_dw;
670 uint64_t gpu_addr;
671 uint32_t *ptr;
672 int ring;
673 struct radeon_fence *fence;
674 struct radeon_vm *vm;
675 bool is_const_ib;
676 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
677 struct radeon_semaphore *semaphore;
678 };
679
680 struct radeon_ring {
681 struct radeon_bo *ring_obj;
682 volatile uint32_t *ring;
683 unsigned rptr;
684 unsigned rptr_offs;
685 unsigned rptr_reg;
686 unsigned rptr_save_reg;
687 u64 next_rptr_gpu_addr;
688 volatile u32 *next_rptr_cpu_addr;
689 unsigned wptr;
690 unsigned wptr_old;
691 unsigned wptr_reg;
692 unsigned ring_size;
693 unsigned ring_free_dw;
694 int count_dw;
695 unsigned long last_activity;
696 unsigned last_rptr;
697 uint64_t gpu_addr;
698 uint32_t align_mask;
699 uint32_t ptr_mask;
700 bool ready;
701 u32 ptr_reg_shift;
702 u32 ptr_reg_mask;
703 u32 nop;
704 u32 idx;
705 u64 last_semaphore_signal_addr;
706 u64 last_semaphore_wait_addr;
707 /* for CIK queues */
708 u32 me;
709 u32 pipe;
710 u32 queue;
711 struct radeon_bo *mqd_obj;
712 u32 doorbell_page_num;
713 u32 doorbell_offset;
714 unsigned wptr_offs;
715 };
716
717 struct radeon_mec {
718 struct radeon_bo *hpd_eop_obj;
719 u64 hpd_eop_gpu_addr;
720 u32 num_pipe;
721 u32 num_mec;
722 u32 num_queue;
723 };
724
725 /*
726 * VM
727 */
728
729 /* maximum number of VMIDs */
730 #define RADEON_NUM_VM 16
731
732 /* defines number of bits in page table versus page directory,
733 * a page is 4KB so we have 12 bits offset, 9 bits in the page
734 * table and the remaining 19 bits are in the page directory */
735 #define RADEON_VM_BLOCK_SIZE 9
736
737 /* number of entries in page table */
738 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
739
740 struct radeon_vm {
741 struct list_head list;
742 struct list_head va;
743 unsigned id;
744
745 /* contains the page directory */
746 struct radeon_sa_bo *page_directory;
747 uint64_t pd_gpu_addr;
748
749 /* array of page tables, one for each page directory entry */
750 struct radeon_sa_bo **page_tables;
751
752 struct mutex mutex;
753 /* last fence for cs using this vm */
754 struct radeon_fence *fence;
755 /* last flush or NULL if we still need to flush */
756 struct radeon_fence *last_flush;
757 };
758
759 struct radeon_vm_manager {
760 struct mutex lock;
761 struct list_head lru_vm;
762 struct radeon_fence *active[RADEON_NUM_VM];
763 struct radeon_sa_manager sa_manager;
764 uint32_t max_pfn;
765 /* number of VMIDs */
766 unsigned nvm;
767 /* vram base address for page table entry */
768 u64 vram_base_offset;
769 /* is vm enabled? */
770 bool enabled;
771 };
772
773 /*
774 * file private structure
775 */
776 struct radeon_fpriv {
777 struct radeon_vm vm;
778 };
779
780 /*
781 * R6xx+ IH ring
782 */
783 struct r600_ih {
784 struct radeon_bo *ring_obj;
785 volatile uint32_t *ring;
786 unsigned rptr;
787 unsigned ring_size;
788 uint64_t gpu_addr;
789 uint32_t ptr_mask;
790 atomic_t lock;
791 bool enabled;
792 };
793
794 struct r600_blit_cp_primitives {
795 void (*set_render_target)(struct radeon_device *rdev, int format,
796 int w, int h, u64 gpu_addr);
797 void (*cp_set_surface_sync)(struct radeon_device *rdev,
798 u32 sync_type, u32 size,
799 u64 mc_addr);
800 void (*set_shaders)(struct radeon_device *rdev);
801 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
802 void (*set_tex_resource)(struct radeon_device *rdev,
803 int format, int w, int h, int pitch,
804 u64 gpu_addr, u32 size);
805 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
806 int x2, int y2);
807 void (*draw_auto)(struct radeon_device *rdev);
808 void (*set_default_state)(struct radeon_device *rdev);
809 };
810
811 struct r600_blit {
812 struct radeon_bo *shader_obj;
813 struct r600_blit_cp_primitives primitives;
814 int max_dim;
815 int ring_size_common;
816 int ring_size_per_loop;
817 u64 shader_gpu_addr;
818 u32 vs_offset, ps_offset;
819 u32 state_offset;
820 u32 state_len;
821 };
822
823 /*
824 * RLC stuff
825 */
826 #include "clearstate_defs.h"
827
828 struct radeon_rlc {
829 /* for power gating */
830 struct radeon_bo *save_restore_obj;
831 uint64_t save_restore_gpu_addr;
832 volatile uint32_t *sr_ptr;
833 u32 *reg_list;
834 u32 reg_list_size;
835 /* for clear state */
836 struct radeon_bo *clear_state_obj;
837 uint64_t clear_state_gpu_addr;
838 volatile uint32_t *cs_ptr;
839 struct cs_section_def *cs_data;
840 };
841
842 int radeon_ib_get(struct radeon_device *rdev, int ring,
843 struct radeon_ib *ib, struct radeon_vm *vm,
844 unsigned size);
845 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
846 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
847 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
848 struct radeon_ib *const_ib);
849 int radeon_ib_pool_init(struct radeon_device *rdev);
850 void radeon_ib_pool_fini(struct radeon_device *rdev);
851 int radeon_ib_ring_tests(struct radeon_device *rdev);
852 /* Ring access between begin & end cannot sleep */
853 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
854 struct radeon_ring *ring);
855 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
856 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
857 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
858 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
859 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
860 void radeon_ring_undo(struct radeon_ring *ring);
861 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
862 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
863 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
864 void radeon_ring_lockup_update(struct radeon_ring *ring);
865 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
866 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
867 uint32_t **data);
868 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
869 unsigned size, uint32_t *data);
870 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
871 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
872 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
873 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
874
875
876 /* r600 async dma */
877 void r600_dma_stop(struct radeon_device *rdev);
878 int r600_dma_resume(struct radeon_device *rdev);
879 void r600_dma_fini(struct radeon_device *rdev);
880
881 void cayman_dma_stop(struct radeon_device *rdev);
882 int cayman_dma_resume(struct radeon_device *rdev);
883 void cayman_dma_fini(struct radeon_device *rdev);
884
885 /*
886 * CS.
887 */
888 struct radeon_cs_reloc {
889 struct drm_gem_object *gobj;
890 struct radeon_bo *robj;
891 struct radeon_bo_list lobj;
892 uint32_t handle;
893 uint32_t flags;
894 };
895
896 struct radeon_cs_chunk {
897 uint32_t chunk_id;
898 uint32_t length_dw;
899 int kpage_idx[2];
900 uint32_t *kpage[2];
901 uint32_t *kdata;
902 void __user *user_ptr;
903 int last_copied_page;
904 int last_page_index;
905 };
906
907 struct radeon_cs_parser {
908 struct device *dev;
909 struct radeon_device *rdev;
910 struct drm_file *filp;
911 /* chunks */
912 unsigned nchunks;
913 struct radeon_cs_chunk *chunks;
914 uint64_t *chunks_array;
915 /* IB */
916 unsigned idx;
917 /* relocations */
918 unsigned nrelocs;
919 struct radeon_cs_reloc *relocs;
920 struct radeon_cs_reloc **relocs_ptr;
921 struct list_head validated;
922 unsigned dma_reloc_idx;
923 /* indices of various chunks */
924 int chunk_ib_idx;
925 int chunk_relocs_idx;
926 int chunk_flags_idx;
927 int chunk_const_ib_idx;
928 struct radeon_ib ib;
929 struct radeon_ib const_ib;
930 void *track;
931 unsigned family;
932 int parser_error;
933 u32 cs_flags;
934 u32 ring;
935 s32 priority;
936 };
937
938 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
939 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
940
941 struct radeon_cs_packet {
942 unsigned idx;
943 unsigned type;
944 unsigned reg;
945 unsigned opcode;
946 int count;
947 unsigned one_reg_wr;
948 };
949
950 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
951 struct radeon_cs_packet *pkt,
952 unsigned idx, unsigned reg);
953 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
954 struct radeon_cs_packet *pkt);
955
956
957 /*
958 * AGP
959 */
960 int radeon_agp_init(struct radeon_device *rdev);
961 void radeon_agp_resume(struct radeon_device *rdev);
962 void radeon_agp_suspend(struct radeon_device *rdev);
963 void radeon_agp_fini(struct radeon_device *rdev);
964
965
966 /*
967 * Writeback
968 */
969 struct radeon_wb {
970 struct radeon_bo *wb_obj;
971 volatile uint32_t *wb;
972 uint64_t gpu_addr;
973 bool enabled;
974 bool use_event;
975 };
976
977 #define RADEON_WB_SCRATCH_OFFSET 0
978 #define RADEON_WB_RING0_NEXT_RPTR 256
979 #define RADEON_WB_CP_RPTR_OFFSET 1024
980 #define RADEON_WB_CP1_RPTR_OFFSET 1280
981 #define RADEON_WB_CP2_RPTR_OFFSET 1536
982 #define R600_WB_DMA_RPTR_OFFSET 1792
983 #define R600_WB_IH_WPTR_OFFSET 2048
984 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
985 #define R600_WB_UVD_RPTR_OFFSET 2560
986 #define R600_WB_EVENT_OFFSET 3072
987 #define CIK_WB_CP1_WPTR_OFFSET 3328
988 #define CIK_WB_CP2_WPTR_OFFSET 3584
989
990 /**
991 * struct radeon_pm - power management datas
992 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
993 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
994 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
995 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
996 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
997 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
998 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
999 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1000 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1001 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1002 * @needed_bandwidth: current bandwidth needs
1003 *
1004 * It keeps track of various data needed to take powermanagement decision.
1005 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1006 * Equation between gpu/memory clock and available bandwidth is hw dependent
1007 * (type of memory, bus size, efficiency, ...)
1008 */
1009
1010 enum radeon_pm_method {
1011 PM_METHOD_PROFILE,
1012 PM_METHOD_DYNPM,
1013 };
1014
1015 enum radeon_dynpm_state {
1016 DYNPM_STATE_DISABLED,
1017 DYNPM_STATE_MINIMUM,
1018 DYNPM_STATE_PAUSED,
1019 DYNPM_STATE_ACTIVE,
1020 DYNPM_STATE_SUSPENDED,
1021 };
1022 enum radeon_dynpm_action {
1023 DYNPM_ACTION_NONE,
1024 DYNPM_ACTION_MINIMUM,
1025 DYNPM_ACTION_DOWNCLOCK,
1026 DYNPM_ACTION_UPCLOCK,
1027 DYNPM_ACTION_DEFAULT
1028 };
1029
1030 enum radeon_voltage_type {
1031 VOLTAGE_NONE = 0,
1032 VOLTAGE_GPIO,
1033 VOLTAGE_VDDC,
1034 VOLTAGE_SW
1035 };
1036
1037 enum radeon_pm_state_type {
1038 POWER_STATE_TYPE_DEFAULT,
1039 POWER_STATE_TYPE_POWERSAVE,
1040 POWER_STATE_TYPE_BATTERY,
1041 POWER_STATE_TYPE_BALANCED,
1042 POWER_STATE_TYPE_PERFORMANCE,
1043 };
1044
1045 enum radeon_pm_profile_type {
1046 PM_PROFILE_DEFAULT,
1047 PM_PROFILE_AUTO,
1048 PM_PROFILE_LOW,
1049 PM_PROFILE_MID,
1050 PM_PROFILE_HIGH,
1051 };
1052
1053 #define PM_PROFILE_DEFAULT_IDX 0
1054 #define PM_PROFILE_LOW_SH_IDX 1
1055 #define PM_PROFILE_MID_SH_IDX 2
1056 #define PM_PROFILE_HIGH_SH_IDX 3
1057 #define PM_PROFILE_LOW_MH_IDX 4
1058 #define PM_PROFILE_MID_MH_IDX 5
1059 #define PM_PROFILE_HIGH_MH_IDX 6
1060 #define PM_PROFILE_MAX 7
1061
1062 struct radeon_pm_profile {
1063 int dpms_off_ps_idx;
1064 int dpms_on_ps_idx;
1065 int dpms_off_cm_idx;
1066 int dpms_on_cm_idx;
1067 };
1068
1069 enum radeon_int_thermal_type {
1070 THERMAL_TYPE_NONE,
1071 THERMAL_TYPE_RV6XX,
1072 THERMAL_TYPE_RV770,
1073 THERMAL_TYPE_EVERGREEN,
1074 THERMAL_TYPE_SUMO,
1075 THERMAL_TYPE_NI,
1076 THERMAL_TYPE_SI,
1077 THERMAL_TYPE_CI,
1078 };
1079
1080 struct radeon_voltage {
1081 enum radeon_voltage_type type;
1082 /* gpio voltage */
1083 struct radeon_gpio_rec gpio;
1084 u32 delay; /* delay in usec from voltage drop to sclk change */
1085 bool active_high; /* voltage drop is active when bit is high */
1086 /* VDDC voltage */
1087 u8 vddc_id; /* index into vddc voltage table */
1088 u8 vddci_id; /* index into vddci voltage table */
1089 bool vddci_enabled;
1090 /* r6xx+ sw */
1091 u16 voltage;
1092 /* evergreen+ vddci */
1093 u16 vddci;
1094 };
1095
1096 /* clock mode flags */
1097 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1098
1099 struct radeon_pm_clock_info {
1100 /* memory clock */
1101 u32 mclk;
1102 /* engine clock */
1103 u32 sclk;
1104 /* voltage info */
1105 struct radeon_voltage voltage;
1106 /* standardized clock flags */
1107 u32 flags;
1108 };
1109
1110 /* state flags */
1111 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1112
1113 struct radeon_power_state {
1114 enum radeon_pm_state_type type;
1115 struct radeon_pm_clock_info *clock_info;
1116 /* number of valid clock modes in this power state */
1117 int num_clock_modes;
1118 struct radeon_pm_clock_info *default_clock_mode;
1119 /* standardized state flags */
1120 u32 flags;
1121 u32 misc; /* vbios specific flags */
1122 u32 misc2; /* vbios specific flags */
1123 int pcie_lanes; /* pcie lanes */
1124 };
1125
1126 /*
1127 * Some modes are overclocked by very low value, accept them
1128 */
1129 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1130
1131 struct radeon_pm {
1132 struct mutex mutex;
1133 /* write locked while reprogramming mclk */
1134 struct rw_semaphore mclk_lock;
1135 u32 active_crtcs;
1136 int active_crtc_count;
1137 int req_vblank;
1138 bool vblank_sync;
1139 fixed20_12 max_bandwidth;
1140 fixed20_12 igp_sideport_mclk;
1141 fixed20_12 igp_system_mclk;
1142 fixed20_12 igp_ht_link_clk;
1143 fixed20_12 igp_ht_link_width;
1144 fixed20_12 k8_bandwidth;
1145 fixed20_12 sideport_bandwidth;
1146 fixed20_12 ht_bandwidth;
1147 fixed20_12 core_bandwidth;
1148 fixed20_12 sclk;
1149 fixed20_12 mclk;
1150 fixed20_12 needed_bandwidth;
1151 struct radeon_power_state *power_state;
1152 /* number of valid power states */
1153 int num_power_states;
1154 int current_power_state_index;
1155 int current_clock_mode_index;
1156 int requested_power_state_index;
1157 int requested_clock_mode_index;
1158 int default_power_state_index;
1159 u32 current_sclk;
1160 u32 current_mclk;
1161 u16 current_vddc;
1162 u16 current_vddci;
1163 u32 default_sclk;
1164 u32 default_mclk;
1165 u16 default_vddc;
1166 u16 default_vddci;
1167 struct radeon_i2c_chan *i2c_bus;
1168 /* selected pm method */
1169 enum radeon_pm_method pm_method;
1170 /* dynpm power management */
1171 struct delayed_work dynpm_idle_work;
1172 enum radeon_dynpm_state dynpm_state;
1173 enum radeon_dynpm_action dynpm_planned_action;
1174 unsigned long dynpm_action_timeout;
1175 bool dynpm_can_upclock;
1176 bool dynpm_can_downclock;
1177 /* profile-based power management */
1178 enum radeon_pm_profile_type profile;
1179 int profile_index;
1180 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1181 /* internal thermal controller on rv6xx+ */
1182 enum radeon_int_thermal_type int_thermal_type;
1183 struct device *int_hwmon_dev;
1184 };
1185
1186 int radeon_pm_get_type_index(struct radeon_device *rdev,
1187 enum radeon_pm_state_type ps_type,
1188 int instance);
1189 /*
1190 * UVD
1191 */
1192 #define RADEON_MAX_UVD_HANDLES 10
1193 #define RADEON_UVD_STACK_SIZE (1024*1024)
1194 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1195
1196 struct radeon_uvd {
1197 struct radeon_bo *vcpu_bo;
1198 void *cpu_addr;
1199 uint64_t gpu_addr;
1200 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1201 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1202 struct delayed_work idle_work;
1203 };
1204
1205 int radeon_uvd_init(struct radeon_device *rdev);
1206 void radeon_uvd_fini(struct radeon_device *rdev);
1207 int radeon_uvd_suspend(struct radeon_device *rdev);
1208 int radeon_uvd_resume(struct radeon_device *rdev);
1209 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1210 uint32_t handle, struct radeon_fence **fence);
1211 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1212 uint32_t handle, struct radeon_fence **fence);
1213 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1214 void radeon_uvd_free_handles(struct radeon_device *rdev,
1215 struct drm_file *filp);
1216 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1217 void radeon_uvd_note_usage(struct radeon_device *rdev);
1218 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1219 unsigned vclk, unsigned dclk,
1220 unsigned vco_min, unsigned vco_max,
1221 unsigned fb_factor, unsigned fb_mask,
1222 unsigned pd_min, unsigned pd_max,
1223 unsigned pd_even,
1224 unsigned *optimal_fb_div,
1225 unsigned *optimal_vclk_div,
1226 unsigned *optimal_dclk_div);
1227 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1228 unsigned cg_upll_func_cntl);
1229
1230 struct r600_audio {
1231 int channels;
1232 int rate;
1233 int bits_per_sample;
1234 u8 status_bits;
1235 u8 category_code;
1236 };
1237
1238 /*
1239 * Benchmarking
1240 */
1241 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1242
1243
1244 /*
1245 * Testing
1246 */
1247 void radeon_test_moves(struct radeon_device *rdev);
1248 void radeon_test_ring_sync(struct radeon_device *rdev,
1249 struct radeon_ring *cpA,
1250 struct radeon_ring *cpB);
1251 void radeon_test_syncing(struct radeon_device *rdev);
1252
1253
1254 /*
1255 * Debugfs
1256 */
1257 struct radeon_debugfs {
1258 struct drm_info_list *files;
1259 unsigned num_files;
1260 };
1261
1262 int radeon_debugfs_add_files(struct radeon_device *rdev,
1263 struct drm_info_list *files,
1264 unsigned nfiles);
1265 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1266
1267
1268 /*
1269 * ASIC specific functions.
1270 */
1271 struct radeon_asic {
1272 int (*init)(struct radeon_device *rdev);
1273 void (*fini)(struct radeon_device *rdev);
1274 int (*resume)(struct radeon_device *rdev);
1275 int (*suspend)(struct radeon_device *rdev);
1276 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1277 int (*asic_reset)(struct radeon_device *rdev);
1278 /* ioctl hw specific callback. Some hw might want to perform special
1279 * operation on specific ioctl. For instance on wait idle some hw
1280 * might want to perform and HDP flush through MMIO as it seems that
1281 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1282 * through ring.
1283 */
1284 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1285 /* check if 3D engine is idle */
1286 bool (*gui_idle)(struct radeon_device *rdev);
1287 /* wait for mc_idle */
1288 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1289 /* get the reference clock */
1290 u32 (*get_xclk)(struct radeon_device *rdev);
1291 /* get the gpu clock counter */
1292 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1293 /* gart */
1294 struct {
1295 void (*tlb_flush)(struct radeon_device *rdev);
1296 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1297 } gart;
1298 struct {
1299 int (*init)(struct radeon_device *rdev);
1300 void (*fini)(struct radeon_device *rdev);
1301
1302 u32 pt_ring_index;
1303 void (*set_page)(struct radeon_device *rdev,
1304 struct radeon_ib *ib,
1305 uint64_t pe,
1306 uint64_t addr, unsigned count,
1307 uint32_t incr, uint32_t flags);
1308 } vm;
1309 /* ring specific callbacks */
1310 struct {
1311 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1312 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1313 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1314 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1315 struct radeon_semaphore *semaphore, bool emit_wait);
1316 int (*cs_parse)(struct radeon_cs_parser *p);
1317 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1318 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1319 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1320 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1321 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1322
1323 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1324 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1325 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1326 } ring[RADEON_NUM_RINGS];
1327 /* irqs */
1328 struct {
1329 int (*set)(struct radeon_device *rdev);
1330 int (*process)(struct radeon_device *rdev);
1331 } irq;
1332 /* displays */
1333 struct {
1334 /* display watermarks */
1335 void (*bandwidth_update)(struct radeon_device *rdev);
1336 /* get frame count */
1337 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1338 /* wait for vblank */
1339 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1340 /* set backlight level */
1341 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1342 /* get backlight level */
1343 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1344 /* audio callbacks */
1345 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1346 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1347 } display;
1348 /* copy functions for bo handling */
1349 struct {
1350 int (*blit)(struct radeon_device *rdev,
1351 uint64_t src_offset,
1352 uint64_t dst_offset,
1353 unsigned num_gpu_pages,
1354 struct radeon_fence **fence);
1355 u32 blit_ring_index;
1356 int (*dma)(struct radeon_device *rdev,
1357 uint64_t src_offset,
1358 uint64_t dst_offset,
1359 unsigned num_gpu_pages,
1360 struct radeon_fence **fence);
1361 u32 dma_ring_index;
1362 /* method used for bo copy */
1363 int (*copy)(struct radeon_device *rdev,
1364 uint64_t src_offset,
1365 uint64_t dst_offset,
1366 unsigned num_gpu_pages,
1367 struct radeon_fence **fence);
1368 /* ring used for bo copies */
1369 u32 copy_ring_index;
1370 } copy;
1371 /* surfaces */
1372 struct {
1373 int (*set_reg)(struct radeon_device *rdev, int reg,
1374 uint32_t tiling_flags, uint32_t pitch,
1375 uint32_t offset, uint32_t obj_size);
1376 void (*clear_reg)(struct radeon_device *rdev, int reg);
1377 } surface;
1378 /* hotplug detect */
1379 struct {
1380 void (*init)(struct radeon_device *rdev);
1381 void (*fini)(struct radeon_device *rdev);
1382 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1383 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1384 } hpd;
1385 /* power management */
1386 struct {
1387 void (*misc)(struct radeon_device *rdev);
1388 void (*prepare)(struct radeon_device *rdev);
1389 void (*finish)(struct radeon_device *rdev);
1390 void (*init_profile)(struct radeon_device *rdev);
1391 void (*get_dynpm_state)(struct radeon_device *rdev);
1392 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1393 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1394 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1395 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1396 int (*get_pcie_lanes)(struct radeon_device *rdev);
1397 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1398 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1399 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1400 int (*get_temperature)(struct radeon_device *rdev);
1401 } pm;
1402 /* pageflipping */
1403 struct {
1404 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1405 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1406 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1407 } pflip;
1408 };
1409
1410 /*
1411 * Asic structures
1412 */
1413 struct r100_asic {
1414 const unsigned *reg_safe_bm;
1415 unsigned reg_safe_bm_size;
1416 u32 hdp_cntl;
1417 };
1418
1419 struct r300_asic {
1420 const unsigned *reg_safe_bm;
1421 unsigned reg_safe_bm_size;
1422 u32 resync_scratch;
1423 u32 hdp_cntl;
1424 };
1425
1426 struct r600_asic {
1427 unsigned max_pipes;
1428 unsigned max_tile_pipes;
1429 unsigned max_simds;
1430 unsigned max_backends;
1431 unsigned max_gprs;
1432 unsigned max_threads;
1433 unsigned max_stack_entries;
1434 unsigned max_hw_contexts;
1435 unsigned max_gs_threads;
1436 unsigned sx_max_export_size;
1437 unsigned sx_max_export_pos_size;
1438 unsigned sx_max_export_smx_size;
1439 unsigned sq_num_cf_insts;
1440 unsigned tiling_nbanks;
1441 unsigned tiling_npipes;
1442 unsigned tiling_group_size;
1443 unsigned tile_config;
1444 unsigned backend_map;
1445 };
1446
1447 struct rv770_asic {
1448 unsigned max_pipes;
1449 unsigned max_tile_pipes;
1450 unsigned max_simds;
1451 unsigned max_backends;
1452 unsigned max_gprs;
1453 unsigned max_threads;
1454 unsigned max_stack_entries;
1455 unsigned max_hw_contexts;
1456 unsigned max_gs_threads;
1457 unsigned sx_max_export_size;
1458 unsigned sx_max_export_pos_size;
1459 unsigned sx_max_export_smx_size;
1460 unsigned sq_num_cf_insts;
1461 unsigned sx_num_of_sets;
1462 unsigned sc_prim_fifo_size;
1463 unsigned sc_hiz_tile_fifo_size;
1464 unsigned sc_earlyz_tile_fifo_fize;
1465 unsigned tiling_nbanks;
1466 unsigned tiling_npipes;
1467 unsigned tiling_group_size;
1468 unsigned tile_config;
1469 unsigned backend_map;
1470 };
1471
1472 struct evergreen_asic {
1473 unsigned num_ses;
1474 unsigned max_pipes;
1475 unsigned max_tile_pipes;
1476 unsigned max_simds;
1477 unsigned max_backends;
1478 unsigned max_gprs;
1479 unsigned max_threads;
1480 unsigned max_stack_entries;
1481 unsigned max_hw_contexts;
1482 unsigned max_gs_threads;
1483 unsigned sx_max_export_size;
1484 unsigned sx_max_export_pos_size;
1485 unsigned sx_max_export_smx_size;
1486 unsigned sq_num_cf_insts;
1487 unsigned sx_num_of_sets;
1488 unsigned sc_prim_fifo_size;
1489 unsigned sc_hiz_tile_fifo_size;
1490 unsigned sc_earlyz_tile_fifo_size;
1491 unsigned tiling_nbanks;
1492 unsigned tiling_npipes;
1493 unsigned tiling_group_size;
1494 unsigned tile_config;
1495 unsigned backend_map;
1496 };
1497
1498 struct cayman_asic {
1499 unsigned max_shader_engines;
1500 unsigned max_pipes_per_simd;
1501 unsigned max_tile_pipes;
1502 unsigned max_simds_per_se;
1503 unsigned max_backends_per_se;
1504 unsigned max_texture_channel_caches;
1505 unsigned max_gprs;
1506 unsigned max_threads;
1507 unsigned max_gs_threads;
1508 unsigned max_stack_entries;
1509 unsigned sx_num_of_sets;
1510 unsigned sx_max_export_size;
1511 unsigned sx_max_export_pos_size;
1512 unsigned sx_max_export_smx_size;
1513 unsigned max_hw_contexts;
1514 unsigned sq_num_cf_insts;
1515 unsigned sc_prim_fifo_size;
1516 unsigned sc_hiz_tile_fifo_size;
1517 unsigned sc_earlyz_tile_fifo_size;
1518
1519 unsigned num_shader_engines;
1520 unsigned num_shader_pipes_per_simd;
1521 unsigned num_tile_pipes;
1522 unsigned num_simds_per_se;
1523 unsigned num_backends_per_se;
1524 unsigned backend_disable_mask_per_asic;
1525 unsigned backend_map;
1526 unsigned num_texture_channel_caches;
1527 unsigned mem_max_burst_length_bytes;
1528 unsigned mem_row_size_in_kb;
1529 unsigned shader_engine_tile_size;
1530 unsigned num_gpus;
1531 unsigned multi_gpu_tile_size;
1532
1533 unsigned tile_config;
1534 };
1535
1536 struct si_asic {
1537 unsigned max_shader_engines;
1538 unsigned max_tile_pipes;
1539 unsigned max_cu_per_sh;
1540 unsigned max_sh_per_se;
1541 unsigned max_backends_per_se;
1542 unsigned max_texture_channel_caches;
1543 unsigned max_gprs;
1544 unsigned max_gs_threads;
1545 unsigned max_hw_contexts;
1546 unsigned sc_prim_fifo_size_frontend;
1547 unsigned sc_prim_fifo_size_backend;
1548 unsigned sc_hiz_tile_fifo_size;
1549 unsigned sc_earlyz_tile_fifo_size;
1550
1551 unsigned num_tile_pipes;
1552 unsigned num_backends_per_se;
1553 unsigned backend_disable_mask_per_asic;
1554 unsigned backend_map;
1555 unsigned num_texture_channel_caches;
1556 unsigned mem_max_burst_length_bytes;
1557 unsigned mem_row_size_in_kb;
1558 unsigned shader_engine_tile_size;
1559 unsigned num_gpus;
1560 unsigned multi_gpu_tile_size;
1561
1562 unsigned tile_config;
1563 uint32_t tile_mode_array[32];
1564 };
1565
1566 struct cik_asic {
1567 unsigned max_shader_engines;
1568 unsigned max_tile_pipes;
1569 unsigned max_cu_per_sh;
1570 unsigned max_sh_per_se;
1571 unsigned max_backends_per_se;
1572 unsigned max_texture_channel_caches;
1573 unsigned max_gprs;
1574 unsigned max_gs_threads;
1575 unsigned max_hw_contexts;
1576 unsigned sc_prim_fifo_size_frontend;
1577 unsigned sc_prim_fifo_size_backend;
1578 unsigned sc_hiz_tile_fifo_size;
1579 unsigned sc_earlyz_tile_fifo_size;
1580
1581 unsigned num_tile_pipes;
1582 unsigned num_backends_per_se;
1583 unsigned backend_disable_mask_per_asic;
1584 unsigned backend_map;
1585 unsigned num_texture_channel_caches;
1586 unsigned mem_max_burst_length_bytes;
1587 unsigned mem_row_size_in_kb;
1588 unsigned shader_engine_tile_size;
1589 unsigned num_gpus;
1590 unsigned multi_gpu_tile_size;
1591
1592 unsigned tile_config;
1593 uint32_t tile_mode_array[32];
1594 };
1595
1596 union radeon_asic_config {
1597 struct r300_asic r300;
1598 struct r100_asic r100;
1599 struct r600_asic r600;
1600 struct rv770_asic rv770;
1601 struct evergreen_asic evergreen;
1602 struct cayman_asic cayman;
1603 struct si_asic si;
1604 struct cik_asic cik;
1605 };
1606
1607 /*
1608 * asic initizalization from radeon_asic.c
1609 */
1610 void radeon_agp_disable(struct radeon_device *rdev);
1611 int radeon_asic_init(struct radeon_device *rdev);
1612
1613
1614 /*
1615 * IOCTL.
1616 */
1617 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1618 struct drm_file *filp);
1619 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1620 struct drm_file *filp);
1621 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1622 struct drm_file *file_priv);
1623 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1624 struct drm_file *file_priv);
1625 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1626 struct drm_file *file_priv);
1627 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1628 struct drm_file *file_priv);
1629 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1630 struct drm_file *filp);
1631 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1632 struct drm_file *filp);
1633 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1634 struct drm_file *filp);
1635 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1636 struct drm_file *filp);
1637 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1638 struct drm_file *filp);
1639 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1640 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1641 struct drm_file *filp);
1642 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1643 struct drm_file *filp);
1644
1645 /* VRAM scratch page for HDP bug, default vram page */
1646 struct r600_vram_scratch {
1647 struct radeon_bo *robj;
1648 volatile uint32_t *ptr;
1649 u64 gpu_addr;
1650 };
1651
1652 /*
1653 * ACPI
1654 */
1655 struct radeon_atif_notification_cfg {
1656 bool enabled;
1657 int command_code;
1658 };
1659
1660 struct radeon_atif_notifications {
1661 bool display_switch;
1662 bool expansion_mode_change;
1663 bool thermal_state;
1664 bool forced_power_state;
1665 bool system_power_state;
1666 bool display_conf_change;
1667 bool px_gfx_switch;
1668 bool brightness_change;
1669 bool dgpu_display_event;
1670 };
1671
1672 struct radeon_atif_functions {
1673 bool system_params;
1674 bool sbios_requests;
1675 bool select_active_disp;
1676 bool lid_state;
1677 bool get_tv_standard;
1678 bool set_tv_standard;
1679 bool get_panel_expansion_mode;
1680 bool set_panel_expansion_mode;
1681 bool temperature_change;
1682 bool graphics_device_types;
1683 };
1684
1685 struct radeon_atif {
1686 struct radeon_atif_notifications notifications;
1687 struct radeon_atif_functions functions;
1688 struct radeon_atif_notification_cfg notification_cfg;
1689 struct radeon_encoder *encoder_for_bl;
1690 };
1691
1692 struct radeon_atcs_functions {
1693 bool get_ext_state;
1694 bool pcie_perf_req;
1695 bool pcie_dev_rdy;
1696 bool pcie_bus_width;
1697 };
1698
1699 struct radeon_atcs {
1700 struct radeon_atcs_functions functions;
1701 };
1702
1703 /*
1704 * Core structure, functions and helpers.
1705 */
1706 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1707 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1708
1709 struct radeon_device {
1710 struct device *dev;
1711 struct drm_device *ddev;
1712 struct pci_dev *pdev;
1713 struct rw_semaphore exclusive_lock;
1714 /* ASIC */
1715 union radeon_asic_config config;
1716 enum radeon_family family;
1717 unsigned long flags;
1718 int usec_timeout;
1719 enum radeon_pll_errata pll_errata;
1720 int num_gb_pipes;
1721 int num_z_pipes;
1722 int disp_priority;
1723 /* BIOS */
1724 uint8_t *bios;
1725 bool is_atom_bios;
1726 uint16_t bios_header_start;
1727 struct radeon_bo *stollen_vga_memory;
1728 /* Register mmio */
1729 resource_size_t rmmio_base;
1730 resource_size_t rmmio_size;
1731 /* protects concurrent MM_INDEX/DATA based register access */
1732 spinlock_t mmio_idx_lock;
1733 void __iomem *rmmio;
1734 radeon_rreg_t mc_rreg;
1735 radeon_wreg_t mc_wreg;
1736 radeon_rreg_t pll_rreg;
1737 radeon_wreg_t pll_wreg;
1738 uint32_t pcie_reg_mask;
1739 radeon_rreg_t pciep_rreg;
1740 radeon_wreg_t pciep_wreg;
1741 /* io port */
1742 void __iomem *rio_mem;
1743 resource_size_t rio_mem_size;
1744 struct radeon_clock clock;
1745 struct radeon_mc mc;
1746 struct radeon_gart gart;
1747 struct radeon_mode_info mode_info;
1748 struct radeon_scratch scratch;
1749 struct radeon_doorbell doorbell;
1750 struct radeon_mman mman;
1751 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1752 wait_queue_head_t fence_queue;
1753 struct mutex ring_lock;
1754 struct radeon_ring ring[RADEON_NUM_RINGS];
1755 bool ib_pool_ready;
1756 struct radeon_sa_manager ring_tmp_bo;
1757 struct radeon_irq irq;
1758 struct radeon_asic *asic;
1759 struct radeon_gem gem;
1760 struct radeon_pm pm;
1761 struct radeon_uvd uvd;
1762 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1763 struct radeon_wb wb;
1764 struct radeon_dummy_page dummy_page;
1765 bool shutdown;
1766 bool suspend;
1767 bool need_dma32;
1768 bool accel_working;
1769 bool fastfb_working; /* IGP feature*/
1770 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1771 const struct firmware *me_fw; /* all family ME firmware */
1772 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1773 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1774 const struct firmware *mc_fw; /* NI MC firmware */
1775 const struct firmware *ce_fw; /* SI CE firmware */
1776 const struct firmware *uvd_fw; /* UVD firmware */
1777 const struct firmware *mec_fw; /* CIK MEC firmware */
1778 const struct firmware *sdma_fw; /* CIK SDMA firmware */
1779 struct r600_blit r600_blit;
1780 struct r600_vram_scratch vram_scratch;
1781 int msi_enabled; /* msi enabled */
1782 struct r600_ih ih; /* r6/700 interrupt ring */
1783 struct radeon_rlc rlc;
1784 struct radeon_mec mec;
1785 struct work_struct hotplug_work;
1786 struct work_struct audio_work;
1787 struct work_struct reset_work;
1788 int num_crtc; /* number of crtcs */
1789 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1790 bool audio_enabled;
1791 bool has_uvd;
1792 struct r600_audio audio_status; /* audio stuff */
1793 struct notifier_block acpi_nb;
1794 /* only one userspace can use Hyperz features or CMASK at a time */
1795 struct drm_file *hyperz_filp;
1796 struct drm_file *cmask_filp;
1797 /* i2c buses */
1798 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1799 /* debugfs */
1800 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1801 unsigned debugfs_count;
1802 /* virtual memory */
1803 struct radeon_vm_manager vm_manager;
1804 struct mutex gpu_clock_mutex;
1805 /* ACPI interface */
1806 struct radeon_atif atif;
1807 struct radeon_atcs atcs;
1808 };
1809
1810 int radeon_device_init(struct radeon_device *rdev,
1811 struct drm_device *ddev,
1812 struct pci_dev *pdev,
1813 uint32_t flags);
1814 void radeon_device_fini(struct radeon_device *rdev);
1815 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1816
1817 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1818 bool always_indirect);
1819 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1820 bool always_indirect);
1821 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1822 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1823
1824 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
1825 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
1826
1827 /*
1828 * Cast helper
1829 */
1830 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1831
1832 /*
1833 * Registers read & write functions.
1834 */
1835 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1836 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1837 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1838 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1839 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1840 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1841 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1842 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1843 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1844 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1845 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1846 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1847 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1848 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1849 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1850 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1851 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1852 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1853 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1854 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
1855 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
1856 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
1857 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
1858 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
1859 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
1860 #define WREG32_P(reg, val, mask) \
1861 do { \
1862 uint32_t tmp_ = RREG32(reg); \
1863 tmp_ &= (mask); \
1864 tmp_ |= ((val) & ~(mask)); \
1865 WREG32(reg, tmp_); \
1866 } while (0)
1867 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1868 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
1869 #define WREG32_PLL_P(reg, val, mask) \
1870 do { \
1871 uint32_t tmp_ = RREG32_PLL(reg); \
1872 tmp_ &= (mask); \
1873 tmp_ |= ((val) & ~(mask)); \
1874 WREG32_PLL(reg, tmp_); \
1875 } while (0)
1876 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1877 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1878 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1879
1880 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
1881 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
1882
1883 /*
1884 * Indirect registers accessor
1885 */
1886 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1887 {
1888 uint32_t r;
1889
1890 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1891 r = RREG32(RADEON_PCIE_DATA);
1892 return r;
1893 }
1894
1895 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1896 {
1897 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1898 WREG32(RADEON_PCIE_DATA, (v));
1899 }
1900
1901 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
1902 {
1903 u32 r;
1904
1905 WREG32(TN_SMC_IND_INDEX_0, (reg));
1906 r = RREG32(TN_SMC_IND_DATA_0);
1907 return r;
1908 }
1909
1910 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1911 {
1912 WREG32(TN_SMC_IND_INDEX_0, (reg));
1913 WREG32(TN_SMC_IND_DATA_0, (v));
1914 }
1915
1916 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
1917 {
1918 u32 r;
1919
1920 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
1921 r = RREG32(R600_RCU_DATA);
1922 return r;
1923 }
1924
1925 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1926 {
1927 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
1928 WREG32(R600_RCU_DATA, (v));
1929 }
1930
1931 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
1932 {
1933 u32 r;
1934
1935 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
1936 r = RREG32(EVERGREEN_CG_IND_DATA);
1937 return r;
1938 }
1939
1940 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1941 {
1942 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
1943 WREG32(EVERGREEN_CG_IND_DATA, (v));
1944 }
1945
1946 void r100_pll_errata_after_index(struct radeon_device *rdev);
1947
1948
1949 /*
1950 * ASICs helpers.
1951 */
1952 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1953 (rdev->pdev->device == 0x5969))
1954 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1955 (rdev->family == CHIP_RV200) || \
1956 (rdev->family == CHIP_RS100) || \
1957 (rdev->family == CHIP_RS200) || \
1958 (rdev->family == CHIP_RV250) || \
1959 (rdev->family == CHIP_RV280) || \
1960 (rdev->family == CHIP_RS300))
1961 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1962 (rdev->family == CHIP_RV350) || \
1963 (rdev->family == CHIP_R350) || \
1964 (rdev->family == CHIP_RV380) || \
1965 (rdev->family == CHIP_R420) || \
1966 (rdev->family == CHIP_R423) || \
1967 (rdev->family == CHIP_RV410) || \
1968 (rdev->family == CHIP_RS400) || \
1969 (rdev->family == CHIP_RS480))
1970 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1971 (rdev->ddev->pdev->device == 0x9443) || \
1972 (rdev->ddev->pdev->device == 0x944B) || \
1973 (rdev->ddev->pdev->device == 0x9506) || \
1974 (rdev->ddev->pdev->device == 0x9509) || \
1975 (rdev->ddev->pdev->device == 0x950F) || \
1976 (rdev->ddev->pdev->device == 0x689C) || \
1977 (rdev->ddev->pdev->device == 0x689D))
1978 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1979 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1980 (rdev->family == CHIP_RS690) || \
1981 (rdev->family == CHIP_RS740) || \
1982 (rdev->family >= CHIP_R600))
1983 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1984 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1985 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1986 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1987 (rdev->flags & RADEON_IS_IGP))
1988 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1989 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1990 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1991 (rdev->flags & RADEON_IS_IGP))
1992 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1993 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
1994 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
1995
1996 /*
1997 * BIOS helpers.
1998 */
1999 #define RBIOS8(i) (rdev->bios[i])
2000 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2001 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2002
2003 int radeon_combios_init(struct radeon_device *rdev);
2004 void radeon_combios_fini(struct radeon_device *rdev);
2005 int radeon_atombios_init(struct radeon_device *rdev);
2006 void radeon_atombios_fini(struct radeon_device *rdev);
2007
2008
2009 /*
2010 * RING helpers.
2011 */
2012 #if DRM_DEBUG_CODE == 0
2013 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2014 {
2015 ring->ring[ring->wptr++] = v;
2016 ring->wptr &= ring->ptr_mask;
2017 ring->count_dw--;
2018 ring->ring_free_dw--;
2019 }
2020 #else
2021 /* With debugging this is just too big to inline */
2022 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2023 #endif
2024
2025 /*
2026 * ASICs macro.
2027 */
2028 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2029 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2030 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2031 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2032 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2033 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2034 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2035 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2036 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2037 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2038 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2039 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2040 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2041 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2042 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2043 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2044 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2045 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2046 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2047 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2048 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2049 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2050 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2051 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2052 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2053 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2054 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2055 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2056 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2057 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2058 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2059 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2060 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2061 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2062 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2063 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2064 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2065 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2066 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2067 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2068 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2069 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2070 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2071 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2072 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2073 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2074 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2075 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2076 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2077 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2078 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2079 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2080 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2081 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2082 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2083 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2084 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2085 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2086 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2087 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2088 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2089 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2090 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2091 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2092 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2093 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2094
2095 /* Common functions */
2096 /* AGP */
2097 extern int radeon_gpu_reset(struct radeon_device *rdev);
2098 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2099 extern void radeon_agp_disable(struct radeon_device *rdev);
2100 extern int radeon_modeset_init(struct radeon_device *rdev);
2101 extern void radeon_modeset_fini(struct radeon_device *rdev);
2102 extern bool radeon_card_posted(struct radeon_device *rdev);
2103 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2104 extern void radeon_update_display_priority(struct radeon_device *rdev);
2105 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2106 extern void radeon_scratch_init(struct radeon_device *rdev);
2107 extern void radeon_wb_fini(struct radeon_device *rdev);
2108 extern int radeon_wb_init(struct radeon_device *rdev);
2109 extern void radeon_wb_disable(struct radeon_device *rdev);
2110 extern void radeon_surface_init(struct radeon_device *rdev);
2111 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2112 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2113 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2114 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2115 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2116 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2117 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2118 extern int radeon_resume_kms(struct drm_device *dev);
2119 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2120 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2121 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2122 const u32 *registers,
2123 const u32 array_size);
2124
2125 /*
2126 * vm
2127 */
2128 int radeon_vm_manager_init(struct radeon_device *rdev);
2129 void radeon_vm_manager_fini(struct radeon_device *rdev);
2130 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2131 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2132 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2133 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2134 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2135 struct radeon_vm *vm, int ring);
2136 void radeon_vm_fence(struct radeon_device *rdev,
2137 struct radeon_vm *vm,
2138 struct radeon_fence *fence);
2139 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2140 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2141 struct radeon_vm *vm,
2142 struct radeon_bo *bo,
2143 struct ttm_mem_reg *mem);
2144 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2145 struct radeon_bo *bo);
2146 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2147 struct radeon_bo *bo);
2148 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2149 struct radeon_vm *vm,
2150 struct radeon_bo *bo);
2151 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2152 struct radeon_bo_va *bo_va,
2153 uint64_t offset,
2154 uint32_t flags);
2155 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2156 struct radeon_bo_va *bo_va);
2157
2158 /* audio */
2159 void r600_audio_update_hdmi(struct work_struct *work);
2160
2161 /*
2162 * R600 vram scratch functions
2163 */
2164 int r600_vram_scratch_init(struct radeon_device *rdev);
2165 void r600_vram_scratch_fini(struct radeon_device *rdev);
2166
2167 /*
2168 * r600 cs checking helper
2169 */
2170 unsigned r600_mip_minify(unsigned size, unsigned level);
2171 bool r600_fmt_is_valid_color(u32 format);
2172 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2173 int r600_fmt_get_blocksize(u32 format);
2174 int r600_fmt_get_nblocksx(u32 format, u32 w);
2175 int r600_fmt_get_nblocksy(u32 format, u32 h);
2176
2177 /*
2178 * r600 functions used by radeon_encoder.c
2179 */
2180 struct radeon_hdmi_acr {
2181 u32 clock;
2182
2183 int n_32khz;
2184 int cts_32khz;
2185
2186 int n_44_1khz;
2187 int cts_44_1khz;
2188
2189 int n_48khz;
2190 int cts_48khz;
2191
2192 };
2193
2194 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2195
2196 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2197 u32 tiling_pipe_num,
2198 u32 max_rb_num,
2199 u32 total_max_rb_num,
2200 u32 enabled_rb_mask);
2201
2202 /*
2203 * evergreen functions used by radeon_encoder.c
2204 */
2205
2206 extern int ni_init_microcode(struct radeon_device *rdev);
2207 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2208
2209 /* radeon_acpi.c */
2210 #if defined(CONFIG_ACPI)
2211 extern int radeon_acpi_init(struct radeon_device *rdev);
2212 extern void radeon_acpi_fini(struct radeon_device *rdev);
2213 #else
2214 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2215 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2216 #endif
2217
2218 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2219 struct radeon_cs_packet *pkt,
2220 unsigned idx);
2221 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2222 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2223 struct radeon_cs_packet *pkt);
2224 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2225 struct radeon_cs_reloc **cs_reloc,
2226 int nomm);
2227 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2228 uint32_t *vline_start_end,
2229 uint32_t *vline_status);
2230
2231 #include "radeon_object.h"
2232
2233 #endif
Linux kernel - Deliverables
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