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Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103 extern int radeon_vm_size;
104 extern int radeon_vm_block_size;
105 extern int radeon_deep_color;
106
107 /*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
111 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
113 /* RADEON_IB_POOL_SIZE must be a power of 2 */
114 #define RADEON_IB_POOL_SIZE 16
115 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
116 #define RADEONFB_CONN_LIMIT 4
117 #define RADEON_BIOS_NUM_SCRATCH 8
118
119 /* fence seq are set to this number when signaled */
120 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122 /* internal ring indices */
123 /* r1xx+ has gfx CP ring */
124 #define RADEON_RING_TYPE_GFX_INDEX 0
125
126 /* cayman has 2 compute CP rings */
127 #define CAYMAN_RING_TYPE_CP1_INDEX 1
128 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129
130 /* R600+ has an async dma ring */
131 #define R600_RING_TYPE_DMA_INDEX 3
132 /* cayman add a second async dma ring */
133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134
135 /* R600+ */
136 #define R600_RING_TYPE_UVD_INDEX 5
137
138 /* TN+ */
139 #define TN_RING_TYPE_VCE1_INDEX 6
140 #define TN_RING_TYPE_VCE2_INDEX 7
141
142 /* max number of rings */
143 #define RADEON_NUM_RINGS 8
144
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* hardcode those limit for now */
152 #define RADEON_VA_IB_OFFSET (1 << 20)
153 #define RADEON_VA_RESERVED_SIZE (8 << 20)
154 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
155
156 /* hard reset data */
157 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
159 /* reset flags */
160 #define RADEON_RESET_GFX (1 << 0)
161 #define RADEON_RESET_COMPUTE (1 << 1)
162 #define RADEON_RESET_DMA (1 << 2)
163 #define RADEON_RESET_CP (1 << 3)
164 #define RADEON_RESET_GRBM (1 << 4)
165 #define RADEON_RESET_DMA1 (1 << 5)
166 #define RADEON_RESET_RLC (1 << 6)
167 #define RADEON_RESET_SEM (1 << 7)
168 #define RADEON_RESET_IH (1 << 8)
169 #define RADEON_RESET_VMC (1 << 9)
170 #define RADEON_RESET_MC (1 << 10)
171 #define RADEON_RESET_DISPLAY (1 << 11)
172
173 /* CG block flags */
174 #define RADEON_CG_BLOCK_GFX (1 << 0)
175 #define RADEON_CG_BLOCK_MC (1 << 1)
176 #define RADEON_CG_BLOCK_SDMA (1 << 2)
177 #define RADEON_CG_BLOCK_UVD (1 << 3)
178 #define RADEON_CG_BLOCK_VCE (1 << 4)
179 #define RADEON_CG_BLOCK_HDP (1 << 5)
180 #define RADEON_CG_BLOCK_BIF (1 << 6)
181
182 /* CG flags */
183 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201 /* PG flags */
202 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
203 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205 #define RADEON_PG_SUPPORT_UVD (1 << 3)
206 #define RADEON_PG_SUPPORT_VCE (1 << 4)
207 #define RADEON_PG_SUPPORT_CP (1 << 5)
208 #define RADEON_PG_SUPPORT_GDS (1 << 6)
209 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
211 #define RADEON_PG_SUPPORT_ACP (1 << 9)
212 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
214 /* max cursor sizes (in pixels) */
215 #define CURSOR_WIDTH 64
216 #define CURSOR_HEIGHT 64
217
218 #define CIK_CURSOR_WIDTH 128
219 #define CIK_CURSOR_HEIGHT 128
220
221 /*
222 * Errata workarounds.
223 */
224 enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228 };
229
230
231 struct radeon_device;
232
233
234 /*
235 * BIOS.
236 */
237 bool radeon_get_bios(struct radeon_device *rdev);
238
239 /*
240 * Dummy page
241 */
242 struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245 };
246 int radeon_dummy_page_init(struct radeon_device *rdev);
247 void radeon_dummy_page_fini(struct radeon_device *rdev);
248
249
250 /*
251 * Clocks
252 */
253 struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
256 struct radeon_pll dcpll;
257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
262 uint32_t default_dispclk;
263 uint32_t current_dispclk;
264 uint32_t dp_extclk;
265 uint32_t max_pixel_clock;
266 };
267
268 /*
269 * Power management
270 */
271 int radeon_pm_init(struct radeon_device *rdev);
272 int radeon_pm_late_init(struct radeon_device *rdev);
273 void radeon_pm_fini(struct radeon_device *rdev);
274 void radeon_pm_compute_clocks(struct radeon_device *rdev);
275 void radeon_pm_suspend(struct radeon_device *rdev);
276 void radeon_pm_resume(struct radeon_device *rdev);
277 void radeon_combios_get_power_modes(struct radeon_device *rdev);
278 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
279 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
284 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
288 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
289 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
296 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
298 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
301 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
307 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode,
317 struct atom_voltage_table *voltage_table);
318 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
320 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
321 u32 mem_clock);
322 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
323 u32 mem_clock);
324 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
325 u8 module_index,
326 struct atom_mc_reg_table *reg_table);
327 int radeon_atom_get_memory_info(struct radeon_device *rdev,
328 u8 module_index, struct atom_memory_info *mem_info);
329 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
330 bool gddr5, u8 module_index,
331 struct atom_memory_clock_range_table *mclk_range_table);
332 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
333 u16 voltage_id, u16 *voltage);
334 void rs690_pm_info(struct radeon_device *rdev);
335 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
336 unsigned *bankh, unsigned *mtaspect,
337 unsigned *tile_split);
338
339 /*
340 * Fences.
341 */
342 struct radeon_fence_driver {
343 uint32_t scratch_reg;
344 uint64_t gpu_addr;
345 volatile uint32_t *cpu_addr;
346 /* sync_seq is protected by ring emission lock */
347 uint64_t sync_seq[RADEON_NUM_RINGS];
348 atomic64_t last_seq;
349 bool initialized;
350 };
351
352 struct radeon_fence {
353 struct radeon_device *rdev;
354 struct kref kref;
355 /* protected by radeon_fence.lock */
356 uint64_t seq;
357 /* RB, DMA, etc. */
358 unsigned ring;
359 };
360
361 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
362 int radeon_fence_driver_init(struct radeon_device *rdev);
363 void radeon_fence_driver_fini(struct radeon_device *rdev);
364 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
365 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
366 void radeon_fence_process(struct radeon_device *rdev, int ring);
367 bool radeon_fence_signaled(struct radeon_fence *fence);
368 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
369 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
370 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
371 int radeon_fence_wait_any(struct radeon_device *rdev,
372 struct radeon_fence **fences,
373 bool intr);
374 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
375 void radeon_fence_unref(struct radeon_fence **fence);
376 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
377 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
378 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
379 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
380 struct radeon_fence *b)
381 {
382 if (!a) {
383 return b;
384 }
385
386 if (!b) {
387 return a;
388 }
389
390 BUG_ON(a->ring != b->ring);
391
392 if (a->seq > b->seq) {
393 return a;
394 } else {
395 return b;
396 }
397 }
398
399 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
400 struct radeon_fence *b)
401 {
402 if (!a) {
403 return false;
404 }
405
406 if (!b) {
407 return true;
408 }
409
410 BUG_ON(a->ring != b->ring);
411
412 return a->seq < b->seq;
413 }
414
415 /*
416 * Tiling registers
417 */
418 struct radeon_surface_reg {
419 struct radeon_bo *bo;
420 };
421
422 #define RADEON_GEM_MAX_SURFACES 8
423
424 /*
425 * TTM.
426 */
427 struct radeon_mman {
428 struct ttm_bo_global_ref bo_global_ref;
429 struct drm_global_reference mem_global_ref;
430 struct ttm_bo_device bdev;
431 bool mem_global_referenced;
432 bool initialized;
433
434 #if defined(CONFIG_DEBUG_FS)
435 struct dentry *vram;
436 struct dentry *gtt;
437 #endif
438 };
439
440 /* bo virtual address in a specific vm */
441 struct radeon_bo_va {
442 /* protected by bo being reserved */
443 struct list_head bo_list;
444 uint64_t soffset;
445 uint64_t eoffset;
446 uint32_t flags;
447 bool valid;
448 unsigned ref_count;
449
450 /* protected by vm mutex */
451 struct list_head vm_list;
452
453 /* constant after initialization */
454 struct radeon_vm *vm;
455 struct radeon_bo *bo;
456 };
457
458 struct radeon_bo {
459 /* Protected by gem.mutex */
460 struct list_head list;
461 /* Protected by tbo.reserved */
462 u32 initial_domain;
463 u32 placements[3];
464 struct ttm_placement placement;
465 struct ttm_buffer_object tbo;
466 struct ttm_bo_kmap_obj kmap;
467 unsigned pin_count;
468 void *kptr;
469 u32 tiling_flags;
470 u32 pitch;
471 int surface_reg;
472 /* list of all virtual address to which this bo
473 * is associated to
474 */
475 struct list_head va;
476 /* Constant after initialization */
477 struct radeon_device *rdev;
478 struct drm_gem_object gem_base;
479
480 struct ttm_bo_kmap_obj dma_buf_vmap;
481 pid_t pid;
482 };
483 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
484
485 int radeon_gem_debugfs_init(struct radeon_device *rdev);
486
487 /* sub-allocation manager, it has to be protected by another lock.
488 * By conception this is an helper for other part of the driver
489 * like the indirect buffer or semaphore, which both have their
490 * locking.
491 *
492 * Principe is simple, we keep a list of sub allocation in offset
493 * order (first entry has offset == 0, last entry has the highest
494 * offset).
495 *
496 * When allocating new object we first check if there is room at
497 * the end total_size - (last_object_offset + last_object_size) >=
498 * alloc_size. If so we allocate new object there.
499 *
500 * When there is not enough room at the end, we start waiting for
501 * each sub object until we reach object_offset+object_size >=
502 * alloc_size, this object then become the sub object we return.
503 *
504 * Alignment can't be bigger than page size.
505 *
506 * Hole are not considered for allocation to keep things simple.
507 * Assumption is that there won't be hole (all object on same
508 * alignment).
509 */
510 struct radeon_sa_manager {
511 wait_queue_head_t wq;
512 struct radeon_bo *bo;
513 struct list_head *hole;
514 struct list_head flist[RADEON_NUM_RINGS];
515 struct list_head olist;
516 unsigned size;
517 uint64_t gpu_addr;
518 void *cpu_ptr;
519 uint32_t domain;
520 uint32_t align;
521 };
522
523 struct radeon_sa_bo;
524
525 /* sub-allocation buffer */
526 struct radeon_sa_bo {
527 struct list_head olist;
528 struct list_head flist;
529 struct radeon_sa_manager *manager;
530 unsigned soffset;
531 unsigned eoffset;
532 struct radeon_fence *fence;
533 };
534
535 /*
536 * GEM objects.
537 */
538 struct radeon_gem {
539 struct mutex mutex;
540 struct list_head objects;
541 };
542
543 int radeon_gem_init(struct radeon_device *rdev);
544 void radeon_gem_fini(struct radeon_device *rdev);
545 int radeon_gem_object_create(struct radeon_device *rdev, int size,
546 int alignment, int initial_domain,
547 bool discardable, bool kernel,
548 struct drm_gem_object **obj);
549
550 int radeon_mode_dumb_create(struct drm_file *file_priv,
551 struct drm_device *dev,
552 struct drm_mode_create_dumb *args);
553 int radeon_mode_dumb_mmap(struct drm_file *filp,
554 struct drm_device *dev,
555 uint32_t handle, uint64_t *offset_p);
556
557 /*
558 * Semaphores.
559 */
560 struct radeon_semaphore {
561 struct radeon_sa_bo *sa_bo;
562 signed waiters;
563 uint64_t gpu_addr;
564 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
565 };
566
567 int radeon_semaphore_create(struct radeon_device *rdev,
568 struct radeon_semaphore **semaphore);
569 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
570 struct radeon_semaphore *semaphore);
571 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
572 struct radeon_semaphore *semaphore);
573 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
574 struct radeon_fence *fence);
575 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
576 struct radeon_semaphore *semaphore,
577 int waiting_ring);
578 void radeon_semaphore_free(struct radeon_device *rdev,
579 struct radeon_semaphore **semaphore,
580 struct radeon_fence *fence);
581
582 /*
583 * GART structures, functions & helpers
584 */
585 struct radeon_mc;
586
587 #define RADEON_GPU_PAGE_SIZE 4096
588 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
589 #define RADEON_GPU_PAGE_SHIFT 12
590 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
591
592 struct radeon_gart {
593 dma_addr_t table_addr;
594 struct radeon_bo *robj;
595 void *ptr;
596 unsigned num_gpu_pages;
597 unsigned num_cpu_pages;
598 unsigned table_size;
599 struct page **pages;
600 dma_addr_t *pages_addr;
601 bool ready;
602 };
603
604 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
605 void radeon_gart_table_ram_free(struct radeon_device *rdev);
606 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
607 void radeon_gart_table_vram_free(struct radeon_device *rdev);
608 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
609 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
610 int radeon_gart_init(struct radeon_device *rdev);
611 void radeon_gart_fini(struct radeon_device *rdev);
612 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
613 int pages);
614 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
615 int pages, struct page **pagelist,
616 dma_addr_t *dma_addr);
617 void radeon_gart_restore(struct radeon_device *rdev);
618
619
620 /*
621 * GPU MC structures, functions & helpers
622 */
623 struct radeon_mc {
624 resource_size_t aper_size;
625 resource_size_t aper_base;
626 resource_size_t agp_base;
627 /* for some chips with <= 32MB we need to lie
628 * about vram size near mc fb location */
629 u64 mc_vram_size;
630 u64 visible_vram_size;
631 u64 gtt_size;
632 u64 gtt_start;
633 u64 gtt_end;
634 u64 vram_start;
635 u64 vram_end;
636 unsigned vram_width;
637 u64 real_vram_size;
638 int vram_mtrr;
639 bool vram_is_ddr;
640 bool igp_sideport_enabled;
641 u64 gtt_base_align;
642 u64 mc_mask;
643 };
644
645 bool radeon_combios_sideport_present(struct radeon_device *rdev);
646 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
647
648 /*
649 * GPU scratch registers structures, functions & helpers
650 */
651 struct radeon_scratch {
652 unsigned num_reg;
653 uint32_t reg_base;
654 bool free[32];
655 uint32_t reg[32];
656 };
657
658 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
659 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
660
661 /*
662 * GPU doorbell structures, functions & helpers
663 */
664 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
665
666 struct radeon_doorbell {
667 /* doorbell mmio */
668 resource_size_t base;
669 resource_size_t size;
670 u32 __iomem *ptr;
671 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
672 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
673 };
674
675 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
676 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
677
678 /*
679 * IRQS.
680 */
681
682 struct radeon_flip_work {
683 struct work_struct flip_work;
684 struct work_struct unpin_work;
685 struct radeon_device *rdev;
686 int crtc_id;
687 struct drm_framebuffer *fb;
688 struct drm_pending_vblank_event *event;
689 struct radeon_bo *old_rbo;
690 struct radeon_bo *new_rbo;
691 struct radeon_fence *fence;
692 };
693
694 struct r500_irq_stat_regs {
695 u32 disp_int;
696 u32 hdmi0_status;
697 };
698
699 struct r600_irq_stat_regs {
700 u32 disp_int;
701 u32 disp_int_cont;
702 u32 disp_int_cont2;
703 u32 d1grph_int;
704 u32 d2grph_int;
705 u32 hdmi0_status;
706 u32 hdmi1_status;
707 };
708
709 struct evergreen_irq_stat_regs {
710 u32 disp_int;
711 u32 disp_int_cont;
712 u32 disp_int_cont2;
713 u32 disp_int_cont3;
714 u32 disp_int_cont4;
715 u32 disp_int_cont5;
716 u32 d1grph_int;
717 u32 d2grph_int;
718 u32 d3grph_int;
719 u32 d4grph_int;
720 u32 d5grph_int;
721 u32 d6grph_int;
722 u32 afmt_status1;
723 u32 afmt_status2;
724 u32 afmt_status3;
725 u32 afmt_status4;
726 u32 afmt_status5;
727 u32 afmt_status6;
728 };
729
730 struct cik_irq_stat_regs {
731 u32 disp_int;
732 u32 disp_int_cont;
733 u32 disp_int_cont2;
734 u32 disp_int_cont3;
735 u32 disp_int_cont4;
736 u32 disp_int_cont5;
737 u32 disp_int_cont6;
738 u32 d1grph_int;
739 u32 d2grph_int;
740 u32 d3grph_int;
741 u32 d4grph_int;
742 u32 d5grph_int;
743 u32 d6grph_int;
744 };
745
746 union radeon_irq_stat_regs {
747 struct r500_irq_stat_regs r500;
748 struct r600_irq_stat_regs r600;
749 struct evergreen_irq_stat_regs evergreen;
750 struct cik_irq_stat_regs cik;
751 };
752
753 struct radeon_irq {
754 bool installed;
755 spinlock_t lock;
756 atomic_t ring_int[RADEON_NUM_RINGS];
757 bool crtc_vblank_int[RADEON_MAX_CRTCS];
758 atomic_t pflip[RADEON_MAX_CRTCS];
759 wait_queue_head_t vblank_queue;
760 bool hpd[RADEON_MAX_HPD_PINS];
761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
763 bool dpm_thermal;
764 };
765
766 int radeon_irq_kms_init(struct radeon_device *rdev);
767 void radeon_irq_kms_fini(struct radeon_device *rdev);
768 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
769 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
770 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
776
777 /*
778 * CP & rings.
779 */
780
781 struct radeon_ib {
782 struct radeon_sa_bo *sa_bo;
783 uint32_t length_dw;
784 uint64_t gpu_addr;
785 uint32_t *ptr;
786 int ring;
787 struct radeon_fence *fence;
788 struct radeon_vm *vm;
789 bool is_const_ib;
790 struct radeon_semaphore *semaphore;
791 };
792
793 struct radeon_ring {
794 struct radeon_bo *ring_obj;
795 volatile uint32_t *ring;
796 unsigned rptr_offs;
797 unsigned rptr_save_reg;
798 u64 next_rptr_gpu_addr;
799 volatile u32 *next_rptr_cpu_addr;
800 unsigned wptr;
801 unsigned wptr_old;
802 unsigned ring_size;
803 unsigned ring_free_dw;
804 int count_dw;
805 atomic_t last_rptr;
806 atomic64_t last_activity;
807 uint64_t gpu_addr;
808 uint32_t align_mask;
809 uint32_t ptr_mask;
810 bool ready;
811 u32 nop;
812 u32 idx;
813 u64 last_semaphore_signal_addr;
814 u64 last_semaphore_wait_addr;
815 /* for CIK queues */
816 u32 me;
817 u32 pipe;
818 u32 queue;
819 struct radeon_bo *mqd_obj;
820 u32 doorbell_index;
821 unsigned wptr_offs;
822 };
823
824 struct radeon_mec {
825 struct radeon_bo *hpd_eop_obj;
826 u64 hpd_eop_gpu_addr;
827 u32 num_pipe;
828 u32 num_mec;
829 u32 num_queue;
830 };
831
832 /*
833 * VM
834 */
835
836 /* maximum number of VMIDs */
837 #define RADEON_NUM_VM 16
838
839 /* number of entries in page table */
840 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
841
842 /* PTBs (Page Table Blocks) need to be aligned to 32K */
843 #define RADEON_VM_PTB_ALIGN_SIZE 32768
844 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
845 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
846
847 #define R600_PTE_VALID (1 << 0)
848 #define R600_PTE_SYSTEM (1 << 1)
849 #define R600_PTE_SNOOPED (1 << 2)
850 #define R600_PTE_READABLE (1 << 5)
851 #define R600_PTE_WRITEABLE (1 << 6)
852
853 /* PTE (Page Table Entry) fragment field for different page sizes */
854 #define R600_PTE_FRAG_4KB (0 << 7)
855 #define R600_PTE_FRAG_64KB (4 << 7)
856 #define R600_PTE_FRAG_256KB (6 << 7)
857
858 /* flags used for GART page table entries on R600+ */
859 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
860 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
861
862 struct radeon_vm_pt {
863 struct radeon_bo *bo;
864 uint64_t addr;
865 };
866
867 struct radeon_vm {
868 struct list_head va;
869 unsigned id;
870
871 /* contains the page directory */
872 struct radeon_bo *page_directory;
873 uint64_t pd_gpu_addr;
874 unsigned max_pde_used;
875
876 /* array of page tables, one for each page directory entry */
877 struct radeon_vm_pt *page_tables;
878
879 struct mutex mutex;
880 /* last fence for cs using this vm */
881 struct radeon_fence *fence;
882 /* last flush or NULL if we still need to flush */
883 struct radeon_fence *last_flush;
884 /* last use of vmid */
885 struct radeon_fence *last_id_use;
886 };
887
888 struct radeon_vm_manager {
889 struct radeon_fence *active[RADEON_NUM_VM];
890 uint32_t max_pfn;
891 /* number of VMIDs */
892 unsigned nvm;
893 /* vram base address for page table entry */
894 u64 vram_base_offset;
895 /* is vm enabled? */
896 bool enabled;
897 };
898
899 /*
900 * file private structure
901 */
902 struct radeon_fpriv {
903 struct radeon_vm vm;
904 };
905
906 /*
907 * R6xx+ IH ring
908 */
909 struct r600_ih {
910 struct radeon_bo *ring_obj;
911 volatile uint32_t *ring;
912 unsigned rptr;
913 unsigned ring_size;
914 uint64_t gpu_addr;
915 uint32_t ptr_mask;
916 atomic_t lock;
917 bool enabled;
918 };
919
920 /*
921 * RLC stuff
922 */
923 #include "clearstate_defs.h"
924
925 struct radeon_rlc {
926 /* for power gating */
927 struct radeon_bo *save_restore_obj;
928 uint64_t save_restore_gpu_addr;
929 volatile uint32_t *sr_ptr;
930 const u32 *reg_list;
931 u32 reg_list_size;
932 /* for clear state */
933 struct radeon_bo *clear_state_obj;
934 uint64_t clear_state_gpu_addr;
935 volatile uint32_t *cs_ptr;
936 const struct cs_section_def *cs_data;
937 u32 clear_state_size;
938 /* for cp tables */
939 struct radeon_bo *cp_table_obj;
940 uint64_t cp_table_gpu_addr;
941 volatile uint32_t *cp_table_ptr;
942 u32 cp_table_size;
943 };
944
945 int radeon_ib_get(struct radeon_device *rdev, int ring,
946 struct radeon_ib *ib, struct radeon_vm *vm,
947 unsigned size);
948 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
949 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
950 struct radeon_ib *const_ib);
951 int radeon_ib_pool_init(struct radeon_device *rdev);
952 void radeon_ib_pool_fini(struct radeon_device *rdev);
953 int radeon_ib_ring_tests(struct radeon_device *rdev);
954 /* Ring access between begin & end cannot sleep */
955 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
956 struct radeon_ring *ring);
957 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
958 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
959 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
960 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
961 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
962 void radeon_ring_undo(struct radeon_ring *ring);
963 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
964 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
965 void radeon_ring_lockup_update(struct radeon_device *rdev,
966 struct radeon_ring *ring);
967 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
968 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
969 uint32_t **data);
970 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
971 unsigned size, uint32_t *data);
972 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
973 unsigned rptr_offs, u32 nop);
974 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
975
976
977 /* r600 async dma */
978 void r600_dma_stop(struct radeon_device *rdev);
979 int r600_dma_resume(struct radeon_device *rdev);
980 void r600_dma_fini(struct radeon_device *rdev);
981
982 void cayman_dma_stop(struct radeon_device *rdev);
983 int cayman_dma_resume(struct radeon_device *rdev);
984 void cayman_dma_fini(struct radeon_device *rdev);
985
986 /*
987 * CS.
988 */
989 struct radeon_cs_reloc {
990 struct drm_gem_object *gobj;
991 struct radeon_bo *robj;
992 struct ttm_validate_buffer tv;
993 uint64_t gpu_offset;
994 unsigned prefered_domains;
995 unsigned allowed_domains;
996 uint32_t tiling_flags;
997 uint32_t handle;
998 };
999
1000 struct radeon_cs_chunk {
1001 uint32_t chunk_id;
1002 uint32_t length_dw;
1003 uint32_t *kdata;
1004 void __user *user_ptr;
1005 };
1006
1007 struct radeon_cs_parser {
1008 struct device *dev;
1009 struct radeon_device *rdev;
1010 struct drm_file *filp;
1011 /* chunks */
1012 unsigned nchunks;
1013 struct radeon_cs_chunk *chunks;
1014 uint64_t *chunks_array;
1015 /* IB */
1016 unsigned idx;
1017 /* relocations */
1018 unsigned nrelocs;
1019 struct radeon_cs_reloc *relocs;
1020 struct radeon_cs_reloc **relocs_ptr;
1021 struct radeon_cs_reloc *vm_bos;
1022 struct list_head validated;
1023 unsigned dma_reloc_idx;
1024 /* indices of various chunks */
1025 int chunk_ib_idx;
1026 int chunk_relocs_idx;
1027 int chunk_flags_idx;
1028 int chunk_const_ib_idx;
1029 struct radeon_ib ib;
1030 struct radeon_ib const_ib;
1031 void *track;
1032 unsigned family;
1033 int parser_error;
1034 u32 cs_flags;
1035 u32 ring;
1036 s32 priority;
1037 struct ww_acquire_ctx ticket;
1038 };
1039
1040 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1041 {
1042 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1043
1044 if (ibc->kdata)
1045 return ibc->kdata[idx];
1046 return p->ib.ptr[idx];
1047 }
1048
1049
1050 struct radeon_cs_packet {
1051 unsigned idx;
1052 unsigned type;
1053 unsigned reg;
1054 unsigned opcode;
1055 int count;
1056 unsigned one_reg_wr;
1057 };
1058
1059 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1060 struct radeon_cs_packet *pkt,
1061 unsigned idx, unsigned reg);
1062 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1063 struct radeon_cs_packet *pkt);
1064
1065
1066 /*
1067 * AGP
1068 */
1069 int radeon_agp_init(struct radeon_device *rdev);
1070 void radeon_agp_resume(struct radeon_device *rdev);
1071 void radeon_agp_suspend(struct radeon_device *rdev);
1072 void radeon_agp_fini(struct radeon_device *rdev);
1073
1074
1075 /*
1076 * Writeback
1077 */
1078 struct radeon_wb {
1079 struct radeon_bo *wb_obj;
1080 volatile uint32_t *wb;
1081 uint64_t gpu_addr;
1082 bool enabled;
1083 bool use_event;
1084 };
1085
1086 #define RADEON_WB_SCRATCH_OFFSET 0
1087 #define RADEON_WB_RING0_NEXT_RPTR 256
1088 #define RADEON_WB_CP_RPTR_OFFSET 1024
1089 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1090 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1091 #define R600_WB_DMA_RPTR_OFFSET 1792
1092 #define R600_WB_IH_WPTR_OFFSET 2048
1093 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1094 #define R600_WB_EVENT_OFFSET 3072
1095 #define CIK_WB_CP1_WPTR_OFFSET 3328
1096 #define CIK_WB_CP2_WPTR_OFFSET 3584
1097
1098 /**
1099 * struct radeon_pm - power management datas
1100 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1101 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1102 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1103 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1104 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1105 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1106 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1107 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1108 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1109 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1110 * @needed_bandwidth: current bandwidth needs
1111 *
1112 * It keeps track of various data needed to take powermanagement decision.
1113 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1114 * Equation between gpu/memory clock and available bandwidth is hw dependent
1115 * (type of memory, bus size, efficiency, ...)
1116 */
1117
1118 enum radeon_pm_method {
1119 PM_METHOD_PROFILE,
1120 PM_METHOD_DYNPM,
1121 PM_METHOD_DPM,
1122 };
1123
1124 enum radeon_dynpm_state {
1125 DYNPM_STATE_DISABLED,
1126 DYNPM_STATE_MINIMUM,
1127 DYNPM_STATE_PAUSED,
1128 DYNPM_STATE_ACTIVE,
1129 DYNPM_STATE_SUSPENDED,
1130 };
1131 enum radeon_dynpm_action {
1132 DYNPM_ACTION_NONE,
1133 DYNPM_ACTION_MINIMUM,
1134 DYNPM_ACTION_DOWNCLOCK,
1135 DYNPM_ACTION_UPCLOCK,
1136 DYNPM_ACTION_DEFAULT
1137 };
1138
1139 enum radeon_voltage_type {
1140 VOLTAGE_NONE = 0,
1141 VOLTAGE_GPIO,
1142 VOLTAGE_VDDC,
1143 VOLTAGE_SW
1144 };
1145
1146 enum radeon_pm_state_type {
1147 /* not used for dpm */
1148 POWER_STATE_TYPE_DEFAULT,
1149 POWER_STATE_TYPE_POWERSAVE,
1150 /* user selectable states */
1151 POWER_STATE_TYPE_BATTERY,
1152 POWER_STATE_TYPE_BALANCED,
1153 POWER_STATE_TYPE_PERFORMANCE,
1154 /* internal states */
1155 POWER_STATE_TYPE_INTERNAL_UVD,
1156 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1157 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1158 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1159 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1160 POWER_STATE_TYPE_INTERNAL_BOOT,
1161 POWER_STATE_TYPE_INTERNAL_THERMAL,
1162 POWER_STATE_TYPE_INTERNAL_ACPI,
1163 POWER_STATE_TYPE_INTERNAL_ULV,
1164 POWER_STATE_TYPE_INTERNAL_3DPERF,
1165 };
1166
1167 enum radeon_pm_profile_type {
1168 PM_PROFILE_DEFAULT,
1169 PM_PROFILE_AUTO,
1170 PM_PROFILE_LOW,
1171 PM_PROFILE_MID,
1172 PM_PROFILE_HIGH,
1173 };
1174
1175 #define PM_PROFILE_DEFAULT_IDX 0
1176 #define PM_PROFILE_LOW_SH_IDX 1
1177 #define PM_PROFILE_MID_SH_IDX 2
1178 #define PM_PROFILE_HIGH_SH_IDX 3
1179 #define PM_PROFILE_LOW_MH_IDX 4
1180 #define PM_PROFILE_MID_MH_IDX 5
1181 #define PM_PROFILE_HIGH_MH_IDX 6
1182 #define PM_PROFILE_MAX 7
1183
1184 struct radeon_pm_profile {
1185 int dpms_off_ps_idx;
1186 int dpms_on_ps_idx;
1187 int dpms_off_cm_idx;
1188 int dpms_on_cm_idx;
1189 };
1190
1191 enum radeon_int_thermal_type {
1192 THERMAL_TYPE_NONE,
1193 THERMAL_TYPE_EXTERNAL,
1194 THERMAL_TYPE_EXTERNAL_GPIO,
1195 THERMAL_TYPE_RV6XX,
1196 THERMAL_TYPE_RV770,
1197 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1198 THERMAL_TYPE_EVERGREEN,
1199 THERMAL_TYPE_SUMO,
1200 THERMAL_TYPE_NI,
1201 THERMAL_TYPE_SI,
1202 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1203 THERMAL_TYPE_CI,
1204 THERMAL_TYPE_KV,
1205 };
1206
1207 struct radeon_voltage {
1208 enum radeon_voltage_type type;
1209 /* gpio voltage */
1210 struct radeon_gpio_rec gpio;
1211 u32 delay; /* delay in usec from voltage drop to sclk change */
1212 bool active_high; /* voltage drop is active when bit is high */
1213 /* VDDC voltage */
1214 u8 vddc_id; /* index into vddc voltage table */
1215 u8 vddci_id; /* index into vddci voltage table */
1216 bool vddci_enabled;
1217 /* r6xx+ sw */
1218 u16 voltage;
1219 /* evergreen+ vddci */
1220 u16 vddci;
1221 };
1222
1223 /* clock mode flags */
1224 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1225
1226 struct radeon_pm_clock_info {
1227 /* memory clock */
1228 u32 mclk;
1229 /* engine clock */
1230 u32 sclk;
1231 /* voltage info */
1232 struct radeon_voltage voltage;
1233 /* standardized clock flags */
1234 u32 flags;
1235 };
1236
1237 /* state flags */
1238 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1239
1240 struct radeon_power_state {
1241 enum radeon_pm_state_type type;
1242 struct radeon_pm_clock_info *clock_info;
1243 /* number of valid clock modes in this power state */
1244 int num_clock_modes;
1245 struct radeon_pm_clock_info *default_clock_mode;
1246 /* standardized state flags */
1247 u32 flags;
1248 u32 misc; /* vbios specific flags */
1249 u32 misc2; /* vbios specific flags */
1250 int pcie_lanes; /* pcie lanes */
1251 };
1252
1253 /*
1254 * Some modes are overclocked by very low value, accept them
1255 */
1256 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1257
1258 enum radeon_dpm_auto_throttle_src {
1259 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1260 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1261 };
1262
1263 enum radeon_dpm_event_src {
1264 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1265 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1266 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1267 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1268 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1269 };
1270
1271 #define RADEON_MAX_VCE_LEVELS 6
1272
1273 enum radeon_vce_level {
1274 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1275 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1276 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1277 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1278 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1279 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1280 };
1281
1282 struct radeon_ps {
1283 u32 caps; /* vbios flags */
1284 u32 class; /* vbios flags */
1285 u32 class2; /* vbios flags */
1286 /* UVD clocks */
1287 u32 vclk;
1288 u32 dclk;
1289 /* VCE clocks */
1290 u32 evclk;
1291 u32 ecclk;
1292 bool vce_active;
1293 enum radeon_vce_level vce_level;
1294 /* asic priv */
1295 void *ps_priv;
1296 };
1297
1298 struct radeon_dpm_thermal {
1299 /* thermal interrupt work */
1300 struct work_struct work;
1301 /* low temperature threshold */
1302 int min_temp;
1303 /* high temperature threshold */
1304 int max_temp;
1305 /* was interrupt low to high or high to low */
1306 bool high_to_low;
1307 };
1308
1309 enum radeon_clk_action
1310 {
1311 RADEON_SCLK_UP = 1,
1312 RADEON_SCLK_DOWN
1313 };
1314
1315 struct radeon_blacklist_clocks
1316 {
1317 u32 sclk;
1318 u32 mclk;
1319 enum radeon_clk_action action;
1320 };
1321
1322 struct radeon_clock_and_voltage_limits {
1323 u32 sclk;
1324 u32 mclk;
1325 u16 vddc;
1326 u16 vddci;
1327 };
1328
1329 struct radeon_clock_array {
1330 u32 count;
1331 u32 *values;
1332 };
1333
1334 struct radeon_clock_voltage_dependency_entry {
1335 u32 clk;
1336 u16 v;
1337 };
1338
1339 struct radeon_clock_voltage_dependency_table {
1340 u32 count;
1341 struct radeon_clock_voltage_dependency_entry *entries;
1342 };
1343
1344 union radeon_cac_leakage_entry {
1345 struct {
1346 u16 vddc;
1347 u32 leakage;
1348 };
1349 struct {
1350 u16 vddc1;
1351 u16 vddc2;
1352 u16 vddc3;
1353 };
1354 };
1355
1356 struct radeon_cac_leakage_table {
1357 u32 count;
1358 union radeon_cac_leakage_entry *entries;
1359 };
1360
1361 struct radeon_phase_shedding_limits_entry {
1362 u16 voltage;
1363 u32 sclk;
1364 u32 mclk;
1365 };
1366
1367 struct radeon_phase_shedding_limits_table {
1368 u32 count;
1369 struct radeon_phase_shedding_limits_entry *entries;
1370 };
1371
1372 struct radeon_uvd_clock_voltage_dependency_entry {
1373 u32 vclk;
1374 u32 dclk;
1375 u16 v;
1376 };
1377
1378 struct radeon_uvd_clock_voltage_dependency_table {
1379 u8 count;
1380 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1381 };
1382
1383 struct radeon_vce_clock_voltage_dependency_entry {
1384 u32 ecclk;
1385 u32 evclk;
1386 u16 v;
1387 };
1388
1389 struct radeon_vce_clock_voltage_dependency_table {
1390 u8 count;
1391 struct radeon_vce_clock_voltage_dependency_entry *entries;
1392 };
1393
1394 struct radeon_ppm_table {
1395 u8 ppm_design;
1396 u16 cpu_core_number;
1397 u32 platform_tdp;
1398 u32 small_ac_platform_tdp;
1399 u32 platform_tdc;
1400 u32 small_ac_platform_tdc;
1401 u32 apu_tdp;
1402 u32 dgpu_tdp;
1403 u32 dgpu_ulv_power;
1404 u32 tj_max;
1405 };
1406
1407 struct radeon_cac_tdp_table {
1408 u16 tdp;
1409 u16 configurable_tdp;
1410 u16 tdc;
1411 u16 battery_power_limit;
1412 u16 small_power_limit;
1413 u16 low_cac_leakage;
1414 u16 high_cac_leakage;
1415 u16 maximum_power_delivery_limit;
1416 };
1417
1418 struct radeon_dpm_dynamic_state {
1419 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1420 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1421 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1422 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1423 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1424 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1425 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1426 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1427 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1428 struct radeon_clock_array valid_sclk_values;
1429 struct radeon_clock_array valid_mclk_values;
1430 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1431 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1432 u32 mclk_sclk_ratio;
1433 u32 sclk_mclk_delta;
1434 u16 vddc_vddci_delta;
1435 u16 min_vddc_for_pcie_gen2;
1436 struct radeon_cac_leakage_table cac_leakage_table;
1437 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1438 struct radeon_ppm_table *ppm_table;
1439 struct radeon_cac_tdp_table *cac_tdp_table;
1440 };
1441
1442 struct radeon_dpm_fan {
1443 u16 t_min;
1444 u16 t_med;
1445 u16 t_high;
1446 u16 pwm_min;
1447 u16 pwm_med;
1448 u16 pwm_high;
1449 u8 t_hyst;
1450 u32 cycle_delay;
1451 u16 t_max;
1452 bool ucode_fan_control;
1453 };
1454
1455 enum radeon_pcie_gen {
1456 RADEON_PCIE_GEN1 = 0,
1457 RADEON_PCIE_GEN2 = 1,
1458 RADEON_PCIE_GEN3 = 2,
1459 RADEON_PCIE_GEN_INVALID = 0xffff
1460 };
1461
1462 enum radeon_dpm_forced_level {
1463 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1464 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1465 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1466 };
1467
1468 struct radeon_vce_state {
1469 /* vce clocks */
1470 u32 evclk;
1471 u32 ecclk;
1472 /* gpu clocks */
1473 u32 sclk;
1474 u32 mclk;
1475 u8 clk_idx;
1476 u8 pstate;
1477 };
1478
1479 struct radeon_dpm {
1480 struct radeon_ps *ps;
1481 /* number of valid power states */
1482 int num_ps;
1483 /* current power state that is active */
1484 struct radeon_ps *current_ps;
1485 /* requested power state */
1486 struct radeon_ps *requested_ps;
1487 /* boot up power state */
1488 struct radeon_ps *boot_ps;
1489 /* default uvd power state */
1490 struct radeon_ps *uvd_ps;
1491 /* vce requirements */
1492 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1493 enum radeon_vce_level vce_level;
1494 enum radeon_pm_state_type state;
1495 enum radeon_pm_state_type user_state;
1496 u32 platform_caps;
1497 u32 voltage_response_time;
1498 u32 backbias_response_time;
1499 void *priv;
1500 u32 new_active_crtcs;
1501 int new_active_crtc_count;
1502 u32 current_active_crtcs;
1503 int current_active_crtc_count;
1504 struct radeon_dpm_dynamic_state dyn_state;
1505 struct radeon_dpm_fan fan;
1506 u32 tdp_limit;
1507 u32 near_tdp_limit;
1508 u32 near_tdp_limit_adjusted;
1509 u32 sq_ramping_threshold;
1510 u32 cac_leakage;
1511 u16 tdp_od_limit;
1512 u32 tdp_adjustment;
1513 u16 load_line_slope;
1514 bool power_control;
1515 bool ac_power;
1516 /* special states active */
1517 bool thermal_active;
1518 bool uvd_active;
1519 bool vce_active;
1520 /* thermal handling */
1521 struct radeon_dpm_thermal thermal;
1522 /* forced levels */
1523 enum radeon_dpm_forced_level forced_level;
1524 /* track UVD streams */
1525 unsigned sd;
1526 unsigned hd;
1527 };
1528
1529 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1530 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1531
1532 struct radeon_pm {
1533 struct mutex mutex;
1534 /* write locked while reprogramming mclk */
1535 struct rw_semaphore mclk_lock;
1536 u32 active_crtcs;
1537 int active_crtc_count;
1538 int req_vblank;
1539 bool vblank_sync;
1540 fixed20_12 max_bandwidth;
1541 fixed20_12 igp_sideport_mclk;
1542 fixed20_12 igp_system_mclk;
1543 fixed20_12 igp_ht_link_clk;
1544 fixed20_12 igp_ht_link_width;
1545 fixed20_12 k8_bandwidth;
1546 fixed20_12 sideport_bandwidth;
1547 fixed20_12 ht_bandwidth;
1548 fixed20_12 core_bandwidth;
1549 fixed20_12 sclk;
1550 fixed20_12 mclk;
1551 fixed20_12 needed_bandwidth;
1552 struct radeon_power_state *power_state;
1553 /* number of valid power states */
1554 int num_power_states;
1555 int current_power_state_index;
1556 int current_clock_mode_index;
1557 int requested_power_state_index;
1558 int requested_clock_mode_index;
1559 int default_power_state_index;
1560 u32 current_sclk;
1561 u32 current_mclk;
1562 u16 current_vddc;
1563 u16 current_vddci;
1564 u32 default_sclk;
1565 u32 default_mclk;
1566 u16 default_vddc;
1567 u16 default_vddci;
1568 struct radeon_i2c_chan *i2c_bus;
1569 /* selected pm method */
1570 enum radeon_pm_method pm_method;
1571 /* dynpm power management */
1572 struct delayed_work dynpm_idle_work;
1573 enum radeon_dynpm_state dynpm_state;
1574 enum radeon_dynpm_action dynpm_planned_action;
1575 unsigned long dynpm_action_timeout;
1576 bool dynpm_can_upclock;
1577 bool dynpm_can_downclock;
1578 /* profile-based power management */
1579 enum radeon_pm_profile_type profile;
1580 int profile_index;
1581 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1582 /* internal thermal controller on rv6xx+ */
1583 enum radeon_int_thermal_type int_thermal_type;
1584 struct device *int_hwmon_dev;
1585 /* dpm */
1586 bool dpm_enabled;
1587 struct radeon_dpm dpm;
1588 };
1589
1590 int radeon_pm_get_type_index(struct radeon_device *rdev,
1591 enum radeon_pm_state_type ps_type,
1592 int instance);
1593 /*
1594 * UVD
1595 */
1596 #define RADEON_MAX_UVD_HANDLES 10
1597 #define RADEON_UVD_STACK_SIZE (1024*1024)
1598 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1599
1600 struct radeon_uvd {
1601 struct radeon_bo *vcpu_bo;
1602 void *cpu_addr;
1603 uint64_t gpu_addr;
1604 void *saved_bo;
1605 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1606 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1607 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1608 struct delayed_work idle_work;
1609 };
1610
1611 int radeon_uvd_init(struct radeon_device *rdev);
1612 void radeon_uvd_fini(struct radeon_device *rdev);
1613 int radeon_uvd_suspend(struct radeon_device *rdev);
1614 int radeon_uvd_resume(struct radeon_device *rdev);
1615 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1616 uint32_t handle, struct radeon_fence **fence);
1617 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1618 uint32_t handle, struct radeon_fence **fence);
1619 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1620 void radeon_uvd_free_handles(struct radeon_device *rdev,
1621 struct drm_file *filp);
1622 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1623 void radeon_uvd_note_usage(struct radeon_device *rdev);
1624 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1625 unsigned vclk, unsigned dclk,
1626 unsigned vco_min, unsigned vco_max,
1627 unsigned fb_factor, unsigned fb_mask,
1628 unsigned pd_min, unsigned pd_max,
1629 unsigned pd_even,
1630 unsigned *optimal_fb_div,
1631 unsigned *optimal_vclk_div,
1632 unsigned *optimal_dclk_div);
1633 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1634 unsigned cg_upll_func_cntl);
1635
1636 /*
1637 * VCE
1638 */
1639 #define RADEON_MAX_VCE_HANDLES 16
1640 #define RADEON_VCE_STACK_SIZE (1024*1024)
1641 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1642
1643 struct radeon_vce {
1644 struct radeon_bo *vcpu_bo;
1645 uint64_t gpu_addr;
1646 unsigned fw_version;
1647 unsigned fb_version;
1648 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1649 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1650 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1651 struct delayed_work idle_work;
1652 };
1653
1654 int radeon_vce_init(struct radeon_device *rdev);
1655 void radeon_vce_fini(struct radeon_device *rdev);
1656 int radeon_vce_suspend(struct radeon_device *rdev);
1657 int radeon_vce_resume(struct radeon_device *rdev);
1658 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1659 uint32_t handle, struct radeon_fence **fence);
1660 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1661 uint32_t handle, struct radeon_fence **fence);
1662 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1663 void radeon_vce_note_usage(struct radeon_device *rdev);
1664 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1665 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1666 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1667 struct radeon_ring *ring,
1668 struct radeon_semaphore *semaphore,
1669 bool emit_wait);
1670 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1671 void radeon_vce_fence_emit(struct radeon_device *rdev,
1672 struct radeon_fence *fence);
1673 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1674 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1675
1676 struct r600_audio_pin {
1677 int channels;
1678 int rate;
1679 int bits_per_sample;
1680 u8 status_bits;
1681 u8 category_code;
1682 u32 offset;
1683 bool connected;
1684 u32 id;
1685 };
1686
1687 struct r600_audio {
1688 bool enabled;
1689 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1690 int num_pins;
1691 };
1692
1693 /*
1694 * Benchmarking
1695 */
1696 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1697
1698
1699 /*
1700 * Testing
1701 */
1702 void radeon_test_moves(struct radeon_device *rdev);
1703 void radeon_test_ring_sync(struct radeon_device *rdev,
1704 struct radeon_ring *cpA,
1705 struct radeon_ring *cpB);
1706 void radeon_test_syncing(struct radeon_device *rdev);
1707
1708
1709 /*
1710 * Debugfs
1711 */
1712 struct radeon_debugfs {
1713 struct drm_info_list *files;
1714 unsigned num_files;
1715 };
1716
1717 int radeon_debugfs_add_files(struct radeon_device *rdev,
1718 struct drm_info_list *files,
1719 unsigned nfiles);
1720 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1721
1722 /*
1723 * ASIC ring specific functions.
1724 */
1725 struct radeon_asic_ring {
1726 /* ring read/write ptr handling */
1727 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1728 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1729 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1730
1731 /* validating and patching of IBs */
1732 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1733 int (*cs_parse)(struct radeon_cs_parser *p);
1734
1735 /* command emmit functions */
1736 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1737 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1738 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1739 struct radeon_semaphore *semaphore, bool emit_wait);
1740 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1741
1742 /* testing functions */
1743 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1744 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1745 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1746
1747 /* deprecated */
1748 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1749 };
1750
1751 /*
1752 * ASIC specific functions.
1753 */
1754 struct radeon_asic {
1755 int (*init)(struct radeon_device *rdev);
1756 void (*fini)(struct radeon_device *rdev);
1757 int (*resume)(struct radeon_device *rdev);
1758 int (*suspend)(struct radeon_device *rdev);
1759 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1760 int (*asic_reset)(struct radeon_device *rdev);
1761 /* ioctl hw specific callback. Some hw might want to perform special
1762 * operation on specific ioctl. For instance on wait idle some hw
1763 * might want to perform and HDP flush through MMIO as it seems that
1764 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1765 * through ring.
1766 */
1767 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1768 /* check if 3D engine is idle */
1769 bool (*gui_idle)(struct radeon_device *rdev);
1770 /* wait for mc_idle */
1771 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1772 /* get the reference clock */
1773 u32 (*get_xclk)(struct radeon_device *rdev);
1774 /* get the gpu clock counter */
1775 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1776 /* gart */
1777 struct {
1778 void (*tlb_flush)(struct radeon_device *rdev);
1779 void (*set_page)(struct radeon_device *rdev, unsigned i,
1780 uint64_t addr);
1781 } gart;
1782 struct {
1783 int (*init)(struct radeon_device *rdev);
1784 void (*fini)(struct radeon_device *rdev);
1785 void (*set_page)(struct radeon_device *rdev,
1786 struct radeon_ib *ib,
1787 uint64_t pe,
1788 uint64_t addr, unsigned count,
1789 uint32_t incr, uint32_t flags);
1790 } vm;
1791 /* ring specific callbacks */
1792 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1793 /* irqs */
1794 struct {
1795 int (*set)(struct radeon_device *rdev);
1796 int (*process)(struct radeon_device *rdev);
1797 } irq;
1798 /* displays */
1799 struct {
1800 /* display watermarks */
1801 void (*bandwidth_update)(struct radeon_device *rdev);
1802 /* get frame count */
1803 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1804 /* wait for vblank */
1805 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1806 /* set backlight level */
1807 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1808 /* get backlight level */
1809 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1810 /* audio callbacks */
1811 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1812 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1813 } display;
1814 /* copy functions for bo handling */
1815 struct {
1816 int (*blit)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
1820 struct radeon_fence **fence);
1821 u32 blit_ring_index;
1822 int (*dma)(struct radeon_device *rdev,
1823 uint64_t src_offset,
1824 uint64_t dst_offset,
1825 unsigned num_gpu_pages,
1826 struct radeon_fence **fence);
1827 u32 dma_ring_index;
1828 /* method used for bo copy */
1829 int (*copy)(struct radeon_device *rdev,
1830 uint64_t src_offset,
1831 uint64_t dst_offset,
1832 unsigned num_gpu_pages,
1833 struct radeon_fence **fence);
1834 /* ring used for bo copies */
1835 u32 copy_ring_index;
1836 } copy;
1837 /* surfaces */
1838 struct {
1839 int (*set_reg)(struct radeon_device *rdev, int reg,
1840 uint32_t tiling_flags, uint32_t pitch,
1841 uint32_t offset, uint32_t obj_size);
1842 void (*clear_reg)(struct radeon_device *rdev, int reg);
1843 } surface;
1844 /* hotplug detect */
1845 struct {
1846 void (*init)(struct radeon_device *rdev);
1847 void (*fini)(struct radeon_device *rdev);
1848 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1849 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1850 } hpd;
1851 /* static power management */
1852 struct {
1853 void (*misc)(struct radeon_device *rdev);
1854 void (*prepare)(struct radeon_device *rdev);
1855 void (*finish)(struct radeon_device *rdev);
1856 void (*init_profile)(struct radeon_device *rdev);
1857 void (*get_dynpm_state)(struct radeon_device *rdev);
1858 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1859 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1860 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1861 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1862 int (*get_pcie_lanes)(struct radeon_device *rdev);
1863 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1864 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1865 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1866 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1867 int (*get_temperature)(struct radeon_device *rdev);
1868 } pm;
1869 /* dynamic power management */
1870 struct {
1871 int (*init)(struct radeon_device *rdev);
1872 void (*setup_asic)(struct radeon_device *rdev);
1873 int (*enable)(struct radeon_device *rdev);
1874 int (*late_enable)(struct radeon_device *rdev);
1875 void (*disable)(struct radeon_device *rdev);
1876 int (*pre_set_power_state)(struct radeon_device *rdev);
1877 int (*set_power_state)(struct radeon_device *rdev);
1878 void (*post_set_power_state)(struct radeon_device *rdev);
1879 void (*display_configuration_changed)(struct radeon_device *rdev);
1880 void (*fini)(struct radeon_device *rdev);
1881 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1882 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1883 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1884 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1885 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1886 bool (*vblank_too_short)(struct radeon_device *rdev);
1887 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1888 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1889 } dpm;
1890 /* pageflipping */
1891 struct {
1892 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1893 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1894 } pflip;
1895 };
1896
1897 /*
1898 * Asic structures
1899 */
1900 struct r100_asic {
1901 const unsigned *reg_safe_bm;
1902 unsigned reg_safe_bm_size;
1903 u32 hdp_cntl;
1904 };
1905
1906 struct r300_asic {
1907 const unsigned *reg_safe_bm;
1908 unsigned reg_safe_bm_size;
1909 u32 resync_scratch;
1910 u32 hdp_cntl;
1911 };
1912
1913 struct r600_asic {
1914 unsigned max_pipes;
1915 unsigned max_tile_pipes;
1916 unsigned max_simds;
1917 unsigned max_backends;
1918 unsigned max_gprs;
1919 unsigned max_threads;
1920 unsigned max_stack_entries;
1921 unsigned max_hw_contexts;
1922 unsigned max_gs_threads;
1923 unsigned sx_max_export_size;
1924 unsigned sx_max_export_pos_size;
1925 unsigned sx_max_export_smx_size;
1926 unsigned sq_num_cf_insts;
1927 unsigned tiling_nbanks;
1928 unsigned tiling_npipes;
1929 unsigned tiling_group_size;
1930 unsigned tile_config;
1931 unsigned backend_map;
1932 unsigned active_simds;
1933 };
1934
1935 struct rv770_asic {
1936 unsigned max_pipes;
1937 unsigned max_tile_pipes;
1938 unsigned max_simds;
1939 unsigned max_backends;
1940 unsigned max_gprs;
1941 unsigned max_threads;
1942 unsigned max_stack_entries;
1943 unsigned max_hw_contexts;
1944 unsigned max_gs_threads;
1945 unsigned sx_max_export_size;
1946 unsigned sx_max_export_pos_size;
1947 unsigned sx_max_export_smx_size;
1948 unsigned sq_num_cf_insts;
1949 unsigned sx_num_of_sets;
1950 unsigned sc_prim_fifo_size;
1951 unsigned sc_hiz_tile_fifo_size;
1952 unsigned sc_earlyz_tile_fifo_fize;
1953 unsigned tiling_nbanks;
1954 unsigned tiling_npipes;
1955 unsigned tiling_group_size;
1956 unsigned tile_config;
1957 unsigned backend_map;
1958 unsigned active_simds;
1959 };
1960
1961 struct evergreen_asic {
1962 unsigned num_ses;
1963 unsigned max_pipes;
1964 unsigned max_tile_pipes;
1965 unsigned max_simds;
1966 unsigned max_backends;
1967 unsigned max_gprs;
1968 unsigned max_threads;
1969 unsigned max_stack_entries;
1970 unsigned max_hw_contexts;
1971 unsigned max_gs_threads;
1972 unsigned sx_max_export_size;
1973 unsigned sx_max_export_pos_size;
1974 unsigned sx_max_export_smx_size;
1975 unsigned sq_num_cf_insts;
1976 unsigned sx_num_of_sets;
1977 unsigned sc_prim_fifo_size;
1978 unsigned sc_hiz_tile_fifo_size;
1979 unsigned sc_earlyz_tile_fifo_size;
1980 unsigned tiling_nbanks;
1981 unsigned tiling_npipes;
1982 unsigned tiling_group_size;
1983 unsigned tile_config;
1984 unsigned backend_map;
1985 unsigned active_simds;
1986 };
1987
1988 struct cayman_asic {
1989 unsigned max_shader_engines;
1990 unsigned max_pipes_per_simd;
1991 unsigned max_tile_pipes;
1992 unsigned max_simds_per_se;
1993 unsigned max_backends_per_se;
1994 unsigned max_texture_channel_caches;
1995 unsigned max_gprs;
1996 unsigned max_threads;
1997 unsigned max_gs_threads;
1998 unsigned max_stack_entries;
1999 unsigned sx_num_of_sets;
2000 unsigned sx_max_export_size;
2001 unsigned sx_max_export_pos_size;
2002 unsigned sx_max_export_smx_size;
2003 unsigned max_hw_contexts;
2004 unsigned sq_num_cf_insts;
2005 unsigned sc_prim_fifo_size;
2006 unsigned sc_hiz_tile_fifo_size;
2007 unsigned sc_earlyz_tile_fifo_size;
2008
2009 unsigned num_shader_engines;
2010 unsigned num_shader_pipes_per_simd;
2011 unsigned num_tile_pipes;
2012 unsigned num_simds_per_se;
2013 unsigned num_backends_per_se;
2014 unsigned backend_disable_mask_per_asic;
2015 unsigned backend_map;
2016 unsigned num_texture_channel_caches;
2017 unsigned mem_max_burst_length_bytes;
2018 unsigned mem_row_size_in_kb;
2019 unsigned shader_engine_tile_size;
2020 unsigned num_gpus;
2021 unsigned multi_gpu_tile_size;
2022
2023 unsigned tile_config;
2024 unsigned active_simds;
2025 };
2026
2027 struct si_asic {
2028 unsigned max_shader_engines;
2029 unsigned max_tile_pipes;
2030 unsigned max_cu_per_sh;
2031 unsigned max_sh_per_se;
2032 unsigned max_backends_per_se;
2033 unsigned max_texture_channel_caches;
2034 unsigned max_gprs;
2035 unsigned max_gs_threads;
2036 unsigned max_hw_contexts;
2037 unsigned sc_prim_fifo_size_frontend;
2038 unsigned sc_prim_fifo_size_backend;
2039 unsigned sc_hiz_tile_fifo_size;
2040 unsigned sc_earlyz_tile_fifo_size;
2041
2042 unsigned num_tile_pipes;
2043 unsigned backend_enable_mask;
2044 unsigned backend_disable_mask_per_asic;
2045 unsigned backend_map;
2046 unsigned num_texture_channel_caches;
2047 unsigned mem_max_burst_length_bytes;
2048 unsigned mem_row_size_in_kb;
2049 unsigned shader_engine_tile_size;
2050 unsigned num_gpus;
2051 unsigned multi_gpu_tile_size;
2052
2053 unsigned tile_config;
2054 uint32_t tile_mode_array[32];
2055 uint32_t active_cus;
2056 };
2057
2058 struct cik_asic {
2059 unsigned max_shader_engines;
2060 unsigned max_tile_pipes;
2061 unsigned max_cu_per_sh;
2062 unsigned max_sh_per_se;
2063 unsigned max_backends_per_se;
2064 unsigned max_texture_channel_caches;
2065 unsigned max_gprs;
2066 unsigned max_gs_threads;
2067 unsigned max_hw_contexts;
2068 unsigned sc_prim_fifo_size_frontend;
2069 unsigned sc_prim_fifo_size_backend;
2070 unsigned sc_hiz_tile_fifo_size;
2071 unsigned sc_earlyz_tile_fifo_size;
2072
2073 unsigned num_tile_pipes;
2074 unsigned backend_enable_mask;
2075 unsigned backend_disable_mask_per_asic;
2076 unsigned backend_map;
2077 unsigned num_texture_channel_caches;
2078 unsigned mem_max_burst_length_bytes;
2079 unsigned mem_row_size_in_kb;
2080 unsigned shader_engine_tile_size;
2081 unsigned num_gpus;
2082 unsigned multi_gpu_tile_size;
2083
2084 unsigned tile_config;
2085 uint32_t tile_mode_array[32];
2086 uint32_t macrotile_mode_array[16];
2087 uint32_t active_cus;
2088 };
2089
2090 union radeon_asic_config {
2091 struct r300_asic r300;
2092 struct r100_asic r100;
2093 struct r600_asic r600;
2094 struct rv770_asic rv770;
2095 struct evergreen_asic evergreen;
2096 struct cayman_asic cayman;
2097 struct si_asic si;
2098 struct cik_asic cik;
2099 };
2100
2101 /*
2102 * asic initizalization from radeon_asic.c
2103 */
2104 void radeon_agp_disable(struct radeon_device *rdev);
2105 int radeon_asic_init(struct radeon_device *rdev);
2106
2107
2108 /*
2109 * IOCTL.
2110 */
2111 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2112 struct drm_file *filp);
2113 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2114 struct drm_file *filp);
2115 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2116 struct drm_file *file_priv);
2117 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2118 struct drm_file *file_priv);
2119 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *file_priv);
2121 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *file_priv);
2123 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2124 struct drm_file *filp);
2125 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *filp);
2127 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2129 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2130 struct drm_file *filp);
2131 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *filp);
2133 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *filp);
2135 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2136 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2137 struct drm_file *filp);
2138 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2139 struct drm_file *filp);
2140
2141 /* VRAM scratch page for HDP bug, default vram page */
2142 struct r600_vram_scratch {
2143 struct radeon_bo *robj;
2144 volatile uint32_t *ptr;
2145 u64 gpu_addr;
2146 };
2147
2148 /*
2149 * ACPI
2150 */
2151 struct radeon_atif_notification_cfg {
2152 bool enabled;
2153 int command_code;
2154 };
2155
2156 struct radeon_atif_notifications {
2157 bool display_switch;
2158 bool expansion_mode_change;
2159 bool thermal_state;
2160 bool forced_power_state;
2161 bool system_power_state;
2162 bool display_conf_change;
2163 bool px_gfx_switch;
2164 bool brightness_change;
2165 bool dgpu_display_event;
2166 };
2167
2168 struct radeon_atif_functions {
2169 bool system_params;
2170 bool sbios_requests;
2171 bool select_active_disp;
2172 bool lid_state;
2173 bool get_tv_standard;
2174 bool set_tv_standard;
2175 bool get_panel_expansion_mode;
2176 bool set_panel_expansion_mode;
2177 bool temperature_change;
2178 bool graphics_device_types;
2179 };
2180
2181 struct radeon_atif {
2182 struct radeon_atif_notifications notifications;
2183 struct radeon_atif_functions functions;
2184 struct radeon_atif_notification_cfg notification_cfg;
2185 struct radeon_encoder *encoder_for_bl;
2186 };
2187
2188 struct radeon_atcs_functions {
2189 bool get_ext_state;
2190 bool pcie_perf_req;
2191 bool pcie_dev_rdy;
2192 bool pcie_bus_width;
2193 };
2194
2195 struct radeon_atcs {
2196 struct radeon_atcs_functions functions;
2197 };
2198
2199 /*
2200 * Core structure, functions and helpers.
2201 */
2202 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2203 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2204
2205 struct radeon_device {
2206 struct device *dev;
2207 struct drm_device *ddev;
2208 struct pci_dev *pdev;
2209 struct rw_semaphore exclusive_lock;
2210 /* ASIC */
2211 union radeon_asic_config config;
2212 enum radeon_family family;
2213 unsigned long flags;
2214 int usec_timeout;
2215 enum radeon_pll_errata pll_errata;
2216 int num_gb_pipes;
2217 int num_z_pipes;
2218 int disp_priority;
2219 /* BIOS */
2220 uint8_t *bios;
2221 bool is_atom_bios;
2222 uint16_t bios_header_start;
2223 struct radeon_bo *stollen_vga_memory;
2224 /* Register mmio */
2225 resource_size_t rmmio_base;
2226 resource_size_t rmmio_size;
2227 /* protects concurrent MM_INDEX/DATA based register access */
2228 spinlock_t mmio_idx_lock;
2229 /* protects concurrent SMC based register access */
2230 spinlock_t smc_idx_lock;
2231 /* protects concurrent PLL register access */
2232 spinlock_t pll_idx_lock;
2233 /* protects concurrent MC register access */
2234 spinlock_t mc_idx_lock;
2235 /* protects concurrent PCIE register access */
2236 spinlock_t pcie_idx_lock;
2237 /* protects concurrent PCIE_PORT register access */
2238 spinlock_t pciep_idx_lock;
2239 /* protects concurrent PIF register access */
2240 spinlock_t pif_idx_lock;
2241 /* protects concurrent CG register access */
2242 spinlock_t cg_idx_lock;
2243 /* protects concurrent UVD register access */
2244 spinlock_t uvd_idx_lock;
2245 /* protects concurrent RCU register access */
2246 spinlock_t rcu_idx_lock;
2247 /* protects concurrent DIDT register access */
2248 spinlock_t didt_idx_lock;
2249 /* protects concurrent ENDPOINT (audio) register access */
2250 spinlock_t end_idx_lock;
2251 void __iomem *rmmio;
2252 radeon_rreg_t mc_rreg;
2253 radeon_wreg_t mc_wreg;
2254 radeon_rreg_t pll_rreg;
2255 radeon_wreg_t pll_wreg;
2256 uint32_t pcie_reg_mask;
2257 radeon_rreg_t pciep_rreg;
2258 radeon_wreg_t pciep_wreg;
2259 /* io port */
2260 void __iomem *rio_mem;
2261 resource_size_t rio_mem_size;
2262 struct radeon_clock clock;
2263 struct radeon_mc mc;
2264 struct radeon_gart gart;
2265 struct radeon_mode_info mode_info;
2266 struct radeon_scratch scratch;
2267 struct radeon_doorbell doorbell;
2268 struct radeon_mman mman;
2269 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2270 wait_queue_head_t fence_queue;
2271 struct mutex ring_lock;
2272 struct radeon_ring ring[RADEON_NUM_RINGS];
2273 bool ib_pool_ready;
2274 struct radeon_sa_manager ring_tmp_bo;
2275 struct radeon_irq irq;
2276 struct radeon_asic *asic;
2277 struct radeon_gem gem;
2278 struct radeon_pm pm;
2279 struct radeon_uvd uvd;
2280 struct radeon_vce vce;
2281 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2282 struct radeon_wb wb;
2283 struct radeon_dummy_page dummy_page;
2284 bool shutdown;
2285 bool suspend;
2286 bool need_dma32;
2287 bool accel_working;
2288 bool fastfb_working; /* IGP feature*/
2289 bool needs_reset;
2290 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2291 const struct firmware *me_fw; /* all family ME firmware */
2292 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2293 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2294 const struct firmware *mc_fw; /* NI MC firmware */
2295 const struct firmware *ce_fw; /* SI CE firmware */
2296 const struct firmware *mec_fw; /* CIK MEC firmware */
2297 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2298 const struct firmware *smc_fw; /* SMC firmware */
2299 const struct firmware *uvd_fw; /* UVD firmware */
2300 const struct firmware *vce_fw; /* VCE firmware */
2301 struct r600_vram_scratch vram_scratch;
2302 int msi_enabled; /* msi enabled */
2303 struct r600_ih ih; /* r6/700 interrupt ring */
2304 struct radeon_rlc rlc;
2305 struct radeon_mec mec;
2306 struct work_struct hotplug_work;
2307 struct work_struct audio_work;
2308 struct work_struct reset_work;
2309 int num_crtc; /* number of crtcs */
2310 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2311 bool has_uvd;
2312 struct r600_audio audio; /* audio stuff */
2313 struct notifier_block acpi_nb;
2314 /* only one userspace can use Hyperz features or CMASK at a time */
2315 struct drm_file *hyperz_filp;
2316 struct drm_file *cmask_filp;
2317 /* i2c buses */
2318 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2319 /* debugfs */
2320 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2321 unsigned debugfs_count;
2322 /* virtual memory */
2323 struct radeon_vm_manager vm_manager;
2324 struct mutex gpu_clock_mutex;
2325 /* memory stats */
2326 atomic64_t vram_usage;
2327 atomic64_t gtt_usage;
2328 atomic64_t num_bytes_moved;
2329 /* ACPI interface */
2330 struct radeon_atif atif;
2331 struct radeon_atcs atcs;
2332 /* srbm instance registers */
2333 struct mutex srbm_mutex;
2334 /* clock, powergating flags */
2335 u32 cg_flags;
2336 u32 pg_flags;
2337
2338 struct dev_pm_domain vga_pm_domain;
2339 bool have_disp_power_ref;
2340 };
2341
2342 bool radeon_is_px(struct drm_device *dev);
2343 int radeon_device_init(struct radeon_device *rdev,
2344 struct drm_device *ddev,
2345 struct pci_dev *pdev,
2346 uint32_t flags);
2347 void radeon_device_fini(struct radeon_device *rdev);
2348 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2349
2350 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2351 bool always_indirect);
2352 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2353 bool always_indirect);
2354 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2355 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2356
2357 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2358 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2359
2360 /*
2361 * Cast helper
2362 */
2363 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2364
2365 /*
2366 * Registers read & write functions.
2367 */
2368 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2369 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2370 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2371 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2372 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2373 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2374 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2375 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2376 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2377 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2378 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2379 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2380 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2381 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2382 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2383 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2384 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2385 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2386 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2387 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2388 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2389 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2390 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2391 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2392 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2393 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2394 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2395 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2396 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2397 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2398 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2399 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2400 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2401 #define WREG32_P(reg, val, mask) \
2402 do { \
2403 uint32_t tmp_ = RREG32(reg); \
2404 tmp_ &= (mask); \
2405 tmp_ |= ((val) & ~(mask)); \
2406 WREG32(reg, tmp_); \
2407 } while (0)
2408 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2409 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2410 #define WREG32_PLL_P(reg, val, mask) \
2411 do { \
2412 uint32_t tmp_ = RREG32_PLL(reg); \
2413 tmp_ &= (mask); \
2414 tmp_ |= ((val) & ~(mask)); \
2415 WREG32_PLL(reg, tmp_); \
2416 } while (0)
2417 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2418 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2419 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2420
2421 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2422 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2423
2424 /*
2425 * Indirect registers accessor
2426 */
2427 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2428 {
2429 unsigned long flags;
2430 uint32_t r;
2431
2432 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2433 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2434 r = RREG32(RADEON_PCIE_DATA);
2435 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2436 return r;
2437 }
2438
2439 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2440 {
2441 unsigned long flags;
2442
2443 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2444 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2445 WREG32(RADEON_PCIE_DATA, (v));
2446 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2447 }
2448
2449 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2450 {
2451 unsigned long flags;
2452 u32 r;
2453
2454 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2455 WREG32(TN_SMC_IND_INDEX_0, (reg));
2456 r = RREG32(TN_SMC_IND_DATA_0);
2457 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2458 return r;
2459 }
2460
2461 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2462 {
2463 unsigned long flags;
2464
2465 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2466 WREG32(TN_SMC_IND_INDEX_0, (reg));
2467 WREG32(TN_SMC_IND_DATA_0, (v));
2468 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2469 }
2470
2471 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2472 {
2473 unsigned long flags;
2474 u32 r;
2475
2476 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2477 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2478 r = RREG32(R600_RCU_DATA);
2479 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2480 return r;
2481 }
2482
2483 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2484 {
2485 unsigned long flags;
2486
2487 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2488 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2489 WREG32(R600_RCU_DATA, (v));
2490 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2491 }
2492
2493 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2494 {
2495 unsigned long flags;
2496 u32 r;
2497
2498 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2499 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2500 r = RREG32(EVERGREEN_CG_IND_DATA);
2501 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2502 return r;
2503 }
2504
2505 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2506 {
2507 unsigned long flags;
2508
2509 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2510 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2511 WREG32(EVERGREEN_CG_IND_DATA, (v));
2512 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2513 }
2514
2515 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2516 {
2517 unsigned long flags;
2518 u32 r;
2519
2520 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2521 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2522 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2523 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2524 return r;
2525 }
2526
2527 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2528 {
2529 unsigned long flags;
2530
2531 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2532 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2533 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2534 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2535 }
2536
2537 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2538 {
2539 unsigned long flags;
2540 u32 r;
2541
2542 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2543 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2544 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2545 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2546 return r;
2547 }
2548
2549 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2550 {
2551 unsigned long flags;
2552
2553 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2554 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2555 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2556 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2557 }
2558
2559 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2560 {
2561 unsigned long flags;
2562 u32 r;
2563
2564 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2565 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2566 r = RREG32(R600_UVD_CTX_DATA);
2567 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2568 return r;
2569 }
2570
2571 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2572 {
2573 unsigned long flags;
2574
2575 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2576 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2577 WREG32(R600_UVD_CTX_DATA, (v));
2578 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2579 }
2580
2581
2582 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2583 {
2584 unsigned long flags;
2585 u32 r;
2586
2587 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2588 WREG32(CIK_DIDT_IND_INDEX, (reg));
2589 r = RREG32(CIK_DIDT_IND_DATA);
2590 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2591 return r;
2592 }
2593
2594 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2595 {
2596 unsigned long flags;
2597
2598 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2599 WREG32(CIK_DIDT_IND_INDEX, (reg));
2600 WREG32(CIK_DIDT_IND_DATA, (v));
2601 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2602 }
2603
2604 void r100_pll_errata_after_index(struct radeon_device *rdev);
2605
2606
2607 /*
2608 * ASICs helpers.
2609 */
2610 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2611 (rdev->pdev->device == 0x5969))
2612 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2613 (rdev->family == CHIP_RV200) || \
2614 (rdev->family == CHIP_RS100) || \
2615 (rdev->family == CHIP_RS200) || \
2616 (rdev->family == CHIP_RV250) || \
2617 (rdev->family == CHIP_RV280) || \
2618 (rdev->family == CHIP_RS300))
2619 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2620 (rdev->family == CHIP_RV350) || \
2621 (rdev->family == CHIP_R350) || \
2622 (rdev->family == CHIP_RV380) || \
2623 (rdev->family == CHIP_R420) || \
2624 (rdev->family == CHIP_R423) || \
2625 (rdev->family == CHIP_RV410) || \
2626 (rdev->family == CHIP_RS400) || \
2627 (rdev->family == CHIP_RS480))
2628 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2629 (rdev->ddev->pdev->device == 0x9443) || \
2630 (rdev->ddev->pdev->device == 0x944B) || \
2631 (rdev->ddev->pdev->device == 0x9506) || \
2632 (rdev->ddev->pdev->device == 0x9509) || \
2633 (rdev->ddev->pdev->device == 0x950F) || \
2634 (rdev->ddev->pdev->device == 0x689C) || \
2635 (rdev->ddev->pdev->device == 0x689D))
2636 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2637 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2638 (rdev->family == CHIP_RS690) || \
2639 (rdev->family == CHIP_RS740) || \
2640 (rdev->family >= CHIP_R600))
2641 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2642 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2643 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2644 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2645 (rdev->flags & RADEON_IS_IGP))
2646 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2647 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2648 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2649 (rdev->flags & RADEON_IS_IGP))
2650 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2651 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2652 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2653 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2654 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2655 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2656 (rdev->family == CHIP_MULLINS))
2657
2658 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2659 (rdev->ddev->pdev->device == 0x6850) || \
2660 (rdev->ddev->pdev->device == 0x6858) || \
2661 (rdev->ddev->pdev->device == 0x6859) || \
2662 (rdev->ddev->pdev->device == 0x6840) || \
2663 (rdev->ddev->pdev->device == 0x6841) || \
2664 (rdev->ddev->pdev->device == 0x6842) || \
2665 (rdev->ddev->pdev->device == 0x6843))
2666
2667 /*
2668 * BIOS helpers.
2669 */
2670 #define RBIOS8(i) (rdev->bios[i])
2671 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2672 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2673
2674 int radeon_combios_init(struct radeon_device *rdev);
2675 void radeon_combios_fini(struct radeon_device *rdev);
2676 int radeon_atombios_init(struct radeon_device *rdev);
2677 void radeon_atombios_fini(struct radeon_device *rdev);
2678
2679
2680 /*
2681 * RING helpers.
2682 */
2683 #if DRM_DEBUG_CODE == 0
2684 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2685 {
2686 ring->ring[ring->wptr++] = v;
2687 ring->wptr &= ring->ptr_mask;
2688 ring->count_dw--;
2689 ring->ring_free_dw--;
2690 }
2691 #else
2692 /* With debugging this is just too big to inline */
2693 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2694 #endif
2695
2696 /*
2697 * ASICs macro.
2698 */
2699 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2700 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2701 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2702 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2703 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2704 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2705 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2706 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2707 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2708 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2709 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2710 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2711 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2712 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2713 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2714 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2715 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2716 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2717 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2718 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2719 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2720 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2721 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2722 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2723 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2724 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2725 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2726 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2727 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2728 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2729 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2730 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2731 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2732 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2733 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2734 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2735 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2736 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2737 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2738 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2739 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2740 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2741 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2742 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2743 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2744 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2745 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2746 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2747 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2748 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2749 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2750 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2751 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2752 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2753 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2754 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2755 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2756 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2757 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2758 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2759 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2760 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2761 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2762 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2763 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2764 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2765 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2766 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2767 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2768 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2769 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2770 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2771 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2772 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2773 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2774 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2775 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2776 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2777 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2778 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2779 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2780 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2781 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2782 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2783
2784 /* Common functions */
2785 /* AGP */
2786 extern int radeon_gpu_reset(struct radeon_device *rdev);
2787 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2788 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2789 extern void radeon_agp_disable(struct radeon_device *rdev);
2790 extern int radeon_modeset_init(struct radeon_device *rdev);
2791 extern void radeon_modeset_fini(struct radeon_device *rdev);
2792 extern bool radeon_card_posted(struct radeon_device *rdev);
2793 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2794 extern void radeon_update_display_priority(struct radeon_device *rdev);
2795 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2796 extern void radeon_scratch_init(struct radeon_device *rdev);
2797 extern void radeon_wb_fini(struct radeon_device *rdev);
2798 extern int radeon_wb_init(struct radeon_device *rdev);
2799 extern void radeon_wb_disable(struct radeon_device *rdev);
2800 extern void radeon_surface_init(struct radeon_device *rdev);
2801 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2802 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2803 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2804 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2805 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2806 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2807 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2808 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2809 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2810 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2811 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2812 const u32 *registers,
2813 const u32 array_size);
2814
2815 /*
2816 * vm
2817 */
2818 int radeon_vm_manager_init(struct radeon_device *rdev);
2819 void radeon_vm_manager_fini(struct radeon_device *rdev);
2820 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2821 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2822 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2823 struct radeon_vm *vm,
2824 struct list_head *head);
2825 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2826 struct radeon_vm *vm, int ring);
2827 void radeon_vm_flush(struct radeon_device *rdev,
2828 struct radeon_vm *vm,
2829 int ring);
2830 void radeon_vm_fence(struct radeon_device *rdev,
2831 struct radeon_vm *vm,
2832 struct radeon_fence *fence);
2833 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2834 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2835 struct radeon_vm *vm);
2836 int radeon_vm_bo_update(struct radeon_device *rdev,
2837 struct radeon_vm *vm,
2838 struct radeon_bo *bo,
2839 struct ttm_mem_reg *mem);
2840 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2841 struct radeon_bo *bo);
2842 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2843 struct radeon_bo *bo);
2844 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2845 struct radeon_vm *vm,
2846 struct radeon_bo *bo);
2847 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2848 struct radeon_bo_va *bo_va,
2849 uint64_t offset,
2850 uint32_t flags);
2851 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2852 struct radeon_bo_va *bo_va);
2853
2854 /* audio */
2855 void r600_audio_update_hdmi(struct work_struct *work);
2856 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2857 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2858 void r600_audio_enable(struct radeon_device *rdev,
2859 struct r600_audio_pin *pin,
2860 bool enable);
2861 void dce6_audio_enable(struct radeon_device *rdev,
2862 struct r600_audio_pin *pin,
2863 bool enable);
2864
2865 /*
2866 * R600 vram scratch functions
2867 */
2868 int r600_vram_scratch_init(struct radeon_device *rdev);
2869 void r600_vram_scratch_fini(struct radeon_device *rdev);
2870
2871 /*
2872 * r600 cs checking helper
2873 */
2874 unsigned r600_mip_minify(unsigned size, unsigned level);
2875 bool r600_fmt_is_valid_color(u32 format);
2876 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2877 int r600_fmt_get_blocksize(u32 format);
2878 int r600_fmt_get_nblocksx(u32 format, u32 w);
2879 int r600_fmt_get_nblocksy(u32 format, u32 h);
2880
2881 /*
2882 * r600 functions used by radeon_encoder.c
2883 */
2884 struct radeon_hdmi_acr {
2885 u32 clock;
2886
2887 int n_32khz;
2888 int cts_32khz;
2889
2890 int n_44_1khz;
2891 int cts_44_1khz;
2892
2893 int n_48khz;
2894 int cts_48khz;
2895
2896 };
2897
2898 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2899
2900 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2901 u32 tiling_pipe_num,
2902 u32 max_rb_num,
2903 u32 total_max_rb_num,
2904 u32 enabled_rb_mask);
2905
2906 /*
2907 * evergreen functions used by radeon_encoder.c
2908 */
2909
2910 extern int ni_init_microcode(struct radeon_device *rdev);
2911 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2912
2913 /* radeon_acpi.c */
2914 #if defined(CONFIG_ACPI)
2915 extern int radeon_acpi_init(struct radeon_device *rdev);
2916 extern void radeon_acpi_fini(struct radeon_device *rdev);
2917 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2918 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2919 u8 perf_req, bool advertise);
2920 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2921 #else
2922 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2923 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2924 #endif
2925
2926 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2927 struct radeon_cs_packet *pkt,
2928 unsigned idx);
2929 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2930 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2931 struct radeon_cs_packet *pkt);
2932 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2933 struct radeon_cs_reloc **cs_reloc,
2934 int nomm);
2935 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2936 uint32_t *vline_start_end,
2937 uint32_t *vline_status);
2938
2939 #include "radeon_object.h"
2940
2941 #endif
Linux kernel - Deliverables
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