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drm/radeon/dpm: add support for SVI2 voltage for SI
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101 extern int radeon_runtime_pm;
102 extern int radeon_hard_reset;
103 extern int radeon_vm_size;
104 extern int radeon_vm_block_size;
105 extern int radeon_deep_color;
106
107 /*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
111 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
113 /* RADEON_IB_POOL_SIZE must be a power of 2 */
114 #define RADEON_IB_POOL_SIZE 16
115 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
116 #define RADEONFB_CONN_LIMIT 4
117 #define RADEON_BIOS_NUM_SCRATCH 8
118
119 /* fence seq are set to this number when signaled */
120 #define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122 /* internal ring indices */
123 /* r1xx+ has gfx CP ring */
124 #define RADEON_RING_TYPE_GFX_INDEX 0
125
126 /* cayman has 2 compute CP rings */
127 #define CAYMAN_RING_TYPE_CP1_INDEX 1
128 #define CAYMAN_RING_TYPE_CP2_INDEX 2
129
130 /* R600+ has an async dma ring */
131 #define R600_RING_TYPE_DMA_INDEX 3
132 /* cayman add a second async dma ring */
133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134
135 /* R600+ */
136 #define R600_RING_TYPE_UVD_INDEX 5
137
138 /* TN+ */
139 #define TN_RING_TYPE_VCE1_INDEX 6
140 #define TN_RING_TYPE_VCE2_INDEX 7
141
142 /* max number of rings */
143 #define RADEON_NUM_RINGS 8
144
145 /* number of hw syncs before falling back on blocking */
146 #define RADEON_NUM_SYNCS 4
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* hardcode those limit for now */
152 #define RADEON_VA_IB_OFFSET (1 << 20)
153 #define RADEON_VA_RESERVED_SIZE (8 << 20)
154 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
155
156 /* hard reset data */
157 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
159 /* reset flags */
160 #define RADEON_RESET_GFX (1 << 0)
161 #define RADEON_RESET_COMPUTE (1 << 1)
162 #define RADEON_RESET_DMA (1 << 2)
163 #define RADEON_RESET_CP (1 << 3)
164 #define RADEON_RESET_GRBM (1 << 4)
165 #define RADEON_RESET_DMA1 (1 << 5)
166 #define RADEON_RESET_RLC (1 << 6)
167 #define RADEON_RESET_SEM (1 << 7)
168 #define RADEON_RESET_IH (1 << 8)
169 #define RADEON_RESET_VMC (1 << 9)
170 #define RADEON_RESET_MC (1 << 10)
171 #define RADEON_RESET_DISPLAY (1 << 11)
172
173 /* CG block flags */
174 #define RADEON_CG_BLOCK_GFX (1 << 0)
175 #define RADEON_CG_BLOCK_MC (1 << 1)
176 #define RADEON_CG_BLOCK_SDMA (1 << 2)
177 #define RADEON_CG_BLOCK_UVD (1 << 3)
178 #define RADEON_CG_BLOCK_VCE (1 << 4)
179 #define RADEON_CG_BLOCK_HDP (1 << 5)
180 #define RADEON_CG_BLOCK_BIF (1 << 6)
181
182 /* CG flags */
183 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201 /* PG flags */
202 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
203 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205 #define RADEON_PG_SUPPORT_UVD (1 << 3)
206 #define RADEON_PG_SUPPORT_VCE (1 << 4)
207 #define RADEON_PG_SUPPORT_CP (1 << 5)
208 #define RADEON_PG_SUPPORT_GDS (1 << 6)
209 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
211 #define RADEON_PG_SUPPORT_ACP (1 << 9)
212 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
214 /* max cursor sizes (in pixels) */
215 #define CURSOR_WIDTH 64
216 #define CURSOR_HEIGHT 64
217
218 #define CIK_CURSOR_WIDTH 128
219 #define CIK_CURSOR_HEIGHT 128
220
221 /*
222 * Errata workarounds.
223 */
224 enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228 };
229
230
231 struct radeon_device;
232
233
234 /*
235 * BIOS.
236 */
237 bool radeon_get_bios(struct radeon_device *rdev);
238
239 /*
240 * Dummy page
241 */
242 struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245 };
246 int radeon_dummy_page_init(struct radeon_device *rdev);
247 void radeon_dummy_page_fini(struct radeon_device *rdev);
248
249
250 /*
251 * Clocks
252 */
253 struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
256 struct radeon_pll dcpll;
257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
262 uint32_t default_dispclk;
263 uint32_t current_dispclk;
264 uint32_t dp_extclk;
265 uint32_t max_pixel_clock;
266 };
267
268 /*
269 * Power management
270 */
271 int radeon_pm_init(struct radeon_device *rdev);
272 int radeon_pm_late_init(struct radeon_device *rdev);
273 void radeon_pm_fini(struct radeon_device *rdev);
274 void radeon_pm_compute_clocks(struct radeon_device *rdev);
275 void radeon_pm_suspend(struct radeon_device *rdev);
276 void radeon_pm_resume(struct radeon_device *rdev);
277 void radeon_combios_get_power_modes(struct radeon_device *rdev);
278 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
279 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
284 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
288 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
289 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
296 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
298 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
301 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
307 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode,
317 struct atom_voltage_table *voltage_table);
318 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
320 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
321 u8 voltage_type,
322 u8 *svd_gpio_id, u8 *svc_gpio_id);
323 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
324 u32 mem_clock);
325 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
326 u32 mem_clock);
327 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
328 u8 module_index,
329 struct atom_mc_reg_table *reg_table);
330 int radeon_atom_get_memory_info(struct radeon_device *rdev,
331 u8 module_index, struct atom_memory_info *mem_info);
332 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
333 bool gddr5, u8 module_index,
334 struct atom_memory_clock_range_table *mclk_range_table);
335 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
336 u16 voltage_id, u16 *voltage);
337 void rs690_pm_info(struct radeon_device *rdev);
338 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
339 unsigned *bankh, unsigned *mtaspect,
340 unsigned *tile_split);
341
342 /*
343 * Fences.
344 */
345 struct radeon_fence_driver {
346 uint32_t scratch_reg;
347 uint64_t gpu_addr;
348 volatile uint32_t *cpu_addr;
349 /* sync_seq is protected by ring emission lock */
350 uint64_t sync_seq[RADEON_NUM_RINGS];
351 atomic64_t last_seq;
352 bool initialized;
353 };
354
355 struct radeon_fence {
356 struct radeon_device *rdev;
357 struct kref kref;
358 /* protected by radeon_fence.lock */
359 uint64_t seq;
360 /* RB, DMA, etc. */
361 unsigned ring;
362 };
363
364 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
365 int radeon_fence_driver_init(struct radeon_device *rdev);
366 void radeon_fence_driver_fini(struct radeon_device *rdev);
367 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
368 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
369 void radeon_fence_process(struct radeon_device *rdev, int ring);
370 bool radeon_fence_signaled(struct radeon_fence *fence);
371 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
372 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
373 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
374 int radeon_fence_wait_any(struct radeon_device *rdev,
375 struct radeon_fence **fences,
376 bool intr);
377 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
378 void radeon_fence_unref(struct radeon_fence **fence);
379 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
380 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
381 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
382 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
383 struct radeon_fence *b)
384 {
385 if (!a) {
386 return b;
387 }
388
389 if (!b) {
390 return a;
391 }
392
393 BUG_ON(a->ring != b->ring);
394
395 if (a->seq > b->seq) {
396 return a;
397 } else {
398 return b;
399 }
400 }
401
402 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
403 struct radeon_fence *b)
404 {
405 if (!a) {
406 return false;
407 }
408
409 if (!b) {
410 return true;
411 }
412
413 BUG_ON(a->ring != b->ring);
414
415 return a->seq < b->seq;
416 }
417
418 /*
419 * Tiling registers
420 */
421 struct radeon_surface_reg {
422 struct radeon_bo *bo;
423 };
424
425 #define RADEON_GEM_MAX_SURFACES 8
426
427 /*
428 * TTM.
429 */
430 struct radeon_mman {
431 struct ttm_bo_global_ref bo_global_ref;
432 struct drm_global_reference mem_global_ref;
433 struct ttm_bo_device bdev;
434 bool mem_global_referenced;
435 bool initialized;
436
437 #if defined(CONFIG_DEBUG_FS)
438 struct dentry *vram;
439 struct dentry *gtt;
440 #endif
441 };
442
443 /* bo virtual address in a specific vm */
444 struct radeon_bo_va {
445 /* protected by bo being reserved */
446 struct list_head bo_list;
447 uint64_t soffset;
448 uint64_t eoffset;
449 uint32_t flags;
450 bool valid;
451 unsigned ref_count;
452
453 /* protected by vm mutex */
454 struct list_head vm_list;
455 struct list_head vm_status;
456
457 /* constant after initialization */
458 struct radeon_vm *vm;
459 struct radeon_bo *bo;
460 };
461
462 struct radeon_bo {
463 /* Protected by gem.mutex */
464 struct list_head list;
465 /* Protected by tbo.reserved */
466 u32 initial_domain;
467 u32 placements[3];
468 struct ttm_placement placement;
469 struct ttm_buffer_object tbo;
470 struct ttm_bo_kmap_obj kmap;
471 unsigned pin_count;
472 void *kptr;
473 u32 tiling_flags;
474 u32 pitch;
475 int surface_reg;
476 /* list of all virtual address to which this bo
477 * is associated to
478 */
479 struct list_head va;
480 /* Constant after initialization */
481 struct radeon_device *rdev;
482 struct drm_gem_object gem_base;
483
484 struct ttm_bo_kmap_obj dma_buf_vmap;
485 pid_t pid;
486 };
487 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
488
489 int radeon_gem_debugfs_init(struct radeon_device *rdev);
490
491 /* sub-allocation manager, it has to be protected by another lock.
492 * By conception this is an helper for other part of the driver
493 * like the indirect buffer or semaphore, which both have their
494 * locking.
495 *
496 * Principe is simple, we keep a list of sub allocation in offset
497 * order (first entry has offset == 0, last entry has the highest
498 * offset).
499 *
500 * When allocating new object we first check if there is room at
501 * the end total_size - (last_object_offset + last_object_size) >=
502 * alloc_size. If so we allocate new object there.
503 *
504 * When there is not enough room at the end, we start waiting for
505 * each sub object until we reach object_offset+object_size >=
506 * alloc_size, this object then become the sub object we return.
507 *
508 * Alignment can't be bigger than page size.
509 *
510 * Hole are not considered for allocation to keep things simple.
511 * Assumption is that there won't be hole (all object on same
512 * alignment).
513 */
514 struct radeon_sa_manager {
515 wait_queue_head_t wq;
516 struct radeon_bo *bo;
517 struct list_head *hole;
518 struct list_head flist[RADEON_NUM_RINGS];
519 struct list_head olist;
520 unsigned size;
521 uint64_t gpu_addr;
522 void *cpu_ptr;
523 uint32_t domain;
524 uint32_t align;
525 };
526
527 struct radeon_sa_bo;
528
529 /* sub-allocation buffer */
530 struct radeon_sa_bo {
531 struct list_head olist;
532 struct list_head flist;
533 struct radeon_sa_manager *manager;
534 unsigned soffset;
535 unsigned eoffset;
536 struct radeon_fence *fence;
537 };
538
539 /*
540 * GEM objects.
541 */
542 struct radeon_gem {
543 struct mutex mutex;
544 struct list_head objects;
545 };
546
547 int radeon_gem_init(struct radeon_device *rdev);
548 void radeon_gem_fini(struct radeon_device *rdev);
549 int radeon_gem_object_create(struct radeon_device *rdev, int size,
550 int alignment, int initial_domain,
551 bool discardable, bool kernel,
552 struct drm_gem_object **obj);
553
554 int radeon_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557 int radeon_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
560
561 /*
562 * Semaphores.
563 */
564 struct radeon_semaphore {
565 struct radeon_sa_bo *sa_bo;
566 signed waiters;
567 uint64_t gpu_addr;
568 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
569 };
570
571 int radeon_semaphore_create(struct radeon_device *rdev,
572 struct radeon_semaphore **semaphore);
573 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
574 struct radeon_semaphore *semaphore);
575 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
576 struct radeon_semaphore *semaphore);
577 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
578 struct radeon_fence *fence);
579 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
580 struct radeon_semaphore *semaphore,
581 int waiting_ring);
582 void radeon_semaphore_free(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore,
584 struct radeon_fence *fence);
585
586 /*
587 * GART structures, functions & helpers
588 */
589 struct radeon_mc;
590
591 #define RADEON_GPU_PAGE_SIZE 4096
592 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
593 #define RADEON_GPU_PAGE_SHIFT 12
594 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
595
596 struct radeon_gart {
597 dma_addr_t table_addr;
598 struct radeon_bo *robj;
599 void *ptr;
600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
602 unsigned table_size;
603 struct page **pages;
604 dma_addr_t *pages_addr;
605 bool ready;
606 };
607
608 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
609 void radeon_gart_table_ram_free(struct radeon_device *rdev);
610 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
611 void radeon_gart_table_vram_free(struct radeon_device *rdev);
612 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
613 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
614 int radeon_gart_init(struct radeon_device *rdev);
615 void radeon_gart_fini(struct radeon_device *rdev);
616 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
617 int pages);
618 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr);
621 void radeon_gart_restore(struct radeon_device *rdev);
622
623
624 /*
625 * GPU MC structures, functions & helpers
626 */
627 struct radeon_mc {
628 resource_size_t aper_size;
629 resource_size_t aper_base;
630 resource_size_t agp_base;
631 /* for some chips with <= 32MB we need to lie
632 * about vram size near mc fb location */
633 u64 mc_vram_size;
634 u64 visible_vram_size;
635 u64 gtt_size;
636 u64 gtt_start;
637 u64 gtt_end;
638 u64 vram_start;
639 u64 vram_end;
640 unsigned vram_width;
641 u64 real_vram_size;
642 int vram_mtrr;
643 bool vram_is_ddr;
644 bool igp_sideport_enabled;
645 u64 gtt_base_align;
646 u64 mc_mask;
647 };
648
649 bool radeon_combios_sideport_present(struct radeon_device *rdev);
650 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
651
652 /*
653 * GPU scratch registers structures, functions & helpers
654 */
655 struct radeon_scratch {
656 unsigned num_reg;
657 uint32_t reg_base;
658 bool free[32];
659 uint32_t reg[32];
660 };
661
662 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
663 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
664
665 /*
666 * GPU doorbell structures, functions & helpers
667 */
668 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
669
670 struct radeon_doorbell {
671 /* doorbell mmio */
672 resource_size_t base;
673 resource_size_t size;
674 u32 __iomem *ptr;
675 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
676 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
677 };
678
679 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
680 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
681
682 /*
683 * IRQS.
684 */
685
686 struct radeon_flip_work {
687 struct work_struct flip_work;
688 struct work_struct unpin_work;
689 struct radeon_device *rdev;
690 int crtc_id;
691 uint64_t base;
692 struct drm_pending_vblank_event *event;
693 struct radeon_bo *old_rbo;
694 struct radeon_fence *fence;
695 };
696
697 struct r500_irq_stat_regs {
698 u32 disp_int;
699 u32 hdmi0_status;
700 };
701
702 struct r600_irq_stat_regs {
703 u32 disp_int;
704 u32 disp_int_cont;
705 u32 disp_int_cont2;
706 u32 d1grph_int;
707 u32 d2grph_int;
708 u32 hdmi0_status;
709 u32 hdmi1_status;
710 };
711
712 struct evergreen_irq_stat_regs {
713 u32 disp_int;
714 u32 disp_int_cont;
715 u32 disp_int_cont2;
716 u32 disp_int_cont3;
717 u32 disp_int_cont4;
718 u32 disp_int_cont5;
719 u32 d1grph_int;
720 u32 d2grph_int;
721 u32 d3grph_int;
722 u32 d4grph_int;
723 u32 d5grph_int;
724 u32 d6grph_int;
725 u32 afmt_status1;
726 u32 afmt_status2;
727 u32 afmt_status3;
728 u32 afmt_status4;
729 u32 afmt_status5;
730 u32 afmt_status6;
731 };
732
733 struct cik_irq_stat_regs {
734 u32 disp_int;
735 u32 disp_int_cont;
736 u32 disp_int_cont2;
737 u32 disp_int_cont3;
738 u32 disp_int_cont4;
739 u32 disp_int_cont5;
740 u32 disp_int_cont6;
741 u32 d1grph_int;
742 u32 d2grph_int;
743 u32 d3grph_int;
744 u32 d4grph_int;
745 u32 d5grph_int;
746 u32 d6grph_int;
747 };
748
749 union radeon_irq_stat_regs {
750 struct r500_irq_stat_regs r500;
751 struct r600_irq_stat_regs r600;
752 struct evergreen_irq_stat_regs evergreen;
753 struct cik_irq_stat_regs cik;
754 };
755
756 struct radeon_irq {
757 bool installed;
758 spinlock_t lock;
759 atomic_t ring_int[RADEON_NUM_RINGS];
760 bool crtc_vblank_int[RADEON_MAX_CRTCS];
761 atomic_t pflip[RADEON_MAX_CRTCS];
762 wait_queue_head_t vblank_queue;
763 bool hpd[RADEON_MAX_HPD_PINS];
764 bool afmt[RADEON_MAX_AFMT_BLOCKS];
765 union radeon_irq_stat_regs stat_regs;
766 bool dpm_thermal;
767 };
768
769 int radeon_irq_kms_init(struct radeon_device *rdev);
770 void radeon_irq_kms_fini(struct radeon_device *rdev);
771 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
772 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
773 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
774 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
775 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
776 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
777 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
778 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
779
780 /*
781 * CP & rings.
782 */
783
784 struct radeon_ib {
785 struct radeon_sa_bo *sa_bo;
786 uint32_t length_dw;
787 uint64_t gpu_addr;
788 uint32_t *ptr;
789 int ring;
790 struct radeon_fence *fence;
791 struct radeon_vm *vm;
792 bool is_const_ib;
793 struct radeon_semaphore *semaphore;
794 };
795
796 struct radeon_ring {
797 struct radeon_bo *ring_obj;
798 volatile uint32_t *ring;
799 unsigned rptr_offs;
800 unsigned rptr_save_reg;
801 u64 next_rptr_gpu_addr;
802 volatile u32 *next_rptr_cpu_addr;
803 unsigned wptr;
804 unsigned wptr_old;
805 unsigned ring_size;
806 unsigned ring_free_dw;
807 int count_dw;
808 atomic_t last_rptr;
809 atomic64_t last_activity;
810 uint64_t gpu_addr;
811 uint32_t align_mask;
812 uint32_t ptr_mask;
813 bool ready;
814 u32 nop;
815 u32 idx;
816 u64 last_semaphore_signal_addr;
817 u64 last_semaphore_wait_addr;
818 /* for CIK queues */
819 u32 me;
820 u32 pipe;
821 u32 queue;
822 struct radeon_bo *mqd_obj;
823 u32 doorbell_index;
824 unsigned wptr_offs;
825 };
826
827 struct radeon_mec {
828 struct radeon_bo *hpd_eop_obj;
829 u64 hpd_eop_gpu_addr;
830 u32 num_pipe;
831 u32 num_mec;
832 u32 num_queue;
833 };
834
835 /*
836 * VM
837 */
838
839 /* maximum number of VMIDs */
840 #define RADEON_NUM_VM 16
841
842 /* number of entries in page table */
843 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
844
845 /* PTBs (Page Table Blocks) need to be aligned to 32K */
846 #define RADEON_VM_PTB_ALIGN_SIZE 32768
847 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
848 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
849
850 #define R600_PTE_VALID (1 << 0)
851 #define R600_PTE_SYSTEM (1 << 1)
852 #define R600_PTE_SNOOPED (1 << 2)
853 #define R600_PTE_READABLE (1 << 5)
854 #define R600_PTE_WRITEABLE (1 << 6)
855
856 /* PTE (Page Table Entry) fragment field for different page sizes */
857 #define R600_PTE_FRAG_4KB (0 << 7)
858 #define R600_PTE_FRAG_64KB (4 << 7)
859 #define R600_PTE_FRAG_256KB (6 << 7)
860
861 /* flags used for GART page table entries on R600+ */
862 #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
863 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
864
865 struct radeon_vm_pt {
866 struct radeon_bo *bo;
867 uint64_t addr;
868 };
869
870 struct radeon_vm {
871 struct list_head va;
872 unsigned id;
873
874 /* BOs freed, but not yet updated in the PT */
875 struct list_head freed;
876
877 /* contains the page directory */
878 struct radeon_bo *page_directory;
879 uint64_t pd_gpu_addr;
880 unsigned max_pde_used;
881
882 /* array of page tables, one for each page directory entry */
883 struct radeon_vm_pt *page_tables;
884
885 struct radeon_bo_va *ib_bo_va;
886
887 struct mutex mutex;
888 /* last fence for cs using this vm */
889 struct radeon_fence *fence;
890 /* last flush or NULL if we still need to flush */
891 struct radeon_fence *last_flush;
892 /* last use of vmid */
893 struct radeon_fence *last_id_use;
894 };
895
896 struct radeon_vm_manager {
897 struct radeon_fence *active[RADEON_NUM_VM];
898 uint32_t max_pfn;
899 /* number of VMIDs */
900 unsigned nvm;
901 /* vram base address for page table entry */
902 u64 vram_base_offset;
903 /* is vm enabled? */
904 bool enabled;
905 };
906
907 /*
908 * file private structure
909 */
910 struct radeon_fpriv {
911 struct radeon_vm vm;
912 };
913
914 /*
915 * R6xx+ IH ring
916 */
917 struct r600_ih {
918 struct radeon_bo *ring_obj;
919 volatile uint32_t *ring;
920 unsigned rptr;
921 unsigned ring_size;
922 uint64_t gpu_addr;
923 uint32_t ptr_mask;
924 atomic_t lock;
925 bool enabled;
926 };
927
928 /*
929 * RLC stuff
930 */
931 #include "clearstate_defs.h"
932
933 struct radeon_rlc {
934 /* for power gating */
935 struct radeon_bo *save_restore_obj;
936 uint64_t save_restore_gpu_addr;
937 volatile uint32_t *sr_ptr;
938 const u32 *reg_list;
939 u32 reg_list_size;
940 /* for clear state */
941 struct radeon_bo *clear_state_obj;
942 uint64_t clear_state_gpu_addr;
943 volatile uint32_t *cs_ptr;
944 const struct cs_section_def *cs_data;
945 u32 clear_state_size;
946 /* for cp tables */
947 struct radeon_bo *cp_table_obj;
948 uint64_t cp_table_gpu_addr;
949 volatile uint32_t *cp_table_ptr;
950 u32 cp_table_size;
951 };
952
953 int radeon_ib_get(struct radeon_device *rdev, int ring,
954 struct radeon_ib *ib, struct radeon_vm *vm,
955 unsigned size);
956 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
957 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
958 struct radeon_ib *const_ib);
959 int radeon_ib_pool_init(struct radeon_device *rdev);
960 void radeon_ib_pool_fini(struct radeon_device *rdev);
961 int radeon_ib_ring_tests(struct radeon_device *rdev);
962 /* Ring access between begin & end cannot sleep */
963 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
964 struct radeon_ring *ring);
965 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
966 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
967 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
968 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
969 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
970 void radeon_ring_undo(struct radeon_ring *ring);
971 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
972 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
973 void radeon_ring_lockup_update(struct radeon_device *rdev,
974 struct radeon_ring *ring);
975 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
976 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
977 uint32_t **data);
978 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
979 unsigned size, uint32_t *data);
980 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
981 unsigned rptr_offs, u32 nop);
982 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
983
984
985 /* r600 async dma */
986 void r600_dma_stop(struct radeon_device *rdev);
987 int r600_dma_resume(struct radeon_device *rdev);
988 void r600_dma_fini(struct radeon_device *rdev);
989
990 void cayman_dma_stop(struct radeon_device *rdev);
991 int cayman_dma_resume(struct radeon_device *rdev);
992 void cayman_dma_fini(struct radeon_device *rdev);
993
994 /*
995 * CS.
996 */
997 struct radeon_cs_reloc {
998 struct drm_gem_object *gobj;
999 struct radeon_bo *robj;
1000 struct ttm_validate_buffer tv;
1001 uint64_t gpu_offset;
1002 unsigned prefered_domains;
1003 unsigned allowed_domains;
1004 uint32_t tiling_flags;
1005 uint32_t handle;
1006 };
1007
1008 struct radeon_cs_chunk {
1009 uint32_t chunk_id;
1010 uint32_t length_dw;
1011 uint32_t *kdata;
1012 void __user *user_ptr;
1013 };
1014
1015 struct radeon_cs_parser {
1016 struct device *dev;
1017 struct radeon_device *rdev;
1018 struct drm_file *filp;
1019 /* chunks */
1020 unsigned nchunks;
1021 struct radeon_cs_chunk *chunks;
1022 uint64_t *chunks_array;
1023 /* IB */
1024 unsigned idx;
1025 /* relocations */
1026 unsigned nrelocs;
1027 struct radeon_cs_reloc *relocs;
1028 struct radeon_cs_reloc **relocs_ptr;
1029 struct radeon_cs_reloc *vm_bos;
1030 struct list_head validated;
1031 unsigned dma_reloc_idx;
1032 /* indices of various chunks */
1033 int chunk_ib_idx;
1034 int chunk_relocs_idx;
1035 int chunk_flags_idx;
1036 int chunk_const_ib_idx;
1037 struct radeon_ib ib;
1038 struct radeon_ib const_ib;
1039 void *track;
1040 unsigned family;
1041 int parser_error;
1042 u32 cs_flags;
1043 u32 ring;
1044 s32 priority;
1045 struct ww_acquire_ctx ticket;
1046 };
1047
1048 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1049 {
1050 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1051
1052 if (ibc->kdata)
1053 return ibc->kdata[idx];
1054 return p->ib.ptr[idx];
1055 }
1056
1057
1058 struct radeon_cs_packet {
1059 unsigned idx;
1060 unsigned type;
1061 unsigned reg;
1062 unsigned opcode;
1063 int count;
1064 unsigned one_reg_wr;
1065 };
1066
1067 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1068 struct radeon_cs_packet *pkt,
1069 unsigned idx, unsigned reg);
1070 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1071 struct radeon_cs_packet *pkt);
1072
1073
1074 /*
1075 * AGP
1076 */
1077 int radeon_agp_init(struct radeon_device *rdev);
1078 void radeon_agp_resume(struct radeon_device *rdev);
1079 void radeon_agp_suspend(struct radeon_device *rdev);
1080 void radeon_agp_fini(struct radeon_device *rdev);
1081
1082
1083 /*
1084 * Writeback
1085 */
1086 struct radeon_wb {
1087 struct radeon_bo *wb_obj;
1088 volatile uint32_t *wb;
1089 uint64_t gpu_addr;
1090 bool enabled;
1091 bool use_event;
1092 };
1093
1094 #define RADEON_WB_SCRATCH_OFFSET 0
1095 #define RADEON_WB_RING0_NEXT_RPTR 256
1096 #define RADEON_WB_CP_RPTR_OFFSET 1024
1097 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1098 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1099 #define R600_WB_DMA_RPTR_OFFSET 1792
1100 #define R600_WB_IH_WPTR_OFFSET 2048
1101 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1102 #define R600_WB_EVENT_OFFSET 3072
1103 #define CIK_WB_CP1_WPTR_OFFSET 3328
1104 #define CIK_WB_CP2_WPTR_OFFSET 3584
1105
1106 /**
1107 * struct radeon_pm - power management datas
1108 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1109 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1110 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1111 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1112 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1113 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1114 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1115 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1116 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1117 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1118 * @needed_bandwidth: current bandwidth needs
1119 *
1120 * It keeps track of various data needed to take powermanagement decision.
1121 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1122 * Equation between gpu/memory clock and available bandwidth is hw dependent
1123 * (type of memory, bus size, efficiency, ...)
1124 */
1125
1126 enum radeon_pm_method {
1127 PM_METHOD_PROFILE,
1128 PM_METHOD_DYNPM,
1129 PM_METHOD_DPM,
1130 };
1131
1132 enum radeon_dynpm_state {
1133 DYNPM_STATE_DISABLED,
1134 DYNPM_STATE_MINIMUM,
1135 DYNPM_STATE_PAUSED,
1136 DYNPM_STATE_ACTIVE,
1137 DYNPM_STATE_SUSPENDED,
1138 };
1139 enum radeon_dynpm_action {
1140 DYNPM_ACTION_NONE,
1141 DYNPM_ACTION_MINIMUM,
1142 DYNPM_ACTION_DOWNCLOCK,
1143 DYNPM_ACTION_UPCLOCK,
1144 DYNPM_ACTION_DEFAULT
1145 };
1146
1147 enum radeon_voltage_type {
1148 VOLTAGE_NONE = 0,
1149 VOLTAGE_GPIO,
1150 VOLTAGE_VDDC,
1151 VOLTAGE_SW
1152 };
1153
1154 enum radeon_pm_state_type {
1155 /* not used for dpm */
1156 POWER_STATE_TYPE_DEFAULT,
1157 POWER_STATE_TYPE_POWERSAVE,
1158 /* user selectable states */
1159 POWER_STATE_TYPE_BATTERY,
1160 POWER_STATE_TYPE_BALANCED,
1161 POWER_STATE_TYPE_PERFORMANCE,
1162 /* internal states */
1163 POWER_STATE_TYPE_INTERNAL_UVD,
1164 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1165 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1166 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1167 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1168 POWER_STATE_TYPE_INTERNAL_BOOT,
1169 POWER_STATE_TYPE_INTERNAL_THERMAL,
1170 POWER_STATE_TYPE_INTERNAL_ACPI,
1171 POWER_STATE_TYPE_INTERNAL_ULV,
1172 POWER_STATE_TYPE_INTERNAL_3DPERF,
1173 };
1174
1175 enum radeon_pm_profile_type {
1176 PM_PROFILE_DEFAULT,
1177 PM_PROFILE_AUTO,
1178 PM_PROFILE_LOW,
1179 PM_PROFILE_MID,
1180 PM_PROFILE_HIGH,
1181 };
1182
1183 #define PM_PROFILE_DEFAULT_IDX 0
1184 #define PM_PROFILE_LOW_SH_IDX 1
1185 #define PM_PROFILE_MID_SH_IDX 2
1186 #define PM_PROFILE_HIGH_SH_IDX 3
1187 #define PM_PROFILE_LOW_MH_IDX 4
1188 #define PM_PROFILE_MID_MH_IDX 5
1189 #define PM_PROFILE_HIGH_MH_IDX 6
1190 #define PM_PROFILE_MAX 7
1191
1192 struct radeon_pm_profile {
1193 int dpms_off_ps_idx;
1194 int dpms_on_ps_idx;
1195 int dpms_off_cm_idx;
1196 int dpms_on_cm_idx;
1197 };
1198
1199 enum radeon_int_thermal_type {
1200 THERMAL_TYPE_NONE,
1201 THERMAL_TYPE_EXTERNAL,
1202 THERMAL_TYPE_EXTERNAL_GPIO,
1203 THERMAL_TYPE_RV6XX,
1204 THERMAL_TYPE_RV770,
1205 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1206 THERMAL_TYPE_EVERGREEN,
1207 THERMAL_TYPE_SUMO,
1208 THERMAL_TYPE_NI,
1209 THERMAL_TYPE_SI,
1210 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1211 THERMAL_TYPE_CI,
1212 THERMAL_TYPE_KV,
1213 };
1214
1215 struct radeon_voltage {
1216 enum radeon_voltage_type type;
1217 /* gpio voltage */
1218 struct radeon_gpio_rec gpio;
1219 u32 delay; /* delay in usec from voltage drop to sclk change */
1220 bool active_high; /* voltage drop is active when bit is high */
1221 /* VDDC voltage */
1222 u8 vddc_id; /* index into vddc voltage table */
1223 u8 vddci_id; /* index into vddci voltage table */
1224 bool vddci_enabled;
1225 /* r6xx+ sw */
1226 u16 voltage;
1227 /* evergreen+ vddci */
1228 u16 vddci;
1229 };
1230
1231 /* clock mode flags */
1232 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1233
1234 struct radeon_pm_clock_info {
1235 /* memory clock */
1236 u32 mclk;
1237 /* engine clock */
1238 u32 sclk;
1239 /* voltage info */
1240 struct radeon_voltage voltage;
1241 /* standardized clock flags */
1242 u32 flags;
1243 };
1244
1245 /* state flags */
1246 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1247
1248 struct radeon_power_state {
1249 enum radeon_pm_state_type type;
1250 struct radeon_pm_clock_info *clock_info;
1251 /* number of valid clock modes in this power state */
1252 int num_clock_modes;
1253 struct radeon_pm_clock_info *default_clock_mode;
1254 /* standardized state flags */
1255 u32 flags;
1256 u32 misc; /* vbios specific flags */
1257 u32 misc2; /* vbios specific flags */
1258 int pcie_lanes; /* pcie lanes */
1259 };
1260
1261 /*
1262 * Some modes are overclocked by very low value, accept them
1263 */
1264 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1265
1266 enum radeon_dpm_auto_throttle_src {
1267 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1268 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1269 };
1270
1271 enum radeon_dpm_event_src {
1272 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1273 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1274 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1275 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1276 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1277 };
1278
1279 #define RADEON_MAX_VCE_LEVELS 6
1280
1281 enum radeon_vce_level {
1282 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1283 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1284 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1285 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1286 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1287 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1288 };
1289
1290 struct radeon_ps {
1291 u32 caps; /* vbios flags */
1292 u32 class; /* vbios flags */
1293 u32 class2; /* vbios flags */
1294 /* UVD clocks */
1295 u32 vclk;
1296 u32 dclk;
1297 /* VCE clocks */
1298 u32 evclk;
1299 u32 ecclk;
1300 bool vce_active;
1301 enum radeon_vce_level vce_level;
1302 /* asic priv */
1303 void *ps_priv;
1304 };
1305
1306 struct radeon_dpm_thermal {
1307 /* thermal interrupt work */
1308 struct work_struct work;
1309 /* low temperature threshold */
1310 int min_temp;
1311 /* high temperature threshold */
1312 int max_temp;
1313 /* was interrupt low to high or high to low */
1314 bool high_to_low;
1315 };
1316
1317 enum radeon_clk_action
1318 {
1319 RADEON_SCLK_UP = 1,
1320 RADEON_SCLK_DOWN
1321 };
1322
1323 struct radeon_blacklist_clocks
1324 {
1325 u32 sclk;
1326 u32 mclk;
1327 enum radeon_clk_action action;
1328 };
1329
1330 struct radeon_clock_and_voltage_limits {
1331 u32 sclk;
1332 u32 mclk;
1333 u16 vddc;
1334 u16 vddci;
1335 };
1336
1337 struct radeon_clock_array {
1338 u32 count;
1339 u32 *values;
1340 };
1341
1342 struct radeon_clock_voltage_dependency_entry {
1343 u32 clk;
1344 u16 v;
1345 };
1346
1347 struct radeon_clock_voltage_dependency_table {
1348 u32 count;
1349 struct radeon_clock_voltage_dependency_entry *entries;
1350 };
1351
1352 union radeon_cac_leakage_entry {
1353 struct {
1354 u16 vddc;
1355 u32 leakage;
1356 };
1357 struct {
1358 u16 vddc1;
1359 u16 vddc2;
1360 u16 vddc3;
1361 };
1362 };
1363
1364 struct radeon_cac_leakage_table {
1365 u32 count;
1366 union radeon_cac_leakage_entry *entries;
1367 };
1368
1369 struct radeon_phase_shedding_limits_entry {
1370 u16 voltage;
1371 u32 sclk;
1372 u32 mclk;
1373 };
1374
1375 struct radeon_phase_shedding_limits_table {
1376 u32 count;
1377 struct radeon_phase_shedding_limits_entry *entries;
1378 };
1379
1380 struct radeon_uvd_clock_voltage_dependency_entry {
1381 u32 vclk;
1382 u32 dclk;
1383 u16 v;
1384 };
1385
1386 struct radeon_uvd_clock_voltage_dependency_table {
1387 u8 count;
1388 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1389 };
1390
1391 struct radeon_vce_clock_voltage_dependency_entry {
1392 u32 ecclk;
1393 u32 evclk;
1394 u16 v;
1395 };
1396
1397 struct radeon_vce_clock_voltage_dependency_table {
1398 u8 count;
1399 struct radeon_vce_clock_voltage_dependency_entry *entries;
1400 };
1401
1402 struct radeon_ppm_table {
1403 u8 ppm_design;
1404 u16 cpu_core_number;
1405 u32 platform_tdp;
1406 u32 small_ac_platform_tdp;
1407 u32 platform_tdc;
1408 u32 small_ac_platform_tdc;
1409 u32 apu_tdp;
1410 u32 dgpu_tdp;
1411 u32 dgpu_ulv_power;
1412 u32 tj_max;
1413 };
1414
1415 struct radeon_cac_tdp_table {
1416 u16 tdp;
1417 u16 configurable_tdp;
1418 u16 tdc;
1419 u16 battery_power_limit;
1420 u16 small_power_limit;
1421 u16 low_cac_leakage;
1422 u16 high_cac_leakage;
1423 u16 maximum_power_delivery_limit;
1424 };
1425
1426 struct radeon_dpm_dynamic_state {
1427 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1428 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1429 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1430 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1431 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1432 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1433 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1434 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1435 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1436 struct radeon_clock_array valid_sclk_values;
1437 struct radeon_clock_array valid_mclk_values;
1438 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1439 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1440 u32 mclk_sclk_ratio;
1441 u32 sclk_mclk_delta;
1442 u16 vddc_vddci_delta;
1443 u16 min_vddc_for_pcie_gen2;
1444 struct radeon_cac_leakage_table cac_leakage_table;
1445 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1446 struct radeon_ppm_table *ppm_table;
1447 struct radeon_cac_tdp_table *cac_tdp_table;
1448 };
1449
1450 struct radeon_dpm_fan {
1451 u16 t_min;
1452 u16 t_med;
1453 u16 t_high;
1454 u16 pwm_min;
1455 u16 pwm_med;
1456 u16 pwm_high;
1457 u8 t_hyst;
1458 u32 cycle_delay;
1459 u16 t_max;
1460 bool ucode_fan_control;
1461 };
1462
1463 enum radeon_pcie_gen {
1464 RADEON_PCIE_GEN1 = 0,
1465 RADEON_PCIE_GEN2 = 1,
1466 RADEON_PCIE_GEN3 = 2,
1467 RADEON_PCIE_GEN_INVALID = 0xffff
1468 };
1469
1470 enum radeon_dpm_forced_level {
1471 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1472 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1473 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1474 };
1475
1476 struct radeon_vce_state {
1477 /* vce clocks */
1478 u32 evclk;
1479 u32 ecclk;
1480 /* gpu clocks */
1481 u32 sclk;
1482 u32 mclk;
1483 u8 clk_idx;
1484 u8 pstate;
1485 };
1486
1487 struct radeon_dpm {
1488 struct radeon_ps *ps;
1489 /* number of valid power states */
1490 int num_ps;
1491 /* current power state that is active */
1492 struct radeon_ps *current_ps;
1493 /* requested power state */
1494 struct radeon_ps *requested_ps;
1495 /* boot up power state */
1496 struct radeon_ps *boot_ps;
1497 /* default uvd power state */
1498 struct radeon_ps *uvd_ps;
1499 /* vce requirements */
1500 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1501 enum radeon_vce_level vce_level;
1502 enum radeon_pm_state_type state;
1503 enum radeon_pm_state_type user_state;
1504 u32 platform_caps;
1505 u32 voltage_response_time;
1506 u32 backbias_response_time;
1507 void *priv;
1508 u32 new_active_crtcs;
1509 int new_active_crtc_count;
1510 u32 current_active_crtcs;
1511 int current_active_crtc_count;
1512 struct radeon_dpm_dynamic_state dyn_state;
1513 struct radeon_dpm_fan fan;
1514 u32 tdp_limit;
1515 u32 near_tdp_limit;
1516 u32 near_tdp_limit_adjusted;
1517 u32 sq_ramping_threshold;
1518 u32 cac_leakage;
1519 u16 tdp_od_limit;
1520 u32 tdp_adjustment;
1521 u16 load_line_slope;
1522 bool power_control;
1523 bool ac_power;
1524 /* special states active */
1525 bool thermal_active;
1526 bool uvd_active;
1527 bool vce_active;
1528 /* thermal handling */
1529 struct radeon_dpm_thermal thermal;
1530 /* forced levels */
1531 enum radeon_dpm_forced_level forced_level;
1532 /* track UVD streams */
1533 unsigned sd;
1534 unsigned hd;
1535 };
1536
1537 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1538 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1539
1540 struct radeon_pm {
1541 struct mutex mutex;
1542 /* write locked while reprogramming mclk */
1543 struct rw_semaphore mclk_lock;
1544 u32 active_crtcs;
1545 int active_crtc_count;
1546 int req_vblank;
1547 bool vblank_sync;
1548 fixed20_12 max_bandwidth;
1549 fixed20_12 igp_sideport_mclk;
1550 fixed20_12 igp_system_mclk;
1551 fixed20_12 igp_ht_link_clk;
1552 fixed20_12 igp_ht_link_width;
1553 fixed20_12 k8_bandwidth;
1554 fixed20_12 sideport_bandwidth;
1555 fixed20_12 ht_bandwidth;
1556 fixed20_12 core_bandwidth;
1557 fixed20_12 sclk;
1558 fixed20_12 mclk;
1559 fixed20_12 needed_bandwidth;
1560 struct radeon_power_state *power_state;
1561 /* number of valid power states */
1562 int num_power_states;
1563 int current_power_state_index;
1564 int current_clock_mode_index;
1565 int requested_power_state_index;
1566 int requested_clock_mode_index;
1567 int default_power_state_index;
1568 u32 current_sclk;
1569 u32 current_mclk;
1570 u16 current_vddc;
1571 u16 current_vddci;
1572 u32 default_sclk;
1573 u32 default_mclk;
1574 u16 default_vddc;
1575 u16 default_vddci;
1576 struct radeon_i2c_chan *i2c_bus;
1577 /* selected pm method */
1578 enum radeon_pm_method pm_method;
1579 /* dynpm power management */
1580 struct delayed_work dynpm_idle_work;
1581 enum radeon_dynpm_state dynpm_state;
1582 enum radeon_dynpm_action dynpm_planned_action;
1583 unsigned long dynpm_action_timeout;
1584 bool dynpm_can_upclock;
1585 bool dynpm_can_downclock;
1586 /* profile-based power management */
1587 enum radeon_pm_profile_type profile;
1588 int profile_index;
1589 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1590 /* internal thermal controller on rv6xx+ */
1591 enum radeon_int_thermal_type int_thermal_type;
1592 struct device *int_hwmon_dev;
1593 /* dpm */
1594 bool dpm_enabled;
1595 struct radeon_dpm dpm;
1596 };
1597
1598 int radeon_pm_get_type_index(struct radeon_device *rdev,
1599 enum radeon_pm_state_type ps_type,
1600 int instance);
1601 /*
1602 * UVD
1603 */
1604 #define RADEON_MAX_UVD_HANDLES 10
1605 #define RADEON_UVD_STACK_SIZE (1024*1024)
1606 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1607
1608 struct radeon_uvd {
1609 struct radeon_bo *vcpu_bo;
1610 void *cpu_addr;
1611 uint64_t gpu_addr;
1612 void *saved_bo;
1613 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1614 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1615 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1616 struct delayed_work idle_work;
1617 };
1618
1619 int radeon_uvd_init(struct radeon_device *rdev);
1620 void radeon_uvd_fini(struct radeon_device *rdev);
1621 int radeon_uvd_suspend(struct radeon_device *rdev);
1622 int radeon_uvd_resume(struct radeon_device *rdev);
1623 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1624 uint32_t handle, struct radeon_fence **fence);
1625 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1626 uint32_t handle, struct radeon_fence **fence);
1627 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1628 void radeon_uvd_free_handles(struct radeon_device *rdev,
1629 struct drm_file *filp);
1630 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1631 void radeon_uvd_note_usage(struct radeon_device *rdev);
1632 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1633 unsigned vclk, unsigned dclk,
1634 unsigned vco_min, unsigned vco_max,
1635 unsigned fb_factor, unsigned fb_mask,
1636 unsigned pd_min, unsigned pd_max,
1637 unsigned pd_even,
1638 unsigned *optimal_fb_div,
1639 unsigned *optimal_vclk_div,
1640 unsigned *optimal_dclk_div);
1641 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1642 unsigned cg_upll_func_cntl);
1643
1644 /*
1645 * VCE
1646 */
1647 #define RADEON_MAX_VCE_HANDLES 16
1648 #define RADEON_VCE_STACK_SIZE (1024*1024)
1649 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1650
1651 struct radeon_vce {
1652 struct radeon_bo *vcpu_bo;
1653 uint64_t gpu_addr;
1654 unsigned fw_version;
1655 unsigned fb_version;
1656 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1657 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1658 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1659 struct delayed_work idle_work;
1660 };
1661
1662 int radeon_vce_init(struct radeon_device *rdev);
1663 void radeon_vce_fini(struct radeon_device *rdev);
1664 int radeon_vce_suspend(struct radeon_device *rdev);
1665 int radeon_vce_resume(struct radeon_device *rdev);
1666 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1667 uint32_t handle, struct radeon_fence **fence);
1668 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1669 uint32_t handle, struct radeon_fence **fence);
1670 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1671 void radeon_vce_note_usage(struct radeon_device *rdev);
1672 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1673 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1674 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1675 struct radeon_ring *ring,
1676 struct radeon_semaphore *semaphore,
1677 bool emit_wait);
1678 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1679 void radeon_vce_fence_emit(struct radeon_device *rdev,
1680 struct radeon_fence *fence);
1681 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1682 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1683
1684 struct r600_audio_pin {
1685 int channels;
1686 int rate;
1687 int bits_per_sample;
1688 u8 status_bits;
1689 u8 category_code;
1690 u32 offset;
1691 bool connected;
1692 u32 id;
1693 };
1694
1695 struct r600_audio {
1696 bool enabled;
1697 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1698 int num_pins;
1699 };
1700
1701 /*
1702 * Benchmarking
1703 */
1704 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1705
1706
1707 /*
1708 * Testing
1709 */
1710 void radeon_test_moves(struct radeon_device *rdev);
1711 void radeon_test_ring_sync(struct radeon_device *rdev,
1712 struct radeon_ring *cpA,
1713 struct radeon_ring *cpB);
1714 void radeon_test_syncing(struct radeon_device *rdev);
1715
1716
1717 /*
1718 * Debugfs
1719 */
1720 struct radeon_debugfs {
1721 struct drm_info_list *files;
1722 unsigned num_files;
1723 };
1724
1725 int radeon_debugfs_add_files(struct radeon_device *rdev,
1726 struct drm_info_list *files,
1727 unsigned nfiles);
1728 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1729
1730 /*
1731 * ASIC ring specific functions.
1732 */
1733 struct radeon_asic_ring {
1734 /* ring read/write ptr handling */
1735 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1736 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1737 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1738
1739 /* validating and patching of IBs */
1740 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1741 int (*cs_parse)(struct radeon_cs_parser *p);
1742
1743 /* command emmit functions */
1744 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1745 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1746 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1747 struct radeon_semaphore *semaphore, bool emit_wait);
1748 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1749
1750 /* testing functions */
1751 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1752 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1753 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1754
1755 /* deprecated */
1756 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1757 };
1758
1759 /*
1760 * ASIC specific functions.
1761 */
1762 struct radeon_asic {
1763 int (*init)(struct radeon_device *rdev);
1764 void (*fini)(struct radeon_device *rdev);
1765 int (*resume)(struct radeon_device *rdev);
1766 int (*suspend)(struct radeon_device *rdev);
1767 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1768 int (*asic_reset)(struct radeon_device *rdev);
1769 /* ioctl hw specific callback. Some hw might want to perform special
1770 * operation on specific ioctl. For instance on wait idle some hw
1771 * might want to perform and HDP flush through MMIO as it seems that
1772 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1773 * through ring.
1774 */
1775 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1776 /* check if 3D engine is idle */
1777 bool (*gui_idle)(struct radeon_device *rdev);
1778 /* wait for mc_idle */
1779 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1780 /* get the reference clock */
1781 u32 (*get_xclk)(struct radeon_device *rdev);
1782 /* get the gpu clock counter */
1783 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1784 /* gart */
1785 struct {
1786 void (*tlb_flush)(struct radeon_device *rdev);
1787 void (*set_page)(struct radeon_device *rdev, unsigned i,
1788 uint64_t addr);
1789 } gart;
1790 struct {
1791 int (*init)(struct radeon_device *rdev);
1792 void (*fini)(struct radeon_device *rdev);
1793 void (*set_page)(struct radeon_device *rdev,
1794 struct radeon_ib *ib,
1795 uint64_t pe,
1796 uint64_t addr, unsigned count,
1797 uint32_t incr, uint32_t flags);
1798 } vm;
1799 /* ring specific callbacks */
1800 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1801 /* irqs */
1802 struct {
1803 int (*set)(struct radeon_device *rdev);
1804 int (*process)(struct radeon_device *rdev);
1805 } irq;
1806 /* displays */
1807 struct {
1808 /* display watermarks */
1809 void (*bandwidth_update)(struct radeon_device *rdev);
1810 /* get frame count */
1811 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1812 /* wait for vblank */
1813 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1814 /* set backlight level */
1815 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1816 /* get backlight level */
1817 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1818 /* audio callbacks */
1819 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1820 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1821 } display;
1822 /* copy functions for bo handling */
1823 struct {
1824 int (*blit)(struct radeon_device *rdev,
1825 uint64_t src_offset,
1826 uint64_t dst_offset,
1827 unsigned num_gpu_pages,
1828 struct radeon_fence **fence);
1829 u32 blit_ring_index;
1830 int (*dma)(struct radeon_device *rdev,
1831 uint64_t src_offset,
1832 uint64_t dst_offset,
1833 unsigned num_gpu_pages,
1834 struct radeon_fence **fence);
1835 u32 dma_ring_index;
1836 /* method used for bo copy */
1837 int (*copy)(struct radeon_device *rdev,
1838 uint64_t src_offset,
1839 uint64_t dst_offset,
1840 unsigned num_gpu_pages,
1841 struct radeon_fence **fence);
1842 /* ring used for bo copies */
1843 u32 copy_ring_index;
1844 } copy;
1845 /* surfaces */
1846 struct {
1847 int (*set_reg)(struct radeon_device *rdev, int reg,
1848 uint32_t tiling_flags, uint32_t pitch,
1849 uint32_t offset, uint32_t obj_size);
1850 void (*clear_reg)(struct radeon_device *rdev, int reg);
1851 } surface;
1852 /* hotplug detect */
1853 struct {
1854 void (*init)(struct radeon_device *rdev);
1855 void (*fini)(struct radeon_device *rdev);
1856 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1857 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1858 } hpd;
1859 /* static power management */
1860 struct {
1861 void (*misc)(struct radeon_device *rdev);
1862 void (*prepare)(struct radeon_device *rdev);
1863 void (*finish)(struct radeon_device *rdev);
1864 void (*init_profile)(struct radeon_device *rdev);
1865 void (*get_dynpm_state)(struct radeon_device *rdev);
1866 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1867 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1868 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1869 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1870 int (*get_pcie_lanes)(struct radeon_device *rdev);
1871 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1872 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1873 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1874 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1875 int (*get_temperature)(struct radeon_device *rdev);
1876 } pm;
1877 /* dynamic power management */
1878 struct {
1879 int (*init)(struct radeon_device *rdev);
1880 void (*setup_asic)(struct radeon_device *rdev);
1881 int (*enable)(struct radeon_device *rdev);
1882 int (*late_enable)(struct radeon_device *rdev);
1883 void (*disable)(struct radeon_device *rdev);
1884 int (*pre_set_power_state)(struct radeon_device *rdev);
1885 int (*set_power_state)(struct radeon_device *rdev);
1886 void (*post_set_power_state)(struct radeon_device *rdev);
1887 void (*display_configuration_changed)(struct radeon_device *rdev);
1888 void (*fini)(struct radeon_device *rdev);
1889 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1890 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1891 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1892 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1893 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1894 bool (*vblank_too_short)(struct radeon_device *rdev);
1895 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1896 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1897 } dpm;
1898 /* pageflipping */
1899 struct {
1900 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1901 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1902 } pflip;
1903 };
1904
1905 /*
1906 * Asic structures
1907 */
1908 struct r100_asic {
1909 const unsigned *reg_safe_bm;
1910 unsigned reg_safe_bm_size;
1911 u32 hdp_cntl;
1912 };
1913
1914 struct r300_asic {
1915 const unsigned *reg_safe_bm;
1916 unsigned reg_safe_bm_size;
1917 u32 resync_scratch;
1918 u32 hdp_cntl;
1919 };
1920
1921 struct r600_asic {
1922 unsigned max_pipes;
1923 unsigned max_tile_pipes;
1924 unsigned max_simds;
1925 unsigned max_backends;
1926 unsigned max_gprs;
1927 unsigned max_threads;
1928 unsigned max_stack_entries;
1929 unsigned max_hw_contexts;
1930 unsigned max_gs_threads;
1931 unsigned sx_max_export_size;
1932 unsigned sx_max_export_pos_size;
1933 unsigned sx_max_export_smx_size;
1934 unsigned sq_num_cf_insts;
1935 unsigned tiling_nbanks;
1936 unsigned tiling_npipes;
1937 unsigned tiling_group_size;
1938 unsigned tile_config;
1939 unsigned backend_map;
1940 unsigned active_simds;
1941 };
1942
1943 struct rv770_asic {
1944 unsigned max_pipes;
1945 unsigned max_tile_pipes;
1946 unsigned max_simds;
1947 unsigned max_backends;
1948 unsigned max_gprs;
1949 unsigned max_threads;
1950 unsigned max_stack_entries;
1951 unsigned max_hw_contexts;
1952 unsigned max_gs_threads;
1953 unsigned sx_max_export_size;
1954 unsigned sx_max_export_pos_size;
1955 unsigned sx_max_export_smx_size;
1956 unsigned sq_num_cf_insts;
1957 unsigned sx_num_of_sets;
1958 unsigned sc_prim_fifo_size;
1959 unsigned sc_hiz_tile_fifo_size;
1960 unsigned sc_earlyz_tile_fifo_fize;
1961 unsigned tiling_nbanks;
1962 unsigned tiling_npipes;
1963 unsigned tiling_group_size;
1964 unsigned tile_config;
1965 unsigned backend_map;
1966 unsigned active_simds;
1967 };
1968
1969 struct evergreen_asic {
1970 unsigned num_ses;
1971 unsigned max_pipes;
1972 unsigned max_tile_pipes;
1973 unsigned max_simds;
1974 unsigned max_backends;
1975 unsigned max_gprs;
1976 unsigned max_threads;
1977 unsigned max_stack_entries;
1978 unsigned max_hw_contexts;
1979 unsigned max_gs_threads;
1980 unsigned sx_max_export_size;
1981 unsigned sx_max_export_pos_size;
1982 unsigned sx_max_export_smx_size;
1983 unsigned sq_num_cf_insts;
1984 unsigned sx_num_of_sets;
1985 unsigned sc_prim_fifo_size;
1986 unsigned sc_hiz_tile_fifo_size;
1987 unsigned sc_earlyz_tile_fifo_size;
1988 unsigned tiling_nbanks;
1989 unsigned tiling_npipes;
1990 unsigned tiling_group_size;
1991 unsigned tile_config;
1992 unsigned backend_map;
1993 unsigned active_simds;
1994 };
1995
1996 struct cayman_asic {
1997 unsigned max_shader_engines;
1998 unsigned max_pipes_per_simd;
1999 unsigned max_tile_pipes;
2000 unsigned max_simds_per_se;
2001 unsigned max_backends_per_se;
2002 unsigned max_texture_channel_caches;
2003 unsigned max_gprs;
2004 unsigned max_threads;
2005 unsigned max_gs_threads;
2006 unsigned max_stack_entries;
2007 unsigned sx_num_of_sets;
2008 unsigned sx_max_export_size;
2009 unsigned sx_max_export_pos_size;
2010 unsigned sx_max_export_smx_size;
2011 unsigned max_hw_contexts;
2012 unsigned sq_num_cf_insts;
2013 unsigned sc_prim_fifo_size;
2014 unsigned sc_hiz_tile_fifo_size;
2015 unsigned sc_earlyz_tile_fifo_size;
2016
2017 unsigned num_shader_engines;
2018 unsigned num_shader_pipes_per_simd;
2019 unsigned num_tile_pipes;
2020 unsigned num_simds_per_se;
2021 unsigned num_backends_per_se;
2022 unsigned backend_disable_mask_per_asic;
2023 unsigned backend_map;
2024 unsigned num_texture_channel_caches;
2025 unsigned mem_max_burst_length_bytes;
2026 unsigned mem_row_size_in_kb;
2027 unsigned shader_engine_tile_size;
2028 unsigned num_gpus;
2029 unsigned multi_gpu_tile_size;
2030
2031 unsigned tile_config;
2032 unsigned active_simds;
2033 };
2034
2035 struct si_asic {
2036 unsigned max_shader_engines;
2037 unsigned max_tile_pipes;
2038 unsigned max_cu_per_sh;
2039 unsigned max_sh_per_se;
2040 unsigned max_backends_per_se;
2041 unsigned max_texture_channel_caches;
2042 unsigned max_gprs;
2043 unsigned max_gs_threads;
2044 unsigned max_hw_contexts;
2045 unsigned sc_prim_fifo_size_frontend;
2046 unsigned sc_prim_fifo_size_backend;
2047 unsigned sc_hiz_tile_fifo_size;
2048 unsigned sc_earlyz_tile_fifo_size;
2049
2050 unsigned num_tile_pipes;
2051 unsigned backend_enable_mask;
2052 unsigned backend_disable_mask_per_asic;
2053 unsigned backend_map;
2054 unsigned num_texture_channel_caches;
2055 unsigned mem_max_burst_length_bytes;
2056 unsigned mem_row_size_in_kb;
2057 unsigned shader_engine_tile_size;
2058 unsigned num_gpus;
2059 unsigned multi_gpu_tile_size;
2060
2061 unsigned tile_config;
2062 uint32_t tile_mode_array[32];
2063 uint32_t active_cus;
2064 };
2065
2066 struct cik_asic {
2067 unsigned max_shader_engines;
2068 unsigned max_tile_pipes;
2069 unsigned max_cu_per_sh;
2070 unsigned max_sh_per_se;
2071 unsigned max_backends_per_se;
2072 unsigned max_texture_channel_caches;
2073 unsigned max_gprs;
2074 unsigned max_gs_threads;
2075 unsigned max_hw_contexts;
2076 unsigned sc_prim_fifo_size_frontend;
2077 unsigned sc_prim_fifo_size_backend;
2078 unsigned sc_hiz_tile_fifo_size;
2079 unsigned sc_earlyz_tile_fifo_size;
2080
2081 unsigned num_tile_pipes;
2082 unsigned backend_enable_mask;
2083 unsigned backend_disable_mask_per_asic;
2084 unsigned backend_map;
2085 unsigned num_texture_channel_caches;
2086 unsigned mem_max_burst_length_bytes;
2087 unsigned mem_row_size_in_kb;
2088 unsigned shader_engine_tile_size;
2089 unsigned num_gpus;
2090 unsigned multi_gpu_tile_size;
2091
2092 unsigned tile_config;
2093 uint32_t tile_mode_array[32];
2094 uint32_t macrotile_mode_array[16];
2095 uint32_t active_cus;
2096 };
2097
2098 union radeon_asic_config {
2099 struct r300_asic r300;
2100 struct r100_asic r100;
2101 struct r600_asic r600;
2102 struct rv770_asic rv770;
2103 struct evergreen_asic evergreen;
2104 struct cayman_asic cayman;
2105 struct si_asic si;
2106 struct cik_asic cik;
2107 };
2108
2109 /*
2110 * asic initizalization from radeon_asic.c
2111 */
2112 void radeon_agp_disable(struct radeon_device *rdev);
2113 int radeon_asic_init(struct radeon_device *rdev);
2114
2115
2116 /*
2117 * IOCTL.
2118 */
2119 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *filp);
2121 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *filp);
2123 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2124 struct drm_file *file_priv);
2125 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *file_priv);
2127 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *file_priv);
2129 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2130 struct drm_file *file_priv);
2131 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *filp);
2133 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *filp);
2135 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *filp);
2137 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *filp);
2139 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2140 struct drm_file *filp);
2141 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2142 struct drm_file *filp);
2143 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2144 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2145 struct drm_file *filp);
2146 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2147 struct drm_file *filp);
2148
2149 /* VRAM scratch page for HDP bug, default vram page */
2150 struct r600_vram_scratch {
2151 struct radeon_bo *robj;
2152 volatile uint32_t *ptr;
2153 u64 gpu_addr;
2154 };
2155
2156 /*
2157 * ACPI
2158 */
2159 struct radeon_atif_notification_cfg {
2160 bool enabled;
2161 int command_code;
2162 };
2163
2164 struct radeon_atif_notifications {
2165 bool display_switch;
2166 bool expansion_mode_change;
2167 bool thermal_state;
2168 bool forced_power_state;
2169 bool system_power_state;
2170 bool display_conf_change;
2171 bool px_gfx_switch;
2172 bool brightness_change;
2173 bool dgpu_display_event;
2174 };
2175
2176 struct radeon_atif_functions {
2177 bool system_params;
2178 bool sbios_requests;
2179 bool select_active_disp;
2180 bool lid_state;
2181 bool get_tv_standard;
2182 bool set_tv_standard;
2183 bool get_panel_expansion_mode;
2184 bool set_panel_expansion_mode;
2185 bool temperature_change;
2186 bool graphics_device_types;
2187 };
2188
2189 struct radeon_atif {
2190 struct radeon_atif_notifications notifications;
2191 struct radeon_atif_functions functions;
2192 struct radeon_atif_notification_cfg notification_cfg;
2193 struct radeon_encoder *encoder_for_bl;
2194 };
2195
2196 struct radeon_atcs_functions {
2197 bool get_ext_state;
2198 bool pcie_perf_req;
2199 bool pcie_dev_rdy;
2200 bool pcie_bus_width;
2201 };
2202
2203 struct radeon_atcs {
2204 struct radeon_atcs_functions functions;
2205 };
2206
2207 /*
2208 * Core structure, functions and helpers.
2209 */
2210 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2211 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2212
2213 struct radeon_device {
2214 struct device *dev;
2215 struct drm_device *ddev;
2216 struct pci_dev *pdev;
2217 struct rw_semaphore exclusive_lock;
2218 /* ASIC */
2219 union radeon_asic_config config;
2220 enum radeon_family family;
2221 unsigned long flags;
2222 int usec_timeout;
2223 enum radeon_pll_errata pll_errata;
2224 int num_gb_pipes;
2225 int num_z_pipes;
2226 int disp_priority;
2227 /* BIOS */
2228 uint8_t *bios;
2229 bool is_atom_bios;
2230 uint16_t bios_header_start;
2231 struct radeon_bo *stollen_vga_memory;
2232 /* Register mmio */
2233 resource_size_t rmmio_base;
2234 resource_size_t rmmio_size;
2235 /* protects concurrent MM_INDEX/DATA based register access */
2236 spinlock_t mmio_idx_lock;
2237 /* protects concurrent SMC based register access */
2238 spinlock_t smc_idx_lock;
2239 /* protects concurrent PLL register access */
2240 spinlock_t pll_idx_lock;
2241 /* protects concurrent MC register access */
2242 spinlock_t mc_idx_lock;
2243 /* protects concurrent PCIE register access */
2244 spinlock_t pcie_idx_lock;
2245 /* protects concurrent PCIE_PORT register access */
2246 spinlock_t pciep_idx_lock;
2247 /* protects concurrent PIF register access */
2248 spinlock_t pif_idx_lock;
2249 /* protects concurrent CG register access */
2250 spinlock_t cg_idx_lock;
2251 /* protects concurrent UVD register access */
2252 spinlock_t uvd_idx_lock;
2253 /* protects concurrent RCU register access */
2254 spinlock_t rcu_idx_lock;
2255 /* protects concurrent DIDT register access */
2256 spinlock_t didt_idx_lock;
2257 /* protects concurrent ENDPOINT (audio) register access */
2258 spinlock_t end_idx_lock;
2259 void __iomem *rmmio;
2260 radeon_rreg_t mc_rreg;
2261 radeon_wreg_t mc_wreg;
2262 radeon_rreg_t pll_rreg;
2263 radeon_wreg_t pll_wreg;
2264 uint32_t pcie_reg_mask;
2265 radeon_rreg_t pciep_rreg;
2266 radeon_wreg_t pciep_wreg;
2267 /* io port */
2268 void __iomem *rio_mem;
2269 resource_size_t rio_mem_size;
2270 struct radeon_clock clock;
2271 struct radeon_mc mc;
2272 struct radeon_gart gart;
2273 struct radeon_mode_info mode_info;
2274 struct radeon_scratch scratch;
2275 struct radeon_doorbell doorbell;
2276 struct radeon_mman mman;
2277 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2278 wait_queue_head_t fence_queue;
2279 struct mutex ring_lock;
2280 struct radeon_ring ring[RADEON_NUM_RINGS];
2281 bool ib_pool_ready;
2282 struct radeon_sa_manager ring_tmp_bo;
2283 struct radeon_irq irq;
2284 struct radeon_asic *asic;
2285 struct radeon_gem gem;
2286 struct radeon_pm pm;
2287 struct radeon_uvd uvd;
2288 struct radeon_vce vce;
2289 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2290 struct radeon_wb wb;
2291 struct radeon_dummy_page dummy_page;
2292 bool shutdown;
2293 bool suspend;
2294 bool need_dma32;
2295 bool accel_working;
2296 bool fastfb_working; /* IGP feature*/
2297 bool needs_reset;
2298 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2299 const struct firmware *me_fw; /* all family ME firmware */
2300 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2301 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2302 const struct firmware *mc_fw; /* NI MC firmware */
2303 const struct firmware *ce_fw; /* SI CE firmware */
2304 const struct firmware *mec_fw; /* CIK MEC firmware */
2305 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2306 const struct firmware *smc_fw; /* SMC firmware */
2307 const struct firmware *uvd_fw; /* UVD firmware */
2308 const struct firmware *vce_fw; /* VCE firmware */
2309 struct r600_vram_scratch vram_scratch;
2310 int msi_enabled; /* msi enabled */
2311 struct r600_ih ih; /* r6/700 interrupt ring */
2312 struct radeon_rlc rlc;
2313 struct radeon_mec mec;
2314 struct work_struct hotplug_work;
2315 struct work_struct audio_work;
2316 struct work_struct reset_work;
2317 int num_crtc; /* number of crtcs */
2318 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2319 bool has_uvd;
2320 struct r600_audio audio; /* audio stuff */
2321 struct notifier_block acpi_nb;
2322 /* only one userspace can use Hyperz features or CMASK at a time */
2323 struct drm_file *hyperz_filp;
2324 struct drm_file *cmask_filp;
2325 /* i2c buses */
2326 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2327 /* debugfs */
2328 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2329 unsigned debugfs_count;
2330 /* virtual memory */
2331 struct radeon_vm_manager vm_manager;
2332 struct mutex gpu_clock_mutex;
2333 /* memory stats */
2334 atomic64_t vram_usage;
2335 atomic64_t gtt_usage;
2336 atomic64_t num_bytes_moved;
2337 /* ACPI interface */
2338 struct radeon_atif atif;
2339 struct radeon_atcs atcs;
2340 /* srbm instance registers */
2341 struct mutex srbm_mutex;
2342 /* clock, powergating flags */
2343 u32 cg_flags;
2344 u32 pg_flags;
2345
2346 struct dev_pm_domain vga_pm_domain;
2347 bool have_disp_power_ref;
2348 };
2349
2350 bool radeon_is_px(struct drm_device *dev);
2351 int radeon_device_init(struct radeon_device *rdev,
2352 struct drm_device *ddev,
2353 struct pci_dev *pdev,
2354 uint32_t flags);
2355 void radeon_device_fini(struct radeon_device *rdev);
2356 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2357
2358 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2359 bool always_indirect);
2360 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2361 bool always_indirect);
2362 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2363 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2364
2365 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2366 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2367
2368 /*
2369 * Cast helper
2370 */
2371 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2372
2373 /*
2374 * Registers read & write functions.
2375 */
2376 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2377 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2378 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2379 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2380 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2381 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2382 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2383 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2384 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2385 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2386 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2387 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2388 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2389 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2390 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2391 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2392 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2393 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2394 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2395 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2396 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2397 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2398 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2399 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2400 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2401 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2402 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2403 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2404 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2405 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2406 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2407 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2408 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2409 #define WREG32_P(reg, val, mask) \
2410 do { \
2411 uint32_t tmp_ = RREG32(reg); \
2412 tmp_ &= (mask); \
2413 tmp_ |= ((val) & ~(mask)); \
2414 WREG32(reg, tmp_); \
2415 } while (0)
2416 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2417 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2418 #define WREG32_PLL_P(reg, val, mask) \
2419 do { \
2420 uint32_t tmp_ = RREG32_PLL(reg); \
2421 tmp_ &= (mask); \
2422 tmp_ |= ((val) & ~(mask)); \
2423 WREG32_PLL(reg, tmp_); \
2424 } while (0)
2425 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2426 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2427 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2428
2429 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2430 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2431
2432 /*
2433 * Indirect registers accessor
2434 */
2435 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2436 {
2437 unsigned long flags;
2438 uint32_t r;
2439
2440 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2441 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2442 r = RREG32(RADEON_PCIE_DATA);
2443 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2444 return r;
2445 }
2446
2447 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2448 {
2449 unsigned long flags;
2450
2451 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2452 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2453 WREG32(RADEON_PCIE_DATA, (v));
2454 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2455 }
2456
2457 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2458 {
2459 unsigned long flags;
2460 u32 r;
2461
2462 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2463 WREG32(TN_SMC_IND_INDEX_0, (reg));
2464 r = RREG32(TN_SMC_IND_DATA_0);
2465 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2466 return r;
2467 }
2468
2469 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2470 {
2471 unsigned long flags;
2472
2473 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2474 WREG32(TN_SMC_IND_INDEX_0, (reg));
2475 WREG32(TN_SMC_IND_DATA_0, (v));
2476 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2477 }
2478
2479 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2480 {
2481 unsigned long flags;
2482 u32 r;
2483
2484 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2485 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2486 r = RREG32(R600_RCU_DATA);
2487 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2488 return r;
2489 }
2490
2491 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2492 {
2493 unsigned long flags;
2494
2495 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2496 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2497 WREG32(R600_RCU_DATA, (v));
2498 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2499 }
2500
2501 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2502 {
2503 unsigned long flags;
2504 u32 r;
2505
2506 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2507 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2508 r = RREG32(EVERGREEN_CG_IND_DATA);
2509 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2510 return r;
2511 }
2512
2513 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2514 {
2515 unsigned long flags;
2516
2517 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2518 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2519 WREG32(EVERGREEN_CG_IND_DATA, (v));
2520 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2521 }
2522
2523 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2524 {
2525 unsigned long flags;
2526 u32 r;
2527
2528 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2529 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2530 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2531 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2532 return r;
2533 }
2534
2535 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2536 {
2537 unsigned long flags;
2538
2539 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2540 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2541 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2542 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2543 }
2544
2545 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2546 {
2547 unsigned long flags;
2548 u32 r;
2549
2550 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2551 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2552 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2553 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2554 return r;
2555 }
2556
2557 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2558 {
2559 unsigned long flags;
2560
2561 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2562 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2563 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2564 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2565 }
2566
2567 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2568 {
2569 unsigned long flags;
2570 u32 r;
2571
2572 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2573 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2574 r = RREG32(R600_UVD_CTX_DATA);
2575 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2576 return r;
2577 }
2578
2579 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2580 {
2581 unsigned long flags;
2582
2583 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2584 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2585 WREG32(R600_UVD_CTX_DATA, (v));
2586 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2587 }
2588
2589
2590 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2591 {
2592 unsigned long flags;
2593 u32 r;
2594
2595 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2596 WREG32(CIK_DIDT_IND_INDEX, (reg));
2597 r = RREG32(CIK_DIDT_IND_DATA);
2598 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2599 return r;
2600 }
2601
2602 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2603 {
2604 unsigned long flags;
2605
2606 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2607 WREG32(CIK_DIDT_IND_INDEX, (reg));
2608 WREG32(CIK_DIDT_IND_DATA, (v));
2609 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2610 }
2611
2612 void r100_pll_errata_after_index(struct radeon_device *rdev);
2613
2614
2615 /*
2616 * ASICs helpers.
2617 */
2618 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2619 (rdev->pdev->device == 0x5969))
2620 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2621 (rdev->family == CHIP_RV200) || \
2622 (rdev->family == CHIP_RS100) || \
2623 (rdev->family == CHIP_RS200) || \
2624 (rdev->family == CHIP_RV250) || \
2625 (rdev->family == CHIP_RV280) || \
2626 (rdev->family == CHIP_RS300))
2627 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2628 (rdev->family == CHIP_RV350) || \
2629 (rdev->family == CHIP_R350) || \
2630 (rdev->family == CHIP_RV380) || \
2631 (rdev->family == CHIP_R420) || \
2632 (rdev->family == CHIP_R423) || \
2633 (rdev->family == CHIP_RV410) || \
2634 (rdev->family == CHIP_RS400) || \
2635 (rdev->family == CHIP_RS480))
2636 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2637 (rdev->ddev->pdev->device == 0x9443) || \
2638 (rdev->ddev->pdev->device == 0x944B) || \
2639 (rdev->ddev->pdev->device == 0x9506) || \
2640 (rdev->ddev->pdev->device == 0x9509) || \
2641 (rdev->ddev->pdev->device == 0x950F) || \
2642 (rdev->ddev->pdev->device == 0x689C) || \
2643 (rdev->ddev->pdev->device == 0x689D))
2644 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2645 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2646 (rdev->family == CHIP_RS690) || \
2647 (rdev->family == CHIP_RS740) || \
2648 (rdev->family >= CHIP_R600))
2649 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2650 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2651 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2652 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2653 (rdev->flags & RADEON_IS_IGP))
2654 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2655 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2656 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2657 (rdev->flags & RADEON_IS_IGP))
2658 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2659 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2660 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2661 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2662 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2663 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2664 (rdev->family == CHIP_MULLINS))
2665
2666 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2667 (rdev->ddev->pdev->device == 0x6850) || \
2668 (rdev->ddev->pdev->device == 0x6858) || \
2669 (rdev->ddev->pdev->device == 0x6859) || \
2670 (rdev->ddev->pdev->device == 0x6840) || \
2671 (rdev->ddev->pdev->device == 0x6841) || \
2672 (rdev->ddev->pdev->device == 0x6842) || \
2673 (rdev->ddev->pdev->device == 0x6843))
2674
2675 /*
2676 * BIOS helpers.
2677 */
2678 #define RBIOS8(i) (rdev->bios[i])
2679 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2680 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2681
2682 int radeon_combios_init(struct radeon_device *rdev);
2683 void radeon_combios_fini(struct radeon_device *rdev);
2684 int radeon_atombios_init(struct radeon_device *rdev);
2685 void radeon_atombios_fini(struct radeon_device *rdev);
2686
2687
2688 /*
2689 * RING helpers.
2690 */
2691 #if DRM_DEBUG_CODE == 0
2692 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2693 {
2694 ring->ring[ring->wptr++] = v;
2695 ring->wptr &= ring->ptr_mask;
2696 ring->count_dw--;
2697 ring->ring_free_dw--;
2698 }
2699 #else
2700 /* With debugging this is just too big to inline */
2701 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2702 #endif
2703
2704 /*
2705 * ASICs macro.
2706 */
2707 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2708 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2709 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2710 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2711 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2712 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2713 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2714 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2715 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2716 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2717 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2718 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2719 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2720 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2721 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2722 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2723 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2724 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2725 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2726 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2727 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2728 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2729 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2730 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2731 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2732 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2733 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2734 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2735 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2736 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2737 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2738 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2739 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2740 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2741 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2742 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2743 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2744 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2745 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2746 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2747 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2748 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2749 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2750 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2751 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2752 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2753 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2754 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2755 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2756 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2757 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2758 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2759 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2760 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2761 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2762 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2763 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2764 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2765 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2766 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2767 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2768 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2769 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2770 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2771 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2772 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2773 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2774 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2775 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2776 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2777 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2778 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2779 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2780 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2781 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2782 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2783 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2784 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2785 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2786 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2787 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2788 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2789 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2790 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2791
2792 /* Common functions */
2793 /* AGP */
2794 extern int radeon_gpu_reset(struct radeon_device *rdev);
2795 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2796 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2797 extern void radeon_agp_disable(struct radeon_device *rdev);
2798 extern int radeon_modeset_init(struct radeon_device *rdev);
2799 extern void radeon_modeset_fini(struct radeon_device *rdev);
2800 extern bool radeon_card_posted(struct radeon_device *rdev);
2801 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2802 extern void radeon_update_display_priority(struct radeon_device *rdev);
2803 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2804 extern void radeon_scratch_init(struct radeon_device *rdev);
2805 extern void radeon_wb_fini(struct radeon_device *rdev);
2806 extern int radeon_wb_init(struct radeon_device *rdev);
2807 extern void radeon_wb_disable(struct radeon_device *rdev);
2808 extern void radeon_surface_init(struct radeon_device *rdev);
2809 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2810 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2811 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2812 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2813 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2814 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2815 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2816 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2817 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2818 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2819 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2820 const u32 *registers,
2821 const u32 array_size);
2822
2823 /*
2824 * vm
2825 */
2826 int radeon_vm_manager_init(struct radeon_device *rdev);
2827 void radeon_vm_manager_fini(struct radeon_device *rdev);
2828 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2829 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2830 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2831 struct radeon_vm *vm,
2832 struct list_head *head);
2833 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2834 struct radeon_vm *vm, int ring);
2835 void radeon_vm_flush(struct radeon_device *rdev,
2836 struct radeon_vm *vm,
2837 int ring);
2838 void radeon_vm_fence(struct radeon_device *rdev,
2839 struct radeon_vm *vm,
2840 struct radeon_fence *fence);
2841 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2842 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2843 struct radeon_vm *vm);
2844 int radeon_vm_clear_freed(struct radeon_device *rdev,
2845 struct radeon_vm *vm);
2846 int radeon_vm_bo_update(struct radeon_device *rdev,
2847 struct radeon_bo_va *bo_va,
2848 struct ttm_mem_reg *mem);
2849 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2850 struct radeon_bo *bo);
2851 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2852 struct radeon_bo *bo);
2853 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2854 struct radeon_vm *vm,
2855 struct radeon_bo *bo);
2856 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2857 struct radeon_bo_va *bo_va,
2858 uint64_t offset,
2859 uint32_t flags);
2860 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2861 struct radeon_bo_va *bo_va);
2862
2863 /* audio */
2864 void r600_audio_update_hdmi(struct work_struct *work);
2865 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2866 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2867 void r600_audio_enable(struct radeon_device *rdev,
2868 struct r600_audio_pin *pin,
2869 bool enable);
2870 void dce6_audio_enable(struct radeon_device *rdev,
2871 struct r600_audio_pin *pin,
2872 bool enable);
2873
2874 /*
2875 * R600 vram scratch functions
2876 */
2877 int r600_vram_scratch_init(struct radeon_device *rdev);
2878 void r600_vram_scratch_fini(struct radeon_device *rdev);
2879
2880 /*
2881 * r600 cs checking helper
2882 */
2883 unsigned r600_mip_minify(unsigned size, unsigned level);
2884 bool r600_fmt_is_valid_color(u32 format);
2885 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2886 int r600_fmt_get_blocksize(u32 format);
2887 int r600_fmt_get_nblocksx(u32 format, u32 w);
2888 int r600_fmt_get_nblocksy(u32 format, u32 h);
2889
2890 /*
2891 * r600 functions used by radeon_encoder.c
2892 */
2893 struct radeon_hdmi_acr {
2894 u32 clock;
2895
2896 int n_32khz;
2897 int cts_32khz;
2898
2899 int n_44_1khz;
2900 int cts_44_1khz;
2901
2902 int n_48khz;
2903 int cts_48khz;
2904
2905 };
2906
2907 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2908
2909 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2910 u32 tiling_pipe_num,
2911 u32 max_rb_num,
2912 u32 total_max_rb_num,
2913 u32 enabled_rb_mask);
2914
2915 /*
2916 * evergreen functions used by radeon_encoder.c
2917 */
2918
2919 extern int ni_init_microcode(struct radeon_device *rdev);
2920 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2921
2922 /* radeon_acpi.c */
2923 #if defined(CONFIG_ACPI)
2924 extern int radeon_acpi_init(struct radeon_device *rdev);
2925 extern void radeon_acpi_fini(struct radeon_device *rdev);
2926 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2927 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2928 u8 perf_req, bool advertise);
2929 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2930 #else
2931 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2932 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2933 #endif
2934
2935 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2936 struct radeon_cs_packet *pkt,
2937 unsigned idx);
2938 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2939 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2940 struct radeon_cs_packet *pkt);
2941 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2942 struct radeon_cs_reloc **cs_reloc,
2943 int nomm);
2944 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2945 uint32_t *vline_start_end,
2946 uint32_t *vline_status);
2947
2948 #include "radeon_object.h"
2949
2950 #endif
Linux kernel - Deliverables
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