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drm/radeon: rework ring function handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
101
102 /*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* RADEON_IB_POOL_SIZE must be a power of 2 */
109 #define RADEON_IB_POOL_SIZE 16
110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
111 #define RADEONFB_CONN_LIMIT 4
112 #define RADEON_BIOS_NUM_SCRATCH 8
113
114 /* max number of rings */
115 #define RADEON_NUM_RINGS 6
116
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
123
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
132
133 /* R600+ */
134 #define R600_RING_TYPE_UVD_INDEX 5
135
136 /* hardcode those limit for now */
137 #define RADEON_VA_IB_OFFSET (1 << 20)
138 #define RADEON_VA_RESERVED_SIZE (8 << 20)
139 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
140
141 /* reset flags */
142 #define RADEON_RESET_GFX (1 << 0)
143 #define RADEON_RESET_COMPUTE (1 << 1)
144 #define RADEON_RESET_DMA (1 << 2)
145 #define RADEON_RESET_CP (1 << 3)
146 #define RADEON_RESET_GRBM (1 << 4)
147 #define RADEON_RESET_DMA1 (1 << 5)
148 #define RADEON_RESET_RLC (1 << 6)
149 #define RADEON_RESET_SEM (1 << 7)
150 #define RADEON_RESET_IH (1 << 8)
151 #define RADEON_RESET_VMC (1 << 9)
152 #define RADEON_RESET_MC (1 << 10)
153 #define RADEON_RESET_DISPLAY (1 << 11)
154
155 /* CG block flags */
156 #define RADEON_CG_BLOCK_GFX (1 << 0)
157 #define RADEON_CG_BLOCK_MC (1 << 1)
158 #define RADEON_CG_BLOCK_SDMA (1 << 2)
159 #define RADEON_CG_BLOCK_UVD (1 << 3)
160 #define RADEON_CG_BLOCK_VCE (1 << 4)
161 #define RADEON_CG_BLOCK_HDP (1 << 5)
162
163 /* max cursor sizes (in pixels) */
164 #define CURSOR_WIDTH 64
165 #define CURSOR_HEIGHT 64
166
167 #define CIK_CURSOR_WIDTH 128
168 #define CIK_CURSOR_HEIGHT 128
169
170 /*
171 * Errata workarounds.
172 */
173 enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
177 };
178
179
180 struct radeon_device;
181
182
183 /*
184 * BIOS.
185 */
186 bool radeon_get_bios(struct radeon_device *rdev);
187
188 /*
189 * Dummy page
190 */
191 struct radeon_dummy_page {
192 struct page *page;
193 dma_addr_t addr;
194 };
195 int radeon_dummy_page_init(struct radeon_device *rdev);
196 void radeon_dummy_page_fini(struct radeon_device *rdev);
197
198
199 /*
200 * Clocks
201 */
202 struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
205 struct radeon_pll dcpll;
206 struct radeon_pll spll;
207 struct radeon_pll mpll;
208 /* 10 Khz units */
209 uint32_t default_mclk;
210 uint32_t default_sclk;
211 uint32_t default_dispclk;
212 uint32_t current_dispclk;
213 uint32_t dp_extclk;
214 uint32_t max_pixel_clock;
215 };
216
217 /*
218 * Power management
219 */
220 int radeon_pm_init(struct radeon_device *rdev);
221 void radeon_pm_fini(struct radeon_device *rdev);
222 void radeon_pm_compute_clocks(struct radeon_device *rdev);
223 void radeon_pm_suspend(struct radeon_device *rdev);
224 void radeon_pm_resume(struct radeon_device *rdev);
225 void radeon_combios_get_power_modes(struct radeon_device *rdev);
226 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
227 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
228 u8 clock_type,
229 u32 clock,
230 bool strobe_mode,
231 struct atom_clock_dividers *dividers);
232 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
233 u32 clock,
234 bool strobe_mode,
235 struct atom_mpll_param *mpll_param);
236 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
237 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
244 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
246 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
247 u16 *voltage,
248 u16 leakage_idx);
249 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
250 u16 *leakage_id);
251 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
252 u16 *vddc, u16 *vddci,
253 u16 virtual_voltage_id,
254 u16 vbios_voltage_id);
255 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
256 u8 voltage_type,
257 u16 nominal_voltage,
258 u16 *true_voltage);
259 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
260 u8 voltage_type, u16 *min_voltage);
261 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
262 u8 voltage_type, u16 *max_voltage);
263 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
264 u8 voltage_type, u8 voltage_mode,
265 struct atom_voltage_table *voltage_table);
266 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
267 u8 voltage_type, u8 voltage_mode);
268 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
269 u32 mem_clock);
270 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
271 u32 mem_clock);
272 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
273 u8 module_index,
274 struct atom_mc_reg_table *reg_table);
275 int radeon_atom_get_memory_info(struct radeon_device *rdev,
276 u8 module_index, struct atom_memory_info *mem_info);
277 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
278 bool gddr5, u8 module_index,
279 struct atom_memory_clock_range_table *mclk_range_table);
280 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
281 u16 voltage_id, u16 *voltage);
282 void rs690_pm_info(struct radeon_device *rdev);
283 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
284 unsigned *bankh, unsigned *mtaspect,
285 unsigned *tile_split);
286
287 /*
288 * Fences.
289 */
290 struct radeon_fence_driver {
291 uint32_t scratch_reg;
292 uint64_t gpu_addr;
293 volatile uint32_t *cpu_addr;
294 /* sync_seq is protected by ring emission lock */
295 uint64_t sync_seq[RADEON_NUM_RINGS];
296 atomic64_t last_seq;
297 unsigned long last_activity;
298 bool initialized;
299 };
300
301 struct radeon_fence {
302 struct radeon_device *rdev;
303 struct kref kref;
304 /* protected by radeon_fence.lock */
305 uint64_t seq;
306 /* RB, DMA, etc. */
307 unsigned ring;
308 };
309
310 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
311 int radeon_fence_driver_init(struct radeon_device *rdev);
312 void radeon_fence_driver_fini(struct radeon_device *rdev);
313 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
314 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
315 void radeon_fence_process(struct radeon_device *rdev, int ring);
316 bool radeon_fence_signaled(struct radeon_fence *fence);
317 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
318 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
319 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
320 int radeon_fence_wait_any(struct radeon_device *rdev,
321 struct radeon_fence **fences,
322 bool intr);
323 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
324 void radeon_fence_unref(struct radeon_fence **fence);
325 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
326 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
327 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
328 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
329 struct radeon_fence *b)
330 {
331 if (!a) {
332 return b;
333 }
334
335 if (!b) {
336 return a;
337 }
338
339 BUG_ON(a->ring != b->ring);
340
341 if (a->seq > b->seq) {
342 return a;
343 } else {
344 return b;
345 }
346 }
347
348 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
349 struct radeon_fence *b)
350 {
351 if (!a) {
352 return false;
353 }
354
355 if (!b) {
356 return true;
357 }
358
359 BUG_ON(a->ring != b->ring);
360
361 return a->seq < b->seq;
362 }
363
364 /*
365 * Tiling registers
366 */
367 struct radeon_surface_reg {
368 struct radeon_bo *bo;
369 };
370
371 #define RADEON_GEM_MAX_SURFACES 8
372
373 /*
374 * TTM.
375 */
376 struct radeon_mman {
377 struct ttm_bo_global_ref bo_global_ref;
378 struct drm_global_reference mem_global_ref;
379 struct ttm_bo_device bdev;
380 bool mem_global_referenced;
381 bool initialized;
382 };
383
384 /* bo virtual address in a specific vm */
385 struct radeon_bo_va {
386 /* protected by bo being reserved */
387 struct list_head bo_list;
388 uint64_t soffset;
389 uint64_t eoffset;
390 uint32_t flags;
391 bool valid;
392 unsigned ref_count;
393
394 /* protected by vm mutex */
395 struct list_head vm_list;
396
397 /* constant after initialization */
398 struct radeon_vm *vm;
399 struct radeon_bo *bo;
400 };
401
402 struct radeon_bo {
403 /* Protected by gem.mutex */
404 struct list_head list;
405 /* Protected by tbo.reserved */
406 u32 placements[3];
407 struct ttm_placement placement;
408 struct ttm_buffer_object tbo;
409 struct ttm_bo_kmap_obj kmap;
410 unsigned pin_count;
411 void *kptr;
412 u32 tiling_flags;
413 u32 pitch;
414 int surface_reg;
415 /* list of all virtual address to which this bo
416 * is associated to
417 */
418 struct list_head va;
419 /* Constant after initialization */
420 struct radeon_device *rdev;
421 struct drm_gem_object gem_base;
422
423 struct ttm_bo_kmap_obj dma_buf_vmap;
424 pid_t pid;
425 };
426 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
427
428 struct radeon_bo_list {
429 struct ttm_validate_buffer tv;
430 struct radeon_bo *bo;
431 uint64_t gpu_offset;
432 bool written;
433 unsigned domain;
434 unsigned alt_domain;
435 u32 tiling_flags;
436 };
437
438 int radeon_gem_debugfs_init(struct radeon_device *rdev);
439
440 /* sub-allocation manager, it has to be protected by another lock.
441 * By conception this is an helper for other part of the driver
442 * like the indirect buffer or semaphore, which both have their
443 * locking.
444 *
445 * Principe is simple, we keep a list of sub allocation in offset
446 * order (first entry has offset == 0, last entry has the highest
447 * offset).
448 *
449 * When allocating new object we first check if there is room at
450 * the end total_size - (last_object_offset + last_object_size) >=
451 * alloc_size. If so we allocate new object there.
452 *
453 * When there is not enough room at the end, we start waiting for
454 * each sub object until we reach object_offset+object_size >=
455 * alloc_size, this object then become the sub object we return.
456 *
457 * Alignment can't be bigger than page size.
458 *
459 * Hole are not considered for allocation to keep things simple.
460 * Assumption is that there won't be hole (all object on same
461 * alignment).
462 */
463 struct radeon_sa_manager {
464 wait_queue_head_t wq;
465 struct radeon_bo *bo;
466 struct list_head *hole;
467 struct list_head flist[RADEON_NUM_RINGS];
468 struct list_head olist;
469 unsigned size;
470 uint64_t gpu_addr;
471 void *cpu_ptr;
472 uint32_t domain;
473 uint32_t align;
474 };
475
476 struct radeon_sa_bo;
477
478 /* sub-allocation buffer */
479 struct radeon_sa_bo {
480 struct list_head olist;
481 struct list_head flist;
482 struct radeon_sa_manager *manager;
483 unsigned soffset;
484 unsigned eoffset;
485 struct radeon_fence *fence;
486 };
487
488 /*
489 * GEM objects.
490 */
491 struct radeon_gem {
492 struct mutex mutex;
493 struct list_head objects;
494 };
495
496 int radeon_gem_init(struct radeon_device *rdev);
497 void radeon_gem_fini(struct radeon_device *rdev);
498 int radeon_gem_object_create(struct radeon_device *rdev, int size,
499 int alignment, int initial_domain,
500 bool discardable, bool kernel,
501 struct drm_gem_object **obj);
502
503 int radeon_mode_dumb_create(struct drm_file *file_priv,
504 struct drm_device *dev,
505 struct drm_mode_create_dumb *args);
506 int radeon_mode_dumb_mmap(struct drm_file *filp,
507 struct drm_device *dev,
508 uint32_t handle, uint64_t *offset_p);
509 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
510 struct drm_device *dev,
511 uint32_t handle);
512
513 /*
514 * Semaphores.
515 */
516 /* everything here is constant */
517 struct radeon_semaphore {
518 struct radeon_sa_bo *sa_bo;
519 signed waiters;
520 uint64_t gpu_addr;
521 };
522
523 int radeon_semaphore_create(struct radeon_device *rdev,
524 struct radeon_semaphore **semaphore);
525 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
526 struct radeon_semaphore *semaphore);
527 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
528 struct radeon_semaphore *semaphore);
529 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
530 struct radeon_semaphore *semaphore,
531 int signaler, int waiter);
532 void radeon_semaphore_free(struct radeon_device *rdev,
533 struct radeon_semaphore **semaphore,
534 struct radeon_fence *fence);
535
536 /*
537 * GART structures, functions & helpers
538 */
539 struct radeon_mc;
540
541 #define RADEON_GPU_PAGE_SIZE 4096
542 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
543 #define RADEON_GPU_PAGE_SHIFT 12
544 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
545
546 struct radeon_gart {
547 dma_addr_t table_addr;
548 struct radeon_bo *robj;
549 void *ptr;
550 unsigned num_gpu_pages;
551 unsigned num_cpu_pages;
552 unsigned table_size;
553 struct page **pages;
554 dma_addr_t *pages_addr;
555 bool ready;
556 };
557
558 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
559 void radeon_gart_table_ram_free(struct radeon_device *rdev);
560 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
561 void radeon_gart_table_vram_free(struct radeon_device *rdev);
562 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
563 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
564 int radeon_gart_init(struct radeon_device *rdev);
565 void radeon_gart_fini(struct radeon_device *rdev);
566 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
567 int pages);
568 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
569 int pages, struct page **pagelist,
570 dma_addr_t *dma_addr);
571 void radeon_gart_restore(struct radeon_device *rdev);
572
573
574 /*
575 * GPU MC structures, functions & helpers
576 */
577 struct radeon_mc {
578 resource_size_t aper_size;
579 resource_size_t aper_base;
580 resource_size_t agp_base;
581 /* for some chips with <= 32MB we need to lie
582 * about vram size near mc fb location */
583 u64 mc_vram_size;
584 u64 visible_vram_size;
585 u64 gtt_size;
586 u64 gtt_start;
587 u64 gtt_end;
588 u64 vram_start;
589 u64 vram_end;
590 unsigned vram_width;
591 u64 real_vram_size;
592 int vram_mtrr;
593 bool vram_is_ddr;
594 bool igp_sideport_enabled;
595 u64 gtt_base_align;
596 u64 mc_mask;
597 };
598
599 bool radeon_combios_sideport_present(struct radeon_device *rdev);
600 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
601
602 /*
603 * GPU scratch registers structures, functions & helpers
604 */
605 struct radeon_scratch {
606 unsigned num_reg;
607 uint32_t reg_base;
608 bool free[32];
609 uint32_t reg[32];
610 };
611
612 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
613 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
614
615 /*
616 * GPU doorbell structures, functions & helpers
617 */
618 struct radeon_doorbell {
619 u32 num_pages;
620 bool free[1024];
621 /* doorbell mmio */
622 resource_size_t base;
623 resource_size_t size;
624 void __iomem *ptr;
625 };
626
627 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
628 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
629
630 /*
631 * IRQS.
632 */
633
634 struct radeon_unpin_work {
635 struct work_struct work;
636 struct radeon_device *rdev;
637 int crtc_id;
638 struct radeon_fence *fence;
639 struct drm_pending_vblank_event *event;
640 struct radeon_bo *old_rbo;
641 u64 new_crtc_base;
642 };
643
644 struct r500_irq_stat_regs {
645 u32 disp_int;
646 u32 hdmi0_status;
647 };
648
649 struct r600_irq_stat_regs {
650 u32 disp_int;
651 u32 disp_int_cont;
652 u32 disp_int_cont2;
653 u32 d1grph_int;
654 u32 d2grph_int;
655 u32 hdmi0_status;
656 u32 hdmi1_status;
657 };
658
659 struct evergreen_irq_stat_regs {
660 u32 disp_int;
661 u32 disp_int_cont;
662 u32 disp_int_cont2;
663 u32 disp_int_cont3;
664 u32 disp_int_cont4;
665 u32 disp_int_cont5;
666 u32 d1grph_int;
667 u32 d2grph_int;
668 u32 d3grph_int;
669 u32 d4grph_int;
670 u32 d5grph_int;
671 u32 d6grph_int;
672 u32 afmt_status1;
673 u32 afmt_status2;
674 u32 afmt_status3;
675 u32 afmt_status4;
676 u32 afmt_status5;
677 u32 afmt_status6;
678 };
679
680 struct cik_irq_stat_regs {
681 u32 disp_int;
682 u32 disp_int_cont;
683 u32 disp_int_cont2;
684 u32 disp_int_cont3;
685 u32 disp_int_cont4;
686 u32 disp_int_cont5;
687 u32 disp_int_cont6;
688 };
689
690 union radeon_irq_stat_regs {
691 struct r500_irq_stat_regs r500;
692 struct r600_irq_stat_regs r600;
693 struct evergreen_irq_stat_regs evergreen;
694 struct cik_irq_stat_regs cik;
695 };
696
697 #define RADEON_MAX_HPD_PINS 6
698 #define RADEON_MAX_CRTCS 6
699 #define RADEON_MAX_AFMT_BLOCKS 6
700
701 struct radeon_irq {
702 bool installed;
703 spinlock_t lock;
704 atomic_t ring_int[RADEON_NUM_RINGS];
705 bool crtc_vblank_int[RADEON_MAX_CRTCS];
706 atomic_t pflip[RADEON_MAX_CRTCS];
707 wait_queue_head_t vblank_queue;
708 bool hpd[RADEON_MAX_HPD_PINS];
709 bool afmt[RADEON_MAX_AFMT_BLOCKS];
710 union radeon_irq_stat_regs stat_regs;
711 bool dpm_thermal;
712 };
713
714 int radeon_irq_kms_init(struct radeon_device *rdev);
715 void radeon_irq_kms_fini(struct radeon_device *rdev);
716 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
717 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
718 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
719 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
720 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
721 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
722 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
723 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
724
725 /*
726 * CP & rings.
727 */
728
729 struct radeon_ib {
730 struct radeon_sa_bo *sa_bo;
731 uint32_t length_dw;
732 uint64_t gpu_addr;
733 uint32_t *ptr;
734 int ring;
735 struct radeon_fence *fence;
736 struct radeon_vm *vm;
737 bool is_const_ib;
738 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
739 struct radeon_semaphore *semaphore;
740 };
741
742 struct radeon_ring {
743 struct radeon_bo *ring_obj;
744 volatile uint32_t *ring;
745 unsigned rptr;
746 unsigned rptr_offs;
747 unsigned rptr_reg;
748 unsigned rptr_save_reg;
749 u64 next_rptr_gpu_addr;
750 volatile u32 *next_rptr_cpu_addr;
751 unsigned wptr;
752 unsigned wptr_old;
753 unsigned wptr_reg;
754 unsigned ring_size;
755 unsigned ring_free_dw;
756 int count_dw;
757 unsigned long last_activity;
758 unsigned last_rptr;
759 uint64_t gpu_addr;
760 uint32_t align_mask;
761 uint32_t ptr_mask;
762 bool ready;
763 u32 ptr_reg_shift;
764 u32 ptr_reg_mask;
765 u32 nop;
766 u32 idx;
767 u64 last_semaphore_signal_addr;
768 u64 last_semaphore_wait_addr;
769 /* for CIK queues */
770 u32 me;
771 u32 pipe;
772 u32 queue;
773 struct radeon_bo *mqd_obj;
774 u32 doorbell_page_num;
775 u32 doorbell_offset;
776 unsigned wptr_offs;
777 };
778
779 struct radeon_mec {
780 struct radeon_bo *hpd_eop_obj;
781 u64 hpd_eop_gpu_addr;
782 u32 num_pipe;
783 u32 num_mec;
784 u32 num_queue;
785 };
786
787 /*
788 * VM
789 */
790
791 /* maximum number of VMIDs */
792 #define RADEON_NUM_VM 16
793
794 /* defines number of bits in page table versus page directory,
795 * a page is 4KB so we have 12 bits offset, 9 bits in the page
796 * table and the remaining 19 bits are in the page directory */
797 #define RADEON_VM_BLOCK_SIZE 9
798
799 /* number of entries in page table */
800 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
801
802 /* PTBs (Page Table Blocks) need to be aligned to 32K */
803 #define RADEON_VM_PTB_ALIGN_SIZE 32768
804 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
805 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
806
807 struct radeon_vm {
808 struct list_head list;
809 struct list_head va;
810 unsigned id;
811
812 /* contains the page directory */
813 struct radeon_sa_bo *page_directory;
814 uint64_t pd_gpu_addr;
815
816 /* array of page tables, one for each page directory entry */
817 struct radeon_sa_bo **page_tables;
818
819 struct mutex mutex;
820 /* last fence for cs using this vm */
821 struct radeon_fence *fence;
822 /* last flush or NULL if we still need to flush */
823 struct radeon_fence *last_flush;
824 };
825
826 struct radeon_vm_manager {
827 struct mutex lock;
828 struct list_head lru_vm;
829 struct radeon_fence *active[RADEON_NUM_VM];
830 struct radeon_sa_manager sa_manager;
831 uint32_t max_pfn;
832 /* number of VMIDs */
833 unsigned nvm;
834 /* vram base address for page table entry */
835 u64 vram_base_offset;
836 /* is vm enabled? */
837 bool enabled;
838 };
839
840 /*
841 * file private structure
842 */
843 struct radeon_fpriv {
844 struct radeon_vm vm;
845 };
846
847 /*
848 * R6xx+ IH ring
849 */
850 struct r600_ih {
851 struct radeon_bo *ring_obj;
852 volatile uint32_t *ring;
853 unsigned rptr;
854 unsigned ring_size;
855 uint64_t gpu_addr;
856 uint32_t ptr_mask;
857 atomic_t lock;
858 bool enabled;
859 };
860
861 /*
862 * RLC stuff
863 */
864 #include "clearstate_defs.h"
865
866 struct radeon_rlc {
867 /* for power gating */
868 struct radeon_bo *save_restore_obj;
869 uint64_t save_restore_gpu_addr;
870 volatile uint32_t *sr_ptr;
871 const u32 *reg_list;
872 u32 reg_list_size;
873 /* for clear state */
874 struct radeon_bo *clear_state_obj;
875 uint64_t clear_state_gpu_addr;
876 volatile uint32_t *cs_ptr;
877 const struct cs_section_def *cs_data;
878 u32 clear_state_size;
879 /* for cp tables */
880 struct radeon_bo *cp_table_obj;
881 uint64_t cp_table_gpu_addr;
882 volatile uint32_t *cp_table_ptr;
883 u32 cp_table_size;
884 };
885
886 int radeon_ib_get(struct radeon_device *rdev, int ring,
887 struct radeon_ib *ib, struct radeon_vm *vm,
888 unsigned size);
889 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
890 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
891 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
892 struct radeon_ib *const_ib);
893 int radeon_ib_pool_init(struct radeon_device *rdev);
894 void radeon_ib_pool_fini(struct radeon_device *rdev);
895 int radeon_ib_ring_tests(struct radeon_device *rdev);
896 /* Ring access between begin & end cannot sleep */
897 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
898 struct radeon_ring *ring);
899 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
900 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
901 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
902 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
903 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
904 void radeon_ring_undo(struct radeon_ring *ring);
905 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
906 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
907 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
908 void radeon_ring_lockup_update(struct radeon_ring *ring);
909 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
910 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
911 uint32_t **data);
912 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
913 unsigned size, uint32_t *data);
914 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
915 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
916 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
917 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
918
919
920 /* r600 async dma */
921 void r600_dma_stop(struct radeon_device *rdev);
922 int r600_dma_resume(struct radeon_device *rdev);
923 void r600_dma_fini(struct radeon_device *rdev);
924
925 void cayman_dma_stop(struct radeon_device *rdev);
926 int cayman_dma_resume(struct radeon_device *rdev);
927 void cayman_dma_fini(struct radeon_device *rdev);
928
929 /*
930 * CS.
931 */
932 struct radeon_cs_reloc {
933 struct drm_gem_object *gobj;
934 struct radeon_bo *robj;
935 struct radeon_bo_list lobj;
936 uint32_t handle;
937 uint32_t flags;
938 };
939
940 struct radeon_cs_chunk {
941 uint32_t chunk_id;
942 uint32_t length_dw;
943 int kpage_idx[2];
944 uint32_t *kpage[2];
945 uint32_t *kdata;
946 void __user *user_ptr;
947 int last_copied_page;
948 int last_page_index;
949 };
950
951 struct radeon_cs_parser {
952 struct device *dev;
953 struct radeon_device *rdev;
954 struct drm_file *filp;
955 /* chunks */
956 unsigned nchunks;
957 struct radeon_cs_chunk *chunks;
958 uint64_t *chunks_array;
959 /* IB */
960 unsigned idx;
961 /* relocations */
962 unsigned nrelocs;
963 struct radeon_cs_reloc *relocs;
964 struct radeon_cs_reloc **relocs_ptr;
965 struct list_head validated;
966 unsigned dma_reloc_idx;
967 /* indices of various chunks */
968 int chunk_ib_idx;
969 int chunk_relocs_idx;
970 int chunk_flags_idx;
971 int chunk_const_ib_idx;
972 struct radeon_ib ib;
973 struct radeon_ib const_ib;
974 void *track;
975 unsigned family;
976 int parser_error;
977 u32 cs_flags;
978 u32 ring;
979 s32 priority;
980 struct ww_acquire_ctx ticket;
981 };
982
983 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
984 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
985
986 struct radeon_cs_packet {
987 unsigned idx;
988 unsigned type;
989 unsigned reg;
990 unsigned opcode;
991 int count;
992 unsigned one_reg_wr;
993 };
994
995 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
996 struct radeon_cs_packet *pkt,
997 unsigned idx, unsigned reg);
998 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
999 struct radeon_cs_packet *pkt);
1000
1001
1002 /*
1003 * AGP
1004 */
1005 int radeon_agp_init(struct radeon_device *rdev);
1006 void radeon_agp_resume(struct radeon_device *rdev);
1007 void radeon_agp_suspend(struct radeon_device *rdev);
1008 void radeon_agp_fini(struct radeon_device *rdev);
1009
1010
1011 /*
1012 * Writeback
1013 */
1014 struct radeon_wb {
1015 struct radeon_bo *wb_obj;
1016 volatile uint32_t *wb;
1017 uint64_t gpu_addr;
1018 bool enabled;
1019 bool use_event;
1020 };
1021
1022 #define RADEON_WB_SCRATCH_OFFSET 0
1023 #define RADEON_WB_RING0_NEXT_RPTR 256
1024 #define RADEON_WB_CP_RPTR_OFFSET 1024
1025 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1026 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1027 #define R600_WB_DMA_RPTR_OFFSET 1792
1028 #define R600_WB_IH_WPTR_OFFSET 2048
1029 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1030 #define R600_WB_UVD_RPTR_OFFSET 2560
1031 #define R600_WB_EVENT_OFFSET 3072
1032 #define CIK_WB_CP1_WPTR_OFFSET 3328
1033 #define CIK_WB_CP2_WPTR_OFFSET 3584
1034
1035 /**
1036 * struct radeon_pm - power management datas
1037 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1038 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1039 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1040 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1041 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1042 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1043 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1044 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1045 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1046 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1047 * @needed_bandwidth: current bandwidth needs
1048 *
1049 * It keeps track of various data needed to take powermanagement decision.
1050 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1051 * Equation between gpu/memory clock and available bandwidth is hw dependent
1052 * (type of memory, bus size, efficiency, ...)
1053 */
1054
1055 enum radeon_pm_method {
1056 PM_METHOD_PROFILE,
1057 PM_METHOD_DYNPM,
1058 PM_METHOD_DPM,
1059 };
1060
1061 enum radeon_dynpm_state {
1062 DYNPM_STATE_DISABLED,
1063 DYNPM_STATE_MINIMUM,
1064 DYNPM_STATE_PAUSED,
1065 DYNPM_STATE_ACTIVE,
1066 DYNPM_STATE_SUSPENDED,
1067 };
1068 enum radeon_dynpm_action {
1069 DYNPM_ACTION_NONE,
1070 DYNPM_ACTION_MINIMUM,
1071 DYNPM_ACTION_DOWNCLOCK,
1072 DYNPM_ACTION_UPCLOCK,
1073 DYNPM_ACTION_DEFAULT
1074 };
1075
1076 enum radeon_voltage_type {
1077 VOLTAGE_NONE = 0,
1078 VOLTAGE_GPIO,
1079 VOLTAGE_VDDC,
1080 VOLTAGE_SW
1081 };
1082
1083 enum radeon_pm_state_type {
1084 /* not used for dpm */
1085 POWER_STATE_TYPE_DEFAULT,
1086 POWER_STATE_TYPE_POWERSAVE,
1087 /* user selectable states */
1088 POWER_STATE_TYPE_BATTERY,
1089 POWER_STATE_TYPE_BALANCED,
1090 POWER_STATE_TYPE_PERFORMANCE,
1091 /* internal states */
1092 POWER_STATE_TYPE_INTERNAL_UVD,
1093 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1094 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1095 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1096 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1097 POWER_STATE_TYPE_INTERNAL_BOOT,
1098 POWER_STATE_TYPE_INTERNAL_THERMAL,
1099 POWER_STATE_TYPE_INTERNAL_ACPI,
1100 POWER_STATE_TYPE_INTERNAL_ULV,
1101 POWER_STATE_TYPE_INTERNAL_3DPERF,
1102 };
1103
1104 enum radeon_pm_profile_type {
1105 PM_PROFILE_DEFAULT,
1106 PM_PROFILE_AUTO,
1107 PM_PROFILE_LOW,
1108 PM_PROFILE_MID,
1109 PM_PROFILE_HIGH,
1110 };
1111
1112 #define PM_PROFILE_DEFAULT_IDX 0
1113 #define PM_PROFILE_LOW_SH_IDX 1
1114 #define PM_PROFILE_MID_SH_IDX 2
1115 #define PM_PROFILE_HIGH_SH_IDX 3
1116 #define PM_PROFILE_LOW_MH_IDX 4
1117 #define PM_PROFILE_MID_MH_IDX 5
1118 #define PM_PROFILE_HIGH_MH_IDX 6
1119 #define PM_PROFILE_MAX 7
1120
1121 struct radeon_pm_profile {
1122 int dpms_off_ps_idx;
1123 int dpms_on_ps_idx;
1124 int dpms_off_cm_idx;
1125 int dpms_on_cm_idx;
1126 };
1127
1128 enum radeon_int_thermal_type {
1129 THERMAL_TYPE_NONE,
1130 THERMAL_TYPE_EXTERNAL,
1131 THERMAL_TYPE_EXTERNAL_GPIO,
1132 THERMAL_TYPE_RV6XX,
1133 THERMAL_TYPE_RV770,
1134 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1135 THERMAL_TYPE_EVERGREEN,
1136 THERMAL_TYPE_SUMO,
1137 THERMAL_TYPE_NI,
1138 THERMAL_TYPE_SI,
1139 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1140 THERMAL_TYPE_CI,
1141 THERMAL_TYPE_KV,
1142 };
1143
1144 struct radeon_voltage {
1145 enum radeon_voltage_type type;
1146 /* gpio voltage */
1147 struct radeon_gpio_rec gpio;
1148 u32 delay; /* delay in usec from voltage drop to sclk change */
1149 bool active_high; /* voltage drop is active when bit is high */
1150 /* VDDC voltage */
1151 u8 vddc_id; /* index into vddc voltage table */
1152 u8 vddci_id; /* index into vddci voltage table */
1153 bool vddci_enabled;
1154 /* r6xx+ sw */
1155 u16 voltage;
1156 /* evergreen+ vddci */
1157 u16 vddci;
1158 };
1159
1160 /* clock mode flags */
1161 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1162
1163 struct radeon_pm_clock_info {
1164 /* memory clock */
1165 u32 mclk;
1166 /* engine clock */
1167 u32 sclk;
1168 /* voltage info */
1169 struct radeon_voltage voltage;
1170 /* standardized clock flags */
1171 u32 flags;
1172 };
1173
1174 /* state flags */
1175 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1176
1177 struct radeon_power_state {
1178 enum radeon_pm_state_type type;
1179 struct radeon_pm_clock_info *clock_info;
1180 /* number of valid clock modes in this power state */
1181 int num_clock_modes;
1182 struct radeon_pm_clock_info *default_clock_mode;
1183 /* standardized state flags */
1184 u32 flags;
1185 u32 misc; /* vbios specific flags */
1186 u32 misc2; /* vbios specific flags */
1187 int pcie_lanes; /* pcie lanes */
1188 };
1189
1190 /*
1191 * Some modes are overclocked by very low value, accept them
1192 */
1193 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1194
1195 enum radeon_dpm_auto_throttle_src {
1196 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1197 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1198 };
1199
1200 enum radeon_dpm_event_src {
1201 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1202 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1203 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1204 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1205 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1206 };
1207
1208 struct radeon_ps {
1209 u32 caps; /* vbios flags */
1210 u32 class; /* vbios flags */
1211 u32 class2; /* vbios flags */
1212 /* UVD clocks */
1213 u32 vclk;
1214 u32 dclk;
1215 /* VCE clocks */
1216 u32 evclk;
1217 u32 ecclk;
1218 /* asic priv */
1219 void *ps_priv;
1220 };
1221
1222 struct radeon_dpm_thermal {
1223 /* thermal interrupt work */
1224 struct work_struct work;
1225 /* low temperature threshold */
1226 int min_temp;
1227 /* high temperature threshold */
1228 int max_temp;
1229 /* was interrupt low to high or high to low */
1230 bool high_to_low;
1231 };
1232
1233 enum radeon_clk_action
1234 {
1235 RADEON_SCLK_UP = 1,
1236 RADEON_SCLK_DOWN
1237 };
1238
1239 struct radeon_blacklist_clocks
1240 {
1241 u32 sclk;
1242 u32 mclk;
1243 enum radeon_clk_action action;
1244 };
1245
1246 struct radeon_clock_and_voltage_limits {
1247 u32 sclk;
1248 u32 mclk;
1249 u32 vddc;
1250 u32 vddci;
1251 };
1252
1253 struct radeon_clock_array {
1254 u32 count;
1255 u32 *values;
1256 };
1257
1258 struct radeon_clock_voltage_dependency_entry {
1259 u32 clk;
1260 u16 v;
1261 };
1262
1263 struct radeon_clock_voltage_dependency_table {
1264 u32 count;
1265 struct radeon_clock_voltage_dependency_entry *entries;
1266 };
1267
1268 union radeon_cac_leakage_entry {
1269 struct {
1270 u16 vddc;
1271 u32 leakage;
1272 };
1273 struct {
1274 u16 vddc1;
1275 u16 vddc2;
1276 u16 vddc3;
1277 };
1278 };
1279
1280 struct radeon_cac_leakage_table {
1281 u32 count;
1282 union radeon_cac_leakage_entry *entries;
1283 };
1284
1285 struct radeon_phase_shedding_limits_entry {
1286 u16 voltage;
1287 u32 sclk;
1288 u32 mclk;
1289 };
1290
1291 struct radeon_phase_shedding_limits_table {
1292 u32 count;
1293 struct radeon_phase_shedding_limits_entry *entries;
1294 };
1295
1296 struct radeon_uvd_clock_voltage_dependency_entry {
1297 u32 vclk;
1298 u32 dclk;
1299 u16 v;
1300 };
1301
1302 struct radeon_uvd_clock_voltage_dependency_table {
1303 u8 count;
1304 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1305 };
1306
1307 struct radeon_vce_clock_voltage_dependency_entry {
1308 u32 ecclk;
1309 u32 evclk;
1310 u16 v;
1311 };
1312
1313 struct radeon_vce_clock_voltage_dependency_table {
1314 u8 count;
1315 struct radeon_vce_clock_voltage_dependency_entry *entries;
1316 };
1317
1318 struct radeon_ppm_table {
1319 u8 ppm_design;
1320 u16 cpu_core_number;
1321 u32 platform_tdp;
1322 u32 small_ac_platform_tdp;
1323 u32 platform_tdc;
1324 u32 small_ac_platform_tdc;
1325 u32 apu_tdp;
1326 u32 dgpu_tdp;
1327 u32 dgpu_ulv_power;
1328 u32 tj_max;
1329 };
1330
1331 struct radeon_cac_tdp_table {
1332 u16 tdp;
1333 u16 configurable_tdp;
1334 u16 tdc;
1335 u16 battery_power_limit;
1336 u16 small_power_limit;
1337 u16 low_cac_leakage;
1338 u16 high_cac_leakage;
1339 u16 maximum_power_delivery_limit;
1340 };
1341
1342 struct radeon_dpm_dynamic_state {
1343 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1344 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1345 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1346 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1347 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1348 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1349 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1350 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1351 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1352 struct radeon_clock_array valid_sclk_values;
1353 struct radeon_clock_array valid_mclk_values;
1354 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1355 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1356 u32 mclk_sclk_ratio;
1357 u32 sclk_mclk_delta;
1358 u16 vddc_vddci_delta;
1359 u16 min_vddc_for_pcie_gen2;
1360 struct radeon_cac_leakage_table cac_leakage_table;
1361 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1362 struct radeon_ppm_table *ppm_table;
1363 struct radeon_cac_tdp_table *cac_tdp_table;
1364 };
1365
1366 struct radeon_dpm_fan {
1367 u16 t_min;
1368 u16 t_med;
1369 u16 t_high;
1370 u16 pwm_min;
1371 u16 pwm_med;
1372 u16 pwm_high;
1373 u8 t_hyst;
1374 u32 cycle_delay;
1375 u16 t_max;
1376 bool ucode_fan_control;
1377 };
1378
1379 enum radeon_pcie_gen {
1380 RADEON_PCIE_GEN1 = 0,
1381 RADEON_PCIE_GEN2 = 1,
1382 RADEON_PCIE_GEN3 = 2,
1383 RADEON_PCIE_GEN_INVALID = 0xffff
1384 };
1385
1386 enum radeon_dpm_forced_level {
1387 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1388 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1389 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1390 };
1391
1392 struct radeon_dpm {
1393 struct radeon_ps *ps;
1394 /* number of valid power states */
1395 int num_ps;
1396 /* current power state that is active */
1397 struct radeon_ps *current_ps;
1398 /* requested power state */
1399 struct radeon_ps *requested_ps;
1400 /* boot up power state */
1401 struct radeon_ps *boot_ps;
1402 /* default uvd power state */
1403 struct radeon_ps *uvd_ps;
1404 enum radeon_pm_state_type state;
1405 enum radeon_pm_state_type user_state;
1406 u32 platform_caps;
1407 u32 voltage_response_time;
1408 u32 backbias_response_time;
1409 void *priv;
1410 u32 new_active_crtcs;
1411 int new_active_crtc_count;
1412 u32 current_active_crtcs;
1413 int current_active_crtc_count;
1414 struct radeon_dpm_dynamic_state dyn_state;
1415 struct radeon_dpm_fan fan;
1416 u32 tdp_limit;
1417 u32 near_tdp_limit;
1418 u32 near_tdp_limit_adjusted;
1419 u32 sq_ramping_threshold;
1420 u32 cac_leakage;
1421 u16 tdp_od_limit;
1422 u32 tdp_adjustment;
1423 u16 load_line_slope;
1424 bool power_control;
1425 bool ac_power;
1426 /* special states active */
1427 bool thermal_active;
1428 bool uvd_active;
1429 /* thermal handling */
1430 struct radeon_dpm_thermal thermal;
1431 /* forced levels */
1432 enum radeon_dpm_forced_level forced_level;
1433 /* track UVD streams */
1434 unsigned sd;
1435 unsigned hd;
1436 };
1437
1438 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1439
1440 struct radeon_pm {
1441 struct mutex mutex;
1442 /* write locked while reprogramming mclk */
1443 struct rw_semaphore mclk_lock;
1444 u32 active_crtcs;
1445 int active_crtc_count;
1446 int req_vblank;
1447 bool vblank_sync;
1448 fixed20_12 max_bandwidth;
1449 fixed20_12 igp_sideport_mclk;
1450 fixed20_12 igp_system_mclk;
1451 fixed20_12 igp_ht_link_clk;
1452 fixed20_12 igp_ht_link_width;
1453 fixed20_12 k8_bandwidth;
1454 fixed20_12 sideport_bandwidth;
1455 fixed20_12 ht_bandwidth;
1456 fixed20_12 core_bandwidth;
1457 fixed20_12 sclk;
1458 fixed20_12 mclk;
1459 fixed20_12 needed_bandwidth;
1460 struct radeon_power_state *power_state;
1461 /* number of valid power states */
1462 int num_power_states;
1463 int current_power_state_index;
1464 int current_clock_mode_index;
1465 int requested_power_state_index;
1466 int requested_clock_mode_index;
1467 int default_power_state_index;
1468 u32 current_sclk;
1469 u32 current_mclk;
1470 u16 current_vddc;
1471 u16 current_vddci;
1472 u32 default_sclk;
1473 u32 default_mclk;
1474 u16 default_vddc;
1475 u16 default_vddci;
1476 struct radeon_i2c_chan *i2c_bus;
1477 /* selected pm method */
1478 enum radeon_pm_method pm_method;
1479 /* dynpm power management */
1480 struct delayed_work dynpm_idle_work;
1481 enum radeon_dynpm_state dynpm_state;
1482 enum radeon_dynpm_action dynpm_planned_action;
1483 unsigned long dynpm_action_timeout;
1484 bool dynpm_can_upclock;
1485 bool dynpm_can_downclock;
1486 /* profile-based power management */
1487 enum radeon_pm_profile_type profile;
1488 int profile_index;
1489 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1490 /* internal thermal controller on rv6xx+ */
1491 enum radeon_int_thermal_type int_thermal_type;
1492 struct device *int_hwmon_dev;
1493 /* dpm */
1494 bool dpm_enabled;
1495 struct radeon_dpm dpm;
1496 };
1497
1498 int radeon_pm_get_type_index(struct radeon_device *rdev,
1499 enum radeon_pm_state_type ps_type,
1500 int instance);
1501 /*
1502 * UVD
1503 */
1504 #define RADEON_MAX_UVD_HANDLES 10
1505 #define RADEON_UVD_STACK_SIZE (1024*1024)
1506 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1507
1508 struct radeon_uvd {
1509 struct radeon_bo *vcpu_bo;
1510 void *cpu_addr;
1511 uint64_t gpu_addr;
1512 void *saved_bo;
1513 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1514 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1515 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1516 struct delayed_work idle_work;
1517 };
1518
1519 int radeon_uvd_init(struct radeon_device *rdev);
1520 void radeon_uvd_fini(struct radeon_device *rdev);
1521 int radeon_uvd_suspend(struct radeon_device *rdev);
1522 int radeon_uvd_resume(struct radeon_device *rdev);
1523 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1524 uint32_t handle, struct radeon_fence **fence);
1525 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1526 uint32_t handle, struct radeon_fence **fence);
1527 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1528 void radeon_uvd_free_handles(struct radeon_device *rdev,
1529 struct drm_file *filp);
1530 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1531 void radeon_uvd_note_usage(struct radeon_device *rdev);
1532 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1533 unsigned vclk, unsigned dclk,
1534 unsigned vco_min, unsigned vco_max,
1535 unsigned fb_factor, unsigned fb_mask,
1536 unsigned pd_min, unsigned pd_max,
1537 unsigned pd_even,
1538 unsigned *optimal_fb_div,
1539 unsigned *optimal_vclk_div,
1540 unsigned *optimal_dclk_div);
1541 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1542 unsigned cg_upll_func_cntl);
1543
1544 struct r600_audio {
1545 int channels;
1546 int rate;
1547 int bits_per_sample;
1548 u8 status_bits;
1549 u8 category_code;
1550 };
1551
1552 /*
1553 * Benchmarking
1554 */
1555 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1556
1557
1558 /*
1559 * Testing
1560 */
1561 void radeon_test_moves(struct radeon_device *rdev);
1562 void radeon_test_ring_sync(struct radeon_device *rdev,
1563 struct radeon_ring *cpA,
1564 struct radeon_ring *cpB);
1565 void radeon_test_syncing(struct radeon_device *rdev);
1566
1567
1568 /*
1569 * Debugfs
1570 */
1571 struct radeon_debugfs {
1572 struct drm_info_list *files;
1573 unsigned num_files;
1574 };
1575
1576 int radeon_debugfs_add_files(struct radeon_device *rdev,
1577 struct drm_info_list *files,
1578 unsigned nfiles);
1579 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1580
1581 /*
1582 * ASIC ring specific functions.
1583 */
1584 struct radeon_asic_ring {
1585 /* ring read/write ptr handling */
1586 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1587 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1588 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1589
1590 /* validating and patching of IBs */
1591 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1592 int (*cs_parse)(struct radeon_cs_parser *p);
1593
1594 /* command emmit functions */
1595 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1596 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1597 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1598 struct radeon_semaphore *semaphore, bool emit_wait);
1599 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1600
1601 /* testing functions */
1602 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1603 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1604 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1605
1606 /* deprecated */
1607 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1608 };
1609
1610 /*
1611 * ASIC specific functions.
1612 */
1613 struct radeon_asic {
1614 int (*init)(struct radeon_device *rdev);
1615 void (*fini)(struct radeon_device *rdev);
1616 int (*resume)(struct radeon_device *rdev);
1617 int (*suspend)(struct radeon_device *rdev);
1618 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1619 int (*asic_reset)(struct radeon_device *rdev);
1620 /* ioctl hw specific callback. Some hw might want to perform special
1621 * operation on specific ioctl. For instance on wait idle some hw
1622 * might want to perform and HDP flush through MMIO as it seems that
1623 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1624 * through ring.
1625 */
1626 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1627 /* check if 3D engine is idle */
1628 bool (*gui_idle)(struct radeon_device *rdev);
1629 /* wait for mc_idle */
1630 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1631 /* get the reference clock */
1632 u32 (*get_xclk)(struct radeon_device *rdev);
1633 /* get the gpu clock counter */
1634 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1635 /* gart */
1636 struct {
1637 void (*tlb_flush)(struct radeon_device *rdev);
1638 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1639 } gart;
1640 struct {
1641 int (*init)(struct radeon_device *rdev);
1642 void (*fini)(struct radeon_device *rdev);
1643
1644 u32 pt_ring_index;
1645 void (*set_page)(struct radeon_device *rdev,
1646 struct radeon_ib *ib,
1647 uint64_t pe,
1648 uint64_t addr, unsigned count,
1649 uint32_t incr, uint32_t flags);
1650 } vm;
1651 /* ring specific callbacks */
1652 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1653 /* irqs */
1654 struct {
1655 int (*set)(struct radeon_device *rdev);
1656 int (*process)(struct radeon_device *rdev);
1657 } irq;
1658 /* displays */
1659 struct {
1660 /* display watermarks */
1661 void (*bandwidth_update)(struct radeon_device *rdev);
1662 /* get frame count */
1663 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1664 /* wait for vblank */
1665 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1666 /* set backlight level */
1667 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1668 /* get backlight level */
1669 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1670 /* audio callbacks */
1671 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1672 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1673 } display;
1674 /* copy functions for bo handling */
1675 struct {
1676 int (*blit)(struct radeon_device *rdev,
1677 uint64_t src_offset,
1678 uint64_t dst_offset,
1679 unsigned num_gpu_pages,
1680 struct radeon_fence **fence);
1681 u32 blit_ring_index;
1682 int (*dma)(struct radeon_device *rdev,
1683 uint64_t src_offset,
1684 uint64_t dst_offset,
1685 unsigned num_gpu_pages,
1686 struct radeon_fence **fence);
1687 u32 dma_ring_index;
1688 /* method used for bo copy */
1689 int (*copy)(struct radeon_device *rdev,
1690 uint64_t src_offset,
1691 uint64_t dst_offset,
1692 unsigned num_gpu_pages,
1693 struct radeon_fence **fence);
1694 /* ring used for bo copies */
1695 u32 copy_ring_index;
1696 } copy;
1697 /* surfaces */
1698 struct {
1699 int (*set_reg)(struct radeon_device *rdev, int reg,
1700 uint32_t tiling_flags, uint32_t pitch,
1701 uint32_t offset, uint32_t obj_size);
1702 void (*clear_reg)(struct radeon_device *rdev, int reg);
1703 } surface;
1704 /* hotplug detect */
1705 struct {
1706 void (*init)(struct radeon_device *rdev);
1707 void (*fini)(struct radeon_device *rdev);
1708 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1709 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1710 } hpd;
1711 /* static power management */
1712 struct {
1713 void (*misc)(struct radeon_device *rdev);
1714 void (*prepare)(struct radeon_device *rdev);
1715 void (*finish)(struct radeon_device *rdev);
1716 void (*init_profile)(struct radeon_device *rdev);
1717 void (*get_dynpm_state)(struct radeon_device *rdev);
1718 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1719 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1720 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1721 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1722 int (*get_pcie_lanes)(struct radeon_device *rdev);
1723 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1724 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1725 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1726 int (*get_temperature)(struct radeon_device *rdev);
1727 } pm;
1728 /* dynamic power management */
1729 struct {
1730 int (*init)(struct radeon_device *rdev);
1731 void (*setup_asic)(struct radeon_device *rdev);
1732 int (*enable)(struct radeon_device *rdev);
1733 void (*disable)(struct radeon_device *rdev);
1734 int (*pre_set_power_state)(struct radeon_device *rdev);
1735 int (*set_power_state)(struct radeon_device *rdev);
1736 void (*post_set_power_state)(struct radeon_device *rdev);
1737 void (*display_configuration_changed)(struct radeon_device *rdev);
1738 void (*fini)(struct radeon_device *rdev);
1739 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1740 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1741 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1742 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1743 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1744 bool (*vblank_too_short)(struct radeon_device *rdev);
1745 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1746 } dpm;
1747 /* pageflipping */
1748 struct {
1749 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1750 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1751 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1752 } pflip;
1753 };
1754
1755 /*
1756 * Asic structures
1757 */
1758 struct r100_asic {
1759 const unsigned *reg_safe_bm;
1760 unsigned reg_safe_bm_size;
1761 u32 hdp_cntl;
1762 };
1763
1764 struct r300_asic {
1765 const unsigned *reg_safe_bm;
1766 unsigned reg_safe_bm_size;
1767 u32 resync_scratch;
1768 u32 hdp_cntl;
1769 };
1770
1771 struct r600_asic {
1772 unsigned max_pipes;
1773 unsigned max_tile_pipes;
1774 unsigned max_simds;
1775 unsigned max_backends;
1776 unsigned max_gprs;
1777 unsigned max_threads;
1778 unsigned max_stack_entries;
1779 unsigned max_hw_contexts;
1780 unsigned max_gs_threads;
1781 unsigned sx_max_export_size;
1782 unsigned sx_max_export_pos_size;
1783 unsigned sx_max_export_smx_size;
1784 unsigned sq_num_cf_insts;
1785 unsigned tiling_nbanks;
1786 unsigned tiling_npipes;
1787 unsigned tiling_group_size;
1788 unsigned tile_config;
1789 unsigned backend_map;
1790 };
1791
1792 struct rv770_asic {
1793 unsigned max_pipes;
1794 unsigned max_tile_pipes;
1795 unsigned max_simds;
1796 unsigned max_backends;
1797 unsigned max_gprs;
1798 unsigned max_threads;
1799 unsigned max_stack_entries;
1800 unsigned max_hw_contexts;
1801 unsigned max_gs_threads;
1802 unsigned sx_max_export_size;
1803 unsigned sx_max_export_pos_size;
1804 unsigned sx_max_export_smx_size;
1805 unsigned sq_num_cf_insts;
1806 unsigned sx_num_of_sets;
1807 unsigned sc_prim_fifo_size;
1808 unsigned sc_hiz_tile_fifo_size;
1809 unsigned sc_earlyz_tile_fifo_fize;
1810 unsigned tiling_nbanks;
1811 unsigned tiling_npipes;
1812 unsigned tiling_group_size;
1813 unsigned tile_config;
1814 unsigned backend_map;
1815 };
1816
1817 struct evergreen_asic {
1818 unsigned num_ses;
1819 unsigned max_pipes;
1820 unsigned max_tile_pipes;
1821 unsigned max_simds;
1822 unsigned max_backends;
1823 unsigned max_gprs;
1824 unsigned max_threads;
1825 unsigned max_stack_entries;
1826 unsigned max_hw_contexts;
1827 unsigned max_gs_threads;
1828 unsigned sx_max_export_size;
1829 unsigned sx_max_export_pos_size;
1830 unsigned sx_max_export_smx_size;
1831 unsigned sq_num_cf_insts;
1832 unsigned sx_num_of_sets;
1833 unsigned sc_prim_fifo_size;
1834 unsigned sc_hiz_tile_fifo_size;
1835 unsigned sc_earlyz_tile_fifo_size;
1836 unsigned tiling_nbanks;
1837 unsigned tiling_npipes;
1838 unsigned tiling_group_size;
1839 unsigned tile_config;
1840 unsigned backend_map;
1841 };
1842
1843 struct cayman_asic {
1844 unsigned max_shader_engines;
1845 unsigned max_pipes_per_simd;
1846 unsigned max_tile_pipes;
1847 unsigned max_simds_per_se;
1848 unsigned max_backends_per_se;
1849 unsigned max_texture_channel_caches;
1850 unsigned max_gprs;
1851 unsigned max_threads;
1852 unsigned max_gs_threads;
1853 unsigned max_stack_entries;
1854 unsigned sx_num_of_sets;
1855 unsigned sx_max_export_size;
1856 unsigned sx_max_export_pos_size;
1857 unsigned sx_max_export_smx_size;
1858 unsigned max_hw_contexts;
1859 unsigned sq_num_cf_insts;
1860 unsigned sc_prim_fifo_size;
1861 unsigned sc_hiz_tile_fifo_size;
1862 unsigned sc_earlyz_tile_fifo_size;
1863
1864 unsigned num_shader_engines;
1865 unsigned num_shader_pipes_per_simd;
1866 unsigned num_tile_pipes;
1867 unsigned num_simds_per_se;
1868 unsigned num_backends_per_se;
1869 unsigned backend_disable_mask_per_asic;
1870 unsigned backend_map;
1871 unsigned num_texture_channel_caches;
1872 unsigned mem_max_burst_length_bytes;
1873 unsigned mem_row_size_in_kb;
1874 unsigned shader_engine_tile_size;
1875 unsigned num_gpus;
1876 unsigned multi_gpu_tile_size;
1877
1878 unsigned tile_config;
1879 };
1880
1881 struct si_asic {
1882 unsigned max_shader_engines;
1883 unsigned max_tile_pipes;
1884 unsigned max_cu_per_sh;
1885 unsigned max_sh_per_se;
1886 unsigned max_backends_per_se;
1887 unsigned max_texture_channel_caches;
1888 unsigned max_gprs;
1889 unsigned max_gs_threads;
1890 unsigned max_hw_contexts;
1891 unsigned sc_prim_fifo_size_frontend;
1892 unsigned sc_prim_fifo_size_backend;
1893 unsigned sc_hiz_tile_fifo_size;
1894 unsigned sc_earlyz_tile_fifo_size;
1895
1896 unsigned num_tile_pipes;
1897 unsigned num_backends_per_se;
1898 unsigned backend_disable_mask_per_asic;
1899 unsigned backend_map;
1900 unsigned num_texture_channel_caches;
1901 unsigned mem_max_burst_length_bytes;
1902 unsigned mem_row_size_in_kb;
1903 unsigned shader_engine_tile_size;
1904 unsigned num_gpus;
1905 unsigned multi_gpu_tile_size;
1906
1907 unsigned tile_config;
1908 uint32_t tile_mode_array[32];
1909 };
1910
1911 struct cik_asic {
1912 unsigned max_shader_engines;
1913 unsigned max_tile_pipes;
1914 unsigned max_cu_per_sh;
1915 unsigned max_sh_per_se;
1916 unsigned max_backends_per_se;
1917 unsigned max_texture_channel_caches;
1918 unsigned max_gprs;
1919 unsigned max_gs_threads;
1920 unsigned max_hw_contexts;
1921 unsigned sc_prim_fifo_size_frontend;
1922 unsigned sc_prim_fifo_size_backend;
1923 unsigned sc_hiz_tile_fifo_size;
1924 unsigned sc_earlyz_tile_fifo_size;
1925
1926 unsigned num_tile_pipes;
1927 unsigned num_backends_per_se;
1928 unsigned backend_disable_mask_per_asic;
1929 unsigned backend_map;
1930 unsigned num_texture_channel_caches;
1931 unsigned mem_max_burst_length_bytes;
1932 unsigned mem_row_size_in_kb;
1933 unsigned shader_engine_tile_size;
1934 unsigned num_gpus;
1935 unsigned multi_gpu_tile_size;
1936
1937 unsigned tile_config;
1938 uint32_t tile_mode_array[32];
1939 };
1940
1941 union radeon_asic_config {
1942 struct r300_asic r300;
1943 struct r100_asic r100;
1944 struct r600_asic r600;
1945 struct rv770_asic rv770;
1946 struct evergreen_asic evergreen;
1947 struct cayman_asic cayman;
1948 struct si_asic si;
1949 struct cik_asic cik;
1950 };
1951
1952 /*
1953 * asic initizalization from radeon_asic.c
1954 */
1955 void radeon_agp_disable(struct radeon_device *rdev);
1956 int radeon_asic_init(struct radeon_device *rdev);
1957
1958
1959 /*
1960 * IOCTL.
1961 */
1962 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1963 struct drm_file *filp);
1964 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *filp);
1966 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1967 struct drm_file *file_priv);
1968 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1969 struct drm_file *file_priv);
1970 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1971 struct drm_file *file_priv);
1972 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1973 struct drm_file *file_priv);
1974 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1975 struct drm_file *filp);
1976 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1977 struct drm_file *filp);
1978 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1979 struct drm_file *filp);
1980 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1981 struct drm_file *filp);
1982 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1983 struct drm_file *filp);
1984 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1985 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1986 struct drm_file *filp);
1987 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1988 struct drm_file *filp);
1989
1990 /* VRAM scratch page for HDP bug, default vram page */
1991 struct r600_vram_scratch {
1992 struct radeon_bo *robj;
1993 volatile uint32_t *ptr;
1994 u64 gpu_addr;
1995 };
1996
1997 /*
1998 * ACPI
1999 */
2000 struct radeon_atif_notification_cfg {
2001 bool enabled;
2002 int command_code;
2003 };
2004
2005 struct radeon_atif_notifications {
2006 bool display_switch;
2007 bool expansion_mode_change;
2008 bool thermal_state;
2009 bool forced_power_state;
2010 bool system_power_state;
2011 bool display_conf_change;
2012 bool px_gfx_switch;
2013 bool brightness_change;
2014 bool dgpu_display_event;
2015 };
2016
2017 struct radeon_atif_functions {
2018 bool system_params;
2019 bool sbios_requests;
2020 bool select_active_disp;
2021 bool lid_state;
2022 bool get_tv_standard;
2023 bool set_tv_standard;
2024 bool get_panel_expansion_mode;
2025 bool set_panel_expansion_mode;
2026 bool temperature_change;
2027 bool graphics_device_types;
2028 };
2029
2030 struct radeon_atif {
2031 struct radeon_atif_notifications notifications;
2032 struct radeon_atif_functions functions;
2033 struct radeon_atif_notification_cfg notification_cfg;
2034 struct radeon_encoder *encoder_for_bl;
2035 };
2036
2037 struct radeon_atcs_functions {
2038 bool get_ext_state;
2039 bool pcie_perf_req;
2040 bool pcie_dev_rdy;
2041 bool pcie_bus_width;
2042 };
2043
2044 struct radeon_atcs {
2045 struct radeon_atcs_functions functions;
2046 };
2047
2048 /*
2049 * Core structure, functions and helpers.
2050 */
2051 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2052 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2053
2054 struct radeon_device {
2055 struct device *dev;
2056 struct drm_device *ddev;
2057 struct pci_dev *pdev;
2058 struct rw_semaphore exclusive_lock;
2059 /* ASIC */
2060 union radeon_asic_config config;
2061 enum radeon_family family;
2062 unsigned long flags;
2063 int usec_timeout;
2064 enum radeon_pll_errata pll_errata;
2065 int num_gb_pipes;
2066 int num_z_pipes;
2067 int disp_priority;
2068 /* BIOS */
2069 uint8_t *bios;
2070 bool is_atom_bios;
2071 uint16_t bios_header_start;
2072 struct radeon_bo *stollen_vga_memory;
2073 /* Register mmio */
2074 resource_size_t rmmio_base;
2075 resource_size_t rmmio_size;
2076 /* protects concurrent MM_INDEX/DATA based register access */
2077 spinlock_t mmio_idx_lock;
2078 void __iomem *rmmio;
2079 radeon_rreg_t mc_rreg;
2080 radeon_wreg_t mc_wreg;
2081 radeon_rreg_t pll_rreg;
2082 radeon_wreg_t pll_wreg;
2083 uint32_t pcie_reg_mask;
2084 radeon_rreg_t pciep_rreg;
2085 radeon_wreg_t pciep_wreg;
2086 /* io port */
2087 void __iomem *rio_mem;
2088 resource_size_t rio_mem_size;
2089 struct radeon_clock clock;
2090 struct radeon_mc mc;
2091 struct radeon_gart gart;
2092 struct radeon_mode_info mode_info;
2093 struct radeon_scratch scratch;
2094 struct radeon_doorbell doorbell;
2095 struct radeon_mman mman;
2096 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2097 wait_queue_head_t fence_queue;
2098 struct mutex ring_lock;
2099 struct radeon_ring ring[RADEON_NUM_RINGS];
2100 bool ib_pool_ready;
2101 struct radeon_sa_manager ring_tmp_bo;
2102 struct radeon_irq irq;
2103 struct radeon_asic *asic;
2104 struct radeon_gem gem;
2105 struct radeon_pm pm;
2106 struct radeon_uvd uvd;
2107 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2108 struct radeon_wb wb;
2109 struct radeon_dummy_page dummy_page;
2110 bool shutdown;
2111 bool suspend;
2112 bool need_dma32;
2113 bool accel_working;
2114 bool fastfb_working; /* IGP feature*/
2115 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2116 const struct firmware *me_fw; /* all family ME firmware */
2117 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2118 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2119 const struct firmware *mc_fw; /* NI MC firmware */
2120 const struct firmware *ce_fw; /* SI CE firmware */
2121 const struct firmware *mec_fw; /* CIK MEC firmware */
2122 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2123 const struct firmware *smc_fw; /* SMC firmware */
2124 const struct firmware *uvd_fw; /* UVD firmware */
2125 struct r600_vram_scratch vram_scratch;
2126 int msi_enabled; /* msi enabled */
2127 struct r600_ih ih; /* r6/700 interrupt ring */
2128 struct radeon_rlc rlc;
2129 struct radeon_mec mec;
2130 struct work_struct hotplug_work;
2131 struct work_struct audio_work;
2132 struct work_struct reset_work;
2133 int num_crtc; /* number of crtcs */
2134 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2135 bool audio_enabled;
2136 bool has_uvd;
2137 struct r600_audio audio_status; /* audio stuff */
2138 struct notifier_block acpi_nb;
2139 /* only one userspace can use Hyperz features or CMASK at a time */
2140 struct drm_file *hyperz_filp;
2141 struct drm_file *cmask_filp;
2142 /* i2c buses */
2143 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2144 /* debugfs */
2145 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2146 unsigned debugfs_count;
2147 /* virtual memory */
2148 struct radeon_vm_manager vm_manager;
2149 struct mutex gpu_clock_mutex;
2150 /* ACPI interface */
2151 struct radeon_atif atif;
2152 struct radeon_atcs atcs;
2153 /* srbm instance registers */
2154 struct mutex srbm_mutex;
2155 };
2156
2157 int radeon_device_init(struct radeon_device *rdev,
2158 struct drm_device *ddev,
2159 struct pci_dev *pdev,
2160 uint32_t flags);
2161 void radeon_device_fini(struct radeon_device *rdev);
2162 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2163
2164 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2165 bool always_indirect);
2166 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2167 bool always_indirect);
2168 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2169 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2170
2171 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2172 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2173
2174 /*
2175 * Cast helper
2176 */
2177 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2178
2179 /*
2180 * Registers read & write functions.
2181 */
2182 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2183 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2184 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2185 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2186 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2187 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2188 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2189 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2190 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2191 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2192 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2193 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2194 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2195 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2196 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2197 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2198 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2199 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2200 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2201 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2202 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2203 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2204 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2205 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2206 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2207 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2208 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2209 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2210 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2211 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2212 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2213 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2214 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2215 #define WREG32_P(reg, val, mask) \
2216 do { \
2217 uint32_t tmp_ = RREG32(reg); \
2218 tmp_ &= (mask); \
2219 tmp_ |= ((val) & ~(mask)); \
2220 WREG32(reg, tmp_); \
2221 } while (0)
2222 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2223 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2224 #define WREG32_PLL_P(reg, val, mask) \
2225 do { \
2226 uint32_t tmp_ = RREG32_PLL(reg); \
2227 tmp_ &= (mask); \
2228 tmp_ |= ((val) & ~(mask)); \
2229 WREG32_PLL(reg, tmp_); \
2230 } while (0)
2231 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2232 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2233 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2234
2235 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2236 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2237
2238 /*
2239 * Indirect registers accessor
2240 */
2241 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2242 {
2243 uint32_t r;
2244
2245 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2246 r = RREG32(RADEON_PCIE_DATA);
2247 return r;
2248 }
2249
2250 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2251 {
2252 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2253 WREG32(RADEON_PCIE_DATA, (v));
2254 }
2255
2256 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2257 {
2258 u32 r;
2259
2260 WREG32(TN_SMC_IND_INDEX_0, (reg));
2261 r = RREG32(TN_SMC_IND_DATA_0);
2262 return r;
2263 }
2264
2265 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2266 {
2267 WREG32(TN_SMC_IND_INDEX_0, (reg));
2268 WREG32(TN_SMC_IND_DATA_0, (v));
2269 }
2270
2271 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2272 {
2273 u32 r;
2274
2275 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2276 r = RREG32(R600_RCU_DATA);
2277 return r;
2278 }
2279
2280 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2281 {
2282 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2283 WREG32(R600_RCU_DATA, (v));
2284 }
2285
2286 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2287 {
2288 u32 r;
2289
2290 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2291 r = RREG32(EVERGREEN_CG_IND_DATA);
2292 return r;
2293 }
2294
2295 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2296 {
2297 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2298 WREG32(EVERGREEN_CG_IND_DATA, (v));
2299 }
2300
2301 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2302 {
2303 u32 r;
2304
2305 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2306 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2307 return r;
2308 }
2309
2310 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2311 {
2312 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2313 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2314 }
2315
2316 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2317 {
2318 u32 r;
2319
2320 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2321 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2322 return r;
2323 }
2324
2325 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2326 {
2327 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2328 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2329 }
2330
2331 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2332 {
2333 u32 r;
2334
2335 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2336 r = RREG32(R600_UVD_CTX_DATA);
2337 return r;
2338 }
2339
2340 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2341 {
2342 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2343 WREG32(R600_UVD_CTX_DATA, (v));
2344 }
2345
2346
2347 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2348 {
2349 u32 r;
2350
2351 WREG32(CIK_DIDT_IND_INDEX, (reg));
2352 r = RREG32(CIK_DIDT_IND_DATA);
2353 return r;
2354 }
2355
2356 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2357 {
2358 WREG32(CIK_DIDT_IND_INDEX, (reg));
2359 WREG32(CIK_DIDT_IND_DATA, (v));
2360 }
2361
2362 void r100_pll_errata_after_index(struct radeon_device *rdev);
2363
2364
2365 /*
2366 * ASICs helpers.
2367 */
2368 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2369 (rdev->pdev->device == 0x5969))
2370 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2371 (rdev->family == CHIP_RV200) || \
2372 (rdev->family == CHIP_RS100) || \
2373 (rdev->family == CHIP_RS200) || \
2374 (rdev->family == CHIP_RV250) || \
2375 (rdev->family == CHIP_RV280) || \
2376 (rdev->family == CHIP_RS300))
2377 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2378 (rdev->family == CHIP_RV350) || \
2379 (rdev->family == CHIP_R350) || \
2380 (rdev->family == CHIP_RV380) || \
2381 (rdev->family == CHIP_R420) || \
2382 (rdev->family == CHIP_R423) || \
2383 (rdev->family == CHIP_RV410) || \
2384 (rdev->family == CHIP_RS400) || \
2385 (rdev->family == CHIP_RS480))
2386 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2387 (rdev->ddev->pdev->device == 0x9443) || \
2388 (rdev->ddev->pdev->device == 0x944B) || \
2389 (rdev->ddev->pdev->device == 0x9506) || \
2390 (rdev->ddev->pdev->device == 0x9509) || \
2391 (rdev->ddev->pdev->device == 0x950F) || \
2392 (rdev->ddev->pdev->device == 0x689C) || \
2393 (rdev->ddev->pdev->device == 0x689D))
2394 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2395 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2396 (rdev->family == CHIP_RS690) || \
2397 (rdev->family == CHIP_RS740) || \
2398 (rdev->family >= CHIP_R600))
2399 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2400 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2401 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2402 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2403 (rdev->flags & RADEON_IS_IGP))
2404 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2405 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2406 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2407 (rdev->flags & RADEON_IS_IGP))
2408 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2409 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2410 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2411
2412 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2413 (rdev->ddev->pdev->device == 0x6850) || \
2414 (rdev->ddev->pdev->device == 0x6858) || \
2415 (rdev->ddev->pdev->device == 0x6859) || \
2416 (rdev->ddev->pdev->device == 0x6840) || \
2417 (rdev->ddev->pdev->device == 0x6841) || \
2418 (rdev->ddev->pdev->device == 0x6842) || \
2419 (rdev->ddev->pdev->device == 0x6843))
2420
2421 /*
2422 * BIOS helpers.
2423 */
2424 #define RBIOS8(i) (rdev->bios[i])
2425 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2426 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2427
2428 int radeon_combios_init(struct radeon_device *rdev);
2429 void radeon_combios_fini(struct radeon_device *rdev);
2430 int radeon_atombios_init(struct radeon_device *rdev);
2431 void radeon_atombios_fini(struct radeon_device *rdev);
2432
2433
2434 /*
2435 * RING helpers.
2436 */
2437 #if DRM_DEBUG_CODE == 0
2438 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2439 {
2440 ring->ring[ring->wptr++] = v;
2441 ring->wptr &= ring->ptr_mask;
2442 ring->count_dw--;
2443 ring->ring_free_dw--;
2444 }
2445 #else
2446 /* With debugging this is just too big to inline */
2447 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2448 #endif
2449
2450 /*
2451 * ASICs macro.
2452 */
2453 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2454 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2455 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2456 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2457 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2458 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2459 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2460 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2461 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2462 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2463 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2464 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2465 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2466 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2467 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2468 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2469 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2470 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2471 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2472 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2473 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2474 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2475 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2476 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2477 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2478 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2479 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2480 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2481 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2482 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2483 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2484 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2485 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2486 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2487 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2488 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2489 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2490 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2491 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2492 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2493 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2494 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2495 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2496 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2497 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2498 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2499 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2500 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2501 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2502 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2503 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2504 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2505 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2506 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2507 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2508 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2509 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2510 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2511 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2512 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2513 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2514 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2515 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2516 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2517 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2518 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2519 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2520 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2521 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2522 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2523 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2524 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2525 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2526 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2527 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2528 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2529 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2530 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2531 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2532 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2533 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2534 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2535
2536 /* Common functions */
2537 /* AGP */
2538 extern int radeon_gpu_reset(struct radeon_device *rdev);
2539 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2540 extern void radeon_agp_disable(struct radeon_device *rdev);
2541 extern int radeon_modeset_init(struct radeon_device *rdev);
2542 extern void radeon_modeset_fini(struct radeon_device *rdev);
2543 extern bool radeon_card_posted(struct radeon_device *rdev);
2544 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2545 extern void radeon_update_display_priority(struct radeon_device *rdev);
2546 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2547 extern void radeon_scratch_init(struct radeon_device *rdev);
2548 extern void radeon_wb_fini(struct radeon_device *rdev);
2549 extern int radeon_wb_init(struct radeon_device *rdev);
2550 extern void radeon_wb_disable(struct radeon_device *rdev);
2551 extern void radeon_surface_init(struct radeon_device *rdev);
2552 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2553 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2554 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2555 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2556 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2557 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2558 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2559 extern int radeon_resume_kms(struct drm_device *dev);
2560 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2561 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2562 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2563 const u32 *registers,
2564 const u32 array_size);
2565
2566 /*
2567 * vm
2568 */
2569 int radeon_vm_manager_init(struct radeon_device *rdev);
2570 void radeon_vm_manager_fini(struct radeon_device *rdev);
2571 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2572 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2573 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2574 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2575 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2576 struct radeon_vm *vm, int ring);
2577 void radeon_vm_fence(struct radeon_device *rdev,
2578 struct radeon_vm *vm,
2579 struct radeon_fence *fence);
2580 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2581 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2582 struct radeon_vm *vm,
2583 struct radeon_bo *bo,
2584 struct ttm_mem_reg *mem);
2585 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2586 struct radeon_bo *bo);
2587 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2588 struct radeon_bo *bo);
2589 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2590 struct radeon_vm *vm,
2591 struct radeon_bo *bo);
2592 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2593 struct radeon_bo_va *bo_va,
2594 uint64_t offset,
2595 uint32_t flags);
2596 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2597 struct radeon_bo_va *bo_va);
2598
2599 /* audio */
2600 void r600_audio_update_hdmi(struct work_struct *work);
2601
2602 /*
2603 * R600 vram scratch functions
2604 */
2605 int r600_vram_scratch_init(struct radeon_device *rdev);
2606 void r600_vram_scratch_fini(struct radeon_device *rdev);
2607
2608 /*
2609 * r600 cs checking helper
2610 */
2611 unsigned r600_mip_minify(unsigned size, unsigned level);
2612 bool r600_fmt_is_valid_color(u32 format);
2613 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2614 int r600_fmt_get_blocksize(u32 format);
2615 int r600_fmt_get_nblocksx(u32 format, u32 w);
2616 int r600_fmt_get_nblocksy(u32 format, u32 h);
2617
2618 /*
2619 * r600 functions used by radeon_encoder.c
2620 */
2621 struct radeon_hdmi_acr {
2622 u32 clock;
2623
2624 int n_32khz;
2625 int cts_32khz;
2626
2627 int n_44_1khz;
2628 int cts_44_1khz;
2629
2630 int n_48khz;
2631 int cts_48khz;
2632
2633 };
2634
2635 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2636
2637 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2638 u32 tiling_pipe_num,
2639 u32 max_rb_num,
2640 u32 total_max_rb_num,
2641 u32 enabled_rb_mask);
2642
2643 /*
2644 * evergreen functions used by radeon_encoder.c
2645 */
2646
2647 extern int ni_init_microcode(struct radeon_device *rdev);
2648 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2649
2650 /* radeon_acpi.c */
2651 #if defined(CONFIG_ACPI)
2652 extern int radeon_acpi_init(struct radeon_device *rdev);
2653 extern void radeon_acpi_fini(struct radeon_device *rdev);
2654 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2655 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2656 u8 perf_req, bool advertise);
2657 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2658 #else
2659 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2660 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2661 #endif
2662
2663 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2664 struct radeon_cs_packet *pkt,
2665 unsigned idx);
2666 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2667 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2668 struct radeon_cs_packet *pkt);
2669 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2670 struct radeon_cs_reloc **cs_reloc,
2671 int nomm);
2672 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2673 uint32_t *vline_start_end,
2674 uint32_t *vline_status);
2675
2676 #include "radeon_object.h"
2677
2678 #endif
Linux kernel - Deliverables
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